Cypress MicroSystems

Application Note AN2025

CTCSS Carrier Generation with a PSoC Microcontroller

By: Jeff Dahlin

Associated Project: AN2025, AN2025_C
Associated Part Family: CY8C25xxx, CY8C26xxx

Summary
This Application Note demonstrates how to implement a Continuous Tone Coded Squelch System (CTCSS)
carrier generator using a 256-byte sine wave look up table in ROM, and a DAC6 User Module. The basic
routine for generating the sine wave is not application specific and can be used to generate other waveforms
and other frequencies.

Introduction If a pair of radios is set to the same CTCSS tone,

Continuous Tone Coded Squelch System then the audio transmitted by one radio will be
(CTCSS) or similar mechanisms are used in output on the other radio’s speaker.
many handheld radios to allow multiple users to
share one carrier frequency. The goal for CTCSS CTCSS works by mixing a single tone with the
is to allow the receiving radio to suppress (or transmitted voice audio at all times. A radio
squelch) signals that are not intended for its user. receiving a signal will check to see if the CTCSS
tone selected for that radio is present. If the tone
is present the receiving radio will output the voice
Tone Frequency Tone Frequency audio. If the tone is not present any signal
1 67.0 Hz 20 131.8 Hz received will not be output to the speaker.
2 71.9 Hz 21 136.5 Hz
This allows multiple radios to coexist on the same
3 74.4 Hz 22 141.3 Hz carrier frequency in the same area without users
4 77.0 Hz 23 146.2 Hz having to listen to everyone.
5 79.7 Hz 24 151.4 Hz
6 82.5 Hz 25 156.7 Hz CTCSS Carrier Frequencies
7 85.4 Hz 26 162.2 Hz CTCSS uses 38 different frequencies between
8 88.5 Hz 27 167.9 Hz 67.0 Hz and 250.3 Hz as the selection tones.
9 91.5 Hz 28 173.8 Hz Table 1 shows the frequency associated with
each of the tones. Some radios use additional
10 94.8 Hz 29 179.9 Hz “nonstandard” frequencies for CTCSS
11 97.4 Hz 30 186.2 Hz functionality. This application only uses the
12 100.0 Hz 31 192.8 Hz standard CTCSS frequencies.
13 103.5 Hz 32 203.5 Hz
14 107.2 Hz 33 210.7 Hz Frequency Generation
15 110.9 Hz 34 218.1 Hz In this project, the CTCSS frequencies are
generated by transferring data from a 256-entry,
16 114.8 Hz 35 225.7 Hz 8-bit look up table (LUT) into a DAC6 User
17 118.8 Hz 36 233.6 Hz Module at a fixed rate. The DAC is updated at a
18 123.0 Hz 37 241.8 Hz constant rate in an Interrupt Service Routine
19 127.3 Hz 38 250.3 Hz (ISR) that is controlled by a Timer8 User Module.
The frequency of the CTCSS tone is adjusted by
varying the step size through the LUT.
Table 1: Standard CTCSS Frequencies

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The 256-byte LUT contains data that represents Phase Coherence

one cycle of a sine wave. This data is stored in A side effect of the way in which the output
sign and magnitude format. Sign and magnitude frequency is changed (the accumulated index
is the native format of the DAC Data register and variable is not cleared) is that the sine wave
allows the write to the DAC to be done more exhibits no discontinuity when the frequency
efficiently than with other formats. changes. Although this is not critical for CTCSS
generation, it may be required in other waveform
In this example project the Timer8 is set to applications.
approximately 10 kHz. The frequency of the
output waveform is determined by the step size
of the index through the LUT. For example, with a Hardware Configuration
10 kHz update rate and a step size of 1, the Figure 1 shows the placement of the three User
resulting sine wave would have a frequency of Modules used in this project. CTCSS_DAC, a
about 39 Hz (10,000 / 256). If a step size of 2 DAC6, outputs the analog signal that is the sine
were used, the resulting sine wave would have a wave. CTCSS_DAC is configured to use a
frequency of twice that, at about 78 Hz. SignAndMagnitude data format. The output to the
analog column bus is enabled and Buf0 is
The 256-byte LUT is stored in ROM and is enabled to output the analog signal to Port0[3].
accessed using the MCU’s INDEX instruction.
The INDEX instruction uses a base address,
which is hardcoded as the operand in the
instruction and an index, which is the value in the
Accumulator at the start of the command. When
the INDEX instruction is executed the table entry
pointed to by the sum of the base address and
the index is loaded into the Accumulator. The 8-
bit index for the LUT comes from the upper byte
of a 16-bit index (iCTCSSFreqIndex in the
project). The upper byte can be thought of as the
integer portion of the index and the lower byte
can be thought of as the fractional portion of the
index. To step through the LUT, a 16-bit index
increment (iCTCSSFreqInc in the project), also
having an integer portion and a fractional portion,
is added to the 16-bit accumulated index. This
allows the use of fractional increments, which
creates a more accurate frequency than is
possible with an integer increment.

In the example above where a step size of 2

resulted in an output frequency of 78 Hz, the
index increment would be 0x0200. To get an
output frequency of 67 Hz (CTCSS tone 1), a
step size of 1.72 is needed. The index increment
in this case would be 0x01b3.

Frequency Selection
In this project a function is provided that sets the
index increment value for the desired frequency.
This function, SetCTCSSFreq(), is passed a 1-
byte argument that is the CTCSS tone number.
The tone number is manipulated (subtract 1 and
multiply by 2) to convert it into an index for a 38
entry 16-bit LUT which contains index increment
values.

Figure 1: CTCSS User Module Placement

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DAC_Timer, a Timer8 configured to divide the

CPU_Clock ISR Overhead
48M clock by 61, is used to generate the column
clock for the DAC6. This results in a DAC update 24 MHz 15 %
rate of 197 kHz. A high DAC update rate is 12 MHz 24 %
desired in this application. The DAC update 6 MHz 44 %
frequency will appear in the spectrum of the
3 MHz 82 %
output and the higher the DAC update rate, the
more effectively it is removed with a simple R-C This project cannot be run below 3 MHz
low pass filter.
Table 2: CTCSS ISR Overhead
Sine_Timer, a Timer8 configured to divide the
output of DAC_Timer by 78, generates an output
frequency of 10.088 kHz. If designer chooses to use different timings for
this application the resulting ISR overhead will
Port0[3] (pin 3 on a 28-pin package) is set to differ from what is shown in Table 2.
AnalogOutBuf0 with a drive mode of High Z to
enable the analog signal to be output. Tradeoffs
There are some tradeoffs that must be made
The frequency accuracy requirement for CTCSS when designing a waveform generator. This
is usually better than the +/-2.5% accuracy of the Application Note will touch on a few.
Internal Main Oscillator in the PSoC
microcontroller; therefore an external crystal ISR overhead versus DAC update rate is one
oscillator is required. The Port1[0] and Port1[1] tradeoff that must be weighed. More steps in
pins are set to High Z and a 32.678 kHz crystal is wavelength will result in a lower harmonic
connected to the part as specified in the distortion of the waveform. Fewer steps in one
CY8C25xxx/CY8C26xxx Device Family Data wavelength will reduce the ISR overhead, leaving
Sheet. more of the CPU available for other tasks.

ISR Overhead Waveform distortion versus output-filter

If other tasks need to be taken care of by the complexity is another part of the same tradeoff. If
PSoC microprocessor, the amount of CPU the DAC update rate is much higher than the
overhead used by the ISR while generating the frequency of the output waveform, the major
CTCSS output is important. There are three contributor to distortion will be at the DAC update
factors that impact what the ISR overhead will be. frequency. In this case a simple R-C low pass
They are the DAC6 analog column clock speed, filter on the output (often called a reconstruction
the CPU Clock speed, and the Sine_Timer clock filter) may acceptably reduce the waveform
rate. distortion. If the DAC update rate is too close to
the frequency of the output waveform, the
The Sine_Timer ISR involves a write stall when harmonics of the output frequency will be the
updating the CTCSS_DAC. A write stall pauses major contributor to distortion. In this case
the CPU until the start of the rising edge of the something more than a simple R-C low pass filter
Phi1 clock in the analog column. This is done to would be needed to clean up the waveform. A
prevent glitches from occurring on the DAC Low Pass Filter User Module may be needed.
output. (See the Analog Synchronization section
of the CY8C25xxx/CY8C26xxx Device Family In some designs, due to limited resources, the
Data Sheet for more details on write stall.) The source for the DAC’s analog column clock must
worst-case stall period for the DAC_Timer period be shared with another function. If this is the
used in this project is 5.1 µsec. Apart from the case, a slower clock may need to be used. This
write stall; the ISR takes an additional 93 CPU will impact the ISR overhead by increasing the
clock cycles to execute. maximum stall time which will increase the
waveform distortion by moving the DAC clock
With a DAC update rate of 10.088 kHz, the worst- frequency closer to the output frequency. Ideally,
case ISR overhead is 15%. Table 2 shows the a frequency close to the DAC6 maximum update
ISR overhead for different CPU clock rates, rate would be used.
assuming an analog column clock of 197 kHz
and a DAC update rate of 10.088 kHz.

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In this project a 6-bit DAC was selected over an The waveform distortions for selected CTCSS
8-bit DAC. The 8-bit DAC would result in more tones (1, 7, 13, 19, 26, 32, and 38) were
precise steps, but would use more analog SoC calculated based on measurements taken with a
blocks. Through experimentation it was found Hewlett-Packard 3585A Spectrum Analyzer. The
that the number of steps per waveform had a measurements were taken directly from the
much greater impact on the accuracy of the output of the PSoC microcontroller with no
output waveform than the DAC resolution. reconstruction filter. The results are graphed in
Figure 2. The maximum distortion, 3.8%,
Performance occurred at the highest output frequency, as
With the timers configured as described in the would be expected.
previous sections of this Application Note and
using an external crystal, data was collected to
% D is t o rt io n v s . F re que nc y
determine the frequency accuracy and the
waveform distortion of the output. 5.00%
4.00%
The output frequencies were measured for all 48
CTCSS tones using a Fluke 87 Digital 3.00%

Multimeter. The results of these measurements 2.00%

are shown in Table 3. The range of the frequency 1.00%
error is between +0.10% and –0.13%. 0.00%
50 100 150 200 250 300

Figure 2: Waveform Distortion

Additional testing was run using a DAC update

rate (Sine_Timer) of 6.5 kHz. The maximum
distortion increased to 6.3%.

Tone # Frequency Measured Error Tone # Frequency Measured Error

1 67.0 67.09 -0.13% 20 131.8 131.83 -0.02%
2 71.9 71.83 0.10% 21 136.5 136.47 0.02%
3 74.4 74.45 -0.07% 22 141.3 141.20 0.07%
4 77.0 77.08 -0.10% 23 146.2 146.16 0.03%
5 79.7 79.71 -0.01% 24 151.4 151.37 0.02%
6 82.5 82.45 0.06% 25 156.7 156.79 -0.06%
7 85.4 85.39 0.01% 26 162.2 162.15 0.03%
8 88.5 88.50 0.00% 27 167.9 167.87 0.02%
9 91.5 91.54 -0.04% 28 173.8 173.83 -0.02%
10 94.8 94.81 -0.01% 29 179.9 179.81 0.05%
11 97.4 97.38 0.02% 30 186.2 186.18 0.01%
12 100.0 100.01 -0.01% 31 192.8 192.72 0.04%
13 103.5 103.51 -0.01% 32 203.5 203.40 0.05%
14 107.2 107.22 -0.02% 33 210.7 210.70 0.00%
15 110.9 110.93 -0.03% 34 218.1 218.10 0.00%
16 114.8 114.78 0.02% 35 225.7 225.60 0.04%
17 118.8 118.83 -0.03% 36 233.6 233.50 0.04%
18 123.0 123.12 -0.10% 37 241.8 242.10 -0.12%
19 127.3 127.22 0.06% 38 250.3 250.30 0.00%
Table 3: Frequency Accuracy

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Shown below are the waveforms for Tone 1

(Figure 3) and for Tone 38 (Figure 4) captured
with a Tektronix TDS 3034 Digital Storage
Oscilloscope. Notice that the individual DAC
increments are more apparent at the higher
frequency. This is because there are fewer steps
per cycle at the higher frequencies. This results
in a greater waveform distortion.

Figure 4: Tone 38 (250.3 Hz) Waveform

Figure 3: Tone 1 (67.0 Hz) Waveform

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Copyright  2002 Cypress MicroSystems, Inc. All rights reserved.
PSoC™ (Programmable System on Chip) is a trademark of Cypress MicroSystems, Inc.
All other trademarks or registered trademarks referenced herein are property of the respective corporations.
The information contained herein is subject to change without notice.

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