Interface (Data Transmission) Texas Instruments Incorporated

Extending the SPI bus for

long-distance communication
By Thomas Kugelstadt
Senior Applications Engineer
The serial peripheral interface (SPI) bus is an unbalanced Over long distances, however, the transmission cable
or single-ended serial interface designed for short-distance introduces significant propagation delay into the signal
communication between integrated circuits. Typically, a path. Assuming a typical signal velocity of 5 ns/m, a 100-m
master device exchanges data with one or multiple slave cable will cause a propagation delay of 500 ns. Because the
devices. The data exchange is full-duplex and requires syn­ data sent from the master to the slave experiences the
chronization to an interface clock signal. However, recent same delay as the master-initiated interface clock, both
trends in the design of industrial data-acquisition systems will remain in sync across the entire data link. In the oppo-
have not taken this synchronization requirement into site direction, however, the slave sends data to the master
account, and distances between the microcontroller and only when the first clock edge reaches the slave. Further­
the corresponding analog-to-digital and digital-to-analog more, this data will experience a second delay on its way
converters (ADCs and DACs) can reach 100 m or more. back to the master, so the slave data will be out of sync by
The impact of the added propagation delay on the data- twice the cable’s propagation delay.
to-clock synchronicity is often ignored, and interface Of course, communicating across a 100-m cable won’t
designs that operate perfectly in the lab environment cease be possible without appropriate line drivers and receivers.
operation when implemented on the factory floor. There These components will further increase the propagation
can be multiple reasons for the interface malfunction. This delay by about another 50 ns, for a total of 550 ns. The
article tries to shed light on the major ones, including: slave data will therefore lag behind the first clock edge by
• Lack of synchronization due to large propagation delays a total of 1100 ns, or 11 bits when a data rate of 10 Mbps
of the signal path is assumed.
• Reduced noise immunity due to long-distance,
unbalanced signal paths
Figure 1. Simplified schematic of an SPI
• Damaged transceivers due to large ground-potential
differences (GPDs)
• Data transmission errors due to unterminated data lines
SCK CLK
• Transceiver latch-up and network downtime due to
MOSI SIMO
large electrical transients ADC1
MCU MISO SOMI
Synchronicity SS1 CE
An SPI primarily uses three interface lines: SS2
• An interface clock initiated by the master device to
ensure synchronous data transfers CLK

• A data line for data sent from the master to a slave SIMO
ADC2
• A data line for data sent from a slave to the master SOMI
CE
A fourth wire that carries what is known as the slave-
select signal is not required for controlling interface flow
(a) MCU master controlling two slaves
but is needed for addressing a specific slave out of a range
of slave devices. Figure 1a shows a simplified schematic of
a microcontroller unit (MCU) operating as the master that SCK
controls two data converters representing the slaves.
With byte lengths ranging from 8 to 12 bits and multiples
thereof, and data rates ranging from 1 to 20 Mbps, the MOSI SIMO Tx1 Tx2 Tx3
standard SPI configuration allows for short propagation
times and hence only short distances in order to maintain
synchronicity between the interface clock and the data MISO SIMO Rx1 Rx2 Rx3
transmitted in both directions. Figure 1b shows the inter-
face timing of the first three data bits when the SPI is (b) Timing of first three data bits
configured to change data at the rising clock edge and to
sample data at the falling clock edge.
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Texas Instruments Incorporated Interface (Data Transmission)

The only possible solution for restoring

Figure 2. Clock-feedback path restores synchronicity
synchronicity between the slave data and
the interface clock while maintaining a
high data rate is to feed the clock signal
Master Data Slave
from the slave back to the master. Figure 2 Link
clarifies the benefit of clock feedback. Here t0 t 0 + tP
SCKM tP CLK
t 0 represents the first rising clock edge, or
the start of a data transmission, and tP is SPl1 =
Master
the data-link propagation delay. After tra- t0 t 0 + tP
versing the data link, both the master clock MOSI tP SIMO1
(SCKM) and the master data (MOSI)
remain in sync. Feeding back the master t 0 + 2tP t 0 + tP
clock signal synchronizes the clock with SCKS tP
the slave data so that both arrive equally SPl2 =
delayed at the master. The only require- Slave
t 0 + 2tP t 0 + tP
ment is that the master provide two inde- SIMO2 tP SOMI
pendent SPI ports, one configured as a
master (SPI1) and the other configured as
a slave (SPI2). Most modern microcontrol­
lers possess two or more SPI ports, so this
requirement poses no problem. Because the conductors of twisted-pair cable are closely
Nevertheless, implementing a long-distance, SPI- electrically coupled, external noise induced equally into
compatible interface in the real world is not a trivial task. both conductors appears as common-mode noise at the
Long-distance data links are always subject to external receiver input. Although differential receivers are sensitive
noise sources, ground-potential differences (GPDs), volt- to signal differences, they are immune to common-mode
age and current surges due to inductive load switching, signals. The receiver therefore rejects common-mode
and often even reflections due to wrong or no termination. noise, and signal integrity is maintained.
The flowing schematic in Figure 3 (see next page) tries to Another benefit of close electric coupling is that the
cover all of these aspects by showcasing the various trans- currents in the two conductors create magnetic fields that
ceiver and protection circuits that can counteract the cancel each other. The initial transversal electromagnetic
derogating effects. (TEM) waves of the two conductors are therefore largely
reduced to electric fields that cannot radiate into the envi-
Increasing noise immunity ronment (see Figure 4). Only the far smaller fringing fields
Unbalanced or single-ended drivers and receivers are outside the conductor loop can radiate, thus yielding
inadequate for accomplishing a robust data link over long much lower electromagnetic interference (EMI).
distances, as they are susceptible to common-mode noise.
An excellent method to eliminate common-mode noise in Eliminating ground loops and GPDs
a synchronous, full-duplex interface such as an SPI is the While the RS-485 and RS-422 standards specify that a data
use of RS-422 differential driver and receiver circuits in link without a ground wire can be operated with a GPD of
combination with twisted-pair cable. up to ±7 V, it is advisable not to assume that these values

Figure 4. TEM-wave radiation effects

Coupled
H Large
Fields
Fringing
Fields

t Small
Fringing
E Large Fields
Fringing
Fields

(a) Relationship of magnetic and electric fields (b) Single conductor (c) Closely coupled conductor pair

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Analog Applications Journal 4Q 2011 www.ti.com/aaj High-Performance Analog Products

 Interface (Data Transmission) Texas Instruments Incorporated

Figure 3. SPI extended via RS-422 data link

VS1b
VS1a
1 kΩ 0.1 µF Master
0.1 µF
Node
DE VCC
DVCC 1Y
RF
UCA0CLK 1D
1Z
SPI CF
Master RF 2Y
2D
UCA0SOMI 2Z
CF
RF 1A 100 Ω
1R
UCB0CLK 1B
SPI CF
Slave RF 2A 100 Ω
2R
UCB0SIMO 2B
CF
DVSS
RE GND

1 kΩ

MSP430G2X33 SN65C1167 4700 pF

2 kV
To PE Mains
PE

VS2_ISO VS2
Slave 1 kΩ 0.1 µF 0.1 µF 1 kΩ 1 kΩ 0.1 µF
Node
VS2
DE VCC VCC1 EN1 EN2 VCC2 0.1 µF
100 Ω 1A RF
1R INA OUTA
1B
CF VCC
100 Ω 2A CLKIN A0
RF INB OUTB
2R
2B SDI ADC
CF
1Y SDO A0
RF OUTC INC GND
1D
1Z
CF
2Y RF
2D OUTD IND
2Z
CF
RE GND GND1 GND2

1 kΩ

4700 pF SN65C1167 ISO7242C

2 kV
To PE Mains
PE

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Texas Instruments Incorporated Interface (Data Transmission)

represent the maximum GPD. Much higher values are often Depending on their location, the wave nodes (minima)
encountered in industrial plants, sometimes reaching sev- and antinodes (maxima) can have varying effects on the
eral hundreds and even thousands of volts. Because GPDs bus transceivers (see Figure 5). A driver close to an anti-
largely depend on factors outside the system designer’s node sees a high impedance and therefore transfers insuf-
control, such as the electric installation and/or the number ficient energy to the bus. A driver close to a node sees a
of electric motors and generators, the most secure way to very low impedance or a short. The resulting output current
prevent transceiver damage from large ground-potential can exceed the driver’s maximum drive capability and
variations is to galvanically isolate any remote network node even trigger its current limit at around 250 mA. Receivers
from the bus. The circuit in Figure 3 demonstrates this by located at antinodes can be damaged by excessively large
having only the remote transceiver connected to the bus, input signals that exceed the receiver’s common-mode
while the data-converter circuit is galvanically isolated. input range. Receivers close to nodes experience insuffi-
Also, to provide the input and output signals of the cient signal strength and are highly susceptible to noise
remote transceiver with a stable ground reference, the and EMI. Any of the foregoing events will result in data
transceiver’s ground terminal as well as the digital isola- errors from either the transmission or the reception of
tor’s ground terminal (GND1) are connected to the master wrong data.
ground potential via a separate ground conductor. This
form of grounding is known as a single ground reference. Protecting the network against
damaging transients
Avoiding antennas through line termination Electrical overstress transients caused by electrostatic dis-
The data link in Figure 3 is terminated with 100-W resis- charge (ESD), switching of inductive loads, or lightning
tors, as suggested by the RS-422 standard, matching the strikes will corrupt data transmission and damage bus
characteristic impedance of the bus cable. A myth exists transceivers unless effective measures are taken to dimin-
that bus cables of a few meters in length or data links ish their impact. Modern transient-voltage suppressors,
operating at low data rates don’t need termination. Don’t such as the ones in Figure 3, are the preferred protection
believe it. Operating the bus without termination can turn components for high-speed data transmission due to their
the transmission line into a nasty receiver/transmitter low capacitance, which allows them to be designed into
antenna. The lack of termination resistors, which usually every node of a multinode network without requiring a
absorb the incident wave power sent by the driver, causes reduction in data rate.
standing waves to occur; and the entire incident wave is Depending on the power rating of the transient-voltage
reflected into the bus. The reflected waves mix with other suppressor chosen, the maximum clamp voltages can
incident waves, thus yielding standing waves for signal fre- range from 25 to 35 V, which is higher than a standard
quencies whose quarter wavelengths, or multiples thereof, transceiver’s maximum bus voltage of 14 V. In this case,
equal the length of the data link. the internal protection circuit of the transceiver must

Figure 5. Effects of an unterminated bus

L=¼×n×λ
for n = 1, 3, 5 Open
L Line
Open
Driver at Antinode Driver at Node Receiver at Node Receiver at Antinode
Line
– Driver sees a – Driver sees – Low signal voltage – Received signal can
high impedance a short – Highly susceptible exceed maximum
Driver sees a low Receiver sees a – Very small supply – Very high to noise/EMI common-mode
impedance (short) high impedance current supply current input range
– Receiver can be
(a) Effects with a quarter-wave line length damaged

(b) Effects of connecting drivers and receivers at nodes and antinodes

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Analog Applications Journal 4Q 2011 www.ti.com/aaj High-Performance Analog Products

 Interface (Data Transmission) Texas Instruments Incorporated

absorb the remaining clamp energy to protect the device high-voltage capacitor that has one plate connected to
from damage. ground and the other plate connected to a protective-
For ESD and burst transients, the clamp energy is rather earth (PE) island. This island is then connected via a
low due to the short pulse duration and does not pose a short, low-inductance earthing wire to the PE terminal of
problem to the internal ESD cells. Clamp energy from the local mains supply.
surge transients, however, can present a serious challenge In addition to the suppressor’s action on the bus side,
due to the much longer pulse duration. For transceivers further protection against signal degradation is required on
specified with low ESD immunity, series resistors might be the transceiver’s single-ended sides. This is accomplished
necessary to reduce the remaining current flowing into the with R-C low-pass filters, which filter transient remnants
transceiver. Common resistor values range from 5 to 10 W. in the reception path and stop high-frequency noise from
Note that these resistors must be surge-rated to provide entering the transmission path.
high pulse robustness.
Although the transient-voltage suppressor’s diodes divert Related Web sites
large transient currents to ground, it must be ensured that interface.ti.com
these currents are further diverted to true earth potential www.ti.com/product/ISO7242C
without disturbing the ground reference of the remaining www.ti.com/product/SN65C1167
circuitry. Often this is accomplished by implementing a

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High-Performance Analog Products www.ti.com/aaj 4Q 2011 Analog Applications Journal

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