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Resistive switching memories based on metal oxides: mechanisms, reliability and scaling

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2016 Semicond. Sci. Technol. 31 063002

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 Semiconductor Science and Technology

Semicond. Sci. Technol. 31 (2016) 063002 (25pp) doi:10.1088/0268-1242/31/6/063002

Topical Review

Resistive switching memories based on

metal oxides: mechanisms, reliability and
scaling
Daniele Ielmini
Dipartimento di Elettronica, Informazione e Bioingegneria and Italian Universities Nanoelectronics Team
(IU.NET) Politecnico di Milano, Piazza L. da Vinci I-32-20133 Milano, Italy

E-mail: [email protected]

Received 6 July 2015, revised 1 March 2016

Accepted for publication 16 March 2016
Published 16 May 2016

Abstract
With the explosive growth of digital data in the era of the Internet of Things (IoT), fast and
scalable memory technologies are being researched for data storage and data-driven
computation. Among the emerging memories, resistive switching memory (RRAM) raises strong
interest due to its high speed, high density as a result of its simple two-terminal structure, and
low cost of fabrication. The scaling projection of RRAM, however, requires a detailed
understanding of switching mechanisms and there are potential reliability concerns regarding
small device sizes. This work provides an overview of the current understanding of bipolar-
switching RRAM operation, reliability and scaling. After reviewing the phenomenological and
microscopic descriptions of the switching processes, the stability of the low- and high-resistance
states will be discussed in terms of conductance fluctuations and evolution in 1D filaments
containing only a few atoms. The scaling potential of RRAM will finally be addressed by
reviewing the recent breakthroughs in multilevel operation and 3D architecture, making RRAM
a strong competitor among future high-density memory solutions.

Keywords: resistance switching memory (RRAM), conductive bridge memory (CBRAM),

memristor, memory scaling, emerging memory, crossbar array, metal-insulator transition
(Some figures may appear in colour only in the online journal)

1. Introduction spin-transfer torque memories (STTRAM) [7–9] have been

proposed, each of them presenting advantages in terms of area
The last 15 years have seen the widespread emergence of occupation, speed, and scaling. A common denominator for
novel device technologies aiming at replacing or com- these devices is that they are resistive memories where the
plementing the limited scaling of flash memories and other resistance serves as a probed state variable. The resistance can
silicon-based memories such as dynamic random access be changed by electrical pulses according to various physical
memory (DRAM) and static random access memory processes: in an RRAM, the resistance usually changes
(SRAM). Devices such as resistive switching memory according to the state of the conductive filament (CF) within
(RRAM) [1–3], phase change memory (PCM) [4–6], and the insulating oxide layer. Resistance change in other devices
can rely on the phase of an active material, as in the case of
PCM, or in the magnetic polarization of a ferromagnetic layer
Original content from this work may be used under the terms
in a magnetic tunnel junction (MTJ), as in the case of
of the Creative Commons Attribution 3.0 licence. Any
further distribution of this work must maintain attribution to the author(s) and STTRAM. All resistive memories have only two external
the title of the work, journal citation and DOI. terminals, instead of the three terminals in conventional

0268-1242/16/063002+25$33.00 1 © 2016 IOP Publishing Ltd Printed in the UK

Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

capacitor (1T1C) structure of DRAM devices, and a crossbar

architecture [28]. RRAM has also been demonstrated with a
relatively small scale (<10 MB), aimed at embedded memory
applications in the automotive industry, smart cards and smart
sensors for the Internet of Things markets [29–31]. While this
technological progress allows RRAM to be supported for
practical implementation, final suitable applications are not
yet clear. Embedded RRAM provides obvious advantages
over flash, such as lower energy consumption and higher
speed [31]; on the other hand, crossbar RRAM offers a higher
density compared to DRAM and a higher speed compared to
Figure 1. Crossbar architecture for resistive memories. The array is flash, in addition to nonvolatile behavior and 3D integration
obtained by perpendicular conductive wordlines (rows) and bitlines
(columns), where a memory element exists at the intersection
[32, 33]. These are ideal properties for storage class memory
between each row and column. The memory element can be (SCM) applications, filling the gap between DRAM (high
accessed for read and write by biasing the corresponding wordline performance, low density) and flash (high density, slow
and bitline. The individual memory cell has a record low area of 4F2, operation) [34].
where F is the minimum lithographic feature size dictated by the Although RRAM looks promising from several per-
technology node. Reprinted with permission from [10]. Copyright
2009 American Chemical Society.
spectives, there are still reliability, technology and knowledge
limits which must be overcome before successful imple-
mentation in the industry. Among the reliability issues,
CMOS-based DRAM or flash. As a result, these memories variability [35–37] and noise [38–43] represent strong
can be accommodated in a crosspoint array, as shown in obstacles to multilevel cell (MLC) operation and high-density
figure 1, where the dense packing of wordlines/bitlines memory arrays [44]. The most critical issue from the tech-
allows for an extremely small bit area of only 4F2, where F is nology point of view is the identification of a viable two-
the minimum feature size accessible by lithography [10–12]. terminal selector for crossbar arrays. To solve these issues,
Another significant advantage is the ability to independently significant improvement in our understanding of resistive
program/erase each device, while flash memories require switching mechanisms is needed.
block erasing if any individual bit in the array needs to be This work reviews current state-of-the-art RRAM phy-
reprogrammed. Finally, resistive memories display faster sics, technology and scaling. First, the basic device types and
switching, usually in the range of 100 ns, or even below the ns operation will be reviewed, covering unipolar, bipolar and
regime in the case of STTRAM. A short switching time, threshold switching modes of operation. Then, physical
combined with relatively low-voltage operation also allows mechanisms for filamentary conduction and switching will be
for low program/erase energy use for low-power summarized, introducing the most widely accepted models for
consumption. device and circuit description. Scaling and reliability issues
Finally, emerging memories can be fabricated in the back will then be reviewed, addressing statistical fluctuations in the
end of line (BEOL) at relatively low temperatures, which current (noise) and switching (variability), endurance and data
allows for easy integration with CMOS devices and stacking retention. Finally, the most relevant technology break-
in 3D [11, 13, 14]. For all these reasons, resistive memories throughs in terms of MLC, 3D architectures, and selector
are very promising not only for nonvolatile memories, but technologies will be summarized.
also for computing memories, allowing fast data access to
overcome the von Neumann bottleneck [15], and for com-
puting architectures blurring the distinction between memory 2. Device structure and operation
and computing circuits, such as nonvolatile memristive logic
computation [16, 17] or neuromorphic networks [18–22]. Figure 2 shows the schematic structure and operation of an
Among the emerging memory technologies, RRAM is RRAM device [45]. The device consists of an insulating layer
one of the most promising devices given its good cycling —usually a metal oxide (MeOx)— interposed between a top
endurance [23, 24], moderately high speed [25, 26], ease of electrode (TE) and a bottom electrode (BE), both generally
fabrication and good scaling behavior. One of the most sig- consisting of metallic layers or stacks (figure 2(a)). The
nificant strengths of RRAM against PCM and STTRAM is its device is initially subjected to the operation of electroforming,
simple structure, consisting as it does of only an insulating or simply forming, where a CF is formed by dielectric
layer inserted between two or more metallic layers. Also, the breakdown (figure 2(b)). The current is limited by a com-
current consumption in RRAM is extremely low thanks to pliance system or a series resistor/transistor during forming,
filamentary conduction, whereas the programming current in which allows the size of the CF to be controlled and avoids
PCM and STTRAM is proportional to the device area, thus the destructive (hard) breakdown of the switching layer. After
meaning it can hardly be reduced below 10 μA. Given this forming, the device manifests improved conductance as the
strong potential, large scale (>1 GB) RRAM prototypes have CF connects the TE and BE by shunting the insulating layer,
been presented using both a one-transistor/one-resistor thus resulting in the low-resistance state (LRS) of the RRAM.
(1T1R) structure [27], similar to the one-transistor/one- The reset operation can then be carried out to disconnect the

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 2. RRAM device structure and operation. The device consists of a metal–insulator–metal stack (MIM), where the insulator is most
typically a binary metal oxide MeOx (a). After electroforming, a conductive filament (CF) is formed connecting the top electrode (TE) and the
bottom electrode (BE), thus resulting in the set state or low resistance state (LRS) of the memory device (b). The device can then be switched
to the reset state, or high resistance state (HRS), by an electrical reset operation aimed at disconnecting the CF (c). Switching to the set state is
then possible by set operation. Reprinted with permission from [45]. Copyright (2014) John Wiley & Sons, Inc.

Figure 3. RRAM switching modes. In the unipolar switching mode (a), both set and reset transitions are achieved by applying electrical
voltages of the same polarity, e.g., a positive voltage as in the figure. In the bipolar switching mode (b), instead, set and reset transitions are
executed by applying voltages of opposite polarities, e.g., a positive voltage set and negative voltage reset. In both cases, the current is limited
by a compliance level during the abrupt set transition, to suitably control the CF size and the corresponding LRS resistance value. Reprinted
with permission from [45]. Copyright (2014) John Wiley & Sons, Inc.

CF, resulting in a high-resistance state (HRS), as shown in

figure 2(c). Alternating the set and reset operation, the CF can
be repeatedly connected/disconnected, thus allowing multiple
transition cycles between HRS and LRS. Note that the con-
ductance of HRS is higher compared to the initial state before
forming [46]: this can be understood by the microscopic
structure of the HRS, where the CF is not entirely dissolved
after the reset, rather only disconnected via a relatively small
depletion gap.
The filamentary switching in figure 2 covers most of the Figure 4. RRAM and CBRAM structures. In oxide-based RRAM
technological applications of RRAM. However, RRAM (a), a metallic cap is introduced to the TE side to induce an oxygen
relying on uniform resistivity change across the device area exchange reaction and generate an initial concentration of defects
has also been demonstrated. This is the case for several (i.e., oxygen vacancies, excess metallic Hf in HfOx and Ti
impurities) serving as a reservoir for the set and reset. In the
manganites, cuprates and titanates, where resistance change is CBRAM device (b), instead, the metallic cap on the TE side consists
supposed to take place uniformly at the interface between the of Ag, Cu, or alloys containing these high-mobility metals, thus
oxide and a reactive-metal electrode via oxygen migration capable of migration and CF connection/disconnection in the solid
and electrode reduction/oxidation [47]. Uniform resistance electrolyte.
switching can be recognized by area-dependent LRS resist-
ance and programming current, in contrast to area-indepen- alternated in bipolar switching (figure 3(b)). Unipolar
dent switching in filamentary-type devices [48]. switching has been explained by the purely thermal accel-
Filamentary RRAM relies on two main methods of eration of redox transitions at the basis of CF connection/
resistance switching, which differ by the polarity of the set disconnection in the gap region [1, 49, 50]. In particular,
and reset operation, as shown in figure 3. Both set and reset oxidation of the metallic filament takes place during reset,
processes take place under positive voltage in unipolar thus causing filament disconnection in correspondence with
switching (figure 3(a)), while the set/reset polarities must be the highest temperature in the CF [51–53]. The gradual

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 5. I–V curves of different types of RRAM. The measured I–V characteristics for a HfO2 RRAM device at a variable compliance
current IC (a) and for a Cu/AlOx CBRAM device at IC = 10 μA (b). RRAM and CBRAM devices display similar features, namely, the
ability to control LRS resistance and Ireset by IC, an abrupt set transition, and a gradual reset transition. Part (a) Copyright (2008) IEEE.
Reprinted, with permission, from [60]. Part (b) Copyright (2013) IEEE. Reprinted, with permission, from [65].

disconnection of the CF was revealed by the quantum con- Among the bipolar RRAM types, two distinct classes of
ductance effects in HfO2 [54]. CF reconnection, instead, devices, differing in the typical electrolyte and cap material,
results from the chemical reduction of the metal oxide due to have been identified, as illustrated in figure 4. The first type is
the extremely high temperatures during set transition. the conventional device with a metal oxide MeOx as the
Threshold switching was also recognized as playing an switching material and a metallic cap at the TE side
important role in triggering set transition, thanks to the local (figure 4(a)). The Me is usually a transition metal, such as Hf
formation of an electronic filament supporting local Joule [22, 26], Ta [23, 25], Ti [59], or many others. The cap also
heating for redox reactions [55]. consists of a transition metal, either different from Me, e.g., a
Bipolar switching, however, has been explained in terms Ti/HfO2 stack [60], or the same, e.g., a Hf/HfO2 stack [61].
of ionic migration assisted by the temperature and the electric The use of the metallic cap has been shown to improve
field [56, 57]. During the reset, ionized defects within the CF switching, in that it allows the forming voltage to be suitably
migrate toward the negatively biased electrode, e.g., the TE, limited and controlled. This is because the metal in the cap
thus depleting the CF in correspondence with the highest acts as an oxygen getter, thus introducing oxygen vacancies
temperature region. The displaced defects are re-injected into and other types of defects within the MeOx layer. The
the depletion region in the subsequent set operation. Note that enhanced defect concentration causes a higher leakage current
defects are conserved during bipolar set/reset processes, as in the initial condition before forming, which in turn results in
supported by the numerical simulations of bipolar RRAM a lower voltage for initiating the breakdown process. After
switching, describing pure ionic transport without generation/ forming, the metal cap serves as a reservoir for defect
recombination [57]. In both unipolar and bipolar switching, migration during the set and reset. Therefore, the metal cap
the current is limited below a given compliance current IC also dictates the polarities of bipolar switching, where set
during set transition to avoid destructive breakdown and transition preferentially takes place by the application of a
control the size of the CF. positive voltage to the electrode at the cap side, thus inducing
Unipolar switching is more attractive than bipolar the migration of positively charged defects (oxygen vacancies
switching, since the application of voltage pulses with posi- and metal cations from the cap and the metal oxide
tive polarity only allows for simple circuits and unipolar [46, 56, 57]) from the reservoir toward the depleted region of
diodes for selection in the array. On the other hand, unipolar the CF. Conversely, the reset transition takes place via the
switching typically shows lower uniformity and cycling application of a negative voltage to the cap side.
endurance compared to bipolar switching [58]. The higher Figure 4(b) shows the second type of RRAM structure,
endurance of bipolar switching can be understood by the re- where the electrolyte serves as a dielectric layer for cations
utilization of the same migrating defects during the set and supplied by the cap, generally consisting of a suitable material
reset, which allows for switching relying on pure migration (e.g., a chalcogenide) containing Ag, or Cu, or a metallic
along the same direction, namely along the CF length normal layer of the same metals. This type of device is generally
to the top/bottom electrodes. Due to this reliability gap, most referred to as conductive-bridge memory (CBRAM), or an
research focus has been aimed at bipolar switching RRAM. In electrochemical metallization (ECM) device [1, 27, 29, 62].
the following, the review will be restricted to the bipolar Reported electrolyte materials for CBRAM include chalco-
switching RRAM device. genides, such as GeSe [62] and GeS2 [29], and oxides, such

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 6. An in situ TEM study of a CBRAM-type device. The application of a positive voltage to the Ag TE induces the formation of
nanocrystals protruding from the TE and gradually extending toward the BE, thus highlighting the essential role of Ag migration in the set
operation of this type of CBRAM. A constant voltage of 12 V was applied at increasing times t = 0 (a), 150 s (b), 350 s (c), 470 s (d) and
500 s (e). The scale bar in the figure is 20 nm. Reprinted by permission from Macmillan Publishers Ltd: nature communications [71],
copyright (2012).

as GdOx [63], ZrOx [64] and Al2O3 [65]. The cap consists of
Cu [62, 64, 65], Ag [29], or CuTe [63].
Figure 5 shows the measured I–V curves of a metal-oxide
RRAM device (a) and a CBRAM (b) [60, 65]. There are
several similarities between the two characteristics, namely (i)
the bipolar behavior, (ii) the controllability of resistance R by
the compliance current IC in the set transition, and (iii) the
linear (ohmic) conduction behavior of the LRS as opposed to
the non-linear (exponential) increase of the current with Figure 7. A filament growth model for RRAM switching. The
voltage in the HRS. Note that CBRAM displays a larger application of a positive voltage to the TE results in the migration of
resistance window, defined as the ratio between resistances in positively ionized defects from the reservoir on the TE side (a)
HRS and LRS, namely a factor of about 104 as compared to toward the BE, thus resulting in the nucleation of the CF (b) and its
growth at an increasing time (c), (d). The increase of the diameter of
about 102 in the case of metal-oxide RRAM. Other exper- the CF f thus results in the decreasing resistance observed during the
imental results confirm the similarities between oxide RRAM set transition. Reprinted with permission from [44]. Copyright
and CBRAM in figure 5, and the higher resistance window of (2013) John Wiley & Sons, Inc.
the CBRAM [66]. The higher resistance window can be
explained by the larger ionic mobility of Ag and Cu, which
are typically used in CBRAM, and results in a larger depleted
gap and consequently a higher resistance in HRS. Another Figure 6 shows in situ TEM micrographs taken at increasing
remarkable difference is the lower programming current that times in a planar CBRAM device while the Ag TE was biased
can be achieved in CBRAM compared to oxide RRAM, with a positive voltage [71]. The electrolyte in the CBRAM
thanks to the higher resistance in the HRS. For instance, set/ device was an amorphous Si electrolyte and the BE was made
reset currents as low as 10 pA were reported in Cu-SiO2 of W. TEM results show a CF developing from the Ag TE in
CBRAM [67]. Apart from these quantitative differences, the CBRAM at increasing times, thus confirming the fila-
oxide RRAM and CBRAM show deep qualitative similarities mentary nature of RRAM switching and the microscopic
in their switching, reliability and scaling behavior, which interpretation based on the migration of defects/impurities
allow us to conclude that the microscopic physical mechan- from the positively biased electrode. Similarly, filament
isms underneath the transport and switching phenomena are retraction back to the negatively biased electrode during reset
fundamentally the same. transition was demonstrated by in situ TEM [64].
To describe the switching phenomenology in RRAM,
both analytical and numerical models were presented in the
3. Switching mechanisms literature. Analytical models provide fast calculations of the
device current and/or voltage for circuit design and evalua-
Since the early work in the 2000s, RRAM switching tions. At the same time, analytical models generally provide
mechanisms have been attributed to the filamentary mod- accurate results capturing the dependence on operation para-
ification of conduction properties. It was possible to reveal meters, such as the positive/negative applied voltages, the
this via several different techniques, including CAFM mea- compliance current and the shape of the applied pulse.
surements [68], area dependence of the LRS resistance [69], A generalized analytical model for RRAM describes
infrared thermal imaging of the device [70], and in situ switching as the voltage-controlled change of the CF size, as
microscopic imaging of the device during switching by illustrated in figure 7. Starting from HRS (figure 7(a)), the
transmission electron microscopy (TEM) [64, 71, 72]. application of a positive bias to the TE induces the migration

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

of defects from the top reservoir along the CF direction, energy barrier lowering and the local Joule heating. Evidence
where the electric field, the current density, and consequently, of this important property of RRAM switching was provided
the local temperature are maximized within the device area. by showing that the voltage across the device is always a sole
Vertical ion migration thus results in the CF growth in function of time in conditions where the device voltage is left
figures 7(b)–(d). The subsequent application of a negative free to naturally evolve in time. This is what routinely hap-
bias to the TE causes the retraction of defects back to the TE, pens when an external voltage is applied to a 1T1R structure
causing a reduction in the size of the CF and the final opening or other similar arrangements [75].
of a depleted gap. This CF growth dynamic can be modeled Figure 8(a) shows the measured and calculated I–V
by a rate equation for the CF effective diameter f according curves for a CBRAM type device at a variable IC [73]. While
to [56, 73]: the set and reset voltages are approximately constant, the R
df EA and current levels change by orders of magnitude in response
= Ae- kT (1 ) to the variation of IC. This is summarized by the measured
dt
LRS resistance as a function of IC (figure 8(b)), where R
where A is a constant, EA is the energy barrier for ion decreases linearly according to R = VC/IC [56]. This can be
migration, and T is the local temperature along the CF. understood by the voltage-controlled kinetics of set transition:
Equation (1) states that the growth rate of the CF is limited by in fact, for any given IC, the voltage across the device settles
the supply of cations, which is ultimately controlled by the to a fixed value VC, which is the characteristic voltage to
ion migration rate. The latter is an Arrhenius function of activate ion migration in the timescale of the switching
temperature, describing the probability of ion hopping by experiment. The resistance thus results from the ratio between
overcoming an energy barrier EA given by [56, 73]: VC and IC, as seen in figure 8(b). On the other hand, the reset
EA = EA0 - aqV (2 ) transition is activated by an approximately constant voltage
Vreset; therefore, the reset current Ireset is given by
where EA0 is the energy barrier for hopping at zero voltage, V
Ireset = Vreset/R = VresetIC/VC. The proportionality between
is the applied voltage, and α is a constant describing the
Ireset and IC is confirmed in figure 8(c), showing the measured
fraction of voltage dropping across an individual barrier for
Ireset as a function of IC. Calculations by the model of
hopping. Equation (2) includes the barrier-lowering term,
equations (1)–(3) are displayed in figure 8, indicating the
where the applied voltage enhances the hopping rate along the
overall close agreement and supporting the accuracy of the
direction of the electric field, which accounts for the
voltage-controlled model for RRAM switching. The ability to
directionality of migration at the basis of bipolar switching.
control the resistance by IC enables MLC operation, where
The temperature in equation (1) takes into account Joule
different R levels correspond to the different effective size of
heating, which is significant due to the extremely high current
the CFs.
density and electric field. Joule heating can be described
Note that Vreset is generally smaller than VC, as suggested
analytically by [56, 73]:
by the ratio η = Ireset/IC < 1 in figure 8(d). This can be
Rth 2
T = T0 + V (3 ) attributed to the asymmetric switching in some types of
R CBRAM, due to the mechanical stress arising from the CF
where T0 is the room temperature and Rth is the effective within the electrolyte layer. The CF is affected by a com-
thermal resistance. For instance, assuming an applied voltage pressive strain on the BE side, which induces an elastic force
of 1 V and a ratio Rth/R = 434 KV−2, which is typical for a in support of the retraction of the CF back to the TE side. This
RRAM device in LRS [74], a local temperature of more than explains Ireset/IC < 1 in figure 8(d) and the spontaneous CF
450 °C at the CF can be evaluated from equation (3). dissolution observed at short set pulse widths in some
The model in equations (1)–(3) allows the dynamic I–V experiments [73].
characteristic to be calculated as follows: for any applied The controllability of R and Ireset by IC generally applies
voltage at a given time iteration ti, equation (1) allows the CF to all types of RRAM devices. Figure 9 shows the measured
diameter from the previous time step ti−1 to be updated. The and calculated R (a) and Ireset (b) in oxide RRAM for various
new value of f can then be used to calculate the new device materials, including HfOx [37, 46, 60], TiOx [76], and HfOx/
resistance according to [73]: ZrOx stacks [77]. The results for unipolar RRAM based on
4rtox NiO are also reported for comparison, indicating behavior
R= (4 ) similar to bipolar RRAM. All data satisfies the expected
pf 2
relationship of voltage-controlled switching with an
where ρ is the CF resistivity and tox is the oxide thickness, approximately constant VC and Vreset around 0.5 V. Notably,
which can be assumed equal to the CF length. Based on the the data for all reported materials displays approximately the
voltage and the calculated resistance, the current can then be same behavior, suggesting the universal nature of voltage-
evaluated, which allows us to calculate the I–V characteristic controlled switching in metal oxides [56, 78]. The calculated
or to simulate the behavior of the RRAM in a given circuit, results by the model of equations (1)–(3) are also shown in
e.g., a 1T1R structure [73] or a logic gate with multiple figure 9 for increasing values of the energy barrier EA0. The
interacting RRAM [17]. calculated results change almost negligibly as EA0 is varied.
Note that the switching kinetics in equations (1)–(3) are This can explain the universal switching behavior of different
completely dictated by the voltage, which controls both the metal oxides: even if the barrier and other microscopic

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 8. I–V characteristics as a function of IC. Measured and calculated I–V curves (a) show a decreasing LRS resistance (b) and an
increasing Ireset for increasing IC (c), thus supporting the picture of a variable CF effective size f controlled by IC during the set transition.
LRS resistance and Ireset span several orders of magnitude as IC is varied. Note that Ireset is generally smaller than IC (d), which can be
explained by the mechanical stress opposing the set transition and assisting the reset transition. Reprinted with permission from [73].
Copyright (2014) John Wiley & Sons, Inc.

Note in figure 9(b) that Ireset is roughly equal to I C, on

average, which reflects Vreset = V C, or symmetric set/reset
processes in oxide-based RRAM. This contrasts with the
asymmetric switching in CBRAM in figure 8. The dif-
ferent set/reset relationships can be attributed to the lack
of stress effects in oxide RRAM, which might be
explained by the combination of anion and cation migra-
tion where cations (e.g., Hf in HfO2) and anions (oxygen)
redistribute along the CF to minimize mechanical stres-
ses [73].
The analytical model in figures 7–9 was extended to take
into account different CF evolutions during set and reset [79]
and applied to simulate small RRAM circuits for com-
plementary resistance switching [79], logic computing [17]
and synaptic networks [22]. Variability models were also
developed to predict the statistical fluctuation of HRS and
LRS by introducing a Monte Carlo variation of EA0 for the
migration of each individual defect [79]. Alternative approa-
ches to RRAM analytical modeling were also reported,
including variable-gap switching [80], a mixed variable gap/
radius [81], and quantum point conductance [82, 83]. Ana-
lytical models therefore seem effective for accurate simula-
tions of RRAM circuits with relatively low computation
complexity.
Figure 9. The universal characteristics of R and Ireset for various Despite their general accuracy, analytical models rarely
RRAM materials. The measured and calculated LRS resistance (a) and capture the microscopic details of the switching process,
Ireset (b) as a function of IC indicate that IC controls the CF size and
useful for predicting scaling and reliability effects. To this
resistance with VC ≈ 0.5 V, as well as a negligible dependence on the
switching mode (unipolar, bipolar) and stack composition or structure. end, numerical models based on different approaches have
Copyright (2011) IEEE. Reprinted, with permission, from [56]. been developed, such as kinetic Monte Carlo (KMC) [84, 85]
or numerical solutions of the drift-diffusion differential
parameters change from material to material, the sensitivity of equations [57, 86, 87]. Figure 10 shows an example of the 2D
the characteristic voltage is very small, thus resulting in KMC simulation results of the reset and set [84]. In the
similar switching behavior. model, the conduction is described by a percolation-like trap-

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 10. KMC modeling of resistance switching. The model can reproduce the reset transition at variable Vstop (a), where Vstop controls the
extension of the depleted gap (b), (c), and the set transition at variable compliance current IC (d), where IC controls the number of CFs
providing the percolation path between the two electrodes (e), (f). Copyright (2012) IEEE. Reprinted, with permission, from [84].

assisted tunneling through the defects, which are generated or

recombined according to suitable probabilities depending on
the local electric field. Figure 10(a) shows the calculated I–V
curves during reset, while figures 10(b) and (c) show the
defect maps for Vstop = −2.5 V and −3 V, respectively.
Increasing Vstop results in a longer gap region, and hence in a
larger resistance in the HRS. Reset transition results in the
formation of a depleted gap region, thus disconnecting the
conduction path. Figure 10(d) shows the calculated I–V
curves during the set, while figures 10(e) and (f) show the
defect map for IC = 100 μA and 200 μA. Increasing the
compliance current results in more defects being generated in
the insulating layer, thus causing the presence of more parallel
CFs [84]. The results in figure 10 support the capability of
KMC models for calculating I–V characteristics and the Figure 11. Measured and calculated I–V characteristics during the
associated fluctuations [88]. reset transition. The numerical model can reproduce the gradual reset
transition at variable LRS resistance by solving the drift/diffusion
An alternative approach is the microscopic description of equations for ionic transport in the CF. Copyright (2012) IEEE.
resistance switching via the solution of differential equations, Reprinted, with permission, from [57].
similar to the thermoelectric models of phase change memory
[89]. Differential equations typically include continuity
equations for charge carriers, namely the Poisson equation, fixed charge by assuming zero charge density. The heat
heat transport, namely the Fourier equation, and ionized transfer is governed by the Fourier equation given by:
defects based on a drift/diffusion model [57, 86, 87]. The
Poisson equation is given by: -k th T = | s Y |2 (6 )

s Y = 0 (5 ) where kth is the thermal conductivity. The right-hand side in

equation (6) represents the local dissipated power density
where σ = 1/ρ is the electrical conductivity and Ψ is the local given by the product of the field by the current density, while
electrostatic potential, linked to the electric field F by the the left-hand side is the corresponding space variation of the
relationship ∇Ψ = −F. In equation (5), we also neglected any heat flow due to thermal conduction. Note that the time

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 12. Numerical modeling of the reset transition in oxide ReRAM. As the voltage increases from A to D in figure 11, the depleted gap
increases its size by the migration of defects toward the BE side (a). Migration is assisted by local Joule heating due to the power dissipation
during reset (b). Copyright (2012) IEEE. Reprinted, with permission, from [57].

Figure 13. Numerical modeling of the reset transition in oxide ReRAM. The contour plot of the defect concentration during reset transition
indicates an increasing length of the depleted gap for both large (a) and small CFs (b). Copyright (2012) IEEE. Reprinted, with permission,
from [57].

dependence was neglected in the steady-state Fourier CF. In fact, it was shown that the thermal time constant for
equation in equation (6), since the typical timing of the set/ the CF, namely the product of thermal resistance Rth and
reset experiments are generally far slower than the typical thermal capacitance Cth, is around 30 ps, and thus much faster
thermal time constant of the RRAM active region, namely the than the electric pulse-width [56]. The thermal capacitance

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

with numerical model solving equations (5)–(7) in a 3D

RRAM device with cylindrical symmetry. An activation
energy EA = 1 eV was assumed for ion diffusivity and
mobility in the simulations, consistent with the measured
activation energy for oxygen self-diffusion in HfO2 [93].
Initially, a CF with a cylindrical shape was assumed with a
diameter of f = 9 nm and 14 nm for R = 1 kΩ and 0.4 kΩ,
respectively. Calculations can reproduce the shape of the I–V
characteristics, namely the gradual resistance increase starting
from a characteristic reset voltage.
Figure 14. Numerical modeling of the reset transition in oxide To gain more insight into the physical mechanism
ReRAM. The data (a) and calculations (b) indicate that the HRS
resistance increases as Vstop increases, and that the corresponding set underneath the reset transition, figure 12 shows the profile of
voltage Vset also increases due to the greater length of the depleted calculated defect concentration nD (a) and of the calculated
gap. Copyright (2012) IEEE. Reprinted, with permission, from [57]. temperature (b) at increasing bias points in figure 11, namely
in correspondence with the reset voltage (A) and at an
increasing voltage along the reset transition (B, C and D) for
can in fact be estimated by Cth = CptoxA, where Cp is the heat
f = 14 nm. At Vreset, the temperature shows a parabolic
capacity of the CF material and A is the effective area of the
profile with a maximum value around 500 K, which triggers
CF, which is assumed to be of length tox. By estimating the
thermal resistance as Rth » tox k th-1A-1 , we can evaluate the ion migration in the direction of the field, namely towards the
thermal time as Cp tox 2 k th, which yields a value of 33 ps negatively biased BE. As a result of migration, the regions
assuming a filament made of Hf (Cp = 1.92 JK−1 cm−3, above the middle of the CF remain depleted of defects, while
kth = 23 Wm−1 K−1) with length tox = 20 nm [56]. Finally, the region below the middle point of the CF shows the
defect migration is controlled by the continuity equation for accumulation of defects. As the voltage increases above Vreset,
the drift/diffusion ionic current which is given by: the depleted gap length increases, which explains the increase
of resistance in the I–V characteristic of figure 11. The local
¶nD temperature in figure 12(b) changes profile as the depleted
=  (D nD - mFnD) (7 )
¶t gap extends, since the voltage drop and consequently power
dissipation occur primarily in the high-resistivity gap. As a
where nD is the defect concentration, D is the ionic result, the remaining regions of the CF above and below the
diffusivity, and μ is the ionic mobility. Diffusivity and depleted gap remain at a relatively low temperature and
mobility depend on the temperature by the Arrhenius law, as electric field, which decrease the migration rate of ionized
is usual for ion transport in oxides [90–92]. Diffusivity and defects. Therefore, the voltage must be increased to sustain
mobility were assumed to be linked by the Einstein equation. more defect migration and the corresponding resistance
Finally, the electric conductivity σ and thermal conductivity increase, which is the reason for the gradual reset transition in
kth were assumed to depend on the local concentration of the I–V curves of figure 11 [57].
defects nD. In fact, since defects act as dopants in metal Figure 13 shows the contour plot of the defect con-
oxides, a large nD leads to a high electrical/thermal centration nD at points A, B, C and D in figure 11. The
conductivity. In contrast, a low nD, e.g., in the depleted contour plot is shown for both CF diameters, namely
gap, causes low electrical/thermal conductivity. The coupled f = 14 nm (a) and 9 nm (b), corresponding to R = 0.4 kΩ and
equations (5)–(7) were then solved in 3D axisymmetric 1 kΩ, respectively, in figure 11. The figure indicates the
geometry: solving equations (5) and (6) yields the space similar evolution of the depleted gap at increasing voltage,
profile of T and F allowing equation (7) to be solved, which in irrespective of the initial diameter of the CF. This can be
turn allows us to update the local profile of defect understood by the independence of the local field and temp-
concentration nD entering σ and kth in equations (5) and (6). erature on the lateral CF size, as also confirmed by the fact
Figure 11 shows the measured and calculated I–V char- that Vreset is usually constant as a function of the compliance
acteristics for the reset transition in an oxide RRAM initially current IC and the oxide material composition [37, 78]. The
prepared in the LRS with two different resistances R = 1 kΩ contour plot in figure 13 also allows the drift/diffusion
and 0.4 kΩ [57]. Note that reset transition occurs under a dynamics of the CF shape evolution at increasing voltage to
positive voltage, as a result of the specific structure and be highlighted. While the CF depletion is primarily driven by
forming operation of the device [46]. However, the physical the directional drift of ionized defects along the electric field
mechanism and CF evolution described here hold irrespective direction, diffusion effects can be seen as a fattening of the
of the set/reset voltage polarities. The data in figure 11 CF at increasing voltage.
indicates that the current increases linearly with voltage below Evidence for the increasing length of the depleted gap at
about Vreset = 0.4 V, which marks the onset of the reset increasing voltage can be directly gained by electrical
transition. Above Vreset, the resistance starts to increase, which characterization of the RRAM device after the reset.
results in a decrease of current, except for a very large voltage Figure 14 shows the I–V curves during the reset (positive
(V > 0.8 V) where the current starts to increase again due to voltage) and the subsequent set (negative voltage) obtained
saturation of the resistance. The calculations were carried out by measurements (a) and numerical simulations (b) [57]. In

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 15. Gap dependence of set voltage Vset and electric field F in the CF. The simplified voltage-divider model (a) allows us to estimate
Vset and F, showing that the electric field F at a given voltage V = 0.4 V decreases with the gap length Δ, resulting in an increase of Vset.

the figures, the reset sweep ended at a characteristic Vstop, Figure 15(b) shows the calculated F in the CF for a
which was increased between 0.5 V and 1 V. Each color voltage V = 0.4 V, and the calculated Vset as a function of the
corresponds to different values of Vstop giving different I–V ratio Δ/tox, assuming tox = 10 nm, ρgap/ρCF = 50 and
curves. As Vstop increases, both the HRS resistance and Vset FC = 25 mV nm−1. The results of the voltage-divider model
at the onset of the set transition in the negative sweep indicate that F decreases with Δ, while Vset increases due to
increase, as can be seen in both the experimental data the increasing voltage drop across the depleted gap. Note that
(figure 14(a)) and the simulations (figure 14(b)). Similar to as ionized defects start to migrate at Vset, the gap length
the HRS resistance, the increase of Vset can be explained by decreases, thus increasing the electric field in the CF and
the increase of the depleted gap length. Most of the applied further enhancing the migration rate. This self-accelerated
voltage drops across the depleted gap during the positive process explains the steep current increase at the set trans-
voltage sweep, therefore a larger voltage is needed to sustain ition, in contrast to the smooth resistance change during the
the necessary electric field at the positively-biased CF tip to self-limiting reset transition. The self-accelerating set trans-
induce ionic migration [57]. To evaluate the voltage at the ition can be counterbalanced by an external limiting system,
set transition, we consider the simplified voltage-divider such as the current compliance provided by an external select
model in figure 15(a), where the RRAM resistance in the transistor [94, 95]. Alternatively, a self-compliance solution
HRS is given by the series of a CF resistance RCF and a gap can be provided by an inherent series resistance within the
resistance Rgap. The gap resistance can be written as RRAM stack, such as a relatively thick layer of oxide with
Rgap = ρgapΔ/A, where ρgap is the gap resistivity, Δ is the relatively high conductance adjacent to the switching oxide
gap length and A is the equivalent cross section area of the layer [96, 97]. The numerical model was also shown to pro-
gap region, approximately equal to the CF area. Similarly, vide an accurate prediction of the set/reset kinetics, e.g., set/
the CF resistance is approximated by RCF = ρCF (tox − Δ)/ reset voltage as a function of the sweep rate in triangular
A, where ρCF is the CF resistivity and tox is the oxide pulses, or the set/reset time at a variable programming
thickness. From the model in figure 15(a), the electric field time [57].
in the CF at a given applied voltage V across the RRAM can
be obtained as:
4. Device reliability
Vr CF V
F= = , (8 )
r CF (tox - D) + rgap D ⎛ rgap ⎞ Reliability is among the strongest concerns for RRAM
tox + ⎜ - 1⎟ D
⎝ r CF ⎠ devices since the repeated migration of atoms under a high
local field (above 1 MV cm−1), high current density (several
which decreases for an increasing Δ, thus causing Vset to MA cm−2), high power dissipation (several TW cm–3) and
increase with Δ. Assuming that the set transition occurs in high temperature (above 1000 °C) [57] can cause significant
correspondence with a critical value Fc of the electric field in degradation of the electrodes and the active material. Cycling
the CF, the set voltage can be estimated as: endurance [98–102] is one of the highest priorities of RRAM,
especially for storage-class memory applications, where the
⎛ ⎛ rgap ⎞⎞
Vset = FC ⎜⎜t ox + D ⎜ - 1⎟ ⎟⎟ . (9 ) memory might be frequently accessed by the central proces-
⎝ ⎝ r CF ⎠⎠ sing unit (CPU) for in-memory computing purposes.
Figure 16(a) shows the measured resistance of HRS and LRS

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

as a function of the number of cycles NC in HfO2 RRAM rapid closure of the resistance window to a value in between
[74]. Triangular set/reset pulses with pulse-width tP = 1 μs the HRS and LRS levels [74].
were applied repeatedly with a limitation of the current Monitoring the I–V curves for each set/reset cycle allows
IC = 50 μA obtained by an integrated transistor. HRS and us to capture the failure event, as illustrated in figure 17,
LRS resistances remain stable, until a failure event takes place which shows the measured I–V curves for a typical cycle
around 1.7 × 105 cycles. Figure 16(b) shows a close-up of the before failure (a), for the failure event (b) and for a typical
resistance evolution close to the failure event, indicating a cycle after failure (c), corresponding to the cycle positions
marked in figure 16(b) [74]. The typical cycle in figure 17(a)
shows the normal set and reset transitions, where the reset
current Ireset is approximately equal to IC. The failure event in
figure 17(b) shows an anomalous reset transition called a
negative set, providing evidence of a steep current increase
after the reset transition. The negative set event can be
understood comparing the CF structures after the normal reset
and after the negative set, which are illustrated in
figures 17(d) and (e), respectively. While the normal reset
transition results in the migration of defects toward the TE
(d), the negative set is believed to take place because of defect
generation and injection from the BE, which is positively
biased during reset [74]. The negative set is thus similar to a
forming operation under negative polarity, enhanced by the
large local field in the gap region close to the BE and by the
high local temperature. Since the current was not subject to
any limitation during the reset half-cycle, defect injection
occurs catastrophically, resulting in a large CF and conse-
quently a low resistance, even in the HRS (figure 17(e)). The
HRS leakage exceeds IC, thus inhibiting set transition during
the positive half-cycle, which explains the resistance window
collapse after negative set.
Figure 18 shows the cycling endurance, namely the
number of set/reset cycles at failure, as a function of the
maximum voltage Vstop during the negative pulse. The data is
reported for tP = 1 μs and various compliance currents
IC = 10 μA, 20 μA and 50 μA. For |Vstop| > 1.6 V, the
endurance lifetime exponentially decreases with Vstop, which
can be understood by the increasing electric field and temp-
Figure 16. The cycling evolution of resistance and endurance failure.
erature in the gap region which are at the origin of the
Endurance failure is due to a collapse of the resistance window to an
intermediate value between LRS and HRS (a), which is triggered by negative set event. On the other hand, the endurance steeply
a negative set event (b). Copyright (2015) IEEE. Reprinted, with drops to zero as |Vstop| decreases below 1.6 V due to the
permission, from [74]. negative voltage not being sufficient to properly reset the

Figure 17. Endurance failure mechanism. The pulsed I-V characteristics reveal normal behavior before the negative set (a), while the negative
set consists of an anomalous transition to low resistance under a negative voltage (b), followed by a negligible hysteresis and lack of set/reset
transitions after the negative set (c). This can be explained by the uncontrolled injection of defects from the BE at the negative set: while the
normal reset transition leads to an HRS with a relatively small CF (d), the large CF size after the negative set causes the HRS to be extremely
leaky (e), thus preventing the set transition from occurring as a result of the insufficient voltage drop at IC = 50 μA across the RRAM
element. Copyright (2015) IEEE. Reprinted, with permission, from [74].

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

device, thus resulting in a collapse of resistance to the LRS temperature, which is mandatory for meeting specifications
level (stuck set). No dependence on compliance current is for embedded memory and/or automotive applications.
seen in figure 18: in fact IC controls the CF size, although all Figure 19(a) shows the measured LRS resistance for HfO2
parameters potentially affecting degradation (electric field, RRAM devices at various annealing temperatures: starting
current density, power density, local temperature due to Joule from about 4 kΩ, the resistance increases with time, even-
heating) remain constant irrespective of the CF size. These tually reaching a large value above 1 MΩ, corresponding to
results are qualitatively similar to other results suggesting the HRS. The unstable LRS can be understood by the oxidation
dominant role of the negative applied voltage in controlling and diffusion of defects within the CF, which results in the
endurance lifetime [101]. These results suggest the key rele- disconnection of the connecting path and a corresponding
vance of the BE in preventing a negative set, thus improving increase of R [104]. CF rupture is strongly accelerated by
cycling endurance, which accounts for the large cycling temperature, as confirmed by the measured retention time as a
endurance achieved in TaOx devices with inert metals such as function of 1/kT in figure 19(b). From the Arrhenius plot, the
Pt [24, 96]. activation energies for data retention can be extracted and
For nonvolatile memory applications, RRAM must also compared among the different oxide compositions, e.g.,
exhibit data retention at both room temperature and elevated stoichiometric HfO2 and Al-doped HfO2 in figure 19(b). The
activation energies are generally in the range between 1 eV
and 2 eV, and thus in qualitative agreement with the values
used for modeling the ion migration during set and reset
transitions [103–105]. To further support the link between
activation energies controlling data retention and set/reset
transitions, voltage-dependent experiments have recently
shown that the activation energies of retention are also
decreased by the application of a voltage bias during
annealing [106]. Based on this evidence, data retention
assessment can be accelerated by both temperature and volt-
age, which might significantly speed up the testing and qua-
lification of RRAM devices. Data retention was also observed
to strongly depend on the size of the CF, namely a large CF
with relatively low LRS resistance is more stable than a small
CF with relatively high LRS resistance [104, 107], which can
be explained in terms of the different concentration gradient
controlling the out-diffusion of defects from the confined
Figure 18. Voltage dependence of RRAM endurance. As Vstop
increases, the endurance, namely the number of set/reset cycles at CF [108].
failure, decreases exponentially, thus providing evidence of the The study of the retention statistics within RRAM arrays
essential role of Vstop in controlling the probability of a negative set. allows a deeper insight into the mechanisms of resistance
For low Vstop, the device operation is limited by the occurrence of the change under various conditions, such as temperature and
stuck set, due to the insufficient voltage for reset transition. set/reset operations. Figure 20 shows the cumulative dis-
Endurance is independent of IC, suggesting that negative set
probability depends solely on the local field, temperature and current tributions of resistance for LRS (a) and HRS (b) at an
density, which are not affected by IC. Copyright (2015) IEEE. increasing time after programming [109]. Variable annealing
Reprinted, with permission, from [74]. conditions were applied as follows: after a first period at room

Figure 19. LRS retention analysis. LRS resistance increases with time indicating a gradual dissolution of the CF (a). As the ambient
temperature is increased, the CF dissolution is accelerated at a shorter retention time. The Arrhenius plot of the retention time indicates
temperature-accelerated retention with an activation energy of about 1.5 eV, consistent with the energy barrier for defect migration in metal
oxides. Copyright (2015) IEEE. Reprinted, with permission, from [103].

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 20. Statistical study of retention for LRS and HRS. Both LRS (a) and HRS distributions (b) indicate broadening with time. Even if the
value of HRS resistance is forced above 105 Ω, the distribution soon extends to lower resistance values due to noise. Copyright (2015) IEEE.
Reprinted, with permission, from [109].

Figure 21. Statistics of HRS distribution with time. The distribution of normalized resistance R(t)/R0—where R0 is the initial value at the
reference time t = 700 s, shows broadening with time over more than two decades (a). A detailed study of individual cells reveals random
variations resulting in a resistance decrease (A), lack of substantial variation (B), or increase (C), as a result of random walk (RW) events or
RTN. Copyright (2015) IEEE. Reprinted, with permission, from [43].

temperature (25 °C), the temperature was increased to flash memories [110]), would immediately be lost as a result
T = 125 °C at time t = 1200 s after programming, then it was of the intrinsic broadening in figure 20 for both LRS
decreased again to 25 °C at 106 s. The final value of R was and HRS.
measured at both 125 °C and 25 °C. While LRS shows a By monitoring individual cell behavior during the time
marked drift towards high R, the median value of the HRS after the reset, the origin of the HRS distribution broadening
remains almost constant with time, which confirms the better in figure 20(b) can be attributed to the statistical fluctuation
stability of the HRS with time. However, both HRS and LRS of the read current [111]. Figure 21(a) shows the cumulative
distributions in figure 20 show a broadening with time, which distribution of the normalized resistance for HRS, namely
results in distribution tails extending to low R for HRS. The the resistance R divided by the resistance R0 measured at the
distribution broadening is relatively fast, occurring in the time first read operation 700 s after the reset [43]. The resistance
range of below 1 min at room temperature in figure 20(b). The was measured at an increasing time at room temperature.
fast distribution broadening and consequent closure of the The normalized distribution indicates significant broad-
resistance window highlights the relevance of room-temper- ening, which is almost symmetric with respect to R/R0 = 1
ature data retention in large RRAM arrays. Note that this and includes both tails of increasing R and tails of
problem makes program/verify algorithms ineffective, decreasing R. Figure 21(b) reports the individual evolution
because accurate positioning of the cell resistance (e.g., by of R for three selected cells, namely a cell in the low R/R0
incremental step-pulse programming (ISPP) similar to NAND tail (A), a cell in correspondence of R/R0 = 1 (B), and a cell

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 22. Simulation of the RTN by bistable defect fluctuation in LRS. Electrostatic simulation of the CF (a) allows the electron carrier
density to be computed in the presence of a negatively charged defect at the surface of the CF (b), (c). Coulombic repulsion results in partial
depletion for a large CF size (b), and full depletion for a small CF size (c), leading to a small and large relative RTN amplitude ΔR/R,
respectively. Copyright (2014) IEEE. Reprinted, with permission, from [41].

in the high R/R0 tail (C) of the final distribution measured at

t = 7 × 105 s. All cells show the noisy evolution of R,
including both isolated steps, called random walk (RW)
events, and alternate fluctuations between two resistance
levels, which can be attributed to random telegraph noise
(RTN). A detailed study of RW time tRW showed that RW
events are more frequent immediately after reset, then gra-
dually decrease in time. The random RW amplitude accounts
for the symmetric broadening of the HRS distribution in
figure 21(a), in that steps to larger R and steps to smaller R
have equal probability. The time decay of RW events was
attributed to a relaxation of the oxide structure along the
conductive path affected by the reset event [43]. A model for
resistance broadening was developed on the basis of the
observed amplitude distribution of RW and RTN events and
Figure 23. Measured and calculated relative amplitude of RTN as a
of a physical description of the defect relaxation in the function of LRS resistance. The relative amplitude of RTN increases
conductive path [43]. The model allows the prediction of with resistance due to the transition from partial depletion (ΔR/R ∝
noise-induced broadening of HRS distributions for retention R at low R) to full depletion (saturated ΔR/R ≈ 1 at large R). The
assessment in large RRAM arrays. Simulation results in data indicates the negligible impact of the RRAM switching mode
figure 21(a) demonstrate the accuracy of the model. (unipolar, bipolar), device structure (oxide RRAM, CBRAM) and
stack material, thus providing evidence of the universal noise
Although RTN is most relevant for HRS, it can also characteristic of RRAM. Copyright (2014) IEEE. Reprinted, with
affect LRS. LRS noise is attributed to the bistable fluctuation permission, from [41].
of a defect close to the surface of the CF: as the defects
randomly switch between a neutral and charged state, the
carriers in correspondence with the negative defect. The CF
carrier density and current within the CF are affected since,
becomes fully depleted at the charged defect as a diameter
e.g., a negatively charged defect would induce local electron
f = 1 nm is assumed in figure 22(c). As a result, the RTN
depletion from the CF, whereas a neutral defect would play
almost no role [38, 41]. This is schematically shown in amplitude is strongly enhanced by reducing the size of the
figure 22(a), illustrating a CF with simplified cylindrical CF [38, 41].
geometry, which is locally depleted by a surface electron trap This is reported in figure 23, showing the measured and
fluctuating between a neutral and a negatively charged state. calculated relative amplitude of RTN as a function of LRS
To better evaluate the impact of the surface defect charge on resistance for an RRAM device with various materials [41].
RRAM resistance, a numerical model was developed to solve The relative amplitude is defined as ΔR/R, where ΔR is the
the Poisson equations for the electrostatic potential, the difference between the high and low resistance levels in the
Fourier equation for local Joule heating and the drift-diffusion RTN fluctuation. RRAM materials include HfO2 [41], NiO
equations for carrier conduction within the CF [41]. [38], and Cu-based CBRAM [112]. The data for Cu nano-
Figure 22(b) shows the calculated carrier density in a CF with bridges is also shown to support the universality of RTN
diameter f = 10 nm, indicating the partial depletion of problems for all 1D conduction problems [113]. The relative

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 24. Switching variability in HfO2 RRAM. All switching parameters, e.g., LRS/HRS resistance, Vset and Vreset, indicate stochastic
variations from cycle to cycle. The relative variation is larger for a small CF size (low IC, (a)) than for large CF (high IC, (b)), as a result of
size-dependent variability phenomena. Copyright (2014) IEEE. Reprinted, with permission, from [37].

amplitude in the figure increases linearly with R until satur-

ation for a value of R around 100 kΩ. The linear increase of
ΔR/R can be understood by the increasing impact of the
depleted volume on the overall carrier conduction in the CF.
As the depleted area extends over the whole CF cross section,
the relative amplitude remains constant at a value close to 1.
Calculations of the relative amplitude at variable doping in
the semiconductor CF confirms that the interpretation relies
on the partial/full depletion of carriers. Note that this concept
is similar to the behavior of RTN taking place in metal-oxide-
semiconductor (MOS) transistors, where localized bistable
defects in the gate dielectric can stimulate fluctuations of
carrier concentration in the inverted channel [114]. This
microscopic picture was further confirmed by voltage-
dependent and temperature-dependent studies, indicating
thermally-activated RTN kinetics as a result of the Arrhenius-
driven fluctuation of bistable defects [41].
Due to the intimate relationship between programming
and conduction processes, RRAM is strongly affected by
switching variability. Conventional MOS-based devices, such
as flash memories, usually display repeatable program/erase
characteristics, since the program only modifies the charge
stored in the floating gate without generally affecting the
structure of the device. On the other hand, the CF in RRAM
devices is systematically reconnected at every set operation Figure 25. The cycling variability of switching parameters in HfO2
and disconnected at every reset operation, thus resulting in the RRAM devices. The measured and calculated variability of LRS
different number and position of defects in the CF and in the resistance (a), Ireset (b), and Vreset (c) show decreasing behavior at an
depleted gap. The stochastic nature of the CF structure and increasing IC, as a result of the larger number of defects in the CF
causing more averaging, hence fewer statistical variations. Copyright
conduction thus leads to variations in all read and switching (2014) IEEE. Reprinted, with permission, from [37].
parameters of the RRAM device. Figure 24 shows the mea-
sured I–V characteristics during the set and reset for a HfO2
RRAM device. All I–V curves were collected in the same consequently increasing variation in the defect number [35]
device repeatedly to highlight the cycle-by-cycle variations of and defect position [37] in the CF for both HRS and LRS.
all device parameters, including Vset, Vreset, Ireset and the Figure 25 shows the measured and calculated variation of
resistance of LRS and HRS. The figure compares the results LRS resistance (a), reset current Ireset (b) and reset voltage
for two values of the compliance current, namely IC = 8 μA Vreset (c) as a function of IC [37]. Variability of LRS resistance
(a) and IC = 80 μA (b), which were imposed via an integrated and Ireset is shown as the ratio between the standard deviation
transistor. The voltage drop across the transistor was sub- σ and the average value μ. In all cases, the statistical varia-
tracted from the reported curves. Note that parameter varia- tions increase for a decreasing IC, hence for a decreasing CF
tions increase significantly at a decreasing IC: this can be size. The statistical variations can be attributed to the size
understood by the decreasing size of the CF and by the fluctuation of the CF, which controls LRS resistance and Ireset.

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 26. Geometrical variation model for LRS resistance statistics. The variation of LRS resistance values can be estimated by assuming a
variable truncated-cone geometry of the CF with a variable angle θ (a). Considering a minimum CF resistance for a cylindrical geometry
(θ = 0, b), calculations indicate that the relative standard deviation σR/R increases linearly with R, in agreement with the experimental results
(c). The slope 0.5 for HRS indicates the dominance of defect number variation in resistance states characterized by the presence of a
depleted gap.

The spread of Vreset is instead due to local variations in the and θ is the angle defining the inclination of the lateral cone
energy barrier for ion migration. As the CF becomes smaller, surface (see figure 26(a)). A cone-shaped CF was previously
there are increasing variations within the local energy profile proposed in a unipolar switching RRAM [116]. Note that L
for defect migration, thus causing the larger spread of Vreset. might generally be smaller than the whole oxide thickness,
The size dependence of switching variability in figure 25 is e.g., it might correspond to a smaller portion (the depleted
reproduced by calculations using a Monte Carlo model for gap) where the cross section for conduction is effectively
discrete defect injection [37]. The model relies on the ana- controlled by IC. Equation (10) becomes the same as
lytical approach in equations (1)–(3), although filament equation (4) for L = tox and θ = 0, corresponding to a
growth and dissolution is fragmented over individual defect cylindrical CF in figure 26(b). The resistance variation can
contributions, each with a specific energy barrier EA. The thus be estimated as the difference between the resistance of
energy barrier was assumed to randomly vary within a uni- the cone-shaped CF (figure 26(a), equation (10)) and the
form distribution between 0.7 eV and 1.7 eV. A broad dis- minimum resistance of the cylinder-shaped CF (figure 26(b),
tribution of energy barrier was recently confirmed by ab initio equation (4)), namely:
calculations and attributed to the random network in the ⎛ ⎞
amorphous structure of HfOx [115]. ⎜ ⎟
Although the discrete-defect injection model captures the 4rL ⎜ 1 ⎟ ⎛ Lq ⎞2
sR = ⎜ - 1 ⎟ » R ⎜ ⎟ , (11)
qualitative dependence on IC, a different slope for the data pf 2 ⎜ ⎛ Lq ⎞2 ⎟ ⎝f⎠
and calculations might be noticed in figure 25. For instance, ⎜1 - ⎜ ⎟ ⎟
⎝ ⎝f⎠ ⎠
the calculated spread of resistance σR normalized by the
average resistance μR shows a slope of −0.5 on the log–log where the approximation holds for q  2f L, i.e., small
plot in figure 25(a), while the data displays a slope around cone angles. Substituting f2 = 4ρL/(πR) in equation (11), we
−1. Note that the slope of −0.5 can be explained by the obtain:
Poisson statistics of the number of defects belonging to the
CF, namely σR/R ∝ N−1/2 ∝ IC-1/2 [35]. The higher slope in sR pLq 2
the figure can instead be explained by a simplified model for » R, (12)
R 4r
the geometrical variation of the CF in the LRS. In this model,
illustrated in figure 26, the resistance variation is not due to a
variation in the number of defects, but rather to a slight which provides evidence of the linear increase of σR/R with
variation in the position of the defects affecting the shape of R, hence σR/R ∝ IC-1 as in figure 25. Figure 26(c) shows the
the CF, hence its resistance. The impact of geometrical fluc- measured σR/R as a function of R, for both LRS and HRS
tuations on CF resistance can be estimated by assuming the indicating slopes of 1 and 0.5, respectively. The figure also
simplified truncated-conical geometry of the CF in displays calculations by equation (12) which can nicely
figure 26(a), for which the resistance is given by: reproduce the LRS data assuming L = 3 nm, ρ = 400 μΩcm
[56], and θ = 0.1, corresponding to about 6°. The change of
4rL 4rL slope in the HRS regime at high resistance suggests the
R= = , (10)
pf1f2 p (f + Lq )(f - Lq ) transition from a continuous CF, where variability is driven
by geometrical shape variation, to a depleted CF, where
where L is the effective length of the CF, f1 is the minimum variability is dominated by the number fluctuation controlled
diameter of the truncated cone, f2 is the maximum diameter by Poisson statistics [35].

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

storage and storage-class memory. In fact, these types of

applications might take full advantage of the excellent device
size, scalability and fast program/read operations in RRAM.
To pursue high-density RRAM, memory architecture is a key
aspect: for instance, a cell size of 6F2 can be achieved by using
1T1R architecture with a minimum transistor size which has a
buried recessed select transistor (BRAD) structure [27]. A
smaller cell size of 4F2 can be obtained in crossbar archi-
tectures with back-end select devices [28].
Device scaling is the top requirement for any memory
technology and should provide continued growth of density
for several generations in the industrial roadmap. RRAM has
been identified as an optimal device from the viewpoint of
scaling, thanks to the filamentary concept of conduction and
switching. In fact, the active device area is defined by the CF,
which can be as small as few nm, or even a few atomic units.
Figure 27 schematically shows an atomic-scale RRAM in
Figure 27. The ultimate scaling of RRAM devices. A minimum LRS (on-state) and HRS (off-state) [123]. According to this
thickness of two atomic diameters, i.e., 2δ, is expected for RRAM, proposal, the ultimate size of the CF is just two atomic
where a 2-atom CF can be arranged in a set (on) state or reset state
(off). The memory cell is postulated to have a lateral size of defects, such as two oxygen vacancies or two Cu atoms
10δ = 2.6 nm. Reprinted with permission from [123]. connecting the top and bottom electrodes. As a result, the
thickness of the switching layer is just two atomic units, or 2δ,
while the width of the active area is around 10δ to allow for
The CF size dependence of data retention [104, 107], lateral displacement of the two defects from the CF. Based on
noise (figure 23) and variability (figure 25) raises a potential this picture, the ultimate device size is therefore around
concern for RRAM. In fact, the limitation of the CF size 10δ = 2.6 nm [123].
enables the reduction of the set/reset currents, which is The extreme scaling of RRAM was confirmed by fabri-
mandatory for operating large crossbar arrays to avoid
cating a device with an electrode size in the range of 2–3 nm,
excessive voltage drop across the high-resistance wordlines
as shown in figure 28 [124]. Due to the difficulty of achieving
and bitlines [117]. This trade-off between reliability and low-
such a small feature size with conventional or electron-beam
current operation can be partially solved by adopting RRAM lithography, the device was fabricated by first forming a Cu
devices with relatively large resistance windows, to improve CF in a sacrificial CBRAM, where the insulating layer and Cu
the read margin against noise and variability. From this TE were etched to use the remaining Cu CF as a BE. This
standpoint, CBRAM devices relying on the migration of Ag method allows the deep sub-lithographic feature size for
and Cu typically show a window of at least three orders of demonstrating extreme RRAM device scaling to be achieved.
magnitude, thanks to a deep HRS level [66, 118]. On the
Figure 28 shows the final device structure (a) and the con-
other hand, oxide-based RRAMs are typically limited to a
ductive atomic force microscopy (CAFM) results (b) indi-
window of roughly one order of magnitude, as a result of the
cating a BE size in the range of 2 to 3 nm. The device can be
relatively small depleted gap formed at the reset. These results operated by bipolar switching set and reset processes, exhi-
suggest that material engineering to improve the resistance biting a large window and the ability to operate under com-
window may play an important role in allowing the devel- plementary switching conditions [125]. RRAM devices
opment of scalable RRAM. developed by electron-beam lithography with a size in the
10 nm range also displayed functional bipolar switching
characteristics [61], supporting the good performance of
5. Scaling RRAM in device size downscaling.
To compete with NAND flash in high-density data sto-
Table 1 shows a summary of the recent RRAM prototypes rage, RRAM must display multilevel cell (MLC) operation
reported in the literature [27–31, 119–122]. RRAM prototypes capabilities and 3D vertical architecture, which are now state-
have generally been fabricated with a relatively low capacity, of-the-art achievements in flash technology. The MLC opera-
typically below 10 MB, and a large technology node, typically tion of RRAM was demonstrated by controlling the resistance
above 100 nm. This provides evidence for the attractiveness of through the maximum voltage Vstop during the reset [126], or
RRAM technology for nonvolatile embedded applications, the current compliance during the set [56, 126, 127]. The latter
e.g., in microcontrollers, where RRAM offers the advantages concept allowed us to demonstrate MLC operation with three
of faster read operation and lower power consumption, due to bits per cell, as described in figure 29 [128]. Here, seven levels
direct overwrite [31]. In two cases in table 1, a device size of compliance current IC were used between 30 μA and
below 30 nm and an array size of several GB were demon- 300 μA, resulting in seven LRS states with an increasing CF
strated [27, 28], which highlights the efforts in developing size, hence decreasing the resistance. Figure 29(a) shows the
high-density RRAM for applications as NAND-type data corresponding I–V curves at an increasing IC for a TaOx

18
Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 28. A nanometer scaled RRAM device. An ultra-small memory device was obtained by fabricating a sub-lithographic Cu BE (a) with
a size between 2 and 3 nm as estimated by CAFM (b). Copyright (2011) IEEE. Reprinted, with permission, from [124].

Figure 29. The 3-bit MLC operation of an RRAM device by controlling the CF size via the compliance current. I–V curves indicate that R can
be accurately modulated by changing the compliance current IC (a), resulting in the tight distributions of seven LRS levels and an HRS level
(b), allowing for 3-bit storage in a single physical memory cell. Copyright (2015) IEEE. Reprinted, with permission, from [128].

Table 1. Summary of RRAM prototypes.

Year Node [nm] Capacity Company Electrode/switching layer Reference

2010 130 64 M Unity CMOX [119]
2011 180 4M ITRI TiN/Ti/HfO2/TiN [120]
2011 130 384 k Adesto Ag/GeS2 [29]
2011 180 4M Sony CuTe/GdOx [121]
2012 180 8M Panasonic TaN/TaO2/Ta2O5/Ir [122]
2013 110 512 k Panasonic TaN/TaO2/Ta2O5/Ir [30]
2013 24 32 G Sandisk/Toshiba Metal oxide [28]
2014 27 16 G Micron/Sony Cu-based/oxide [27]
2015 90 2M Renesas Metal/Ta2O5/Ru [31]

RRAM device with a Ta cap electrode serving as an oxygen Figure 29(b) shows the cumulative distributions of read current
exchange layer to control the forming voltage [128]. Both the measured at 0.2 V, indicating seven LRS distributions and one
resistance and reset current are repeatedly controlled by IC as a HRS distribution, which make eight resistance levels corresp-
result of changing the size of the CF during set transition. onding to three bits per cell. Note that HRS distribution

19
Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 30. The 3-bit MLC operation of an RRAM device by control of the CF size and direction. The device can be written into PLRS by the
application of a positive voltage to NHRS, or it can be written into NLRS by application of a negative voltage to PHRS (a). The two CFs
have the same size as a result of the same value of IC during set transition, but a different orientation, namely down and up for PLRS and
NLRS, respectively. Although the read at low voltage yields the same resistance value, the completion of a positive read sweep to a
sufficiently high voltage reveals CS or a normal bipolar reset for PLRS and NLRS, respectively (b), thus allowing the different CF orientation
to be discriminated. The CS of PLRS is due to the migration of the defect reservoir from the TE side to the BE side (c), while the bipolar reset
of NLRS is due to the retraction of defects back to the BE (d). Reprinted with permission from [44]. Copyright (2013) John Wiley &
Sons, Inc.

negligibly depends on IC, suggesting that the HRS conductive have been accumulated to the TE (state one in figure 30(c)) by
path is almost independent of the CF size in the previous LRS a reset process under negative voltage. Then, set transition is
before reset transition. Distribution spread gradually increases induced by the application of a positive voltage, resulting in a
with read current and IC, consistent with the size-dependent positive low-resistance state (PLRS, state two in figure 30(c))
variability of LRS in figures 24–26. The stability of the eight where the final CF size and resistance are dictated by the
resistance levels was further verified against read pulses and compliance current (IC = 1.25 mA in the figure). Similarly, the
elevated temperature to test the immunity to noise and temp- device could be prepared in a positive high-resistance state
erature-accelerated CF dissolution. (PHRS, state one in figure 30(d)) by the reset transition under a
The approach in figure 29 relies on an increased range of positive voltage, then programmed in a negative low-resistance
IC spanning one order of magnitude, which might result in state (NLRS, state two in figure 30(d)) by the set transition
excessive power consumption. Also, this scheme may only be under negative voltage. Such bidirectional set/reset operations
applied to RRAM devices with a relatively large resistance are generally possible in RRAM with symmetric stacks, e.g. a
window, to accommodate all resistance levels and their TiN/HfO2/TiN stack without an intentional oxygen exchange
corresponding spread due to program and read noise. For layer or an asymmetric defect profile [125]. In these devices,
instance, the resistance window of the TaOx-based RRAM in the application of a positive voltage sweep without current
figure 29 is close to two orders of magnitude, whereas a limitation results in a set transition followed by a reset trans-
window around 10 is most typically reported for metal-oxide ition, reflecting the transfer of defects from a TE electrode
RRAM. Similarly, 3-bit/cell MLC storage was achieved by reservoir to the BE. The defect reservoir can be transferred
varying Vstop in a HfO2 RRAM with a resistance window back to the TE by applying a negative voltage sweep with no
larger than six orders of magnitude [129]. current limitation, thus inducing a set transition followed by a
To enable 3-bit MLC operation with a smaller resistance reset transition within the same voltage polarity [125]. This
window, an alternative concept can be adopted which allows operation mode, which goes under the name of complementary
different logic states to be attributed to the same resistance switching (CS), was sometimes in evidence in asymmetric
level [44]. This can be achieved by reversing the directionality stacks, such as Pd/Ta2O5−x/TaOy/Pd [130] and Pt/HfO2/TiN
of CF formation, as shown in figure 30. In normal conditions, [131]. Note that PLRS and NLRS in figure 30(a) have the same
the defect reservoir will be located at the TE, and thus the resistance, since the same value of IC was used, resulting in the
application of a positive voltage to the TE would result in a same size of the CF. However, the two CFs show the opposite
migration of defects toward the BE and the consequent for- direction (figures 30(c) and (d)), evidence of which can be
mation of the CF. This is shown by the set process under the provided by their different response to a positive voltage
positive voltage in figure 30(a): initially, the device is prepared sweep, as shown in figure 30(b). In fact, PLRS shows evidence
in a negative high-resistance state (NHRS) where all defects of the CS process, consisting of a current increase due to the set

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Figure 31. Horizontal and vertical 3D RRAM. In horizontal RRAM arrays, several layers of crossbar arrays (as in figure 1) are stacked (a),
while vertical 3D RRAM is achieved by perpendicular crossing between vertical electrodes and horizontal metallic planes (b), similar to 3D
flash technology. Copyright (2012) IEEE. Reprinted, with permission, from [132].

transition as defects migrate from the TE toward the BE. This element such as a threshold switch [136]. Select devices include
is followed by a current decrease (reset transition) due to the heterojunction metal-oxide diodes [14], threshold switches
CF disconnection at the TE side (figure 30(c)). On the other based on metal oxides [136–138] or chalcogenide glasses
hand, NLRS displays a simple bipolar reset operation due to [139, 140], mixed ion-electron conduction (MIEC) devices
the defect migrating back to the reservoir at the BE [141], multilayer tunnel junctions [142], threshold vacuum
(figure 30(d)). The different response is reflected by different switches [143], and others [144]. Selectors must display a
values of the reset current, since Ireset in CS is generally larger combination of properties including high non-linearity, high
than Ireset ≈ IC during conventional bipolar switching. The current density in the on-state, sufficient stability, low cell-to-
measurement of R and IC allows both the CF size and its cell variability, high endurance, and suitability for back-end
direction to be distinguished, thus allowing 3 bits to be stored processes and 3D processes. Matching all these specifications
in just 4 resistance levels—only half of the eight levels needed with one selector option is still challenging, and may require the
in conventional MLC schemes [44]. diversification of selector concepts according to the specific
High densities comparable to NAND flash must be memory characteristics, e.g., the operation current and resistance
achieved by 3D architectures, as summarized in figure 31
window. Technological solutions for select devices will pave the
[132]. Two possible 3D solutions were explored, namely
way for 3D RRAM architectures to support high memory and
horizontal 3D, where several 2D memory arrays are stacked
computing demand with high density and high performance.
in a multilayer structure (figure 31(a)), and vertical 3D
structures, where each memory cell is located at the inter-
section between a vertical line and a horizontal line
(figure 31(b)). Similar to vertical 3D NAND flash, vertical
6. Conclusions
RRAM has been recognized as the most suitable option for
achieving extreme density at a high manufacturing yield, due
This work reviews RRAM technology from the viewpoints of
to the limited number of critical masks and the possibility of
device switching mechanisms, reliability and scaling. RRAM
re-adapting, at least partially, the same vertical architecture of
has reached maturity in terms of our understanding of the
NAND memory [132, 133]. Horizontal stackable crossbar
switching concept and the main reliability mechanisms. The
arrays were demonstrated from two layers [28] to six layers
[13]. The vertical RRAM memory cells were fabricated by the main obstacles regarding the commercialization of the RRAM
deposition of a conformal metal/oxide bilayer on the sidewall concept are (i) the control of variability and noise processes
of a micro-trench or via-hole formed on a multilayer stack of affecting data stability after programming, and (ii) finding sui-
insulating and metallic films. Each memory cell was defined table selector devices enabling 3D crossbar arrays with high
by the intersection between a horizontal metal plane and a density and high performance. Both challenges require a careful
vertical metal electrode [134–136]. The devices in different study of switching/electrode materials to engineer memory/
layers were shown to display similar characteristics, which selector stacks with the required properties. Material engineer-
supports the integration of ultra-high-density vertical 3D ing might, for instance, allow relatively large resistance win-
arrays with several stacked layers [134]. dows between LRS and HRS to be achieved, thus enlarging the
To provide the necessary immunity from program/read read margin in support of noise immunity and MLC operation.
disturbs in the crossbar array, the memory device displayed a This would support scalable 3D RRAM for high-density,
strongly nonlinear characteristic, either obtained by careful high-speed operation regarding memory and in-memory
engineering of the stack [135], or by inserting a non-linear select computing.

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Semicond. Sci. Technol. 31 (2016) 063002 Topical Review

Acknowledgments [21] Indiveri G, Linares-Barranco B, Legenstein R,

Deligeorgis G and Prodromakis T 2013 Integration of
The author would like to thank S Ambrogio, V Milo and R nanoscale memristor synapses in neuromorphic computing
architectures Nanotechnology 24 384010
Carboni for their critical reading of the manuscript. This work [22] Wang Z-Q, Ambrogio S, Balatti S and Ielmini D 2015 A
was supported in part by the European Research Council 2-transistor/1-resistor artificial synapse capable of
Consolidator, grant ERC-2014-CoG-648635-RESCUE. communication and stochastic learning for neuromorphic
systems Front. Neurosci. 8 438
[23] Lee M-J et al 2011 A fast, high-endurance and scalable non-
volatile memory device made from asymmetric Ta2O5/
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