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BITS Pilani Presentation
BITS Pilani Dr. Sanjay Vidhyadharan
EEE WILP
Pilani Campus
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
BITS Pilani
Pilani Campus
MEL ZG623 Advanced VLSI Design
Lecture No. 0
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Introduction to AVLSI Design Course
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Course Content
1. Introduction to AVLSI Design
2. Sequential Circuits
3. Dynamic Latches
4. Timing Issues in Clocked Systems
5. Clock Generation and Distribution Networks
6. Asynchronous System Design
7. Interfacing Circuits
8. Wire Design Principles
9. High Speed Computer Arithmetic Design
10.Computer Arithmetic
11.Deep Sub-micron Device Engineering
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Textbooks
➢ T1: Digital Integrated Circuits - A design Perspective , Jan M Rabaey, Anantha
Chandrakasan, Borivoje Nikolic, 2nd edition, Prentice Hall, 2005.7
➢ Reference Books:
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Evaluation
Sl.No. Evaluation Component Type Weight Duration Day, Date,
Session, Time
EC - 1 Quiz 1 Online 10% TBA To be announced
Assignment Online 20% To be announced
EC - 2 Mid-Semester Test Open Book 30% 2 hours
EC - 3 Comprehensive Exam Open Book 40% 3 hours
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
VLSI Design / Advanced VLSI Design:
2021-22
Lecture 1
Introduction to VLSI Design
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
VLSI Design
Integrated circuits are also categorized according to the number of
transistors or other active circuit devices they contain.
➢ An IC is said to use small-scale integration (SSI) if it
contains fewer than 10 transistors.
➢ An IC that contains from 10 to 100 transistors is said to use
medium-scale integration.
➢ A large-scale integration (LSI) IC contains from 100 to 1,000
transistors
➢ And one that uses Very-Large-Scale Integration (VLSI)
contains more than 1,000 transistors.
2
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
ENAIC - The First Electronic Computer
1945
17,468 vacuum tubes and consumed 160 kW 3
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Evolution of Digital Technology
➢ Resistor Transistor Logic : 1961
➢ Diode Transistor Logic : 1962
➢ Transistor Transistor Logic : 1963 Discrete IC
➢ Emitter-coupled Logic : First Microprocessor 360
➢ CMOS :
➢ 1974 Intel 4004 which had 2000 Transistors
Channel Length of 10 µm.
➢ 2021 AMD 7 nm has billions of Transistors
Channel Length of 7 nm.
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
RTL Logic
Advantages
➢ The primary advantage of RTL technology
was that it involved a minimum number of
transistors, which was an important
consideration before integrated circuit
technology
Disadvantages
➢ The obvious disadvantage of RTL is its high
current dissipation when the transistor
conducts to overdrive the output biasing
resistor.
➢ Passive Pull up.
➢ Limited Fanout
➢ No Rail-to-Rail Output
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
DTL Logic
Advantages
➢ Diodes perform the logical function
Disadvantages
➢ The obvious disadvantage of DTL is its high
current dissipation when the transistor
conducts to overdrive the output biasing
resistor.
➢ Passive Pull up.
➢ Limited Fanout
➢ No Rail-to-Rail Output
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
TTL Logic
Advantages
➢ Multi-Emitter perform the logical function
➢ Active Pull-up and Active Pull down
Disadvantages
➢ The obvious disadvantage of TTL is its high
current dissipation
➢ No Rail-to-Rail Output
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
ECL Logic
Advantages
➢ Fast
➢ High Fan-out
Disadvantages
➢ High current dissipation
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advantages of CMOS Technology
➢ Low Static power consumption VDD
➢ High input impedance
➢ Rail to Rail Output
➢ Active Pull-up and Pull-down of Output
➢ Simple Design Vin Vout
➢ High Packing Density
➢ High noise immunity CL
➢ Temperature Stability
➢ Scalability
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Pentium
1993 : Technology : 0.8 μm (16.7 mm by 17.6 mm)
60–66 MHz
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latest CPUs and GPUs
Latest Trends :- Intel : 14 nm AMD : 7nm
➢ Billions of Transistors/ Chip
➢ Frequency of Operation in GHz
➢ Complex Computational Capability
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Moore’s Law
In 1965, Gordon E. Moore—co-founder of Intel (NASDAQ: INTC)—postulated that
the number of transistors that can be packed into a given unit of space will double
about every two years.
Million-transistor/chip barrier crossed in the late 1980s
12
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Die Size Growth
100
Die size (mm)
P6
486 Pentium ® proc
10 386
286
8080 8086
8085 ~7% growth per year
8008
4004 ~2X growth in 10 years
1
1970 1980 1990 2000 2010
Year
13
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Frequency
10000
Doubles every
1000
2 years
Frequency (Mhz)
P6
100
Pentium ® proc
486
10 8085 386
8086 286
1 8080
8008
4004
0.1
1970 1980 1990 2000 2010
Year
Microprocessors frequency doubles every 2 years
14
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
ITRS Prediction of Power Consumption
Semiconductor Industry Assoc., International Technology Roadmap for
Semiconductors, 2002 Update; http://public.itrs.net.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Limitations of Static CMOS
Intel’s Prediction of Power Consumption
Online Available: http://computerscience.chemeketa.edu/cs160Reader/Parallel Processing/
MooresLaw.html
16
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Power Dissipation in CMOS Circuits
Total Power
Dynamic Power Static Power
Switching Short circuit Glitch Leakage
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Loss
Static Power Dissipation in CMOS
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Loss
➢ Causes for High Static Power Consumption
Effect of Decreasing VDD on Delay
𝐾1 𝐶𝐿 𝐾2𝐶𝐿
𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦 (𝑡𝑝𝑑) = = 2`
𝐼𝐷 𝑉𝐷𝐷−𝑉𝑡ℎ
Effect of Decreasing Vth on Power
• Intel estimated leakage power consumption at more than 50W for a
100nm technology node.
• Leakage depends strongly on a Threshold voltage (Vth) of the transistor
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Loss
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Loss
➢ Reducing Static Loss
• Device Level Techniques
Tunnel Field Effect Transistors
CNFETs
• Circuit Level Techniques when using CMOS
[3] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage c rre mecha sms
and leakage reduction techniques in deep-submicrometer CMOS c rc s,” Pr ceed gs f he
IEEE, vol. 91, no. 2, pp. 305–327, Feb. 2003.
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Short Circuit Loss
𝑉𝐷𝐷
➢ Use devices with Vth close to & steep switching characteristics
2
➢ Short Circuit loss reduces with Cload
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Short Circuit Loss
➢ Short Circuit loss reduces with Cload
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Switching Loss
𝑉 1 2
Energy stored in CLoad (𝐶𝐿)= 0 𝐷𝐷 𝑉𝐶 . 𝐶𝐿𝑑𝑉𝑐 = . 𝑉𝐷𝐷 ∗ 𝐶𝐿
2
𝑇 2
Energy consumed from power supply= 𝑉𝐷𝐷 0 𝑖 𝑡 𝑑𝑡 = 𝑉𝐷𝐷 . 𝑄𝐶𝐿 = 𝑉𝐷𝐷 . 𝐶𝐿
21
Energy dissipated in pMOSFET during charging = . 𝑉𝐷𝐷 . 𝐶𝐿
2
2 1
Energy dissipated in nMOSFET during discharging = . 𝑉𝐷𝐷 . 𝐶𝐿
2
2
Power Consumption = Frquency. 𝑉𝐷𝐷 . 𝐶𝐿
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
High Dynamic Power Consumption
PDynamic = Freq * VDD2 * CL
➢ VDD & CL : Reduced by 30 % each generation
➢ Frequency : 43 % Increase
▪ Architectural optimizations
▪ Consumer requirements
➢ Transistors per chip : Increased exponentially
▪ Advancement in lithography
▪ Multilayer metallization
▪ Efficient partitioning and routing techniques
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Figure of Merits of a Digital Circuit
1. Noise Margin
26
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Figure of Merits of a Digital Circuit
2. Propagation Delay (Eg. Inverter)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Figure of Merits of a Digital Circuit
3. Fan-in and Fan-Out
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Figure of Merits of a Digital Circuit
4. Power and Energy Consumption
➢ Power consumption of design determine
➢ How much energy is consumed per operation
➢ How much heat the circuit dissipates
➢ Determine critical design decision
➢ Power supply capacity, battery lifetime,
➢ Supply line sizing, packaging and cooling
➢ Peak power is important for supply line sizing
➢ Average power dissipation is important for cooling or
battery requirements
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Figure of Merits of a Digital Circuit
5. Power Delay Product
PDynamic = Freq * VDD2 * CL
𝐾1 𝐶𝐿 𝐾 2 𝐶𝐿
𝑃𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛 𝐷𝑒𝑙𝑎𝑦 (𝑡𝑝𝑑) = = 2`
𝐼𝐷 𝑉𝐷𝐷−𝑉𝑡ℎ
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 2
Sequential Circuits: Latch and Flip-flops
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Combinational vs. Sequential Circuits
n-inputs Combinational m-outputs
Circuit (Depend only on inputs)
Combinational Circuit
n-inputs m-outputs
Combinational
Circuit Storage
Next Elements Present
state state
Sequential Circuit
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch vs. Flip-flop
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch
Storing 1
0 1
1 0
Stores 1 as Long as Power Supply is Provided
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch
Storing 0
1 0
0 1
Stores 0 as Long as Power Supply is Provided
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch
How to Write Data into a Latch?
1 0
1
0
We are going to use this property of NOR and NAND to
write data into the latch
6
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
S R Q ഥ
𝑸
1
0 0 Q ഥ
𝑸
0 1 0 1 0
1 0 1 0
1 1 0 0
0
1
0
1
0
7
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
S R Q ഥ
𝑸
1
0 0 Q ഥ
𝑸
0 1 0 1 0
1 0 1 0
1 1 0 0
1 0 1
0
1 1
0 1 0
1
0
8
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
S R Q ഥ
𝑸
1
0 0 Q ഥ
𝑸
0 1 0 1 0
1 0 1 0
1 1 0 0
0 1
0 1
1 0 0
1
1 1
9
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
S R Q ഥ
𝑸
0 0 Q ഥ
𝑸 No change
0 1 0 1 Reset Q = 0
1 0 1 0 Set Q = 1
1 1 0 0 Forbidden
10
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
SR Latch with NOR Gates
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
SR Latch with NAND Gates
0
1
S’ R’ Q Q’
0 0 1 1 Forbidden
0 1 1 0 Set
1 0 0 1 Reset
1 1 Q Q’ No change
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
Clocked SR Latch
NAND Implementation AND-NOR Implementation
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
SR Latch
Clocked SR Latch
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
D Latch
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
D Latch
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
D Latch
Mux Based Latch
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
D Latch
Mux Based Latch
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
D Latch
Multiplexer-based NMOS latch using NMOS-only pass transistors.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Race around in Latches
Xn
D
Yn = Xn . X’n-1
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch vs. Flip-flop
Latch – Responds to change in level of clock pulse
The key to the proper operation of a flip-flop is to trigger it
only during signal transition.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Timing Constraints of a Flip-flop
➢ Setup Time
➢ Hold Time
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Master-slave positive edge-triggered register using multiplexers.
The set-up time is equal to 3*tpd_inv + tpd_tx
Hold time is Nil
Propagation delay = tpd_tx + tpd_inv
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Set-up time simulation
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Simulation of propagation delay
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Reduced load clock load static master-slave register.
The penalty for the reduced clock load is increased design complexity. The
transmission gate (T1) and its source driver must overpower the feedback
inverter (I2 ) to switch the state of the cross-coupled inverter.
The transistors of inverter I2 should be made weaker. This can be accomplished by
making their channel-lengths larger than minimum.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Clock Jitter
When the clock goes high, the slave stage should
stop sampling the master stage output and go into a
hold mode. However, since CLK and CLK are both
high for a short period of time (the overlap period),
both sampling pass transistors conduct and there is a
direct path from the D input to the Q output. As a
result, data at the output can change on the rising
edge of the clock, which is undesired for a negative
edge- triggered register.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Two-phase non-overlapping clocks
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Single Phase Global Clock Generation
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Non-overlapping Clock Generation
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flip-Flop
Solving the leakage problem using multiple-threshold CMOS.
Negative latch
➢ During normal mode of operation, the sleep devices are tuned on.
➢ The shaded inverters and transmission gates are implemented in low-threshold devices.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 3
Dynamic Registers
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static CMOS Latch
➢Area Large
➢Complexity
➢Static Dissipation
➢Dynamic Dissipation
Short Circuit
Switching Loss
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Dynamic Register
Principle of Operation:
➢ Temporary storage of charge on parasitic capacitors.
➢ A stored value can hence only be kept for a limited amount of
time, typically in the range of milliseconds.
➢ To preserve signal integrity, a periodic refresh of its value
➢ Registers are used in computational structures are constantly
clocked such as pipelined datapath.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Dynamic Register
Dynamic Positive edge-triggered register
➢ Only 8 transistors
➢ Only 6 transistors if NMOS Gates used
➢ Low Power
➢ Low Propagation Delay ( One Pass Transistor Delay + One Inverter Delay)
➢ Set-up Time : (One Pass Transistor Delay + One Inverter Delay)
➢ Hold Time : Nil
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Dynamic Register
Dynamic Positive edge-triggered register
Limitations
During the 0-0 overlap direct path for data from D to Q (T1PMOS – T2PMOS)
During the 1-1 overlap direct path for data from D to Q (T1NMOS – T2NMOS)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Dynamic Register
Dynamic Positive edge-triggered register
Suppose data changes
here . Node 1 not
effected
Limitations Node 1 salved to D
Q salved to D
Q can change on the falling edge
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock-Skew Insensitive C2MOS Register
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock-Skew Insensitive C2MOS Register
If the D input changes during the overlap period, node X can make a transition, but cannot
propagate to the output.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock-Skew Insensitive C2MOS Register
If the D input changes during the overlap period, node X can make a transition, but cannot
propagate to the output.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock-Skew Insensitive C2MOS Register
If the D input changes during the overlap period, node X can make a transition, but cannot propagate to the
output. However, as soon as the overlap period is over, the PMOS M8 is turned on and the 0 propagates to
output. This effect is not desirable. The problem is fixed by imposing a hold time constraint on the input
data, D, or, in other words, the data D should be stable during the overlap period.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock-Skew Insensitive C2MOS Register
Clock rise time (or fall time) should be smaller than approximately five times the
propagation delay of the register.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Dual-edge Registers
➢ Input sampled on both edges
➢ Lower frequency for same functional
throughput
➢ Power savings in the clock distribution
network
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
True Single-Phase Clocked Register (TSPCR)
➢ When Clock is Low :
➢ If data is 0 , Node 1 is Charged to ‘High’. Node Out retains previous value.
➢ If data is 1 , Node 1 is retains previous value. Node Out retains previous value.
➢ When Clock is High :
➢ Chain of two inverters Latch is transparent and Q slaved to D
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
True Single-Phase Clocked Register (TSPCR)
➢ In two-phase clocking schemes, care must be taken in routing the two clock signals to
ensure that overlap is minimized.
➢ A register can be constructed by cascading positive and negative latches.
➢ The main advantage is the use of a single clock phase.
➢ The disadvantage is the slight increase in the number of transistors -12 transistors are
required.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
True Single-Phase Clocked Register (TSPCR)
➢ TSPC offers an additional advantage: the possibility of embedding logic functionality
into the latches.
➢ This reduces the delay overhead associated with the latches.
➢ This approach of embedding logic into latches has been used extensively in the design of
high-performance processors.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
True Single-Phase Clocked Register (TSPCR)
In a 0.25 mm, the set-up time of such a circuit using minimum-size devices is 140 psec. A
conventional approach, composed of an AND gate followed by a positive latch has an effective set-up
time of 600 psec (we treat the AND plus latch as a black box that performs both functions). The
embedded logic approach hence results in significant performance improvements.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
True Single-Phase Clocked Register (TSPCR)
➢ The TSPC latch circuits can be further reduced in complexity, where only the first
inverter is controlled by the clock.
➢ Not all node voltages in the latch experience the full logic swing the voltage at node A
(for Vin = 0 V) for the positive latch maximally equals VDD– VTn, which results in a
reduced drive for the output NMOS transistor and a loss in performance.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Positive Edge-Triggered Register TSPC
When CLK = 0 :
The input inverter is sampling the inverted D input on node X.
The second (dynamic) inverter is in the precharge mode, Y to VDD.
The third inverter is in the hold mode, since M8 and M9 are off.
On the rising edge of the clock :
The dynamic inverter M4-M6 evaluates. If X is high on the rising edge, Y discharges.
The third inverter M7-M8 is on during the high phase, and the node value on Y is
passed to the output Q.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Positive Edge-Triggered Register TSPC
Hold Time: On the positive phase of the clock, note that node X transitions to a low if the D
input transitions to a high level. Therefore, the input must be kept stable till the value on node
X before the rising edge of the clock propagates to Y. This represents the hold time of the
register (note that the hold time less than 1 inverter delay since it takes 1 delay for the input to
affect node X).
Set-up Time: The set-up time is the time for node X to be valid, which is one inverter delay.
Propagation Delay : The propagation delay of the register is essentially three inverters since
the value on node X must propagate to the output Q.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Positive Edge-Triggered Register TSPC
Transistor sizing is critical to avoid Glitch
➢ Case D is 0
➢ Y and Q’ Both pulled to Zero initially and Q’ pulled
up again after Y brough sufficiently low
➢ M4 & M5 needs to be made stronger w.r.t. M7 & M8
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Pulse Register
➢ Propagation Delay : Two Inverter Delay
➢ Set-up Time : Nil
➢ Hold Time : Glitch Time
➢ The disadvantage is a substantial increase in verification complexity
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Sense amplifier Register
Sense amplifier circuits are used extensively in memory cores and in low swing bus drivers
to amplify small voltage swings present in heavily loaded wires.
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 4 : Part-1
Pipelined Registers and
Static Timing Analysis
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
4-Bit Adder
Performance Figure Value
Function Delay 3* _ ( ) _ ( )
Power 4
Throughput @ (3 * _ ( ) _ ( ))
Gate complexity 4*
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Pipelined 4-Bit Adder
Principle of Operation:
Performance Figure Value
Function Delay Tclock (Tclock > _ + +
Power 4 + 22
Throughput @ TClock
2/6/2022 Gate complexity 4* + 22 * 3
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
4-Bit Multiplier
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
4-Bit Pipelined Multiplier
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Pipelining with Latches
A non-overlapping clock essential for correct operation. Else there will be race around
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Pipelined Logic using C2MOS
Potential race condition during (0-0) overlap in C2MOS-based design
Similar considerations are valid for the (1-1) overlap.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
NORA CMOS
It combines C2MOS pipeline registers and NORA dynamic logic functional blocks.
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NORA CMOS
It combines C2MOS pipeline registers and NORA dynamic logic functional blocks.
NORA offers designers a wide range of design choices. Dynamic and static logic can be mixed freely. A NORA datapath
consists of a chain of alternating CLK and CLK modules. While one class of modules is precharging with its output latch
in hold mode, preserving the pre-vious output value, the other class is evaluating. Data is passed in a pipelined fashion
from module to module.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 4 - Part 2
Pipelined Registers and
Static Timing Analysis
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Timing Constraints of a Flip-flop
Setup Time
Hold Time
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Clock Skew and Jitter
Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital
circuit systems (such as computer systems) in which the same sourced clock signal arrives
at different components at different times.
Clock Jitter: Sometimes some external sources like noise, voltage variations may cause
to disrupt the natural periodicity or frequency of the clock. This deviation from the natural
location of the clock is termed to be clock jitter.
Clock Uncertainty = Clock Jitter + Clock Skew
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Timing Constraints of a Flip-flop
Data setup violation caused by clock jitter
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Timing Constraints of a Flip-flop
Data hold time violation caused by clock jitter
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Static Time Analysis
There are two main problems that can arise in synchronous logic:
Max Delay: The data doesn’t have enough time to pass from one register
to the next before the next clock edge.
Min Delay: The data path is so short that it passes through several
registers during the same clock cycle.
Max delay violations are a result of a slow data path, including the
registers, tsu therefore it is often called the “Setup” path.
Min delay violations are a result of a short data path, causing the data to
change before the thold has passed, therefore it is often called the “Hold”
path.
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Static Time Analysis
Setup (Max) Constraint
After the clock rises, it takes tcq for the data to propagate to point A.
Then the data goes through the delay of the logic to get to point B.
The data has to arrive at point B, tsu before the next clock.
Setup Slack = Data Required Time – Data Arrival Time
Positive Slack : No Timing Violation
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Negative Slack : Timing Violation 16
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Time Analysis
Hold (Min) Constraint
Hold problems occur due to the logic changing before thold has passed.
This is not a function of cycle time – it is relative to a single clock edge!
• The clock rises and the data at A changes after tcq . The data at B changes tpd (logic) later.
• Since the data at B had to stay stable for thold after the clock (for the second register), the
change at B has to be at least thold after the clock edge.
Hold Slack = Data Arrival Time– Data Required Time
Positive Slack : No Timing Violation
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Negative Slack : Timing Violation 17
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Static Time Analysis
T= 15 ns
Setup slack = Min. Clock Path Delay - Max. Data Arrival Time
= (15 ns + 2ns + 5 ns + 2 ns - 4 ns) - ( 2 ns + 11 ns +2 ns + 9 ns + 2 ns)
= 20 ns – 26 ns = -6 ns : Setup Time Violation.
Hold time slack = Min. Data Arrival Time - Max. Clock Path Delay
= (1 ns + 9 ns + 1 ns + 6 ns + 1 ns) - (3 ns + 9ns + 3 ns + 2 ns) -
2/6/2022
= 18 ns – 17 ns = + 1ns : No Hold Time Violation. 18
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Timing Constraints of a Sequential Circuit
Maximum Clock Frequency
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Static Time Analysis
Given the data setup time of the flop is 6ns, the hold time of the flop is 2ns, and the clock to
Q delay is given as 10ns.
a. Calculate the minimum clock period required to handle the circuit by drawing a digital
logic circuit for function clock frequency divided by 2.
b. Also determine the status of hold time violation and give a proper reason.
Tminimum >= Tsetup_time + Tclock_Q + dly
Tminimum >= 6ns + 10ns + 0
Tminimum >= 16ns
fmaximum = 1/16ns = 62.5MHz is the maximum possible frequency of operation
Thold_time <= Tclock_Q + delay
2ns <= 10ns + 0
2ns <= 10ns No Hold Time Violation
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Thank you
2/6/2022 21
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Advanced VLSI Design: 2021-22
Lecture 5
Clock Generation and Distribution
Part-1
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Phase-Locked Loops
Crystal oscillators generate accurate, low-jitter clocks with a frequency range
from 10’s of Megahertz to approximately 200MHz.
To generate a higher frequency required by digital circuits, a phase-locked loop
(PLL) structure is typically used. A PLL takes an external low-frequency
reference crystal frequency signal and multiplies its frequency by a rational
number N
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Phase-Locked Loops
PLL
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Phase-Locked Loops
The XOR as a phase detector
➢ Any deviation in a positive or negative direction from the perfect in-phase condition
produces the same change in duty factor resulting in the same average voltage.
➢ If the local clock is a multiple of the reference clock frequency, the output of the phase
detector will still be a square wave of 50% duty cycle, albeit at a different frequency
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Phase-Locked Loops
Phase-Frequency Detector
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Phase-Locked Loops
Phase-Frequency Detector
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Phase-Locked Loops
Charge Pump
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VCO
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VCO
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VCO
Delay-Locked Loop
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VCO
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VCO
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 5
Clock Generation and Distribution
Part-2
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Clock Distribution
Network Types: H-Tree Model
➢ One large central driver
➢ Recursive H-style structure
to match wire-lengths
➢ Halve wire width at
branching points to reduce
reflections
Flip-flops
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Clock Distribution
Network Types: H-Tree Model
Advantages
Low cost wiring
Low Capacitance
Disadvantages
Difficult to balance path delays due to
asymmetric FF distribution
Sensitive to variations
Flip-flops
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Clock Distribution
Network Types: H-Tree Model
Slew degradation along long RC paths
unrealistically large central driver
Clock drivers can create large temperature A B
gradients (ex. Alpha 21064 ~30° C)
Inherently non-scalable (wire resistance
skyrockets)
Solution to some problems
Introduce intermediate buffers along
the way Specifically at branching points
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Clock Distribution
Network Types: H-Tree Model
Alpha 21264 clock
distribution -- grid + H-
tree approach
Power = 32% of total
Wire usage = 3% of
metals 3 & 4
4 major clock quadrants, each with a large driver connected to local grid
structures
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CAD for Tree Architecture
• Topology generation
– H-tree: widely used
– Method of means and medians (MMM) [Jackson et al. DAC 90]
• Goal: reduce wirelength while minimizing skew.
• Divide set S of points into Sleft and Sright, based on median.
– | Sleft | = | Sright |
• Connect/route center of mass (CM) of S to CM of Sleft and Sright.
• Recurse on Sleft and Sright.
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Clock Distribution
Grid/Mesh
• Gridded clock distribution was common on
earlier DEC Alpha microprocessors
• Advantages:
– Skew determined by grid density and not
overly sensitive to load position
– Clock signals are available everywhere
– Tolerant to process variations
– Usually yields extremely low skew values
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Clock Distribution
Grid/Mesh
• Huge amounts of wiring & power
– Wire cap large
– Strong drivers needed – pre-driver cap large
– Routing area large
• To minimize all these penalties, make grid pitch coarser
– Skew gets worse
– Losing the main advantage
• Don’t overdesign
– let the skew be as large as tolerable Still
– grids seem non-feasible for SOC’s
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Clock Distribution
Hybrid Architecture: Tree + Cross-links
• Reducing Clock Skew Variability via Cross Links
– [Rajaram et. al., DAC 2004]
• tree + short-circuit some sink pairs => non-tree topology
– clock signal propagates through multiple paths; reduces skew and skew
variability between shorted sinks
• reduces skew variability by 30-70%
• very small wire-length penalty (2%) over tree topology
• Drawback:
source
– does not consider buffering
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Clock Distribution
Hybrid Architecture: Mesh + Trees
• Hybrid Structured Clock Network (Da, CDa)
Construction [Hu & Sapatnekar, ICCAD 01] source
– Hybrid clock topology
a c
• simple top-level global mesh
• zero-skew local trees at bottom
d
b
– Presents wire sizing scheme to achieve
latency and skew reduction..
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Clock Architectures
Clock source
Mesh
-- excellent for low skew, jitter
-- high power, area, capacitance
Flip-flops
flip flops
-- difficult to analyze
-- used in modern processors
Tree
-- low cost (wiring, power, cap)
-- higher skew, jitter than mesh
-- widely used in ASIC designs Best architecture depends on the application
Clock source
Flip flops
crosslink
crosslink
tree
Hybrid: tree + cross-links
-- low cost (wiring, power, cap)
Hybrid: mesh + local trees
-- smaller skew, jitter than tree Local trees
-- suitable for coarse mesh
-- difficult to analyze Flip flops
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Clock Gating
0
1
0/1 0
1
0
0/1 1
1/0
1
[5] M. Pedram and J.M. Rabaey, “Power aware design Methodologies,”
[Online]. Available: https://www.springer.com/gp/book/9781402071522
2/13/2022 25
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Clock Gating
[5] M. Pedram and J.M. Rabaey, “Power aware design Methodologies,”
[Online]. Available: https://www.springer.com/gp/book/9781402071522
2/13/2022 26
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Clock Gating
m Watts 20 % Reduction in Power due to Clock Gating
60 SHIFT REGISTER
SCALER
ALU m Watts
50
ADDER
Powe
FF
r
MUX
EQUAL TO
Before Clock After Clock
Gating Gating
[5] V. Natarajan, A. Nagarajan, N. Pandian, and V. Savithri “Power aware design Methodologies,” DOI: 10.5772/intechopen.73729
[Online]. Available: https://www.intechopen.com/books/very-large-scale-integration/low-power-design-methodology
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Clock Gating
Cl M
S
Conventional
ll dder
S
Modified
ll dder
i e ns
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Current conduction mechanism in CMOS and Tunnel FETs
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Thank you
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 6
Latch Based Clocking & Asynchronous
Clocking
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Pipelining
т𝑝𝑑 , 𝑃𝑎𝑑𝑑𝑒𝑟
A
+ Reg
B
+ Reg F
C Reg
+ Clock
D Clock
Performance Figure Value
Function Delay 2*TClock
Power 3 ∗ 𝑃𝑎𝑑𝑑𝑒𝑟 + 3 ∗ 𝑃𝑅𝑒𝑔𝑠𝑖𝑡𝑒𝑟
Throughput @ TClock ( т𝑐𝑙𝑘−𝑄 + т𝑝𝑑_𝑎𝑑𝑑𝑒𝑟 + т𝑠𝑒𝑡𝑢𝑝 )
Gate complexity 3 * 𝐺𝑎𝑑𝑑𝑒𝑟 + 2 * 𝐺𝑅𝑒𝑔𝑖𝑠𝑡𝑒𝑟
Functional Flexibility Nil
2/20/2022 Function Expandability Nil 2
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Latch Based Clocking
▪ A stable input is available to the combinational logic block A (CLB_A) on the falling edge of CLK1
(at edge 2 ) and it has a maximum time equal to the T CLK /2 to evaluate (that is, the entire low
phase of CLK1). On the falling edge of CLK2 (at edge 3 ), the output CLB_A is latched and the
computation of CLK_B is launched. CLB_B computes on the low phase of CLK2 and the output is
available on the falling edge of CLK1 (at edge 4 )
➢ It possible for a logic block to utilize time that is left over from the previous logic block
and this is referred to as slack borrowing
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Latch Based Clocking
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Latch Based Clocking
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Synchronous Clocking
➢ Clock period is chosen to be larger than the worst-case delay of each pipeline stage.
➢ Hence, The throughput rate of the pipelined system is directly linked to the worst-case
delay of the slowest element in the pipeline
➢ As all the clocks in a circuit transitions at the same time, significant current flows over a
very short period of time (due to the large capacitance load). This causes significant noise
problems due to package inductance and power supply grid resistance.
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Self-Timed Circuit Design
This avoids all problems and overheads associated with distributing high-speed clocks.
A self-timed circuit proceeds at the average speed of the hardware in contrast to the worst-case model
of synchronous logic.
The automatic shut-down of blocks that are not in use can result in power savings. Additionally, the
power consumption overhead of generating and distributing high-speed clocks can be partially avoided.
Self-timed circuits are by nature robust to variations in manufacturing and operating conditions such as
temperature.
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Completion-Signal Generation
Dual-Rail Coding
Redundant signal representation to include transition state.
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Completion-Signal Generation
Dual-Rail Coding
Dual-rail coding above allows tracking of the signal statistics, it comes at the cost of power
dissipation. Every single gate must transition for every new input vector, regardless of the
value of the data vector
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The Ripple-Carry Adder
𝐹𝑜𝑟 4 − 𝑏𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 12 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠
𝐹𝑜𝑟 8 − 𝑏𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 24 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠 𝐹𝑜𝑟 16 − 𝑏𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 48 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Manchester-Carry Adder Circuit
𝐹𝑜𝑟 4 − 𝐵𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 6 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠 𝐹𝑜𝑟 8 − 𝐵𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 12 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠
2/20/2022 𝐹𝑜𝑟 16 − 𝐵𝑖𝑡 𝐴𝑑𝑑𝑒𝑟 ≈ 18 𝐺𝑎𝑡𝑒 𝐷𝑒𝑙𝑎𝑦𝑠 11
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Self-Timed Adder Circuit
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Replica Delay
The advantage of this approach is that the logic can be implemented using a standard non-
redundant circuit style such as complementary CMOS.
Also, if multiple logic units are computing in parallel, it is possible to amortize the
overhead of the delay line over multiple blocks
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Completion-Signal Generation using Current Sensing
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Self-Timed Signaling
The four events, data change, request, data acceptance, and acknowledge, proceed in a cyclic
order. This protocol is called two-phase.
➢ The Req event terminates the active cycle of the sender. The sender is free to change the data
during its active cycle.
➢ The receiver’s cycle is completed by the Ack event. The receiver can only accept data during
its active cycle.
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Muller C-element.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Self-Timed Signaling
Data Ready Ack Ack’ Req
0 0 1 0
0 -> 1 0 1 0 -> 1
1/1 -> 0 0 1 1
1/0 0 -> 1 1 -> 0 1/1 -> 0
1 -> 0 1 0 1 -> 0
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Two-Phase Self-Timed FIFO
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Four-Phase Self-Timed FIFO
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Four-Phase Self-Timed FIFO
Data Ready Req S S’ Ack Ack’
0 0 0 1 0
0 -> 1 -> 0 0 -> 1 0 1 0
0->1
0 0 1 0 1
0 -> 1 -> 0 0 1 0 1
1 -> 0
0 1
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 7
Interfacing Circuits – Part-1
Synchronizer and Arbiters
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Synchronizer
PT Switch
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Synchronizer
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Synchronizer
𝐹𝑜𝑟 𝑇 = 0, 𝑅𝑎𝑛𝑔𝑒 = 𝑉𝐼𝐻 − 𝑉𝐼𝐿
𝐹𝑜𝑟 𝑇 = 2𝜏, 𝑅𝑎𝑛𝑔𝑒 = (𝑉𝐼𝐻 −𝑉𝐼𝐿 ) 𝑒 −2
𝐹𝑜𝑟 𝑇 = 4𝜏, 𝑅𝑎𝑛𝑔𝑒 = (𝑉𝐼𝐻 −𝑉𝐼𝐿 ) 𝑒 −4
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Synchronizer
Vin is a periodical waveform with an average period T signal between transitions and
with identical rise and fall times tr .
Average synchronization errors per second with no synchronizer
Average synchronization errors per second with synchronizer
errors/sec
Mean time-to-failure (MTF) = 1/Nsyn(T)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Arbiters
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Thank you
2/27/2022 7
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 7
Interfacing Circuits – Part-2
Schmitt Triggers
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Nosie Margin Variation with VDD
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Delay Variation with VDD
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Inverter Switching Threshold
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Inverter Switching Threshold
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Subthreshold Conduction
IDO is a process-dependent parameter that is dependent on VT
.
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Subthreshold Inverter
Analysis of the subthreshold CMOS logic inverter
Sherif M.Sharroush
Ain Shams Engineering Journal Volume 9, Issue 4, December 2018, Pages 1001-1017
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Schmitt Trigger
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Schmitt Trigger
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Schmitt Trigger
With Vin less than the threshold voltage of M1, VX remains at VDD - VTHN3
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Schmitt Trigger Design Example
Design and simulate a Schmitt trigger using the short-channel CMOS process with
VSPL = 400 mV and VSPH = 700 mV. Given Vth = 0.25 V and (W/L) min = 10
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Schmitt Trigger Delays
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Applications of the Schmitt Trigger
Oscillator design using a Schmitt trigger
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Applications of the Schmitt Trigger
Voltage-controlled oscillator using Schmitt trigger
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Schmitt Trigger Power
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Schmitt Trigger Design
Adjustment of Hysteresis Width
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Schmitt Trigger Design
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Schmitt Trigger
Vidhyadharan, A.S. and Vidhyadharan, S. "Improved hetero-junction TFET-based Schmitt
trigger designs for ultra-low-voltage VLSI applications", World Journal of Engineering,
Vol. ahead-of-print No. ahead-of-print. 2021 DOI: 10.1108/WJE-08-2020-0367
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Schmitt Trigger
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Schmitt Trigger
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 8
Interfacing Circuits – Part-3
Level Shifters and IO PADS
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
TTL to CMOS Level Shifter
2.0V
0.8V
Voltage level of TTL and CMOS The corresponding VTC
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CMOS Inverter Switching Threshold
The Switching Threshold, VM , is the point where Vin = Vout .
This can be calculated:
» Graphically, at the intersection of the VTC with Vin = Vout
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
TTL to CMOS Level Shifter
Designing the Receiving Inverter Gate
• Adjust the TR ratio such that the Inverter Threshold VM is midpoint between
0.8V and 2.0V
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TTL to CMOS Level Shifter
𝑉𝐷𝐷 +𝑉𝑇𝑝 +𝑟𝑉𝑇𝑛
𝑉𝑀 =
1+𝑟
0.8+2
For 𝑉𝐷𝐷 = 5 𝑉 𝑎𝑛𝑑 VM = 2
= 1.4 𝑉 , 𝑉𝑇𝑛 = 1 𝑉, 𝑎𝑛𝑑 𝑉𝑇𝑝𝑛 = −1 𝑉
r = 6.5
𝜇𝑛 𝐶𝑜𝑥 𝑊𝑛 /𝐿𝑛
𝑟=
𝜇𝑝 𝐶𝑜𝑥 𝑊𝑝 /𝐿𝑝
𝑊𝑛 /𝐿𝑛 1 2 169
= 6.5 =
𝑊𝑝 /𝐿𝑝 3 12
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
TTL to CMOS Level Shifter
Non-inverting TTL Level-shifting Circuit
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CMOS Level Shifter
VDDH = 1.8 V VDDH = 1.8 V
VDDH = 1.8 V
VT = 0.75 V VT = 0.75 V VT = 0.75 V
VDDL = 1.2 V
VDDL = 0.9 V VDDL = 0.7 V
Works Fine VDDH and VDDL
are Close.
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CMOS Level Shifter
Works Fine for VDDL > VT.
P.O. Pouliquen, in Proceedings of 2010 IEEE International Symposium on Circuits and
Systems (2010), pp. 40974100. DOI 10.1109/ISCAS.2010.5537627
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CMOS Level Shifter
VDDH = 1 V ( 90 nm)
VDDL = 0.18 V
VHVT = 0.535 V
VSVT = 0.360 V
VLVT = 0.230 V
M. Lanuzza, P. Corsonello, S. Perri, IEEE Transactions on Circuits and Systems II:
Express Briefs 59(12), 922 (2012). DOI 10.1109/TCSII.2012.2231037
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Electrostatic Discharge (ESD)
(b) machine model
(a) Human Body 1.5 kV of static voltage stress
(c) charged device model, for ESD testing
Effective protection networks can withstand as high as 8-kV
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Electrostatic Discharge (ESD)
Models for ESD testing
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Electrostatic Discharge (ESD)
ESD Protection Network
-0.7 V < VA < VDD+.7V
1-3kὨ
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Electrostatic Discharge (ESD)
Protection network with thick-oxide transistor
Ml and M2 have threshold values of 20 to 30 V.
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Electrostatic Discharge (ESD)
Typical ESD failure modes.
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Input Circuits
Internal Drivers to Prevent
Voltage drop in bonding wires
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Output Circuits
12 transistors Four Very large Sized transistors
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Output Circuits
High rate of change in the current di/dt and can cause significant on-chip noise problems due
to the L(di/dt)drop across the bonding wire connecting the output pad to the package.
Cload = 100 pF and t = 5 ns, then
𝑄 = 𝐶𝑉
𝐼𝑚𝑎𝑥 𝑡𝑠 𝑉𝐷𝐷
∗ = 𝐶𝑙𝑜𝑎𝑑
2 2 2
for a bonding wire with L = 2 nH,
This voltage drop would be quadrupled if t were reduced by a factor of two.
Trade-off between the delay time and the noise
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Output Circuits
In a CMOS chip the current surge can be as high as 1100 mA/ns at power and ground
terminals. For a microprocessor with 32 bits or higher number of data bus lines, the noise
problem can be significantly escalated if all output drivers are driven simultaneously. In such
cases, it is desirable to stagger the switching times with built-in delays
The role of two nMOS transistors controlled by the strobe signal (ST) is to pre-charge
the gate potentials of the last-stage driver transistors at an approximate midpoint
between the initial and final potentials of the load capacitor.
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Output Circuits
The circuit sends out only changes in
the data pattern
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Output Circuits
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Packages
Package functions
– Electrical connection of signals and power from chip to board
– Little delay or distortion
– Mechanical connection of chip to board
– Removes heat produced on chip
– Protects chip from mechanical damage
– Compatible with thermal expansion
– Inexpensive to manufacture and test
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Package Types
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Multichip Modules
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Chip-to-Package Bonding
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Heat Dissipation
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Thank you
3/20/2022 26
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Advanced VLSI Design: 2021-22
Lecture 9
Arithmetic Circuits: Part-1
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Microprocessor Design
Pads for Bus Control, Clock, Reset, Interrupts, Testing and Power Supply
Clock-Phase Bus Controller
Generators
State Instruction
Control Store
Sequencer Decoders
Control word Decoder
Instruction Pre-fetch Register
Internal A Bus
Address Data
out PC R0 R1 Rn Shifter ALU In/out
Buffer Reg
Internal B Bus
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ALU Design
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Half Adder
X Sum = X•Y’ + X’•Y = X ⊕ Y
HS Carry = X•Y
Y
Time Delay for the Half Adder?
1 gate delay
A gate delay of an xor for the half sum
CO A gate delay of an AND gate for the carry out
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Full Adder
Full-adder can also implemented with two half adders and one OR gate.
S = A ⊕ B ⊕ Cin
Cout = AB + BCin + ACin
= AB + Cin (A+B)
= AB + Cin (A ⊕ B+ AB)
= AB + Cin (A ⊕ B) + Cin AB = AB(1+ Cin) + Cin (A ⊕ B)
= AB + Cin (A ⊕ B)
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Full Adder
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
CMOS 28T Adder
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CMOS 28T Mirror Adder
𝐶𝑎𝑟𝑟𝑦 = 𝐴𝐵 + 𝐵𝐶 + 𝐶𝐴 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵
𝑃𝑢𝑙𝑙 − 𝐷𝑜𝑤𝑛 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴𝐵 + 𝐶 𝐴 + 𝐵
𝑃𝑢𝑙𝑙 − 𝑈𝑃 𝑁𝑒𝑡𝑤𝑜𝑟𝑘 𝑓𝑜𝑟 𝐶𝑎𝑟𝑟𝑦 𝐵𝑎𝑟 = 𝐴′ 𝐵′ + 𝐵′ 𝐶 ′ + 𝐶 ′ 𝐴′
= 𝐴′ 𝐵′ + 𝐶′(𝐴′ + 𝐵′ )
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CMOS 28T Mirror Adder
12 12 12
12 12
6 6
6 6 6
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Ripple Carry Adder
This is called Ripple Carry Adder, because of the
construction with full adders are connected in cascade.
Delay= 4 X Full Adder Delay = 8 Gate Delays
Delay= (N-1) tcarry + tsum 10
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Carry Look-Ahead Adder
1-bit CLA
B A
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Carry Look-Ahead Adder
CLA
CLLB
C1=G0+P0C0
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Carry Look-Ahead Adder
C2=G1+P1C1
C2 = G1+P1(G0+P0C0)
= G1+P1G0+P1P0C0
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Carry Look-Ahead Adder
C2= G1+P1G0+P1P0C0 C1=G0+P0C0
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Carry Look-Ahead Adder
C1=G0+P0C0
C2= G1+P1G0+P1P0C0
C3=G2+P2G1+ P2P1G0 +P2P1P0C0
C4=G3+P3G2+ P3P2G1 +P3P2P1G0 +P3P2P1P0C0
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Carry Look-Ahead Adder
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Carry Look-Ahead Adder
8 Bit Full Adder
Delay = 2 X 3 = 6 Gate Delay
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Ripple Carry Adder
8 Bit Full Adder
Delay = 8 X 2 Gate Delay
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Carry Look-Ahead Adder
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Carry Bypass or Carry Skip Adder
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Carry Bypass or Carry Skip Adder
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Carry Ripple versus Carry Bypass
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Manchester Carry Chain
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Linear Carry-Select Adder
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Square Root Carry-Select Adder
𝑡𝑎𝑑𝑑 = 𝑡𝑠𝑒𝑡𝑢𝑝 + 𝑀𝑡𝑐𝑎𝑟𝑟𝑦 + 2𝑁 𝑡𝑚𝑢𝑥 + 𝑡𝑠𝑢𝑚
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Square Root Carry-Select Adder
𝑁 𝐵𝑖𝑡 𝑎𝑑𝑑𝑒𝑟, 𝑀 − 𝐵𝑖𝑡𝑠 𝑖𝑛 𝐹𝑖𝑟𝑠𝑡 𝑆𝑡𝑎𝑔𝑒 , 𝑃 − 𝑁𝑢𝑚𝑏𝑒𝑟 𝑜𝑓 𝑆𝑡𝑎𝑔𝑒𝑠
𝑁 = 𝑀 + 𝑀 + 1 + 𝑀 + 2 + 𝑀 + 3 + ⋯ . +(𝑀 + 𝑃 − 1)
Series: a, a+d, a+2d,……,a+(n-1)d
𝑃(𝑃 − 1)
𝑁 = 𝑀𝑃 + sn = n/2(2a + (n-1)d)
2
𝑃 2 1
𝑁= + 𝑃(𝑀 − )
2 2
𝑀 ≪ 𝑁 𝑒. 𝑀 = 2 𝑎𝑛𝑑 𝑁 = 64
𝑃2
𝑁≈
2
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Adder Delays - Comparison
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Serial Adder
Initialize to
0
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4 Bit-Adder Subtractor
Add 4 & -3 Add -4 & -5 Add -8 & 4 Add 4 & 4
0100 1100 1000 0100
1101 1011 0100 0100
1 0001 1 0111 1100 1000
Overflow
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Binary Coded Decimal
General digital systems
User enters decimal → BCD i/p→ Binary i/p → compute in binary
→ Binary o/p → BCD o/p → Decimal output shown to user
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Binary Coded Decimal
BCD addition
4+5 4 0100
5 0101
9 1001 Expected Result
4+8 4 0100
8 1000
1100 Is this expected Result ?
Expected answer 0001 0010
is BCD of 12 31
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Binary Coded Decimal
BCD addition
4+8 4 0100
8 1000
Greater than 9 1100
0110 Add correction of +6
00010010
1 2 = To skip 6 invalid
states (10 - 15) BCDs
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Binary Coded Decimal
BCD addition
9+9 9 1001
9 1001
Carry out generated 1 0 0 1 0 Expected result ?
0110 Add correction of +6
00011000
1 8
After addition if carry out is generated or if sum is greater
than 9 there is need for correction
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Binary Coded Decimal
BCD addition 0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
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Advanced VLSI Design: 2021-22
Lecture 10
Arithmetic Circuits: Part-2
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
The Binary Multiplication
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The Array Multiplier
A0B3 A0B2 A0B1 A0B0
A1B3 A1B2 A1B1 A1B0
A2B3 A2B2 A2B1 A2B0
A3B3 A3B2 A3B1 A3B0
A1B3 A1B2 A0B3 A1B1 A0B2 A1B0 A0B1 A0B0
HA FA FA HA
A2B3 A2B2 A2B1 A2B0
FA FA FA HA
A3B3 A3B2 A3B1 A3B0
FA FA FA HA
P7 P6 P5 P4 P3 P2 P1 P0
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The Array Multiplier
𝑀 𝐵𝑖𝑡 𝑋 𝑁 𝐵𝑖𝑡 −> 𝑃 = (𝑁 + 𝑀 − 1) A1B3 A1B2 A0B3 A1B1 A0B2 A1B0 A0B1 A0B0
HA FA FA HA
A2B3 A2B2 A1B3 A2B1 A2B0
FA FA FA HA
A3B3 A3B2 A3B1 A3B0
FA FA FA HA
P7 P6 P5 P4 P3 P2 P1 P0
𝑅𝑒𝑞𝑢𝑖𝑟𝑒 𝑁 − 1 𝑀 − 𝐵𝑖𝑡 𝐴𝑑𝑑𝑒𝑟𝑠 𝑅𝑒𝑞𝑢𝑖𝑟𝑒 𝑀 𝑋 𝑁 𝐴𝑁𝐷 𝐺𝑎𝑡𝑒𝑠
𝑡𝑚𝑢𝑙 = 𝑀 − 1 + 𝑁 − 2 𝑡𝑐𝑎𝑟𝑟𝑦 + 𝑁 − 1 𝑡𝑠𝑢𝑚 + 𝑡𝑎𝑛𝑑
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The Carry-Save Multiplier
A0B0
HA HA HA HA
HA FA FA FA
HA FA FA FA
Vector Merging Adder
HA FA FA HA
P7 P6 P5 P4 P3 P2 P1 P0
𝑅𝑒𝑞𝑢𝑖𝑟𝑒 𝑁 𝑀 − 𝐵𝑖𝑡 𝐴𝑑𝑑𝑒𝑟𝑠 𝑅𝑒𝑞𝑢𝑖𝑟𝑒 𝑀 𝑋 𝑁 𝐴𝑁𝐷 𝐺𝑎𝑡𝑒𝑠
𝑡𝑚𝑢𝑙 = 𝑡𝑎𝑛𝑑 + 𝑁 − 1 𝑡𝑐𝑎𝑟𝑟𝑦 + 𝑡𝑚𝑒𝑟𝑔𝑒
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Multiplier Floorplan
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Transmission Gate XOR
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Adder Cells in Array Multiplier
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Sequential Multiplier
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Booth Algorithm
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Booth Algorithm
Example:
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Comparators
• 0’s detector: A = 00…000
• 1’s detector: A = 11…111
• Equality comparator: A = B
• Magnitude comparator: A < B
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1’s & 0’s Detectors
• 1’s detector: N-input AND gate
• 0’s detector: NOTs + 1’s detector (N-input NOR)
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Equality Comparator
• Check if each bit is equal (XNOR, aka equality gate)
• 1’s detect on bitwise equality
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Magnitude Comparator
1 0 1
1 1 0
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Magnitude Comparator
1 0 1
1 1 0
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Magnitude Comparator
1-Bit Comparator A0 B0 G0 L0 E0
A0 0 0 0 0 1
B0 0 1 0 1 0
Let G0 indicate greater, L0 indicate 1 0 1 0 0
Lesser and E0 indicate equal 1 1 0 0 1
G0= A0B0’
L0= A0’B0
E0= (A0 ⊕ B0)’ = (A0 ʘ B0) = (G0 + L0)’
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Magnitude Comparator
1-Bit Comparator G0= A0B0’
A0
B L0= A0’B0
0
E0= (G0 + L0)’ = (A0 ⊕ B0)’
B0 A0
1-Bit
Comp
L0 E0 G0
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Magnitude Comparator
2-Bit Comparator B1 A1 B0 A0
A A1A0 1-Bit 1-Bit
Comp Comp
B BB
1 0
L1 E1 G1 L0 E0 G0
A = B When A0 = B0 and A1=B1
AND
E = E0 . E1
E (A=B)
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Magnitude Comparator
B1 A1 B0 A0
2-Bit Comparator
1-Bit 1-Bit
A A1A0 Comp Comp
B BB
L1 E1 G1 L0 E0 G0
1 0
E1 G0
A > B When A1 > B1 OR
When A1 = B1 and A0 > B0 AND G1
G= G1 + E1 . G0
OR
G
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Magnitude Comparator
B1 A1 B0 A0
2-Bit Comparator
1-Bit 1-Bit
A A1A0 Comp Comp
B BB
L1 E1 G1 L0 E0 G0
1 0
E1 L0
A < B When A1 < B1 OR
When A1 = B1 and A0 < B0 AND L1
L = L1 + E1 . L0
OR
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Magnitude Comparator
1-Bit Comparator
G =G0 L =L0 E =E0
2-Bit Comparator
G = G1 + E1. G0 L = L1 + E1. L0 E = E1. E0
3-Bit Comparator
G = G2 + E2. G1 + E2. E1. G0
E = E2 .E1. E0
L = L2 + E2. L1 + E2. E1. L0
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Magnitude Comparator
L3
4-Bit Comparator
E3 E = E2 .E1. E0
G3
G = G3 + E3.G2 + E3.E2. G1 + E3.E2. E1. G0
L2 L = L3 + E3.L2 + E3.E2. L1 + E3.E2. E1. L0
E2
G2
L1
E1
G1
L0
E0
G0
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Shifters
Logical Shift:
– Shifts number left or right and fills with 0’s
• 1011 LSR 1 = 0101, 1011 LSL1 = 0110
• Arithmetic Shift:
– Shifts number left or right. Rt shift sign extends
• 1011 ASR1 = 1101 1011 ASL1 = 0110
• Rotate:
– Shifts number left or right and fills with lost bits
• 1011 ROR1 = 1101 1011 ROL1 = 0111
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The Binary Shifter
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Multi-bit Shifters
• Cascade one-bit shifters?
• Complex, unwieldy, slow for larger number of shifts
• Two other types of shifters
– Barrel shifter
– Logarithmic shifter
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The Barrel Shifter
Area dominated by wiring
Propagation delay is theoretically constant
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The Barrel Shifter
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Logarithmic Shifter
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Shifter Using Mux
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 11: Memory Design
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Semiconductor Memory Classification
Volatile Non-Volatile Non-Volatile
Read-Write Memory Read-Write Memory Read-Only Memory
Random Access Non-Random Access
EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FIFO FLASH
SRAM LIFO
DRAM Shift Register
CAM
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Memory Timing: Definitions
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Memory Architecture
Decoder reduces the number of select signals K = log2N
Problem: ASPECT RATIO or HEIGHT >> WIDTH
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Array-Structured Memory Architecture
Better ASPECT RATIO
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Hierarchical Memory Architecture
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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Hierarchical Memory Architecture
Column Column Column
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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6T SRAM
Write bit bit_b
word
➢ Drive one bitline high, the other low P1 P2
N2 N4
➢ Then turn on wordline
A A_b
➢ Bitlines overpower cell with new value
N1 N3
➢ Writability
➢Must overpower feedback inverter
A_b
➢N2 >> P1
1.5 A
Ex: A = 0, A_b = 1, bit_b
1.0
bit = 1, bit_b = 0
Force A_b low, then A rises high
0.5
word
0.0
0 100 200 300 400 500 600 700
time (ps)
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
6T SRAM
Read bit bit_b
word
➢ Precharge both bitlines high
P1 P2
➢ Then turn on wordline N2 N4
➢ One of the two bitlines will be pulled A A_b
down by the cell N1 N3
➢ Read stability
➢A must not flip A_b bit_b
➢N1 >> N2 1.5
1.0
bit
Ex: A = 0, A_b = 1 word
bit discharges, bit_b stays high 0.5
But A bumps up slightly A
0.0
0 100 200 300 400 500 600
time (ps)
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
6T SRAM
SRAM Sizing
High bitlines must not overpower inverters during reads
But low bitlines must write new value into cell
bit bit_b
word
weak
med med
A A_b
strong
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
6T SRAM
SRAM Sense Amplifier
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
3-Transistor DRAM Cell
No constraints on device ratios Reads are non-destructive
Value stored at node X when writing a “1” = VWWL-VTn
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1-Transistor DRAM Cell
Write: CS is charged or discharged by asserting WL and BL.
Read: Charge redistribution takes places between bit line and storage capacitance
Voltage swing is small; typically around 250 mV
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1-Transistor DRAM Cell
➢ 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution
read-out
➢ DRAM memory cells are single-end in contrast to SRAM cells.
➢ The read-out of the 1T DRAM cell is destructive; read and refresh operations are
necessary for correct operation.
➢ Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be
explicitly included in the design.
➢ When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss
can be circumvented by bootstrapping the word lines to a higher value than VDD
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Read-Only Memory
Internal Logic 32 X 8 ROM
In General for 2k X n ROM
K x 2k Decoder and n OR gates
Each OR gate has 2k inputs
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
Address 3 = 10110010 is permanent storage using fuse link
X : means connection
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
1. Masking During Metallization
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
2. Fuse (PROM)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
3. EPROM
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
3. EPROM
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
4. EEPROM
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Programming the ROM
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
Example: Design a combinational circuit using a ROM. The
circuit accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programming the ROM
Example: Design a combinational circuit using a ROM. The
circuit accepts a 3-bit number and generates an output binary
number equal to the square of the input number.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOS OR ROM
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MOS NOR ROM
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MOS NAND ROM
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Pre-charged MOS NOR ROM
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Row Decoders
Example 8 bit Decoder
1. Implementation 8 Inverters + 256 NAND
2. Implementation 8 Inverters + 256 NOR
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Row Decoders
Multi-stage implementation improves performance
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Row Decoders
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4-to-1 tree based column decoder
Number of devices drastically reduced. Delay increases quadratically with # of sections;
prohibitive for large decoders
Solution : Buffers
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Programable Logic Array (PLA)
Programmable device capable of implementing
functions expressed in SOP.
➢ Consists of input buffers and inverters followed by:
➢ Programmable AND plane, followed by
➢ Programmable OR plane.
➢ Can implement m logic functions of n variables. Limit is the number of
product terms that can be generated inside of the device.
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Programable Logic Array (PLA)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Logic Array (PLA)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Array Logic Array (PAL)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Array Logic Array (PAL)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Array Logic Array (PAL)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Array Logic Array (PAL)
Example
W(A, B, C, D) = ∑ (2, 12, 13)
X(A, B, C, D) = ∑ (7,8,9,10,11,12,13,14,15)
Y(A, B, C, D) = ∑ (1,2,8,12,13)
W(A, B, C, D) = ABC’ + A’B’CD’
X(A, B, C, D) = A + BCD
Y(A, B, C, D) = ABC’ + A’B’CD’+ AC’D’ + A’B’C’D
= W + AC’D’ + A’B’C’D
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Programable Array Logic Array (PAL)
Example
W(A, B, C, D) = ABC’ + A’B’CD’
X(A, B, C, D) = A + BCD
Y(A, B, C, D) = W + AC’D’ + A’B’C’D
Product AND Inputs Outputs
A B C D w
1 1 1 0 -- -- W = ABC’ + A’B’CD’
2 0 0 1 0 -- Section 1
3 -- -- -- -- --
4 1 -- -- -- -- X = A + BCD
5 -- 1 1 1 -- Section 2
6 -- -- -- -- --
7 -- -- -- -- 1 Y = W + AC’D’ + A’B’C’D
8 1 -- 0 0 -- Section 3
9 0 0 0 1 --
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Programable Array Logic Array (PAL)
Example
W(A, B, C, D) = ABC’ + A’B’CD’
X(A, B, C, D) = A + BCD
Y(A, B, C, D) = W + AC’D’ + A’B’C’D
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Flash Storage
• Most prominent solid state storage technology
– No other technology is available at scale
• NAND- and NOR- flash types available
– NOR-flash can be byte-addressed, expensive
– NAND-flash is page addressed, cheap
– Except in very special circumstances, all flash-storage we see are NAND-flash
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Flash Storage
Flash memories store information in memory cells made from floating gate transistors.
NOR flash is faster to read than NAND flash, but it's also more expensive.
NAND has a higher memory capacity than NOR.
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Flash Storage
NOR flash
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Flash Storage
NOR flash
NOR FLASH memories are very fast to program and read. Erasure through tunneling is
much slower. However, this kind of array suffers from low density due to the same
reason that impacts NOR ROM density the need for multiple grounds.
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Flash Storage
NAND flash
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Content Addressable Memory (CAM)
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CAMs
10T CAM Cell
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CAMs
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Thank you
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Advanced VLSI Design: 2021-22
Lecture 12-A: Low Power VLSI Design
Part-1: Gate Level Optimization
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Overview of Power Consumption
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Overview of Power Consumption
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Overview of Power Consumption
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Transition Activity
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Transition Activity
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Transition Activity
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Transition Activity
• Low-Power Gate-Level Design
• Low-Power Architecture-Level Design
• Algorithmic-Level Power Reduction
• RTL Techniques for Optimizing Power
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Gate-Level Design – Technology Mapping
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Gate-Level Design – Technology Mapping
𝛼1 = (1 − 0.2 ∗ 0.2 ) 0.2 ∗ 0.2 = 0.0384
𝛼2 = (1 − 0.04 ∗ 05 ) 0.04 ∗ 0.5 = 0.0196
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Gate-Level Design – Technology Mapping
Switching Activity Minimization in
Combinational Logic Design
R. V. Menon, S. Chennupati, N. K.
Samala, D. Radhakrishnan and B. Izadi
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Gate-Level Design – Phase Assignment
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Gate-Level Design – Pin Swapping
➢ An input signal to a gate is called critical if it is the last signal of all inputs to assume a
stable value.
➢ The path through the logic which determines the ultimate speed of the structure is called
the critical path.
➢ Putting the critical-path transistors closer to the output of the gate can result in a speed-up.
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Gate-Level Design – Pin Swapping
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Gate-Level Design – Glitching Power
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Gate-Level Design – Glitching Power
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Static Glitch Example
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Static Glitch Elimination
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Static Glitch Elimination
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Gate-Level Design – Precomputation
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Gate-Level Design – Precomputation
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Gate-Level Design – Clock Gating
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Gate-Level Design – Clock Gating
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Gate-Level Design – Input Gating
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Reduced-Power Shift Register
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Thank you
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design: 2021-22
Lecture 12-B: Low Power VLSI Design
Part-2: Architecture, Algorithmic &
RTL Level Optimization
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Architecture-Level Design – Parallelism
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Architecture-Level Design – Pipelining
Performance Figure Circuit (a) Circuit (b)
Function Delay in ns 2 ns 2 ns
Throughput @ 2ns @ 1 ns
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Architecture-Level Design – Retiming
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Architecture-Level Design – Retiming
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Architecture-Level Design – Bus Segmentation
• Avoid the sharing of resources
Reduce the switched capacitance
• For example: a global system bus
A single shared bus is connected to all modules, this structure results in
a large bus capacitance due to
The large number of drivers and receivers sharing the same bus
The parasitic capacitance of the long bus line
• A segmented bus structure
Switched capacitance during each bus access is significantly reduced
Overall routing area may be increased
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Architecture-Level Design – Bus Segmentation
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Algorithmic-Level Design – factivity Reduction
• Two-bit binary counter:
State sequence, 00 → 01 → 10 → 11 → 00
Six bit transitions in four clock cycles
6/4 = 1.5 transitions per clock
• Two-bit Gray-code counter
State sequence, 00 → 01 → 11 → 10 → 00
Four bit transitions in four clock cycles
4/4 = 1.0 transitions per clock
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Algorithmic-Level Design – factivity Reduction
Binary Counter
Gray Counter
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Algorithmic-Level Design – factivity Reduction
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Algorithmic-Level Design – factivity Reduction
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FSM State Encoding
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Bus Encoding for Reduced Power
• Example: Four bit bus
0000 → 1110 has three transitions.
If bits of second pattern are inverted then 0000 ,
then 0000 → 0001 will have only one transition.
• Bit-inversion encoding for N-bit bus
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Bus Encoding for Reduced Power
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RTL-Level Design – Datapath Reordering
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RTL-Level Design – Memory Partition
BHE
BHE
BHE
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
RTL-Level Design – Memory Partition
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
RTL-Level Design – Memory Partition
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Thank you
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Advanced VLSI Design : 2021-22
Lecture 12 C
Low Power VLSI Design – Part-3
Adiabatic Logic
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Adiabatic Logic
1. Adiabatic Operation
2
Adiabatic Logic
CMOS Symmetric Pass Gate Adiabatic Logic
3
Adiabatic Logic
4
Adiabatic Logic vs. Static CMOS
Sanjay Vidhyadharan et all “An advanced adiabatic logic using Gate Overlap Tunnel FET
(GOTFET) devices for ultra-low power VLSI sensor applications”
5
Thank you
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Advanced VLSI Design : 2021-22
Lecture 13
Interconnects
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Interconnects
• Chips are mostly made of wires called interconnect
– In stick diagram, wires set size
– Transistors are little things under the wires
– Many layers of wires
• Wires are as important as transistors
– Speed
– Power
– Noise
– Area
• Alternating layers run orthogonally
2
Wire Geometry
3
Layer Stack
4
Choice of Metals
5
Metal Layers 45 nm Technology
6
Wire Resistance
7
Sheet Resistance
8
Contacts Resistance
9
Wire Capacitance
10
Capacitance Trends
11
Capacitance Trends
12
Capacitance Trends
13
Polysilicon
• Diffusion capacitance is very high (about 2 fF/mm)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion runners for wires!
• Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between gates
14
Lumped Element Models
15
Lumped Element Models
L Model
The delay of a wire is a quadratic function of its length! This means that doubling
the length of the wire quadruples its delay
16
Lumped Element Models
Example
17
Lumped Element Models
Elmore delay model
18
Repeaters
19
Repeaters
20
Crosstalk
A capacitor does not like to change its voltage instantaneously
A wire has high capacitance to its neighbor
When the neighbor switches from 1→0 or 0→1, the wire tends
to switch too Called capacitive coupling or crosstalk
Crosstalk effects
Noise on nonswitching wires
Increased delay on switching wires
21
Crosstalk Delay
22
Crosstalk
𝐶𝑎𝑑𝑗 ∆𝑉𝑎𝑔𝑔 − ∆𝑉𝑣𝑖𝑐 = 𝐶𝑔𝑛𝑑 (∆𝑉𝑣𝑖𝑐 )
23
Crosstalk
Driven Victims
If the noise is less than the noise margin, nothing happens Static CMOS logic will eventually
settle to correct output even if disturbed by large noise spikes
But glitches cause extra delay, also cause extra power from false transitions
Dynamic logic never recovers from glitches.
Memories and other sensitive circuits also can produce the wrong answer
24
Thank you
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Advanced VLSI Design : 2021-22
Lecture 14-A
Deep-Submicron MOSFET operation
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET Operation
Cut-off Region
𝐹𝑜𝑟 𝑉𝐺𝑆 < 𝑉𝑇 𝐼𝐷 = 0
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The Threshold Voltage
As a practical definition, The threshold Voltage VT is that gate voltage when
the surface is said to be inverted, i.e. the density of mobile electrons on the
surface becomes equal to the density of holes in the bulk (p-type) substrate.
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The Threshold Voltage
1. The work function difference TGC between the gate
and the channel reflects the built-in potential of the MOS
system, which consists of the
p-type substrate, the thin silicon dioxide layer, and the
gate electrode. Depending on the gate material, the work
function difference is
∅𝐺𝐶 = ∅𝐹_𝑆𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 - ∅𝐹𝑚𝑒𝑡𝑎𝑙 𝐹𝑜𝑟 𝑀𝑒𝑡𝑎𝑙 𝐺𝑎𝑡𝑒
∅𝐺𝐶 = ∅𝐹_𝑆𝑢𝑏𝑠𝑡𝑟𝑎𝑡𝑒 - ∅𝐹𝑃𝑜𝑙𝑦𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝐹𝑜𝑟𝑃𝑜𝑙𝑦𝑠𝑖𝑙𝑖𝑐𝑜𝑛 𝐺𝑎𝑡𝑒
2. The externally applied gate voltage must be changed to
achieve surface inversion, i.e., to change the surface
potential by - 2 ∅ F. This will be the second component of
the threshold voltage.
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The Threshold Voltage
3. Another component of the applied gate voltage is necessary
to offset the depletion region charge, which is due to the fixed
acceptor ions located in the depletion region near the surface.
4. There always exists a fixed positive charge density Qox at
the interface between the gate oxide and the silicon
substrate, due to impurities and/or lattice imperfections at
the interface. The gate voltage component that is necessary
to offset this positive charge at the interface is - QOX/Cox.
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The Threshold Voltage
The body effect occurs in a MOSFET when the source is not tied to the substrate
(which is always connected to the most negative power supply in the integrated circuit
for n-channel devices and to the most positive for p-channel devices). The substrate
then acts as a “second gate” or a back-gate for the MOSFET
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MOSFET Current
Linear Region- Small VDS
𝑉𝑜𝑣 = 𝑉𝐺𝑆 - 𝑉𝑇
𝑄
𝐶𝑜𝑥 𝑊𝐿 =
𝑉𝑜𝑣
𝑄
𝐶ℎ𝑎𝑟𝑔𝑒 𝑝𝑒𝑟 𝑢𝑛𝑖𝑡 𝐿𝑒𝑛𝑔𝑡ℎ = = 𝐶𝑜𝑥 𝑊𝑉𝑜𝑣
𝐿
𝑉𝐷𝑆
𝐸𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝐹𝑖𝑒𝑙𝑑 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 =
𝐿
𝑉𝐷𝑆 µ𝑛
𝑉𝑒𝑙𝑜𝑐𝑖𝑡𝑦 𝑜𝑓 𝐶ℎ𝑎𝑟𝑔𝑒 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙(𝑣) = µ𝑛 𝐸 =
𝐿
𝑄 𝑉𝐷𝑆 µ𝑛
𝐶𝑢𝑟𝑟𝑒𝑛𝑡 𝑖𝑛 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 (𝐼𝐷 ) = 𝑣 ∗ 𝐿 = * 𝐶𝑜𝑥 𝑊𝑉𝑜𝑣
𝐿
µ𝑛𝐶𝑜𝑥 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET Current
Linear Region- Small VDS
𝑉𝑜𝑣
µ𝑛𝐶𝑜𝑥 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
µ𝑛𝐶𝑜𝑥 𝑊𝑉𝑜𝑣
𝑇𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 𝑔𝐷𝑆 =
𝐿
𝑘𝑛′ 𝑊𝑉𝑜𝑣 𝑉𝐷𝑆
𝑃𝑟𝑜𝑐𝑒𝑠𝑠 𝑡𝑟𝑎𝑛𝑠𝑐𝑜𝑛𝑑𝑢𝑐𝑡𝑎𝑛𝑐𝑒 𝑝𝑎𝑟𝑎𝑚𝑒𝑡𝑒𝑟 𝑘𝑛′ = µ𝑛𝐶𝑜𝑥 𝐼𝐷 =
𝐿
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET Current
Linear Region as VDS is Increased
Charge in the tapered channel is proportional to the
channel cross-sectional area
𝑉𝐷𝑆
𝑘𝑛′ 𝑊(𝑉𝑜𝑣 − 2 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET Current
Saturation Region
𝑉𝐷𝑆 = 𝑉𝑜𝑣 = 𝑉𝐺𝑆 - 𝑉𝑇
𝑉𝐷𝑆
𝑘𝑛′ 𝑊(𝑉𝑜𝑣 − 2 )𝑉𝐷𝑆
𝐼𝐷 =
𝐿
𝑘𝑛′ 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2𝐿
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET Current
𝑘𝑛′ 𝑊(𝑉𝐺𝑆 − 𝑉𝑇 )2
𝐼𝐷 =
2𝐿
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET BODY CONNECTION
➢ NMOS Body to Lowest Possible Potential (Gnd)
➢PMOS Body to Highest Possible Potential (VDD)
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET BODY CONNECTION
5/8/2022 13
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET BODY CONNECTION
5/8/2022 14
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET BODY CONNECTION
➢ NMOS Double well : Body not same as Substrate
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET LATCH
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET LATCH
5/8/2022 17
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
MOSFET LATCH
5/8/2022 18
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Deep-submicron MOSFET operation
5/8/2022 19
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Deep-submicron MOSFET operation
➢ Threshold voltage reduction
➢ VT Roll Off
➢ Drain-induced barrier lowering (DIBL)
➢ Mobility degradation due to a vertical field
➢ Velocity saturation effects
➢ Channel length modulation
➢ Subthreshold (weak inversion) conduction
➢ Hot-electron effects on output resistance
5/8/2022 20
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
VT Variation
➢ VT Roll Off
➢ Drain-induced barrier lowering (DIBL)
5/8/2022 21
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Mobility Degradation
There also exists a normal (vertical) field originating from the gate voltage that further
inhibits channel carrier mobility. This effect, which is called mobility degradation, reduces
the surface mobility with respect to the bulk mobility.
5/8/2022 22
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Velocity Saturation Effect
When the electric field reaches a critical value EC the velocity of the carriers tends to
saturate.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Velocity Saturation Effect
5/8/2022 24
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Velocity Saturation Effect
5/8/2022 25
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Channel Length Modulation
When the VDS is increased beyond VOV , the pinch-off point is moved slightly away from the drain,
toward the source. The additional voltage applied to the drain appears as a voltage drop across the narrow
depletion region between the end of the channel and the drain region. This voltage accelerates the
electrons that reach the drain end of the channel and sweeps them across the depletion region into the
drain.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Channel Length Modulation
5/8/2022 27
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Channel Length Modulation
𝑉𝐴 𝐸𝑎𝑟𝑙𝑦 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
1
𝜆= λ ∝ 1/L
𝑉𝐴
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Subthreshold Conduction
where IS and n are empirical parameters, with
n > 1 and typically ranging around 1.5.
Subthreshold current has some important repercussions. In general, we want the
current through the transistor to be as close as possible to zero at VGS = 0. This is
especially important in the so-called dynamic circuits, which rely on the storage of
charge on a capacitor and whose operation can be severely degraded by subthreshold
leakage.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Hot Carrier Effects
Increase in the electric field strength causes an increasing energy
of the electrons.
➢ Some electrons are able to leave the silicon and tunnel into the gate oxide.
➢ Such electrons are called “Hot carriers”.
➢ Electrons trapped in the oxide change the VT of the transistors.
➢ This leads to a long term reliability problem.
➢ For an electron to become hot an electric field of 104 V/cm is necessary.
➢ This condition is easily met with channel lengths below 1µm.
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ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
5/8/2022 31
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Advanced VLSI Design : 2021-22
Lecture 14-B
CMOS Scaling
By Dr. Sanjay Vidhyadharan
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
• Currently, technology scaling has a threefold objective:
– Reduce the gate delay by 30% (43% increase in frequency)
– Double the transistor density
– Saving 50% of power (at 43% increase in frequency)
• How is scaling achieved?
– All the device dimensions (lateral and vertical) are reduced by 1/
– Concentration densities are increased by
– Device voltages reduced by 1/ (not in all scaling methods)
– Typically 1/ = 0.7 (30% reduction in the dimensions)
Trieste, 8-10
CMOS technology 2
November 1999
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
• The scaling variables are:
– Supply voltage: Vdd → Vdd /
– Gate length: L → L/
– Gate width: W → W/
– Gate-oxide thickness: tox → tox /
– Junction depth: Xj → Xj /
– Substrate doping: NA → NA × α
This is called constant field scaling because the electric field across
the gate-oxide does not change when the technology is scaled
If the power supply voltage is maintained constant the scaling is called
constant voltage. In this case, the electric field across the gate-oxide
increases as the technology is scaled down.
Due to gate-oxide breakdown, below 0.8µm only “constant field”
scaling is used.
3
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
Some consequences 30% scaling in the
constant field regime ( = 1.43, 1/ = 0.7):
• Device/die area:
W L → (1/)2 = 0.49
– In practice, microprocessor die size grows about 25% per technology
generation! This is a result of added functionality.
• Transistor density:
(unit area) /(W L) → 2 = 2.04
– In practice, memory density has been scaling as expected.
(not true for microprocessors…)
4
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
• Gate capacitance:
W L / tox → 1/ = 0.7
• Drain current:
(W/L) (V2/tox) → 1/ = 0.7
• Gate delay:
(C V) / I → 1/ = 0.7
Frequency → = 1.43
– In practice, microprocessor frequency has doubled every
technology generation (2 to 3 years)! This faster increase rate is
due to two factors:
• the number of gate delays in a clock cycle decreases with time (the
designs become highly pipelined)
• advanced circuit techniques reduce the average gate delay beyond
30% per generation.
5
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
• Power:
C V2 f → (1/)2 = 0.49
• Power density:
1/tox V2 f → 1
• Active capacitance/unit-area:
•
Power dissipation is a function of the operation frequency, the power
supply voltage and of the circuit size (number of devices).
If we normalize the power density to V2 f we obtain the active
capacitance per unit area for a given circuit. This parameter can be
compared with the oxide capacitance per unit area:
1/tox → = 1.43
– In practice, for microprocessors, the active capacitance/unit-area
only increases between 30% and 35%. Thus, the twofold
improvement in logic density between technologies is not
achieved.
6
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
• Interconnects scaling:
– Higher densities are only possible if the interconnects
also scale.
– Reduced width → increased resistance
– Denser interconnects → higher capacitance
– To account for increased parasitics and integration
complexity more interconnection layers are added:
• thinner and tighter layers → local interconnections
• thicker and sparser layers → global interconnections and
power
Interconnects are scaling as expected
7
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
Quantity Sensitivity Constant Field Constant Voltage
Scaling Parameters
Length L 1/S 1/S
Width W 1/S 1/S
Gate Oxide Thickness tox 1/S 1/S
Supply Voltage Vdd 1/S 1
Threshold Voltage VT0 1/S 1
Doping Density NA, ND S S2
Device Characteristics
Area (A) WL 1/S2 1/S2
W/Ltox S S
D-S Current (IDS) (Vdd - vT)2 1/S S
Gate Capacitance (Cg) WL/tox 1/S 1/S
Transistor On-Resistance (Rtr) Vdd/IDS 1 S
Intrinsic Gate Delay () RtrCg 1/S 1/S
Clock Frequency f f f
Power Dissipation (P) IDSVdd 1/S2 S
Power Dissipation Density (P/A) P/A 1 S3 8
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
Lithography:
Optics technology Technology node
248nm mercury-xenon lamp 180 - 250nm
248nm krypton-fluoride laser 130 - 180nm
193nm argon-fluoride laser 100 - 130nm
157nm fluorine laser 70 - 100nm
13.4nm extreme UV 50 - 70nm
9
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Technology Scaling
Lithography:
• Electron Beam Lithography (EBL)
– Patterns are derived directly from digital data
– The process can be direct: no masks
– Pattern changes can be implemented quickly
– However:
• Equipment cost is high
• Large amount of time required to access all the points
on the wafer
CMOS technology 10
ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION
Thank you
5/8/2022 11
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