Combinational Building Blocks – Decoder

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One-hot representation

• Represent a set of N elements with N bits

• Exactly one bit is set
• Example – encode numbers 0-7
Binary One-hot
000 00000001
001 00000010
010 00000100
… …
110 01000000
111 10000000

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 Decoder

• A decoder converts symbols from one code to another.

• A binary to one-hot decoder converts a symbol from binary code
to a one-hot code.
– One-hot code: exactly one bit is high at any given time and
each bit represents a symbol.

Decoder
Binary input a to one-hot output b
b[i] = 1 if a = i a b
n m
b = 1<<a
n
m≤2

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Example

2 4 Decoder
a1
a0

a1 a0 b3 b2 b1 b0
0 0 0 0 0 1
0 1 0 0 1 0 b3
1 0 0 1 0 0
1 1 1 0 0 0 b2

b1

b0

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 Can build a large decoder from several small
decoders
• Example – build a 6 : 64 decoder from three 2 : 4 decoders
• Each 2 : 4 decodes 2 bits
• a[5:4]→x[3:0], a[3:2]→y[3:0], a[1:0]→z[3:0]
• AND one bit each of x, y, and z to generate an output
• b[a] = x[a[5:4]] & y[a[3:2]] & z[a[1:0]]

a5 a4 x3 x2 x1 x0 a3 a2 y3 y2 y1 y0 a1 a0 z3 z2 z1 z0
0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1
0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0
1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0
1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0

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2-Stage decoders

a[5:0]
6 a[5:4] a[3:2] a[1:0]
2 2 2

2:4 2:4 2:4

4 4 4
z[3]
y[3] b63
x[3]
z[2]
y[3] b62
x[3]
x[3:0]

y[3:0]

z[3:0]

z[0]
y[0] b0
x[0]

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 Verilog implementation of a decoder

// a - binary input (n bits wide)

// b - one hot output (m bits wide)
module Dec(a, b) ;
parameter n=2 ;
parameter m=4 ;

input [n-1:0] a ;

Decoder
output [m-1:0] b ;

wire [m-1:0] b = 1<<a ;

endmodule a b
n m
m ≤ 2n

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 Logic implementation using decoder
Example – 3-bit prime number function

3:8
in [2 :0 ] b [7 :0 ]
3 8 b [7 ]
b [5 ]
b [3 ] i sp ri me

b [2 ]
module Primed(in, isprime) ;
input [2:0] in ; b [1 ]
output isprime ;
wire [7:0] b ;
// compute the output as the OR of the required minterms
wire isprime = b[1] | b[2] | b[3] | b[5] | b[7] ;
// instantiate a 3->8 decoder
Dec #(3,8) d(in,b) ;
endmodule

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Combinational Building Blocks – Encoder

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 Encoder

• An encoder is an inverse of a decoder.

• Encoder is a logic module that converts a one-hot input signal to a binary-
encoded output signal.
• Example: a 4 : 2 encoder.

a3

a2

a1

a0
a3 a2 a1 a0 b1 b0
0 0 0 1 0 0
0 0 1 0 0 1
b1
0 1 0 0 1 0
1 0 0 0 1 1
b0
b0 = a3  a1

b1 = a3  a2
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 Designing a large encoder – 16 : 4 from five 4 : 2
encoders
Need an ‘any input true’ output on first rank of encoders
First rank encodes low bits, second rank encodes high bits
Repeat as needed
High bits
Low bits

4:2
a[15:12]
4 2

4:2
4:2
a[11:8] b[3:2]
4 2 2
One hot or all zero
4:2

a[7:4]
4 2

b[1:0]
4:2

a[3:0]
2
4 2
Summary

• Assemble combinational circuits from pre-defined building blocks

– Decoder – converts codes (e.g., binary to one-hot)
– Encoder – encodes one-hot to binary
– Multiplexer – select an input (one-hot select)
– Arbiter – pick first true bit
– Comparators – equality and magnitude
– ROMs
– RAMs
– PLAs
• Divide and conquer to build large units from small units
– Decoder, encoder, multiplexer
• Logic with multiplexers or decoders
• Bit-slice coding style
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Combinational Building Blocks – MUX

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 Multiplexer

• Multiplexer:
– n k-bit inputs
– n-bit one-hot select signal s
– Multiplexers are commonly used as data selectors

Selects one of n k-bit inputs

s must be one-hot
b = ai if s[i] = 1

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Multiplexer Implementation

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// four input k-wide mux with one-hot select
module Mux4(a3, a2, a1, a0, s, b) ;
parameter k = 1 ;
input [k-1:0] a0, a1, a2, a3 ; // inputs
input [3:0] s ; // one-hot select
output[k-1:0] b ;
wire [k-1:0] b = ({k{s[0]}} & a0) |
({k{s[1]}} & a1) |
({k{s[2]}} & a2) |
({k{s[3]}} & a3) ;
endmodule

Mux4 #(2) mx(2'd3, 2'd2, 2'd1, 2'd0, f, h) ;

f h
# 0001 00
# 0010 01
# 0100 10
# 1000 11
module Mux3a(a2, a1, a0, s, b) ;
parameter k = 1 ;
input [k-1:0] a0, a1, a2 ; // inputs
input [2:0] s ; // one-hot select
output[k-1:0] b ;
reg [k-1:0] b ;

always @(*) begin

case(s)
3'b001: b = a0 ;
3'b010: b = a1 ;
3'b100: b = a2 ;
default: b = {k{1'bx}} ;
endcase
end
endmodule
k-bit Binary-Select Multiplexer

Selects one of n k-bit inputs

b = ai if sb = i

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k-bit Binary-Select Multiplexer

s1
s0

a0
k b
k a3
an-1
k
a2
Decoder

b
s
a b
m n a1

a0

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Implementing k-bit Binary-Select Multiplexer using Verilog
// 3:1 multiplexer with binary select (arbitrary width)
module Muxb3(a2, a1, a0, sb, b) ;
parameter k = 1 ;
input [k-1:0] a0, a1, a2 ; // inputs
input [1:0] sb ; // binary select
output[k-1:0] b ;
wire [2:0] s ;

Dec #(2,3) d(sb,s) ; // Decoder converts binary to one-hot

Mux3 #(k) m(a2, a1, a0, s, b) ; // multiplexer selects input
endmodule

a0
k b
an-1 k
k

Decoder
s a b
m n
// 3:1 multiplexer with binary select (arbitrary width)
module Muxb3a(a2, a1, a0, sb, b) ;
parameter k = 1 ;
input [k-1:0] a0, a1, a2 ; // inputs
input [1:0] sb ; // binary select
output[k-1:0] b ;
reg [k-1:0] b ;

always @(*) begin

case (sb)
0 : b = a0 ;
1 : b = a1 ;
2 : b = a2 ;
default: b = {k{1'bx}} ;
endcase
end

endmodule

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 Implementing a large one-hot select mux using
small ones

// 6:1 multiplexer with one-hot select (arbitrary width)

module Mux6a(a5, a4, a3, a2, a1, a0, s, b) ;
parameter k = 1 ;
input [k-1:0] a0, a1, a2, a3, a4, a5 ; // inputs
input [5:0] s ; // one-hot select
output[k-1:0] b ;
wire [k-1:0] ba, bb ;

assign b = ba | bb ;

Mux3 #(k) ma(a2, a1, a0, s[2:0], ba) ;

Mux3 #(k) mb(a5, a4, a3, s[5:3], bb) ;
endmodule

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Implementing a large binary-select mux using
small ones

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 Logic with Muxes

module Primem(in, isprime) ;

input [2:0] in ;
output isprime ;

Muxb8 #(1) m(1, 0, 1, 0, 1, 1, 1, 0, in, isprime) ;

endmodule
Summary

• Assemble combinational circuits from pre-defined building blocks

– Decoder – converts codes (e.g., binary to one-hot)
– Encoder – encodes one-hot to binary
– Multiplexer – select an input (one-hot select)
– Arbiter – pick first true bit
– Comparators – equality and magnitude
– ROMs
– RAMs
– PLAs
• Divide and conquer to build large units from small units
– Decoder, encoder, multiplexer
• Logic with multiplexers or decoders
• Bit-slice coding style
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Combinational Building Blocks - Arbiter

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 Arbiter

Arbiter handles requests from multiple devices to use a single resource

Arbiter
r g
n n

Finds first “1” bit in r

g[i]=1 if r[i]=1 and r[j]=0 for j>i

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Logic Diagram of one Bit of an Arbiter
Two Implementations of a 4-bit Arbiter

Using bit-cell Using look-ahead

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 Arbiter using Verilog with LSB as the highest priority

// arbiter (arbitrary width)

module Arb(r, g) ;
parameter n=8 ;
input [n-1:0] r ;
output [n-1:0] g ;
wire [n-1:0] c ;

assign c = {(~r[n-2:0] & c[n-2:0]),1'b1} ;

assign g = r & c ;

endmodule

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 Priority Encoder

• Priority encoder:
– n-bit input signal a
– m-bit output signal b
– b indicates the position of the first 1 bit in a

Encoder
Arbiter

r g a b
n n m

m= log2n
Encoder
Priority

a b
n m

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 Verilog for Priority Encoder

// priority encoder (arbitrary width)

module PriorityEncoder83(r, b) ;
input [7:0] r ;
output [2:0] b ;
wire [7:0] g ;
Arb #(8) a(r, g) ;
Enc83 e(g, b) ;
endmodule

Encoder
Arbiter

r g a b
n n m

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Summary

• Assemble combinational circuits from pre-defined building blocks

– Decoder – converts codes (e.g., binary to one-hot)
– Encoder – encodes one-hot to binary
– Multiplexer – select an input (one-hot select)
– Arbiter – pick first true bit
– Comparators – equality and magnitude
– ROMs
– RAMs
– PLAs
• Divide and conquer to build large units from small units
– Decoder, encoder, multiplexer
• Logic with multiplexers or decoders
• Bit-slice coding style
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Combinational Building Blocks
- Comparator and shifter

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 Equality Comparator

a3
a
Comparator
eq3
b3
n
eq a2
eq2
b2
eq
b a1
n eq1
b1
// equality comparator a0
eq0
module EqComp(a, b, eq) ; b0
parameter k=8;
input [k-1:0] a, b;
output eq ;

assign eq = (a==b) ;
endmodule

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 Magnitude Comparator

gtbi+1
a
Comparator
n Magnitude
gt

ai
b gti
n

eqi
// magnitude comparator bi

gtbi
module MagComp(a, b, gt) ;
parameter k=8 ;
input [k-1:0] a, b ;
output gt ;
wire [k-1:0] eqi = a ~^ b ;
wire [k-1:0] gti = a & ~b ;
wire [k:0] gtb {((eqi[k-1:0] & gtb[k-1:0]) | gti[k-1:0]), 1’b0} ;
wire gt = gtb[k] ;
endmodule

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// Behavioral Magnitude comparator
module MagComp_b(a, b, gt) ;
parameter k=8 ;
input [k-1:0] a, b ;
output gt ;

assign gt = (a > b) ;
endmodule

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Putting things together – Maximum unit

a
n n 1 ma x

Mux
0 n
n
a Comparator
Magnitude
a>b
gt

b
b
n

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 Shifters

module ShiftLeft(n, a, b) ;
parameter k=8 ;
parameter lk=3 ;
input [lk-1:0] n ;
input [k-1:0] a ;
output [2*k-2:0] b ;
assign b = a<<n ;
endmodule

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module BarrelLeftShift(n, a, b) ;
parameter k=8 ;
parameter lk=3 ;
input [lk-1:0] n ;
input [k-1:0] a ;
output [k-1:0] b ;
wire [2*k-2:0] x = a<<n ;
assign b = x[k-1:0] | {1'b0, x[2*k-2:k]} ;
endmodule

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Summary

• Assemble combinational circuits from pre-defined building blocks

– Decoder – converts codes (e.g., binary to one-hot)
– Encoder – encodes one-hot to binary
– Multiplexer – select an input (one-hot select)
– Arbiter – pick first true bit
– Comparators – equality and magnitude
– Shifters
– ROMs, RAMs
– PLAs
• Divide and conquer to build large units from small units
– Decoder, encoder, multiplexer
• Logic with multiplexers or decoders
• Bit-slice coding style
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Combinational Building Blocks
- ROM, RAM, PLA

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Read-only memory (ROM)

a d
a ROM d
n m

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 Conceptual block diagram
w0
d0

w1

Decoder
d1
a
n

m
w 2n -1
d2n -1

m
 2-D array implementation
w0
d0 d1 d2 d3
256 word x
16 bit/word ROM
64 rows x 64 columns
w1

Decoder
d4 d5 d6 d7
a7:2
6

a
8 w63
d252 d253 d254 d255

16 16 16 16

a1:0
Multiplexer

16
Read-write memory (RAM)

46
Dual-port RAM implementation
Programmable logic array