ECPE13

Computer Architecture and

Organization
Dr. P. Maheswaran
Assistant Professor, Dept. Of ECE
NIT Trichy

[email protected]
 Syllabus
Unit 2: Representation of Instructions


Machine instructions

Memory locations & Addresses, Operands

Addressing modes

Instruction formats, Instruction sets

Instruction set architectures - CISC and RISC architectures

Superscalar Architectures

Fixed point and floating point operations
Machine instructions:

The operation of the processor is determined by the instructions it executes.

Referred to as machine instructions or computer instructions.

The processor’s instruction set: The collection of different instructions that the processor can execute.
Elements of a Machine Instruction:

Operation code (opcode): Specifies the operation to be performed (e.g., ADD, I/O).

Source operand reference: Operands that are inputs for the operation.

Result operand reference: The operation may produce a result.

Next instruction reference: The next instruction address for the processor.
Source and result operands can be in:

Main or virtual memory: Address reference.

Processor register: With rare exceptions, a processor contains one or more registers that may be
referenced by machine instructions.

Immediate: The value of the operand is contained in a field in the instruction being executed.

I/O device: The instruction must specify the I/O module and device for the operation.
Instruction Representation:


An instruction is read into an instruction register (IR) in the processor during execution.

The processor extracts the data from the various instruction fields to perform the required operation.

Binary representations of machine instructions are given symbolic representation or mnemonics.

Operands are also represented symbolically.

Add the content of location Y to the content of register R.

Y is the address in memory.

Operations are performed on location, not on its address.
Instruction Types:

A statement in high level language: X = Y + X.

Assume location of X is 513, location of Y is 514.

The operation is accomplished with three instructions:

The single BASIC instruction may require three machine instructions.

A high-level language expresses operations in a concise algebraic form, using variables.

A machine language expresses operations in a basic form:

Involving the movement of data to or from registers.

A computer should have a set of instructions that allows the user to formulate any data processing task.

Must be sufficient to express any of the instructions from a high-level language.

Categorize instruction types as:

Data processing: Arithmetic and logic instructions.

Data storage: Movement of data into or out of register and or memory locations.

Data movement: I/O instructions.

Control: Test and branch instructions.
Operands:

Machine instructions operate on data.

The most important general categories of data are:

Addresses – discussed later.

Numbers

Characters

Logical data
Numbers:

All machine languages include numeric data types.

In nonnumeric data proessing, there is a need for numbers to act as counters, field widths, etc.

Numbers stored in a computer are limited.

A limit to the magnitude of numbers representable on a machine.

The case of floating-point numbers, a limit to their precision.

The programmer has to understand the consequences of rounding, overflow, and underflow.
Operands: Numbers

Three types of numerical data are common in computers:

Binary integer or binary fixed point

Binary floating point

Decimal

The human users of the system deal with decimal numbers.

In packed decimal representation, each decimal digit is represented by a 4-bit code, with two digits stored
per byte.

To form numbers, 4-bit codes are strung together: 246 is 0000 0010 0100 0110.

The code is less compact than a straight binary representation, avoids conversion.

Negative numbers are represented by including a 4-bit sign digit

Either the left or right end of a string of packed decimal digits.

1100 for positive (+), 1101 for negative (-).
Operands: Characters

Computers store binary data. Textual data are convenient for humans.

Codes are devised by which characters are represented by a sequence of bits.

The most commonly used character code in the International Reference Alphabet (IRA):

AKA American Standard Code for Information Interchange (ASCII).

Each character in this code is represented by a unique 7-bit pattern.

128 different characters can be represented.

The eighth bit may be set to 0 or used as a parity bit for error detection.

The bit is set such that the total number of binary 1s in each octet:

Is always odd (odd parity) or always even (even parity).

For IRA bit pattern 011XXXX:

0 -- 0000, 9 – 1001, the rightmost 4 bits.

For other languages:

Unicode Transformation Format(UTF)

UTF-7, UTF-8, UTF-16, UTF-32.
 Operands: Characters

For other languages:

Unicode Transformation Format (UTF)

UTF-7, UTF-8, UTF-16, UTF-32.
Block:U+0B80 -
Block:U+0900 - Tamil
Block 0: Basic Latin
Devanagari

https://www.compart.com/en/unicode/block
Operands: Logical Data

Each word or other addressable unit (byte, halfword, and so on) is treated as a single unit of data.

Sometimes an n-bit unit is considered as consisting of n 1-bit items of data, each item having the value 0 or
1.

When data are viewed this way, they are considered to be logical data.

Scenarios where logical representation is useful:

An array of Boolean or binary data items, in which each item can take on only the values 1 (true) and 0
(false).

Manipulate the bits of a data item. If floating-point operations are implemented in software, we need to be
able to shift significant bits in some operations.

To convert from IRA to packed decimal: extract the rightmost 4 bits of each byte.

The same data are treated sometimes as logical and other times as numerical or text.

The “type” of a unit of data is determined by the operation being performed on it.
Memory Locations and Addresses

The memory is organized in a group of n bits.

The can be stored or retrieved in a single, basic operation.

Group of n bits is referred to as a word of information, n is called the word length.

Modern computers have word lengths that typically range from 16 to 64 bits.

If the word length of a computer is 32 bits:

A single word can store a 32-bit signed number or four ASCII-encoded characters.

Machine instructions may require one or more words for their representation.

Distinct names or addresses for each location to:

Accessing the memory to store or retrieve a single item of information.

The addresses of successive locations in the memory:

The memory can have up to 2k addressable locations.

These addresses constitute the address space of a computer.

32-bit address creates an address space of 2 32 or 4G (4 giga) locations

1G is 230.
Memory Locations and Addresses
Byte Addressability:

A byte is always 8 bits. The word length typically ranges from 16 to 64 bits.

Impractical to assign distinct addresses to individual bit locations in the memory.

A practical approach: Successive addresses refer to successive byte locations in the memory.

Byte locations have addresses 0, 1, 2, . . . .

If the word length of the machine is 32 bits:

Each word consisting of four bytes.

Successive words are located at addresses 0, 4, 8, . . . .
Big-Endian and Little-Endian Assignments:

Two ways byte addresses can be assigned across words.

Big-endian: Lower byte addresses are used for the more significant bytes
(the leftmost bytes) of the word.

Little-endian: Lower byte addresses are used for the less significant bytes
(the rightmost bytes) of the word.
Addressing Modes:

A program operates on data that reside in the computer’s memory.

Data can be organized in a variety of ways.

Programmers use data structures such as lists and arrays for organizing the data used in computations.

The compiler generates appropriate sequences of low-level instructions for a given high-level code.

Addressing modes: Different ways for specifying the locations of instruction operands.
Implementation of variables and constants:

In assembly language, a variable is represented by allocating a register or a memory location to hold its
value.
 Straight-line sequencing
Addressing Modes:

Register mode: The operand is the contents of a processor register; the name of the
register is given in the instruction.

Absolute mode: The operand is in a memory location; the address of this location is given
explicitly in the instruction.


The number of bits that can be used to give an absolute address is limited.

Typically to 16 bits if the word length is 32 bits.

To generate a 32-bit address:

The 16-bit value is usually extended to 32 bits by replicating bit b15 into bit positions
b31−16 (as in sign extension).

The Absolute mode can represent global variables in a program.

High level language declaration:

The compiler to allocate a memory location to each of the variables NUM1, NUM2,
and SUM.
Addressing Modes:
Conditional Branching
Immediate mode: The operand is given explicitly in the instruction.

Example:

A common convention is to use the number sign (#) in front of the value to indicate that
this value is to be used as an immediate operand.

Branch instructions: Loads a new address (called the branch target) into the program
counter.


The processor fetches and executes the instruction at this new address, instead of the
instruction at the location that follows the branch instruction in sequential address order.

A conditional branch instruction causes a branch only if a specified condition is
satisfied.

If the condition is not satisfied, the PC is incremented in the normal way, and the next
instruction in sequential address order is fetched and executed.
Addressing Modes:
 Sometimes, the instruction does not give the operand or its address explicitly.
 It provides information from which an effective address (EA) can be derived by the processor when the instruction is
executed.
 The effective address is then used to access the operand.
 Fig 2.6 requires a capability for modifying the address of the memory operand during each pass through the loop.

Use a processor register to hold the address of the operand.

The contents of the register are then changed (incremented) during each pass.

The register acts as a pointer to the list.

An item in the list is accessed indirectly by using the address in the register.
Register Indirect mode - The effective address of the operand is the contents of a register that is specified in the
instruction.

Indirection is denoted by placing the name of the register given in the instruction
in parentheses.
Addressing Modes:
 Indirection permit the same code to be used to operate on different data.
 Register R5 in Fig 2.7 serves as a pointer for the Load instruction to load an operand from the memory into register
R2.
 At one time, R5 may point to location B in memory.
 Later, the program may change the contents of R5 to point to a different location.

The same Load instruction will load the value from that location into R2.

A program segment that includes Load instruction is conveniently reused with only a change in the pointer value.
 Indirect addressing can be used to access successive numbers in the list.
 Load instruction can operate only on memory source operands.
 The Move instruction is used for immediate values.
Addressing Modes:
 RISC-type processors, one general-purpose register is dedicated to holding a constant value zero.

This is register R0 - contents cannot be changed by a program instruction.
 The Move instruction can be implemented as
 Move is provided as a pseudoinstruction for the convenience of programmers.

It is implemented using the Add instruction.
 Consider the C-language statement:

B is a pointer variable and the ‘*’ symbol is the operator for indirect accesses.

The contents of the memory location pointed to by B to be loaded into memory location A.
 Indirect addressing through registers is used extensively.
Addressing Modes:
Stack Addressing:
 A stack is a linear array of locations.

Referred to as pushdown list or last-in-first-out queue.

The stack is a reserved block of locations.

Items are appended to the top of the stack.

A stack pointer contains the address of the top of the stack.

The stack pointer is maintained in a register.

References to stack locations in memory are in fact register indirect addresses.
 The stack mode of addressing is a form of implied addressing.
 The machine instructions need not include a memory reference.

Implicitly operate on the top of the stack.
Addressing Modes:
Indexing and Arrays:
Index mode-The effective address of the operand is generated by adding a constant value to the contents of a register.

 This is also known as Displacement Addressing.

 Combines the capabilities of direct addressing and register indirect addressing.
 The register used in this mode are the index register.
 The Index mode is given as

X denotes a constant signed integer value contained in the instruction.

Ri is the name of the register involved.
 The effective address of the operand is:
 The contents of the register are not changed in the process.
 Fig. 2.9 (a) – X – offset, R5 – address of memory location.
 Fig. 2.9 (b) – X – memory location, R5 - the offset to the operand.
 The effective address is the sum of two values in either cases.
Indexing and Arrays:
The usefulness of indexed addressing:
 The list of scores, beginning at location LIST.
 A student record: Four-word memory block.

Student ID, three test scores.
 n students in the class, n is stored in location N immediately in front of the list.
 The list is a two-dimensional array having n rows and four columns.

Each row: A student’s entries. Each column: the IDs and test scores.
 The sum of all scores obtained on each of the tests and store these three sums in memory locations SUM1, SUM2,
and SUM3.
 R3, R4, and R5 are initially cleared to 0.
 Scores are accessed using the Index addressing modes

4(R2), 8(R2), and 12(R2)
 The contents of the index register, R2, are not changed
when it is used in the Index addressing mode. It is changed only to move to
next student.
Indexing and Arrays:
 The Index mode facilitates access to an operand:

If its location is defined relative to a reference point within the data structure.

The ID locations of successive student records are the reference points.
 Variants:

Rj used to contain the offset X.

The effective address is the sum of the contents of registers Ri and Rj.

The second register is usually called the base register.

Provides flexibility, both components of the effective address can be changed.
 Variants:

The effective address is the sum of the constant X and the contents of registers Ri and Rj.

Useful in accessing multiple components inside each item in a record. The beginning of an item is specified by the
(Ri,Rj).
 Absolute mode from Index mode:

If content of Ri = 0, index mode becomes absolute mode.
 If R0 = 0, the Absolute mode is X(R0).
Instruction Format:
 Assembly-language instructions symbolically express the actions that must be performed by the processor circuitry.

Must be converted by the assembler program into machine instructions, encoded in a compact binary pattern.
 Add instruction represents a class of three operand instruction.

Operands are stored in processor registers.

Rdst – destination operand register, Rsrc1 and Rsrc2 – source operand register.
 A processor: 32 bits wide, has 32 registers.

Five bits to specify each of the three registers in such instructions = 15 bits.

Remaining 17 bits can be used to specify the OP code that indicates the operation to be performed.

Instruction with immediate addressing mode:

Ten bits are needed to specify the two registers.

Remaining 22 bits must give the OP code and the value of the immediate operand.

Useful sizes of immediate operand: 32, 16, and 8 bits.

Allocate 16 bits for the immediate operand, six bits for specifying the OP code.
Instruction Format:
 (b) can be used for Load and Store instructions.

The Index addressing mode uses the 16-bit field, specify the offset that is added to the contents of the index
register.
 (b) can also be used to encode the Branch instructions.

Branch instruction at 128 can be written as

Content of R0 is zero. R2 and R0 can be specified in two register fields of (b).

The six-bit OP code has to identify the BGT operation.

16-bit immediate field can be for the branch target address (location of LOOP).

The target address generally comprises 32 bits.

The BGT instruction makes use of the immediate field to give an offset from the location.

When at BGT, PC = 132 (next instruction).

Branch offset = 132 – 112 = 20.

Target address calculated by addition. So, Branch offset = -20.
Instruction Format:
 The Call instruction: used to call a subroutine.

Specify the OP code of call instruction.

Specify the immediate value that is used to determine the address of the first instruction in the subroutine.

Six bits are used for the OP code.

The remaining 26 bits can be used to denote the immediate value.
 Some possibilities of machine instruction format (encoding) are shown here.
 Different commercial processors have instruction sets that vary in the details of implementation.
 Refer to Appendices B to E in Hamacher for the instruction formats of:

Altera Nios II Processor – RISC architecture

ColdFire Processor – CISC architecture

ARM Processor – RISC architecture

Intel IA-32 Architecture – find out
Instruction sets:
 The nature of the computer instructions distinguish them.

Two fundamentally different approaches in the design of instruction sets for modern computers.

Approach 1: Each instruction occupies exactly one word in memory.

Approach 2: more complex instructions which may span more than one word of memory.
 Approach 1 is based on the premise that higher performance can be achieved if instructions occupy one word in
memory.

All operands needed to execute a given arithmetic or logic operation of the instruction is available in processor
registers.

Approach 1 is conducive to implementation of the processing unit.

The various operations needed to process a sequence of instructions are performed in “pipelined” fashion.

Due to overlap, total execution time of a program is reduced.
 As each instruction fits in a word:

The complexity reduces.

The number of different types of instructions that may be included in the instruction set of a computer reduces.
 Computers based on Approach 1 are called Reduced Instruction Set Computers (RISC).
Instruction sets:
 An alternative to the RISC approach is to make use of more complex instructions.

May span more than one word of memory.

May specify more complicated operations.

This approach was prevalent prior to the introduction of the RISC approach in the 1970s.
 Computers based on this idea have been called Complex Instruction Set Computers (CISC).

Introduction of RISC instruction set architechture:

 Two key characteristics of RISC instruction sets are:

Each instruction fits in a single word.

A load/store architecture is used, in which

Memory operands are accessed only using Load and Store instructions.

All operands involved in an arithmetic or logic operation must either be:

In processor registers.

Or one of the operands may be given explicitly within the instruction word.
Introduction of RISC instruction set architechture:
 At the start of execution of a program:

All instructions and data used in the program are stored in the memory of a computer.

Processor registers do not contain valid operands.
 Operands are expected to be in processor registers before they can be used by an instruction.

It is necessary to first bring these operands into the registers.

Load instructions copy the contents of a memory location into a processor register.

The memory location can be specified in several ways (based on addressing mode followed).
 The operation C = A + B requires
 The contents of memory locations A and B are fetched from the memory and transferred into the processor.
 The desired addition can be accomplished by using only two registers, R2 and R3.
CISC vs RISC:
 See the site.

https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/
Pipelining: Basic Concept
 Ways to improve performance of processor:

Use faster circuit technology to implement the processor and the main memory.

Arrange the hardware so that more than one operation can be performed at the same time.

The number of operations performed per second is increased.

The time needed to perform any one operation is not changed.
 Pipelining is a way of organizing concurrent activity in a computer system.

In manufacturing plants, pipelining is commonly known as an assembly-line operation.

First station: Prepare the automobile chassis, by group 1, on automobile 1.

Second station: Adds the body, by group 2, on automobile 2.

Third stations: Installs the engine, by group 3, on automobile 3.
 Overlapping pattern of execution would be possible for all instructions.
Superscalar Architectures:
 The maximum throughput of a pipelined processor is one instruction per clock cycle.
 It is possible to equip the processor with multiple execution units, each of which may be pipelined.

To increase the processor’s ability to handle several instructions in parallel.
 Several instructions start execution in the same clock cycle, but in different execution units.

The processor in this case is called multiple-issue.

Can achieve an instruction execution throughput of more than one instruction per cycle, known as superscalar
processors.
 A superscalar processor has a more elaborate fetch unit: Fetches two or more instructions per cycle before they are
needed and places them in an instruction queue.
 The dispatch unit, takes two or more instructions from the front of the queue:

Decodes them, and sends them to the appropriate execution units.
 At the end of the pipeline, another unit is responsible for writing results into the register file.
Superscalar Architectures:
 Figure shows superscalar processor with this organization.
 It incorporates:

Two execution units: One for arithmetic instructions, another for Load and Store instructions.

Arithmetic operations normally require only one cycle, hence the first execution unit is simple.

Load and Store instructions involve an address calculation for the Index mode before each memory access.

Due to this, the Load/Store unit has a two-stage pipeline.
 An arithmetic instruction and a Load or Store instruction must obtain all their operands from the register file when
they are dispatched in the same cycle to the two execution units.
The register file must now have four output ports instead of
the two output ports needed in the simple pipeline.

An arithmetic instruction and a Load instruction must write their results into the
register file when they complete in the same cycle.
The register file must have two input ports instead of the single input port for the
simple pipeline.
Superscalar Architectures:
 The fetch unit fetches two instructions every cycle.
 The instructions are decoded and their source registers are read in the next cycle.
 Then, they are dispatched to the arithmetic and Load/Store units.
 Arithmetic operations can be initiated every cycle.
 A Load or Store instruction can be initiated every cycle:

The two-stage pipeline overlaps the address calculation for one Load or Store instruction with the memory access
for the preceding Load or Store instruction.
 Once instructions complete execution in each unit:

The register file allows two results to be written in the same cycle.

As the destination registers have two input ports.
Fixed point operations:
 Arbitrary numbers can be represented with just the digits zero and one, the minus sign, and the period, or radix point.
 The minus signs and periods are represented only with ones and zeros.
 An n-bit sequence of binary digits is interpreted as an unsigned integer A

Sign-Magnitude Representation:

 In general it can be represented as

Drawbacks:
 Addition and subtraction require a consideration of both the signs of the numbers and their relative magnitudes to
carry out the required operation.
 There are two representations of 0.

Sign-magnitude representation is rarely used in implementing the integer portion of the ALU. The most common
scheme is twos complement representation.
Fixed point operations: Twos Complement Representation
 Twos complement representation uses the most significant bit as a sign bit.
 Twos complement representation is best understood by defining it in terms of a weighted sum of bits.

 Consider an n-bit integer, A, in twos complement representation. a n - 1 is zero if A >=0.

 The remaining bits represent the magnitude of the number:
 The range of positive integers: 0 to 2(n - 1) – 1.

 For A < 0, an – 1 is one.


The range of negative integers: -1 to -2(n – 1).

The weight of the most significant bit is -2(n – 1).

The expression for negative numbers:
Fixed point operations: Twos Complement Representation
Converting between Different Bit Lengths:
 Take an n-bit integer and store it in m-bits, where m > n.
 In sign-magnitude representation. For twos complement, this won’t work.

 For twos complement integers, move the sign bit to the new leftmost position and fill in with copies of the sign bit.
 For positive numbers, fill in with zeros, and for negative numbers, fill in with ones.

 With m > n, the two values must be equal for negative number:
Fixed point operations: Integer Arithmetic
Negation with twos complement:
 The bitwise complement of an-1 is

Special cases:

Carry out of the most significant bit position is ignored.

Special cases:
Negation of the bit pattern of 1 followed by n - 1 zero is the same number.

For an n-bit length, in twos complement representation, there is a

representation for - 2n - 1 but not for + 2n – 1.
Fixed point operations: Integer Arithmetic
Addition and Subtraction:
 On any addition, the result may be larger than can be held in the word size being used. This condition is called
overflow.

The ALU must signal this fact so that no attempt is made to use the result.
Fixed point operations: Integer Arithmetic
Addition and Subtraction:
 If an arithmetic operation results in traversal of the point where the endpoints are joined, an incorrect answer is given
(overflow).
Fixed point operations: Integer Arithmetic
Twos Complement Multiplication:
 In addition: Unsigned integers: 9 (1001) plus 3 (0011) to get 12 (1100).
Twos complement integers: - 7 (1001) to 3 (0011) to get - 4 (1100).
Both are correct.

 In multiplication, this will not work.

Unsigned: Multiply 11 (1011) by 13 (1101) to get 143 (10001111) (correct).

Twos complement: - 5 (1011) times -3 (1101) equals -113 (10001111) (wrong).

Straightforward multiplication will not work if both the multiplicand and multiplier
are negative.

It will not work if either the multiplicand or the multiplier is negative

The partial products should be viewed as 2n-bit numbers generated from the n-bit multiplicand.

Each contribution of the negative multiplicand as a partial product must be a negative number on a 2n-bit field.
The sign bits of the partial products must line up.
Fixed point operations: Integer Arithmetic
Twos Complement Multiplication:
Each partial product must be a negative twos complement number of 2n
(8) bits.

This is accomplished by padding out each partial product to the left with
binary 1s.
The 4-bit decimal number - 3 is written 1101 in twos complement.

Taking partial products based on each bit position, we would have:

What is desired is -(21 + 20).

Solution:
1. Convert both multiplier and multiplicand to positive numbers.
2. Perform the multiplication.
3. Take the twos complement of the result if and only if the sign of the two original numbers differed.

Techniques that do not require the final transformation step is used in practice, called Booth’s algorithm.
Fixed point operations: Integer Arithmetic
Twos Complement Multiplication:
1. The multiplier and multiplicand are placed in the Q and M registers.
2. A 1-bit register placed logically to the right of the least significant bit (Q 0) of the Q
register and designated Q-1.
3. The results of the multiplication will appear in the A and Q registers.
4. A and Q-1 are initialized to 0.
5. Control logic scans the bits of the multiplier one at a time.
6. If the two bits are the same (1–1 or 0–0), then all of the bits of the A, Q, and Q -1
registers are shifted to the right 1 bit.
7. If the two bits differ, then the multiplicand is added to or subtracted from the A
register, depending on whether the two bits are 0–1 or 1–0.
8. Following the addition or subtraction, the right shift occurs.
9. In either case, the right shift is such that the leftmost bit of A, namely A n - 1, not
only is shifted into An - 2, but also remains in An – 1.

This is required to preserve the sign of

the number in A and Q. It is known as an
arithmetic shift, because it
preserves the sign bit.
Fixed point operations: Integer Arithmetic
Twos Complement Multiplication:
Fixed point operations: Integer Arithmetic
Division:
1. The bits of the dividend are examined from left to right, until the set of bits examined represents a number greater than or equal to the
divisor.
2. Until Step 1 is satisfied, 0s are placed in the quotient from left to right.
3. When Step 1 is satisfied, a 1 is placed in the quotient and the divisor is subtracted from the partial dividend. The result is a partial
remainder.
4. At each cycle, additional bits from the dividend are appended to the partial remainder until the result is greater than or equal to the
divisor.
5. The divisor is subtracted from this number to produce a new partial remainder.
6. The process continues until all the bits of the dividend are exhausted.
Fixed point operations: Integer Arithmetic
Division:
1. The divisor is placed in the M register, the dividend in the Q register.
2. The A and Q registers together are shifted to the left 1 bit at each step.
3. M is subtracted from A to determine whether A divides the partial remainder.
4. If it does, then Q0 gets a 1 bit.

5. Otherwise, Q0 gets a 0 bit and M must be added back to A to restore the previous value.

6. The count is then decremented, and the process continues for n steps.
7. At the end, the quotient is in the Q register and the remainder is in the A register.
Fixed point operations: Integer Arithmetic
Division:
• Algorithm in Fig. 9.16 can be extended to negative numbers.
• Algorithm in Fig. 9.16 assumes that the divisor V and the dividend D are positive and that |V| < |D|.
• If |V| = |D|, then Q = 1, R = 0.
• If |V| > |D|, then Q = 0, R = D.
Fixed point operations: Integer Arithmetic
Division:
• To deal with negative numbers, we recognize that the remainder is defined by:
• Integer divisions with all possible combinations of signs of D and V:
• Fig. 9.17 produces different remainders for (-7)/(3) and (7)/(-3).
• The magnitudes of Q and R are unaffected by the input signs.
• The signs of Q and R are easily derivable form the signs of D and V.
●
sign(R) = sign(D)
●
sign(Q) = sign(D) x sign(V)
• One way to do twos complement division:
●
Convert the operands into unsigned values.
●
At the end, complement where needed to account for signs.
Floating-point representation:
Principles: William Stallings, pg. 327 – 331.

Floating-point arithmetic: William Stallings.

Addition and Subtraction – pg. 334 – 337.
Multiplication and Division – pg. 337 – 338.