Synopsys’ CUSTOMER EDUCATION SERVICES PrimeTime Workshop Lab Guide 10-1.034-816-015 2018.08 ‘Synopsys Customer Education Services 690 E, Middlefield Road Mountain View, California 94043 Workshop Registration: hutp:/training.synopsys.comCopyright Notice and Proprietary Information © 2018 Synopsys, Ine. Allrights reserved. This software and documentation contain confidential and proprietary information thats the propery of Synopsys, Ine, The software and docutrentation are fumished Under a ieense agreement and may be used or copied only in accordance wth the tam of te leonse agreement. No pat of the sofware and documentation may be reproduced, transmit, or translated. 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Synopsys, Inc. 90 E, Middlefield Road Mountain View, CA 94043 \worw.synopsys.com Document Order Number: 104-084-SL.6.015 PrimeTime Lab GuidePrimeTime Flow After completing this lab, you should be able Restore a previously saved PrimeTime session * OPTIONALLY, Take advantage of helpful PrimeTime commands that will make you more efficient when using PrimeTime interactively and show you how to find more information on commands, variables and your design library ‘© Validate a restored save-session. ‘* Exercise recommended Primetime flow © Interpret key components of a timing report for setup and hold timing checks Lab Duration: 45 minutes PrimeTime Flow Lab 1-1 Synopsys 10-I-034-SLG-015Lab1 Overview i command ui Relevant Files and Directories Al files for this lab are located in the 1ab1_£1ow directory under your home directory. labi_flow/ Current working directory common_setup. tel multi-tool shared setup file pt_setup.tel tool-specific PrimeTime setup file pt_scripts/ Run file directory pt.tel Run file -synopsys_pt .setup automatically-read PT setup file. orca_savesession Saved session directory RUNatel Run script for orea_savesession Answers / Solutions This lab guide contains answers and solutions to all questions. If you need some help with answering a question or would like to confirm your results, check the back portion of this lab. Lab 1-2 PrimeTime Flow ‘Synopsys PrimeTime WorkshopLab1 Instructions Your goal is to get used to Prime'Time by validating a restored save session, exercising the recommended flow, and analyzing the setup/hold reports. Task 1. Restore a PrimeTime Sesssion Invoke a previously saved PrimeTime session to perform STA. 1. Invoke PrimeTime from the 1ab1_f£1ow workshop lab Unix directory. unix’ cd labl_flow unix’ pt_shell 2. Restore a previously saved PrimeTime session. This step will read in the design netlist, libraries, and constraints. The design is now ready for analysis. Note: ‘The orca_savesession below is a Unix directory. Note: ‘The orca_savesession can be recreated, if needed, using: pt_shell -£ RUN.tcl | tee -i run.log Note: Any PARA-124 Errors during the execution of RUN.tcl ean be safely ignored for the purpose of our labs. Note: PrimeTime supports command, option, variable and file completion. Type a few letters and then hit the tab key, pt_shell> restore session orca_savesession 3. Generate coverage analysis report pt_shell> report_analysis_coverage Que: ion 1. What is the name of the design under analysis? Question 2, How many setup and hold violations does ORCA have? Generate global timing report PrimeTime Flow Lab 1-3 ‘Synopsys PrimeTime WorkshopLab1 pt_shell> report_global_timing Question 3. How many are reg-reg sefup and hold violations? Lab 1-4 PrimeTime Flow ‘Synopsys PrimeTime WorkshopLab1 Task 2. [OPTIONAL TASK] Explore Helpful Commands 1. 3. 5. PrimeTime Flow Execute the following three history short cut commands: pt_shell> history pt_shell> !! pt_shell> 12 Question 4. Describe the difference between the last two history commands above. Use up and down arrows to scroll through the history eveat list as an alternative to the previous step. ‘Type the following to see all the available key bindings (in the default emacs editing mode). pt_shell> list_key bindings Explore the page mode alias; execute the following command, which will generate a report that scrolls off the screen: pt_shell> report_timing -group [get_path_group *] ‘Tum on page mode, pt_shell> page_on pt_shell> !rep Use the space bar to page through a long report. Quit from a long report in page mode by typing “q”. Ifyou want to tum off page mode, use the command alias page_of£. Send a timing report to a separate window with the view Tel procedure. pt_shell> view report_timing -group [get_path_group *| Lab 1-5 Synopsys PrimeTime WorkshopLab1 9 10. Lab 1-6 Find the command to restore a PrimeTime session and then display help information on this command. pt_shell> help restore* pt_shell> man restore_session pt_shell> restore session -help Note: The following is an alternative way to display syntax help. pt_shell> help -v restore session Question 5. From the last command above, does the command restore_session accept switches? ‘The time unit PrimeTime is determined by the main technology library. To find the time unit for ORCA, first list all libraries in memory. Note: The * in the following report indicates the main library. pt_shell> list_lib Generate a report for the main library which will state the time unit. Note: Use copy and paste to avoid mistyping the lib name. The time unit is at the very top of the report. pt_shell> report_1ib cb13£s120_tsmc_max Question 6. What is the time unit used for timing reports (as well as all other reports) for the ORCA design? Note: Do not forget to use “q” to quit from a long report in page mode and return to the pt_she11 prompt without reading the entire report! Display units used by the current design, pt_shell> report_units PrimeTime Flow ‘Synopsys PrimeTime WorkshopLab1 Task 3. Validate an Existing PrimeTime Session In this task, you will validate the inputs that have been read into PrimeTime: the current design and libraries, the backannotation and constraints. 1. Verify that the current design is your top-level module: ORCA pt_shell> current design 2. Compare the unix paths of the libraries to what has been read into PrimeTime pt_shell> printvar search path pt_shell> printvar link path pt_shell> list libraries Question 7. Have the 4 libraries in the link_path been successfully read into PrimeTime? Question 8. Which library defines the defaults for time units, operating conditions, and other delay calculation information? Question 9. What time unit is used? 3. Verify that the nets are completely annotated. pt_shell> report_annotated parasitics Question 10, Are there any nets that are not annotated? Question 11, What option to report_annotated_parasitica would be good to use as a ‘nex: step’ in debugging the missing nets? PrimeTime Flow Lab 1-7 ‘Synopsys PrimeTime WorkshopLab1 4. Verify that the design is completely constrained. pt_shell> check timing Question 12, What option to check_timing would be good to use as a ‘next step’ in debugging the missing constraints? Verify that the checks in your cells are completely exercised; look at possible causes for your findings. pt_shell> report_analysis_coverage pt_shell> report_case_analysis Question 13. Is it logical that many of your timing checks are untested? 6. Quit PrimeTime. pt_shell> quit Lab 1-8 PrimeTime Flow Synopsys PrimeTime WorkshopTask 4. 1. Execute the run script logging the results to the log file run. log. -/pt_scripts/pt.tel | tee -i run.log UNIX> pt_shell Question 14. Were there any errors during the execution of the tun seript? 2. If'there are any errors, address these first before moving on to the next step. 3. Evaluate your log file. With a text editor, open your log file. Search for the update timing messages (UITE-214), print_message_info output, and the quit output, Then, in your profile directory, examine the file tcl_profile_sorted_by_cpu_time Question 15. What step required the most CPU ti Question 16, What commands were causing UITE-214 messages? Question 17. Can any of the timing updates be avoided? Question 18. Why might the quit command output be a good place to start before reviewing your log file? PrimeTime Flow Lab 1-9 ‘Synopsys PrimeTime WorkshopLab1 Task 5. Analyze STA Reports Generate and intepret two STA reports for setup and hold for S¥8_CLK. Lab 1-10 Invoke PrimeTime and restore the session that you saved in the previous task unix’ pt_shell Pt_shell> restore_session my_savesession Execute the following to display the clocks in ORCA: pt_shell> report_clock Question 19. How many clocks are in ORCA? Create a single, “short” timing report for setup for the clock S¥S_CLK. Use command-line expansion (the tab key) to expand both the command AND the options ~group and ~path. pt_shell> report_timing -group SYS_CLK -path short Note: The lines containing the data path cells and their delays are removed from the data arrival section making this report “short”. Note: The above command generates a report for setup by default, Question 20. There are at least 4 clues that this report is for setup and not for hold. How many can you identify? Question 21. Identify the instance names of the start and end point flip-flops. Question 22. The clock skew for this timing path is 0.511ns; which two lines in the report can you use to calculate this? PrimeTime Flow Synopsys PrimeTime WorkshopLab1 Question 23. How does this clock skew affect slack (je. does the clock skew help or hurt slack)? Question 24. How large is the violation in comparison to the clock period? 4, Generate a timing report for hold time. ‘The following is a short cut that will execute the last command in history starting with the letters “rep” and add the switch -delay min (which will generate a report for hold time). pt_shell> !rep -delay min Question 25. There are at least 4 clues that indicate this is a hold report and not a setup report. How many can you find? Question 26. How does the clock skew in this hold report affect slack ( does the clock skew help or hurt slack)? 5. Quit PrimeTime. pt_shell> quit This completes Lab 1. Return to lecture. PrimeTime Flow Lab 1-11 Synopsys PrimeTime WorkshopLab 14 Answers / Solutions Answers / Solutions ‘Question 1. Question 2. Question 3. Question 4, Question 5. Question 6. Question 8. Lab 1-12 What is the name of the design under analysis? ‘The design is ORCA. How many setup and hold violations does ORCA have? There are 23 setup and 53 hold violations. How many are reg-reg setup and hold violations? ‘There are 9 setup and 53 hold violations of type reg-reg. Describe the difference between the last two history ‘commands above. ‘The command 12 repeats the 2"! command executed in history. The command 1 | repeats the last executed command in history. From the last command above, does the command restore_session accept switches? ‘Yes, it accepts a session name, allowing a user to specify which of many saved sessions to restore. What is the time unit used for timing reports (as well as all other reports) for the ORCA design? Ins. Have the 4 libraries in the link_path been successfully read into PrimeTime? Yes ~ the four libraries specified with Link library are the same as those displayed with 1ist_libraries. Which library defines the defaults for time units, operating conditions, and other delay calculation information? cb13{3120_tsme_max ~ the asterisk to the left of the library (from List_libraries) indicates ‘main library’ PrimeTime Flow ‘Synopsys PrimeTime WorkshopAnswers / Solutions Question 9. Question 10. Question 11. Question 12. PrimeTime Flow Synopsys PrimeTime Workshop Lab1 ‘What time unit is used? pt_shell> report lib cb13£e120_temc_max PIR EEE R IRAE EAE Report : library Library: ch13fs120_tsmc_max ‘Time unit pine pt_shell> report_units TEENIE ono ono anion Report : units Design : ORCA Units Capacitive load unit le-12 Farad Current unit te-06 Amp Resistance unit : 1000 Ohm Time unit : 1e-09 Second ‘Are there any nets that are not annotated? Yes; there are some internal driverless nets and some boundary pin-to-pin nets that are not annotated, What option to report_annotated_parasitics would be good to use as a ‘next step’ in debugging the missing nets? xeport_annotated_parasitics -help shows options; the -1ist_not_annotated option shows the net names; you might want to focus in on the pin-to-pin nets by using the -pin_to_pin_nets option. ‘What option to check_timing would be good to use as a ‘next step’ in debugging the missing constraints? check_timing —help displays alist of options: the -verbose option lists the unconstrained endpoints Lab 1-13Lab 1 Lab 1-14 Question 13. Question 14, Question 17. Question 18. Question 20. Answers / Solutions Is it logical that many of your checks are untested? Yes — test_mode, scan_en, and power_save are constrained off performing STA on additional modes might enable more checks to be tested. Were there any errors during the execution of the run script? No. The “run script” is setup such that any errors will terminate the script in the middle of execution, If the script completes, no errors occurred during execution of the run script. Moreover, from the “Diagnostics Summary” messages at the end of the log file from the quit command, there were no errors during the run. What step required the most CPU time? For this lab, sourcing the constraints took the most CPU time, ‘What commands were responsible for UITE-214 messages? update timing -full anda call toamacro PLL_SHIFT which invoked update_timing Can any of the timing updates be avoided? ‘Yes, there is an update_timing both before and after set_propagated_clocks — the one before set_propagated_clocks is unnecessary. One update_timing command is in pt.tcl— the other is ina constraint file (orca_pt_other.tcl) sourced by orca_pt_constraints which is sourced by pt.icl Why might the quit command output be a good place to start before reviewing your log file? It gives a high-level summary of potential trouble spots: messages, both warning and information, timing updates, and performance statisties, How many clocks are in ORCA? There are 6 clocks in ORCA. There are at least 4 clues that this report is for setup and not for hold. How many can you identify? ‘The most glaring clue is the “library setup time” in the generated report. The more subtle clues are: © The clock edges used for the data arrival and data required are Ons and 8ns respectively (and not Ons and Ons as for hold time). PrimeTime Flow ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 1 The “Path Type” in the header is max which indicates that this report is for setup (a “Path Type” of min indicates a hold report). nally, the data arrival time is after the data required time and the slack is violated (whereas if this was a report for hold, the slack would be met!) Question 21. Identify the instance names of the start and end point flip-flops, Startpoint: ELORCATOP/T BLENDER/s3//op2/veg (18) (rising edge-triggered flip-flop clocked by SYS_CLK) Endpoint: [ORCA TOB/T) BLENDER/s4_op2/ireg (31) (Tising edge-triggered flip-flop clocked by S¥S_CLK) Path Group: S¥S_CLK Path Type: max Min Clock Paths Derating Factor Question 22. The clock skew for this timing path is 0.511 ns. Which lines in the report can you use to calculate this? 0.900 Point Incr Path clock S¥5_CLK (rise edge) 0.000 0.000 Glock ‘network delay” (propagated) 3.247 3.287 T_ORCA_T0P/T_BUENDER/s3_op2_reg|18] /CP (sdnrb1) 0.000 31247 v ‘ORCA_T0P/T_BLENDER/s3_op2_reg [18] /Q (sénzbi) 01516 & 3.763 ORCA_TOP/T_BLENDER/s4_op2_reg{31]/D (sdnrb2) 8.242 & 12,004 £ data arrival tine 12.008 clock SYS_CLK (rise edge) 8.000 8.000 clock network delay (propagated) 2.736 10.736 Question 23. How does this clock skew affect slack (i.e. does the clock skew help or burt slack)? ‘The clock skew hurts the slack for setup in this specific timing report, The clock latency to the start point flip-flop causes the data to arrive 0.51 Ins later causing a larger setup timing violation.. Question 24. How large is the violation in comparison to the clock period? ‘The clock period is 8ns. The violation is 0.987. It is approximately 12% of the clock period. PrimeTime Flow Lab 1-15 Synopsys PrimeTime WorkshopLab1 Answers / Solutions Question 25. There are at least 4 clues that indicate this is a hold report and not a setup report. How many can you find? ‘The most glaring clue is the highlighted “library hold time” in the report below. The more subtle clues are: * The clock edges used for the data arrival and data required are Ons and Ons respectively. © The “Path Type” in the header is min which indicates that this report is for hold time. + Finally, the data arrival time is before the data required time and the slack is violated. Question 26. How does the clock skew for this hold report affect slack (Le. does the clock skew help or hurt slack)? From the report, you can see (after applying the clock network delay) that the capture clock edge arrives later than the launch clock edge. This hurts the hold slack, causing a violation. Point Incr clock s¥S_cLK (rise edge) 0.000 0.000 clock ‘network delay’ (propagated) 2.360 2.360 T_ORCA_TOP/T_PARSER/out_bus_reg[10]/CP (sderq1) 0.000 2.360 r F_ORCA_TOP/I_PARSER/out bus regl10]/Q (sderql) 0.353 & 2.713 T_ORCA_TOP/T_BLENDER/ren_green_reg/D (sdernl) 0.142 & ©~—«-2.855 £ data arrival time 2.855 clock S¥S_CLX (rise edge) 0.000 0.000 elock!network delay | (propagated) 3.206 3.206 clock reconvergence pessimism ~0.216 2.990 Z_ORCA_TOP/T_BLENDER/ren_green_reg/CP (sdcrm1) 2.990 x iibrary hold time 0.006 2.997 data required time 2.997 data required time 2.997 data arrival time -2.855 Lab 1-16 PrimeTime Flow Synopsys PrimeTime WorkshopLab Duration: 30 minutes Constraining Methodology ‘Synopsys 10-1-034-SLG-015 Constraining Methodology ‘After completing this lab, you should be able to: ‘© Validate constraints by checking for ‘* Constraint Completeness and © Untested timing checks ‘© Identify and interpret constraints in a timing report © Clock constraints ‘© Interface constraints Lab 2-1Lab 2 Overview Relevant Files and Directories Al files for this lab are located in the lab2_constraints directory under your home directory. lab2_constraints/ Current working directory orca_savesession/ Session to restore for labs -synopsys_pt.setup PT setup file RUNicl Run script for orca_savesession Answers & Solutions This lab guide contains answers and solutions to all questions. If you need some help with answering a question or would like to confirm your results, check the back portion of this lab. Lab 2-2 Constraining Methodology ‘Synopsys PrimeTime WorkshopLab2 Instructions Task 1. Validate constraints 1. _ Invoke PrimeTime from the lab2_constraints directory and restore the PrimeTime session using the orca_savesession directory. Note: The oxca_savesession can be recreated, if needed, using: pt_shell -£ RUN.tcl | tee -i run.log Note: Any PARA-124 Errors during the execution of RUN.tel can be safely ignored for the purpose of our labs. 2. Check for constraint completeness pt_shell> check timing -verbose Question 1. Are all registers in the design clocked? Question 2, Are there any missing constraints? Can you explain? 3. Check for the untested timing checks in the design pt_shell> report_analysis_coverage Question 3. Nearly two thirds of the setuprhold checks are untested! — What are the 2 causes? Question 4. Why are there unexercised min_pulse_width checks? Question §. How many output delay constraints are there for setup and for hold and are these constraints met or violated? Constraining Methodology Lab 2-3 ‘Synopsys PrimeTime WorkshopLab2 Task 2. Analyze a Timing Report For Input Delay 2 Lab 2-4 Constraint Generate a report for the input delay constraints applied to the port pad [0] . pt_shell> report_port -input_deley pad(0) Question 6. What are the min and max arrival times to pad [0] ? Question 7, What is the name of the external start point clock constraining pad[0]? Generate a timing report for setup starting at the port pad [0] Answer the following questions using this report. Use your job aid labeled “timing reports” for help recalling the appropriate switch for report_timing, Question 8. Which lines in the timing report did you use to ensure the reported path starts at the port pad [0] and is for setup? Question 9, List all user specified constraints in this timing report. Question 10. Where must the clock latency be included for the start point clock BCI_CLK? Question 11. Describe the direction of the port pad [0] (ic. is it an input, ‘output or inout port). Question 12, Describe the end point of this timing path (i. is it an output port or an internal flip-flop). Constraining Methodology ‘Synopsys PrimeTime WorkshopLab 2 3. Generate anew report from the same port pad [0] for setup, which also shows the details of the calculated clock network delay, Use the job aid labeled “timing reports” for help recalling the appropriate switch for report_timing. Remember to take advantage of history commands. Que N13, How large is the clock source latency versus the clock network latency for the end point clock PCT_CLK? Question 14. Where has the clock PCI_CLK been defined (the clock definition point)? 4. Generate a report starting at the port pad [0] for hold time. Question 15, Does the value of the input external delay constraint match. your expectations? Constraining Methodology Lab 2-5 Synopsys PrimeTime WorkshopLab 2 Lab 2-6 Task 3. Analyze a Timing Report For Output Delay Constraint 2 Generate a report for the output delay constraints applied to the port pad[0] . Question 16. What are the min and max output delay constraints for this port? Question 17. How will the negative min output delay constraint be applied to this port (ie. will it impose a positive or negative hold requirement)? Question 18. What is the name of the external end point clock constraining this port? Generate a “short” timing report ending at the port pad [0] for hold time, Question 19. Describe the start point of this timing path (ic. is it an input port or an intemal flip-flop). Question 20, Does the path group for this timing path match your expectations? Question 21. Does the “data required time” match your expectations? Optionally, apply the following constraint which will impose a positive output delay constraint for hold on pad [0] and then re-execute the steps in this task to see the affect. pt_shell> set_output_delay -min 1.0 clock PCI_CLK pad{0] Quit PrimeTime. This completes Lab2. Return to lecture. Constraining Methodology Synopsys PrimeTime WorkshopAnswers / Solutions Lab 2 Answers / Solutions Question 1, Are all registers in the design clocked? Yes. There are no clock pins reported following the mi Information: Checking ‘no_clock’ Question 2. Are there any missing constraints? Can you explain? Yes. There are 2 output ports reported to be missing their output delays. Waring: There are 2 endpoints which are not constrained for maximum delay. sd_OKn sd_CK The above warning can be ignored since these 2 are the clock output ports (Use the report_clock command to confirm) that should not be constrained for output delay. Question 3, Nearly two thirds of the setup/hold checks are untested! — ‘What are the 2 causes? constant_disabled and false_path. (Using report_analysis_coverage -status untested -check “setup hold”) Question 4. Why are there unexercised tin_pulse_width checks? min_pulse_width checks are exercised only if the pins have clocks. Since these are non clock asynchronous pins like “set or clear”, no clocks have been defined on them, (Use the command report_analysis_coverage - status untested -check min pulse width to confirm) Question 5. How many output delay constraints are there for setup and for hold and are these constraints met or violated? From report_analysis_coverage, there are 75 output delay constraints for doth setup and hold; 9 output delay constraints for setup are violated; 39 output delay constraints for hold are violated. Remember to verify that all output ports are constrained for both setup as well as for hold. Constraining Methodology Lab 2-7 ‘Synopsys PrimeTime WorkshopLab 2 Answers / Solutions pt_shell> restore session orca_sav pt_shell> report_analysis_coverage Type of check Total Met Violated untested setup 9629 3575 ( 37%) a3 (08 6042 ( 638) noia 9629 3517 ( 378) 1 18) 6041 ( 638) recovery asi6 3220 ( 92%) 0 ( on aos (88) removal ais 1206 ( 91%) 6 ( 8) 10s (8%) min_period 20 20 (2008) 0 ( om) 2 ( om) min_pulee width 273 5957 ( 828) 2 ( of 1326 ( 188) out_setup 5 66 ( 888) 9 (128) 0 om) out_hold 1s 36 ( 48%) 39 (528) 0 ow ALL Checks 2933315585 ( 538) 338 ( 08) 13610 ( 468) Question 6, What are the min and max arrival times to pad [0]? The min and max arrival times are 2ns and 8ns respectively (with the same constraint for both rise and fall data transitions at the port pad [0] ) . Question 7. What is the name of the external start point clock constraining pad [0]? ‘The name of the clock is PCT_CLK. Lab 2-8 Constraining Methodology Synopsys PrimeTime WorkshopAnswers / Solutions Lab2 Question 8. Which lines in the timing report did you use to ensure the reported path starts at the port pad [0] and is for setup? pt_shell> report_timing -from pad[0) Startpoint: pad[0] (input port clocked by PCI_CLK) Endpoint: I_ORCA_TOP/T_PCT_CORE/d_out_i_bus_reg{o] (rising edge-triggered flip-flop clocked by PCT_CLK) Path Group: PCI_CLK Path Type: max Question 9. _List all user specified constraints involved in this timing report. The clock period is a constraint. The clock PCZ_CLK is propagated (not ideal). ‘The input external delay (which comes from an input delay constraint). Question 10. Where must the clock latency be included for the start point clock PCT_CLE? ‘The clock network delay is zero. Therefore, the only other place to represent the external clock latency is as a part of the input delay constraint (i.e. the input extemal delay). ‘The appropriate way to model this is to use the switches -network_latency_included and -source_latency_included for set_input_delay. Question 11. Describe the direction of the port pad [0] (i.e. is it an input, output or inout port). ‘he port pad [0] is an inout port; therefore, itis both a timing path start point as well as a timing path end point! Poit Inex Path 000 clock PCI_CLK (rise edge) 0.000 ° clock network delay (propagated) 0.000 0.000 input external delay 8.000 8.000 x pad(o}) (inout) 0.000 8.000 r Question 12. Describe the end point of this timing path (ie. is it an output port or an internal flip-flop). ‘The end point is a rising-edge triggered flip-flop clocked by PCI_CLK (it is actually a timing model that looks like a flip-flop with setup and hold timing checks). ‘Constraining Methodology Lab 2-9 ‘Synopsys PrimeTime WorkshopLab 2 Answers / Solutions. Question 13. How large is the clock source latency versus the clock network latency for the end point clock PCI_CLK? Shown below is only the data required time section of the timing report. The source latency is Ons. The clock network latency is 0.768ns (15.768 — 15.000). pt_shell> !rep -path full_clock clock PCI_CLK (rise edge) 15.000 clock source latency 15.000 pelk (in) 15.000 x pclk_iopad/CIN (pe3401) HO 15.728 r T_CLOCK_GEN/T PLL _PCI/CLK (PLL) Ho 14.508 r T_CLOCK_GeN/bufbdéG1B111_1/2 (butbdf) & i625 T_CLOCK_GEN/U21/Z_(mx02d2) & 14.857 r (CLOCK_GEN/bufbatG23111_2/2 (bufbdt) & 15.010 r 3_CLOCK_GEN/U17/2N (invbak) & 15.086 £ F_CLOCK_GEN/U14/2N (invbdk) & 15.245 x T_CLK_SOURCE_PCLK/2 (bufbdk) & 15.313 5 invbd7658112/2N (invbd7) & 15.421 £ ¥_ORCA_TOP/invbak¢sB213_1/ZN (invbdk) & 15.541 5 TLORCA_TOP/T_PCT_CORE/buffd7G5B3132/2 (buf£d7) & 15.680 5 FLORCA_T0P/T_PCT_CORE/d_out_i_bus_reg(0]/CP (sderql) & 15.768 x Library setup time 35.635 data required time 1615 Question 14. Where has the clock PCT_CLK been defined (the clock definition point)? The clock PCT_CHK is defined at the input port pelk. The clock definition point separates the clock source latency from the clock network latency. lLab 2-10 Constraining Methodology ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 2 Question 15. Does the value of the input external delay constraint match your expectations? Yes. From xeport_port above, the input extemal delay should be 2ns with respect to the rising edge of PCT_CLK. This is confirmed in the timing report below. pt_ehell> report_timing -delay min -from pad{0] Startpoint: pad(0] (input port clocked by PCI_CLK) Endpoint: I_ORCA_TOP/I_PCT_CORE/d out_i_bus_reg{0] (rising edge-triggered flip-flop clocked by PCI_CLK) Path Group: PCI_CLK Path Type: min Min Data Paths Derating Factor : 0.900 Min Clock Paths Derating Factor : 0.900 Point Incr Path clock PCT_CLK (rise edge) 0.000 0.000 clock network delay (propagated) 0.000 0.000 input external delay 2.000 2.000 x pad{o] (inout) 0.000 2.000 r pad_iopad_0/PAD (pc3b03) 0.044 2.044 x pad_iopad_0/CIN (pc3b03) 0.662 & © 2.706 = Question 16. What are the min/max output delay constraints for this port? pt_shell> report_port -help Usage: eport_port # Report port info verbose] (show all port info) [-design_rulel (only port design rule info) [-@rive] (Only port drive info) [-input_delay] (only port input delay info) [-output_delay] (only port output delay info) [-wire_load] (Only port wire load infc) [-nosplit] (Don't split lines if column overflows) (port_list: (List of ports) pt_ehell> xeport_port ~output_delay pad[0] output Delay Min Max Related Related output Port Rise Fall Rise Fall Clock Pin pad[o] 1,00 -1.00 4.00 © 4.00 Constraining Methodology Lab 2-41 Synopsys PrimeTime WorkshopLab2 Answers / Solutions Question 17, How will the negative min output delay constraint be applied to this port (i.e. will it impose a positive or negative hold requirement)? In lecture, it was stated that a negative hold output delay constraint will impose a positive hold requirement. Question 18. What is the name of the external end point clock constraining this port? ‘The port pad [01 is constrained with respect to PCT_CLK. Question 19. Describe the start point of this timing path, ‘The start point of the timing path is an internal flip-flop. pt_chcll> report_timing -delay min to pad{0] Startpoint: I_ORCA_TOP/I_PCI_CORE/pad_out_buf_reg{0] (rising edge-triggered flip-flop clocked bby PCI_CLK) Endpoint: pad{0] (output port clocked by PCI_CLK) Question 20. Does the path group for this timing path match your expectations? ‘Yes, The path group is PCT_CLK which is the same as the external capture clock name. Question 21. Does the “data required time” match your expectations? Yes. The capture clock edge is zero, which is appropriate for hold. The hold requirement of Ins is positive, and the propagated clock network delay is Ons, ‘The data required section of the timing report is shown below. clock PCT_CLK (rise edge) 0.000 0.000 clock network delay (propagated) 0.000 0.000 output external delay 1.000 1.000 data required time 1.000 Lab 2-12 Constraining Methodology Synopsys PrimeTime WorkshopAnswers / Solutions Lab 2 # Anewers for optional step pt_shell> report_port -output_delay pad[0] output Delay Min Max Related Related output Port Rise Fall Rise Fall Clock Pin pad{o] 2.00 1.00 4.00 4,00 PCT_CLK pt_shell> report_timing -to pad{0] -delay min -path short Point incr Path clock PCr (rise ease) 0.000 0.000 clock network delay (propagated) 0.772 0.772 _ORCA_TOP/T_PCT_CORS/pad_out_buf_reg|0]/CP (ederql) 0.000 0.772 © T_ORCA_TOP/T_®CI_CORE/pad_out_but_reg{0]/Q (sderg) 0.350 & 1.322 pad_out_buf_reg_0_ASTttcInst778/2 (butbdt) 0.199 = asa pad_iopad_0/PAD (pc3b03) 2.081 H 2.402 x pad{o] (inoue) 0.048 3.445 data arrival tine 3.445 CLK (rise edge) 0.000 0.000 clock network delay (propagated) 0.000 0.000 clock reconvergence pessimism 0.000 0.000 output external delay -1,000 © -1.000 data required time -1.000 data required time 1.000 data arrival time 3.445 445 prom the above report, you can see that using a positive hold constraint for an output delay INCREASES the positive slack. This confirms that Hepecifying a negative hold constraint for an output delay actually Hepecifies the hold requirement on the output port. Constraining Methodology Lab 2-13 ‘Synopsys PrimeTime WorkshopLab2 Answers / Solutions This page is left blank intentionally. Lab 2-14 Constraining Methodology ‘Synopsys PrimeTime WorkshopGenerating Reports After completing this lab, you should be able to: © Generate summary reports for the violations in ORCA * Analyze timing reports for setup and hold ‘© Apply the correct timing report switches ‘© Identify half clock cycle paths Generating Reports Lab3-4 ‘Synopsys 10-1-034-SLG-O15Lab3 Overview Restore a PrimeTime session. Generate various summary Generate and analyze timing reports, Relevant Files and Directories Alll files for this lab are located in the lab3_reporte directory under your home directory. ab3_reporte/ Current working directory orca_savesession/ Session to restore for labs -synopsys_pt.setup PT setup file Answers & Solutions This lab guide contains answers and solutions to all questions. Ifyou need some help with answering a question or would like to confirm your results, check the back portion of this lab. Lab 3-2 Generating Reports ‘Synopsys PrimeTime WorkshopLab3 Instructions Task 1. Setup PrimeTime For Lab 3 1. Invoke PrimeTime from the 1ab3_reportss (which is a symbolic link to the lab2_constraints) workshop lab directory. Restore the PrimeTime session using the orca_savesession directory. Find the variable that controls the significant digits for many reports and set it to4 significant digits. [Hint: aa significant] Question 1. What is this variable’s default value? (Hint: man page] Generating Reports Lab 3-3 ‘Synopsys PrimeTime WorkshopLab 3 Task 2. _ Generate Summary Reports From lab 1, we know that there are setup violations in ORCA. 1. Answer the following questions by generating the appropriate summary reports: Question 2. Identify the top five setup violations with the worst slack. The required details are the endpoint names and the slack. Question 3. List the 2 clock domains that have violating setup timing paths, and the 5 clock domains that have violating hold timing paths (ORCA has 6 clock domains in total). Question 4, Identify how many hold violations are on input paths, how many on output paths, and how many are register- to-register violations. 2. Generate a report for the worst slack for setup to each bit of a 16-bit bus ending at the output ports s4_DQ[0] to s4_DQ[15] (the output ports are all constrained by a single clock, SD_DDR_CLK). Question S. List the end point with the largest margin (the best slack). 3. Generate a high-level overview of the quality of the design Question 6. Which clock group has the highest number of violating paths? Lab 3-4 Generating Reports Synopsys PrimeTime WorkshopLab3 Task 3.__ Analyze Timing Reports for Setup and Hold 1. Turn page mode on. 2. Execute the following command to generate a timing report for PCT_CLK: pt_shell> report_timing -group PCT_CLK Question 7. Does this timing path meet or violate timing? Question 8. What type of timing path is this - internal flip-flop to flip-flop, input, or output timing path? Generate a timing report for hold time for the same clock group PCT_CLK. pt_shell> report_timing -group PCI_CLK -delay min Question 9, What type of timing path is this - internal flip-flop to flip-flop, input, or output timing path? Question 10. How many cells are on the data path of this timing path? The cell delay used for the clock pin (CP) to Q pin of the start point flip-flop is for arise transition. Offer one possible reason why this results in a worse slack for hold than using the faster fall delay through this flip-flop? In the next step, you will continue to explore and confirm your answer for the above question. Question 12. What additional information do you need to confirm your answer for the above question? Generating Reports Lab 3-5 ‘Synopsys PrimeTime WorkshopLab3 4, Generate another timing report for the same timing path for hold time but with a fall transition at the end point (instead of a rise transition). Use copy and paste to avoid mistyping the end point and start point pin names. Use the job aid labeled “timing reports” to find the appropriate switches for report timing. Question 13, Which lines in this report did you use to confirm that the correct path has been reported? Question 14, Was the guess correct — the faster fall delays results in a faster data arrival time but a smaller hold time requirement and thus a better slack? Generating Reports Lab 3-6 ‘Synopsys PrimeTime WorkshopLab 3 Task 4. Apply the Correct ing Report Switches 1. Answer the following questions by experimenting and exploring in PrimeTime. Use the job aid labeled “timing reports” for help identifying the appropriate commands and switches. Question 15. Write the command to generate a single timing report for each path group for setup. Question 16. Write the command to generate a single timing report for setup for each path group which has a violation. Question 17, What are the names of the two path groups that have violating timing paths in ORCA (che answer will come from the result of the previous question)? Question 18, Write the command to generate a timing report with the worst slack for setup to any output port constrained by the clock PCZ_CLK. Question 19, There are a few latches in ORCA; write the command to identify the data pins of these letches. Question 20, Write the command to generate a siming report for hold to the D pin of the latched_clk_en_reg latches. Generating Reports Lab 3-7 Synopsys PrimeTime WorkshopLab 3 Task 5. __dentify Half-Clock Cycle Paths ‘The clock SDRAM_CLK constrains many half clock cycle paths in ORCA (i.e. it constrains paths from a falling edge triggered flip-flop to a rising edge triggered flip-flop and vice versa). These paths must be carefully monitored for various reasons (e.g. the duty cycle of SDRAM_CLK is not yet well defined or for analysis of the clock skew). 1. Execute the following command to report the clock period for SDRAM_CLK and use this information to answer the following questions: pt_shell> report_clock SDRAM CLK Question 21. Given that the first number under the waveform column is the first rising edge for the clock SDRAM_CLK and the second number is the falling edge — what duty cycle has been defined for this elock? Question 22. Describe the specific clock edges that will be used in a timing report for setup for a timing path constrained by the rising edge of SDRAM_CLK to the falling edge of SDRAM_CLK. Question 23. For this same timing path, describe the s] edges that will be used in a timing report for hold timing checks. Confirm the information in the following table by generating the appropriate timing reports for the half clock cycle timing paths constrained by the clock SDRAM_CLK. Launch | Capture | Wor | Launch | Capture | Worst clock edge | clock edge | u0P | clock edge | clock edge | Hold Slack Rise Ons | Fall 3.75ns | 0.680ns | Rise 7.5ns | Fall 3.75ns | 3.558ns Fall 3.75ns | Rise 7.50ns | 0.635ns | Fall3.75ns | Rise Ons | 3.514ns Lab 3-8 Generating Reports ‘Synopsys PrimeTime WorkshopQuestion 24. Question 25. Question 26. 3. Quit PrimeTime, Lab3 Which switch is useful for generating the worst 10 timing reports for each of these half clock cycle timing paths? Why does PrimeTime report “no constrained paths?” (hint - the options PrimeTime is using are shown immediately following the report_timing command) ‘What additional option must you use to report the worst 10 timing paths? This completes Lab 3. End of Day-1. Generating Reports ‘Synopsys PrimeTime Workshop Lab 3-9Answers / Solutions Lab3 Answers / Solutions Question 1. What is this variable’s default value? set_app_var report_defanIt_significant digits -defaule > report_default significant digits = "2" pt_shell> set report default _significant digits 3 Question 2. Identify the top five setup violations with the worst slack. The details that are required are the endpoint names and the slack. The following command will list all setup violations sorted by slack. Use page mode to quit from the long report because the only information desired are the top 5 violations. # No need to type the entire command name! pt_shell> report_analysis -status violated ~check setup -nosplit constrained Bin Related check Pin Clock Type __ Slack TORCH. Lab 3-10 Question 3, P/E_BLENDER/s4_op2_reg(3i]/D CP(rise) SYS_CLK setup -0.9072 TLORCA_T0P/T_BUENDER/s4_op1. TCORCA_TOP/T_BLENDER/s4_op2 TLORCA_TOP/T_BLENDER/s4_op1_regl. FLORCA_TOP/T_BLENDER/s4_op1_reg[30]/D CP(rise) SYS_CL! eg(31]/D CP(rise) SYS_CLK setup -0.8410 CP(rise) SYS_CLK setup -0.8305 CP(rise) SYS CLK setup -0.6918 setup -0.6843 List the 2 clock domains that have violating setup timing patiis, and the 5 clock domains that have violating hold timing paths (ORCA has 6 clock domains in total), (the following answer just shows the path group headers — the names of the endpoints have been removed to conserve space. pt_shel1> report_¢ -all_violators \ -max_delay -mi delay max_delay/setup ('PCI_CLK' group) max_delay/setup ('SYS_CLK' group) min_delay/hold ('PCI_CLK' group) min_delay/hold ('SDRAM_CLK' group) min _delay/hold ('SD_DDR_CLK’ group) min_delay/hold ('SY8_2x_CLK' group) min_delay/hold ('SYS_CLK' group) Generating Reports ‘Synopsys PrimeTime WorkshopAnswers / Solutions Question 4. Generating Reports ‘Synopsys PrimeTime Workshop Lab3 Identify how many hold violations are on input paths, how many on output paths, and how many are register-to-register violations. pt_shell> report_global_timing Hold violations Total reg->reg in->reg reg->cut in->out WS -0.4375 -0.1420 -0.2363 -0.1281 0.4375 INS -12.6317 -3.5616 -2.5768 -0.5954 -5.8979 um 100 59 18 7 16 Lab 3-11Lab 3 Answers / Solutions Question 5. List the end point with the largest margin (the best slack). The output port s4_DQ [0] has the largest margin at, 1,5994ns. Generally, the following command will only generate a single report ‘for every end point because nworst is, by default, I and there is only asingle clock constraining every output port. However, because increasing the value of max_paths causes an implicit slack_lesser 0 to be used, and because all the slacks to this endpoint are positive, PrimeTime will not report any paths unless we change the value of s1ack_lesser to a large positive number —in this case, 100. pt_shell> report timing -path end -max 16 -slack lesser 100 -to sd_po* Report : timing -path type end -delay type max -slack Jeaser_than 100.0000 -max_paths 16 -sort_by slack Design : ORCA Version: J-2014.06 Date: Wed dui 23 12:01:52 2014 Endpoint Path Delay Path Required CRP_——Slack s@ Dg(24] (inout) 8.4133 £ 9.6649 0.2418 1.4933 sd DQ{6) (inout) 8.4133 £ 9.6649 0.2418 1.4934 sdDQ{5) (inout) 8.4133 € 9.6649 o.24ie 2.4934 sd_DO(4) (inout) 8.4133 £ 91.6649 0.241a 1.4934 sdpol3] (inout) @.4139 ¢ 9.6649 0.2416 1.4934 sd_pg{10] (inout) @.4112 f 9.6649 0.2418 1495s sd_pglis} (inout) 8.4111 £ 9.6649 0.2418 114955 sd pg{i3} (inout) 8.4111 9.6649 0.2418 1.4955 sd_poli2} (inout) 6.4111 9.6649 0.2418 1.4955 sd_po{9} (inout) @.4211 9.6649 0.2418 1.4955 sd pli) (inout) @.4106 9.6649 0.2418 1.4960 s4_pg{2] (inout) 9.4054 9.6649 0.2418 11019 sd pg[1} (inout) 9.4054 £ 9.6649 0.2418 1.5013 sd pole] (inout) 8.4032 916649 012418 1.5035 sd_DQl7] (inout) 8.4032 £ 9.6649 0.2418 1.5035, sd_pQl0] (inout) 8.0654 f* 9.5649 0.0000 3.5994 Question 6. Which clock group has the highest number of violating paths? report_qor ~only_violated SDRAM_CLK has 30 violating paths Lab 3-12 Generating Reports ‘Synopsys PrimeTime WorkshopAnswers / Solutions Question 7. Question 8. Question 9. Question 10. Question 11. Question 12. pt_shell> Question 13. Generating Reports Synopsys PrimeTime Workshop Lab 3 Does this timing path meet or violate timing? It violates timing with a slack of -1.157ns. What type of timing path is this - intemal flip-flop to flip- flop, input, or output timing path? This is an output timing path ending at the output port named pad [1] - What type of timing path is this - internal flip-flop to flip- flop, input, or output timing path? This is an internal timing path, The end point looks i flip-flop, but is one of many timing ares in a RAM ti model. ing How many cells are on the data path of this timing path? There is only one cell on this data path, the start point flip-flop, The timing path consists of a start point flip-flop tied directly to the end point flip-flop. ‘The cell delay used for the clock pin (CP) to Q pin of the start point flip-flop is a rise delay. Offer one reason why this would result in a worse slack for hold than using a fall delay through this flip-flop? Typically, fall delays are faster than rise delays and would offer a worse slack for hold! ‘The one exception is if the fall delay at the data pin of the end point flip-flop resulted in a smaller library hold time requirement. This is what occurs in this case. Write the command to generate a single timing report for each path group for setup, xeport_timing -group [get_path_group *] What additional information do you need to confirm your answer for the above question? Generate another timing report where the data arrival time is calculated with fall transition at the end point and compare the two reports. In this way you can confirm that the library hold time is in fact smaller with a falling transition at the data pin of the end point flip-flop and thus the resulting slack better, You will explore this in the next lab step. Lab 3-13Lab 3 Answers / Solutions Question 14, Which lines in this report did you use to confirm that the correct path has been reported? Note: ‘The backslash in the command below is a line continuation character. pt_shell> report_timing delay min fall \ to 1_ORCA_TOP/t_PCI_READ_FIFO/PCT_RFTFO_RAM/A1(1] \ ~from 1 ORCA TOP/T_PCI_READ_FIFO/count_int_xeg{1]1/cP Startpoiat: r ORCA TOP/T_PCT_READ_FTFO/count_int_reg{1]1 (rising edge-triggered flip-flop clocked by PCI_CLK) EnapOLRE: 1_ORCA_TOP/T_PCI_READ_FIFO/PCI_RFIFO_RAM (rising edge-triggéred flip-flop Glocked by PCZ_cLx) Path Group: PCI_CLK Path Type: mim Min Data Paths Derating Factor Min Clock Paths Derating Factor Point incr Path ock PCI_CLK (rise edge) 0.000 0.000 clock network delay (propagated) ol779 0.779 T_ORCA_TOP/I_PCI_READ_FIFO/count_int_reg[1]1/CP (sderqi) 0.000 0.779 = 1_ORCA_TOP/T_PCT_READ_FTFO/count_int_reg{1]1/Q (sderq1) 0.344 1,123 £ 1_ORCA_TOP/T_PCT_READ_FIFO/PC1_RFIFO_RAM/A1[1] (ram32x32) 0.016 & 1.139 £ data arrival time 2.139 clock PCI_CLK (rise edge) 0.000 0.000 clock network delay (propagated) aoa 1.088 clock reconvergence pessimism 0.274 ole2a T_ORCA_TOP/Z_PCT_READ_PIFO/2CT_RPIFO_RAM/CEL (ram32x32) ole1a x library hold tine oat + 1.025 data required tine 1.025 data required tine 1.025 data arrival tine -11139 slack (MET) Question 15. Was the guess correct — the faster fall delays results in a faster data arrival time but a smaller hold time requirement and thus a better slack? Yes! The data arrival time is faster (1.139ns versus 1.150ns) but the hold time requirement is smaller (0.21 Ins versus 0.41 Ins) thus the slack is better than the original Lab 3-14 Generating Reports ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 3 timing report. Recall that hold time (and setup time) are a function of the transition at the data pin of the flip-flop, Question 16. Write the command to generate a single timing report for setup for each path group which has a violation. pt_shell> report timing -group [get_path_group *] -slack_lesser_than 0 # When using PrimeTime interactively ~ abbreviate # command names or switches by typing enough letters to # distinguish from other commands or switches ~ or, # better yet, use command expansion by pressing tab pt_shell> report_timing -slack less 0 Question 17. What are the names of the two path groups that have violating timing paths in ORCA (the answer will come from the result of the previous question? ‘The two path groups are BCT_CLK and SYS_CLK. Question 18. Write the command to generate a timing report with the worst slack for setup to any output port constrained by the clock PCT_CLK. pt_shell> help all_* pt_shell> all_outputs -help pt_shell> report_timing -to [all_outputs -clock PCI_CLK] # Or, another way to do the same thing pt_shell> report_timing -to [all_outputs] -group PCI_CLK Question 19. There are a few latches in ORCA; write the command to identify the data pins of these latches. pt_shell> all_registers -level_sensitive -data pins Question 20. Write the command to generate a timing report for hold to the D pin of the latched_clk_en_reg latches. # Use copy and paste to avoid mistyping the long end point pin name pt_shell> report_timing -delay min \ to I_ORCA TOP/I_BLENDER*/latched_clk_en_reg/D Generating Reports Lab 3-15. ‘Synopsys PrimeTime WorkshopLab 3 Answers / Solu Question 21. Given that the first number under the waveform column is the first rising edge for the clock SDRAM_CLK and the second number is the falling edge ~ what duty cycle has been defined for this clock? The rising edge of SDRAM_CLX is at Ons, the falling edge at 3.75ns and the period is 7.50ns. ‘The duty cyele is 50%, Question 22, Describe the specific clock edges that will be used in a timing report for setup for a timing path constrained by the rising edge of SDRAM_CLK to the falling edge of, SDRAM CLK. Use the following clock waveform for this and the next question. The clock edges will be Ons to 3.75ns. Lab 3-16 rao! | \, Setup Hold 7 / seup| ons! asas\ 7808 7 ons \ 3750s/° 7508 , / , ons 375m 75s ons 3.750878 Generating Reports ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 3 Question 23. For this same timing path, describe the specific clock edges that will be used in a timing report for hold timing checks. ‘The clock edges will be 7.5ns to 3.75ns. # Commands for the final task # The backslash is a line continuation character # the switch -delay min max will generate one report for setup and # one for hold xeport_timing -ris 5 from [get_clocks SPRAM_CLK) \ -fall_to [get_clocks SDRAM CLK) -delay_type min_max xeport timing =£al1_from [get_clocks SURAM_CLX) \ tise to [get_clocks SDRAM CLK] -delay type min_max Question 24, Which switch is useful for generating the worst 10 timing reports for each of these half clock cycle timing paths? ‘The switch -max_paths 10 to the above command. Question 25. Why does PrimeTime report “no constrained paths?” ‘The -max_paths option implicitly sets another option: slack lesser_than 0, which, because slack is positive, results in no constrained paths. What additional option must you use to report the worst 10 timing paths? Since there are no violating paths that could be reported in this case, add the option: slack_less_than 100 Generating Reports Lab 3-17 ‘Synopsys PrimeTime WorkshopLab 3 Answers / Solutions This page is left blank intentionally. Lab 3-18, Generating Reports ‘Synopsys PrimeTime WorkshopConstraining Multiple Clocks After completing this lab, you should be able to: * Apply the commands taught in lecture to gather information about the design clocks © Use the GUI for another view of the design clocks and their relationships Lab Duration: 45 minutes Constraining Multiple Clocks Lab 4-1 Synopsys 10-1-034-SLG-015Lab 4 Overview Relevant Files and Directories All files for this lab are located in the Lab4_clocks directory under your home directory. lab4_clocks/ Current working directory Lab 4-2 orca_savesession/ orca_savesession_violations/ RUN. tel -synopsys_pt.setup scripte/ orca_pt_variables.tcl Initial Saved ORCA session Saved ORCA session with an issue Run script for ORCA PT setup filet ‘Variable script Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopLab4 Instructions Task 1. Get to Know the Design Clocks 1. Make sure your current directory is lab4_clocks 2 Invoke PrimeTime (pt_shell). Restore the session saved in. /orea_savesession Take advantage of command and file name completion by typing a few letters and then using the tab key. 3. Use the commands taught in lecture to answer the following questions. Use the job aid labeled “Clocks and More” for help recalling the specific commands. Question 1. How many clocks are in this design and how many of these are generated? Question 2, Which input ports have defined, master clocks? Question 3. Which output ports have defined, outgoing clocks? Question 4. Are the clocks propagated or ideal? Question 8. Which 3 clock pairs have constrained timing paths? Constraining Multiple Clocks Lab 4-3 ‘Synopsys PrimeTime WorkshopLab 4 Lab 4-4 Task 2. Use the GUI to Report Clock Relationships If your design has many clocks, the GUI may simplify the task of understanding how the clocks are related. 1. Start the GUI by executing the following command, pt_shell> start_gui Note: The original pt_shell session is still running in the terminal window. You can keep the GUI open and use either the shell or the GUI interface as appropriate to the desired tasks. 2. Lookat clock domain crossings: Open the “clock domain matrix” from the pull-down menu: Clock > Clock Analyzer. ‘The Clock4nalyzer window that opens (expand if needed by clicking on the plus signs to the left of the clocks) should match the information from. check_timing when reporting the clock crossings in the design, Mouse over the blocks in the matrix to see information on what type o false paths exist. It is sometimes easier to digest this information as a graphical matrix table in comparison to the text output from check_timing -override clock_crossing -verbose. The left part of the window lists each master clock and any generated clocks that are created from each master clock. Question 6. What is the master clock for SY8_2x_CLK? Question 7. S¥S_2x_CLK is defined on which pin/port (its “source”)? (note: you may have to drag the clock matrix out of the way, exposing more columns of information about the clocks) Question 8, The master clock for SYS_2x_CLK is defined on which pin/port? Explore in more detail by displaying the clock schematic for SYS_2x_CLK: select the clock, then right mouse button->Schematic of Selected Clocks. Expand the fanin for the schematic for the MUX called 1_CLOCK_GEN/U20 [Hint: To locate/highlight U20, use Select -> By Name] by double-clicking the input stubs, as shown in the following screen captures. Continue the double clicks until the fanin is exhausted [Example: an input port Constraining Multiple Clocks ‘Synopsys PrimaTime WorkshopLab 4 has been reached] Legendi[C- Fully constrained paths Launchi[svs2mciK || C locks 7 [perio waveform fa | 2 | sf [sie rrcck 1s (075) a é lb somamcik 75 (0375) [aK Gol - esp... 75 (0375) © sooo. 75 37575) [al OF SYS CKO (0:l icaliipze all Selectedlclocks Expand all Selected Clocks hide all Selected Clocks Deep Select all Generated Clocks Clock Graph of Selected Clocks Clock Graph for Clock Domain [== 5 schematic of selected clocks Select Source Pins or Ports Double-click input pin stubs Result of double-clicking input pin stubs Question 9. What port is connected to the select pin of the MUX I_CLOCK_GEN/U20? Constraining Multiple Clocks Lab 4-5 ‘Synopsys PrimeTime WorkshopLab4 Lab 4-6 4, 6. % 10. Question 10. Does seeing the schematic give you insight into the clocking scheme for test? Explore clock relationships with the abstract clock graph: Close the schematic window, then, on the TopLevel window, select Clock-> Clock Graph for All Clocks. Ifnecessary, display a toolbar next to the schematic by pressing the F8 key. Display various elements by checking the toolbar and pressing Apply. Find a pair of muxed clocks: In the Abstract Clock Graph toolbar, select Mux and click Apply. In the Abstract Clock Graph, find instance | CLOCK_GEN/U10 of mx02d1. (Hint: To locate/highlight U10, use Select -> By Name] Question 11. What clocks drive | CLOCK_GEN/U10? From the clock graph window, ‘zoom into’ an interesting object by displaying a schematic for it: Select | CLOCK_GEN/UIO, then Schematic > Schematic View. Question 12. What port drives the select line to I_CLOCK_GEN/UI0? Go back to the Abstract Clock Graph. Question 13. From the abstract clock graph window, is it possible to open and display the same clock schematic for SYS_2x_CLK you displayed in the clock analyzer [Right Click on SYS_2x_CLK and find the option]? Close the Clock Analyzer window by clicking on the small “X” in its upper right comer. Close the Clock Schematic and Clock Analyzer windows by clicking on the small “X” in the upper right comer, Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopTask 3. __Use the GUI to explore detail of timing paths Investigate paths between launch and capture clocks —in this case, you will look at network lateney for the launch and capture paths clocked by SYS_CLK. 1. Propagate all the clocks to have the clock network delays calculated by Primetime before examining paths, by executing these commands in the shell, which remains open behind the GUI (this will take a minute or so to complete). Tell PrimeTime to save the arrival times for all pins (thi you will examine). Then, define a collection of timing paths to examine, what set_propagated_clock [al1_clocks] set timing _save pin arrival_and_slack true update_timing set my_paths (get_timing paths -max 10 -group SYS CLK =path full clock expanded] 2. Enter your collection of violating paths from the pull-down menu Timing > Path Analyzer. Enter your collection of timing paths and click Apply 3. Bring up a histogram of your ten timing paths. Cr | Right mouse Sa click on ALL and. |} egletionsl| fery_paths select Create Histogram, then Arp | caree select OK on the resulting Categories: en Seles bow epee ee [gras {rom Si on eae Sled caso bs Tia es Constraining Multiple Clocks Lab 4-7 Synopsys PrimeTime WorkshopLab4 4, From the histogram, bring up the Path Inspector on a selected path. ‘eps renee oar nd rte uring paths oe: tning pores ‘ce starponts Ge: enpoirts ‘er lanch dock pats Ce eapure cock pate ‘mngrath | Crate cabecien Lab 4-8 (ropecto]Reron|emen [abe whic. OT 2: Select the worst path, then click on. “Inspector” Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopLab4 5. Inthe Path Inspector, examine clock reconvergent pessimism: In the data required and data arrival section, scroll down until you find CRP. Then, scroll across until you find the percent of delay for the CRP. Launch clock Oey Capture Cock Delay Path ype max Path croup: S¥S.0UK ‘tarpon’ LORCA, TOPf_ ALENOER/#3.0p2.reg(18 (sing edpe-viggeed fp-fop cocked by 5S CLK) EEndpont. —LORCA“TOP/_SLENOER/#4_op2/r09(31 ising edge-tiggered fp:Nop cocked by SYS_CLK) uneh Code $¥5.cuer ‘Capture dock: SYSCUXr vez _[ Fore [Paella Cpr Oa soar Beare arr | 000 3000 ase Question 14, What percent of the capture delay comes from CRP? Question 15. Is this percent representative of all designs? Constraining Multiple Clocks Lab 4-9 ‘Synopsys PrimeTime Workshoper b 6. Look at a schematic of the path by clicking on the Schematic tab on the bottom of the path inspector window. TELUS eck LeU CcM em ee fle_Wiew Select ighight Schematic ECO Window Lely JslQagalliraanz ojaall* +B 2x [fer lke slay __— AO [cfck objects or drag a boxto select (Hold Grito add, shiftto remove | In the schematic window, find the CRP (clock reconvergent pessimism) point This is the last pin before the launch and capture paths diverge. Note: Mouse “gestures” or “strokes” are available for easier zooming: While pressing the middle mouse button drag the cursor vertically for ‘zoom full’; Drag diagonally up across an object to zoom in, and down across an object to zoom out. 8 Zoom Mouse Tools Select Lighight Selected objects ‘colapse Al Hierarchy i All Buffersfinverters/Crossings, [see —slfcers slat ———"H_anuncomecte ne [cick objects or drag a box to select (Hold Chito add, shitto remove)|Num] 3. Lab 4-10 Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopLab 4 9, View the acrival times (and any other attributes of interest) by selecting the output pin of the buffer just before the register, then by selecting View->Property Question 16. How wide is the arrival window for thee buffer output pin? Question 17. Does this match what we saw earlier in the data arrival data required section of the path inspector? 10, Examine the path waveform: Click on the Waveform tab atthe bottom of the Path Inspector window. Question 18, What can you add to the wavforms by clicking the right mouse button in the waveform window? 11. Close the GUI while keeping the original pt_she11 session going in the terminal window: File > Close GUT (inthe main GUI window) Or pt_shell> stop gui (inthe pt_shell window) 12, Exit PrimeTime. Constraining Mutiple Clocks Lab 4-11 ‘Synopsys PrimeTime WorkshopLab 4 Task 4. Report a False Violation 1. Bring up PrimeTime and restore the saved session orca_savesession_violations 2 Determine the number and type of timing violations in ORCA: report_anelysis_coverage Question 19, How many, and what kind of violations does ORCA have? 3. Generate a “short” timing report for the worst slack for an out_setup timing check, Question 20. How will you identify the endpoint port which has the worst slack for out_setup (use the job aid labeled “Timing Reports” for help recalling the two appropriate switches)? Question 21. Which clocks (launch and capture) are involved in this violation? From task 1, you know that SD_DDR_CLK is a generated clock defined at an output port. The purpose of defining outgoing clocks is that PrimeTime calculates source latency for this clock and include this latency as part of the data required time. 4. Look at the data required time section of the timing report from the last step and notice that no clock latency is reported. Confirm this with the following command: # This report will return nothing as PrimeTime has not # calculated source latency for SD_DDR_CLK pt_shell> report_clock -skew SD_DDR_CLK Question 22. Why has PrimeTime not calculated source latency for the outgoing clock SD_DDR_CLK? Lab 4-12 Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopLab4 After speaking with the designer, it turns out there was a miscommunication. The designer was expecting you to turn on a variable that will propagate all clocks! 5. There is a variable that can be used to make all clocks propagated. Use the Tel procedure aa to help you identify the appropriate variable: aa propagate Question 23. What is the name of this variable? Question 24. Using a man page, explain what this variable will do? 6. Use the man page for check_t.iming to find the name of the additional check that will flag all ideal clocks. The following command opens the man page in a pop-up window with a scroll bar that simplifies viewing long reports pt_shell> vman check timing The above command is an alias created in the .synopsys_pt.setup file. It uses a command called view that is available on SolvNet, Doc Id 014947. The alias vman will not work if the “wish” executable, the main executable in the Tk package, is not installed and made available in your lab environment Question 25. How will you modify check_timing to adda check to validate that all clocks are propagated? 7. Quit PrimeTime, Constraining Mutiple Clocks Lab 4-13 Synopsys PrimeTime WorkshopLab4 Task 5. _Re-Execute the Run Script to reduce violation L 4. Lab 4-14 You are provided with the file . /acripts/orca_pt_variables.tcl that will accomplish the following two things. © Adds to the default checks performed by check_timing the check that will flag ideal clocks. + All created clocks will be created as propagated clocks. Execute the run script . /RUN. te from the lab4_clocks Unix directory Log the results to the log file run. log. unix> pt_shell -£ ./RUN.tcl | tee -i run.log Invoke PrimeTime and restore the newly saved session in the Unix directory ./orca _savesession Use the appropriate commands to confirm the information below: ‘The out_setup violations have been reduced, © Allclocks are propagated. © Execute check_timing to confirm it is performing its default checks in addition to the check for ideal clocks. * The source latency is now calculated for SD_DDR_CLK. © The timing report to s4_DQ[31 includes this calculated source latency. There will be additional violations (more setup violations as well as out_hold violations) that you can ignore. Quit PrimeTime. This completes lab 4. Return to lecture. Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab4 Answers / Solutions Question 1. How many clocks are in this design and how many of these are generated? This information can be gathered frum xeport_clock, ot using the following commands. pt_shell> sizeof_collection [all_clocks] 6 pt_shell> sizeof collection [get_generated clocks *] 3 Question 2, Which input ports have defined, master clocks? pt_shell> rpt_clock ports Port Name Direction Clock Name ‘Is Generated pelk in PCI_CLK false sys_clk ain SYS_CLK false sdr_clk in SDRAM_CLK false 86_CK out SD_DDRCIK true sd_ckn out SD_DDRCLKn true Question 3. Which output ports have defined, outgoing clocks? From the same report, s_CK and sd_Ckn. Question 4, Are the clocks propagated or ideal? Use report_clock to see that all the design clocks are ideal. Constraining Multiple Clocks Lab 4-15 Synopsys PrimeTime WorkshopLab4 Answers / Solutions. Question 5. Which 3 clock pairs have constrained timing paths? pt_shell> check timing -over clock crossing -verbose Information: Checking 'clock_crossing'. Information: There are 4 clocks having domains interacting. * all paths are false paths + part of paths are false paths From Clock Crossing Clocks PCI CLK SYS_CLK* SDRAM_CLK SD_DDR_CLEH, SYS _CLK* SYS_2x_CLK SDRAM_CLK*, SYS_CLK sys CLR PCI_CLK*, SDRAM CLK*, SYS_2x CLK Question 6. What is the master clock for SYS_2x_CLK? SYS_CLK Question 7. SY¥S_2x_CLK is defined on which pin/port (its “source”)? I_CLOCK_GEN/T_CLEMUL/CLE_2x (You may have to drag the window containing the matrix out of the way in order to see the source pins) Question 8. ‘The master clock for SYS_2x_CLK is defined on which pin/port? sys_clk Question 9. What port is connected to the select pin of the MUX 1_CLOCK_GEN/U20? test_mode Question 10. Does seeing the schematic give you insight into the clocking scheme for test? ‘Yes ~two clocks come into the mux: one from the clock generator, one directly from the port. The test_mode port controls the select line, making it possible to bypass the clock generator during test mode and letting the design be driven directly from the port, Question 11. What clocks drive | CLOCK_GEN/U10? SYS_CLK and SYS_2x CLK Lab 4-16 Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 4 Question 12. What port drives the select line to | CLOCK_GEN/U10? power_save Question 13. From the abstract clock graph window, is it possible to display the same clock schematic you displayed in the clock analyzer? Yes. Select the clock SYS_2x_CLK (you may have to zoom in to select just the clock), then press right mouse button and select Schematic for Selected Clocks. You may have to expand input or output stubs (by double clicking on them) to get the exact same schematic. Question 14, What percent of the capture delay comes from CRP? 4.18% Question 15. Is this percent representative of all designs? No, this number is dependent on the particular design and on the particular path. Question 16. How wide is the arrival window for the buffer output pin? tis 2.86939 minus 2.40107, or about 468. Question 17. Does this match what we saw earlier in the data arrival data required section of the path inspector? Yes. Question 18. What can you add to the waveforms by clicking the right mouse button in the waveform window? You can add input pins and output pins, allowing you to see the detail for the whole path. Question 19. How many, and what kind of violations does ORCA have? There are 23 setup violations, 53 hold violations, and 32 cout_setup violations. Question 20, How will you identify the endpoint port which has the worst slack for out_setup? pt_chell> report_timing -path short -to [all_outpute] on pt_shell> page_on pt_shell> report_analysis coverage -status violated ~check out_setup type of Check Total Met violated untested Constraining Multiple Clocks Lab 4-17 Synopsys PrimeTime WorkshopLab 4 Answers / Solutions out_setup 15 43 ( 87%) 32 ( 43%) 0 « 08) All Checks 15 43. (57%) 32 ( 438) 0 ¢ of) Constrained Related check Pin Pin Type Slack Ba DOTeN ‘SDLDDR_CLK out setup =i 4006 sd_pQts} SD_DDR CLK out _setup -1,4006 5d DQLa] SD_DDR CLK out setup, -1.4006 Which clocks (launch and capture) are involved in this violation? pt_shell> report_timing -to sd_DQ{6] path short Startpoint: sdr_clk (clock source 'SDRAM_CLK!) Endpoint: sd_D9Q{6] (output port clocked by SD_DDR_CLK) Path Group: SD_DDR_CLK Path Type: max Min Clock Paths Derating Factor : 0.9000 Point incr Path clock SDRAM_CLK (fall edge) 3.7500 3.7500 clock source latency 0.0000 © 3.7500 sdr_clk (in) 0.0000 3.7500 £ sd_Dg{6} (inout) 4.4006 8.1506 £ data arrival time 8.1506 clock SD_DDR_CLK (rise edge) 7.5000 7.5000 clock reconvergence pessimism 0.0000 = 7.5000 output external delay 0.7800 6.7500 data required tine 6.7500 data required tine 6.7500 data arrival time 8.1506 slack (VIOLATED) 1.4006 Question 22. Why has PrimeTime not calculated source latency for the outgoing clock SD_DDR_CLK? The clocks (specifically the master clock) must be propagated for PrimeTime to calculate the source latency for generated clocks. All clocks in this design are ideal. Lab 4-18 Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopAnswers / Solutions Lab 4 Question 23. What is the name of this variable? pt_shell> aa propagate dtiieese Commands *** remove propagated clock # Remove a propagated clock specification set_propagated_clock # Specify propagated clock latency desteeiek Variables tsnores case_analysis propagate through icg = "false" timing all clocks propagated = "false" ‘timing_clock_gating propagate enable = "false" timing propagate_interclock_uncertainty = "false" timing_propagate_through_non_latch d pin arcs = "false" Question 24. Using a man page, explain what this variable will do? All clocks created after this variable is set to true will be created as propagated clocks. The clocks will be set to propagated in the next task. Question 25. How will you modify check_timing toadd a check to validate that all clocks are propagated? The added check is named ideal_clocks. You can add this check to the variable timing_check_defaults using lappend such that it is executed automatically with check_timing. ‘This will be done in the next task. ## Answers for TASK 5 STEP 1 # Add the following to ./scripte/orca_pt_variables.tcl append timing check defaults ideal_clocks set timing all clocks propagated true Constraining Multiple Clocks Lab 4-19 Synopsys PrimeTime WorkshopLab4 Answers / Solutions # Answers for Task 5 Step 4 # Out_setup violations should be reduced. pt_shell> report_analysis coverage # All clocks should be propagated pt_shell> report_clock # The command check timing does not flag ideal clocks pt_shell> check timing Information: Checking 'no_clock'. Information: Checking ‘no_input_delay'. Information: Checking ‘partial _input_delay' Information: Checking 'ideal_clocks # The source latency is being calculated for SD_DDR_CLK pt_shell> report_clock -skew SD_DDR_CLK # The source latency is applied to the timing report to sD_DOL6] pt_shell> report_timing -to sd_pQ{6] -path short Startpoint: sdr_clk (clock source 'SDRAM_CLK') Endpoint: sd_D9[6] (output port clocked by SD_DDR_CLK) Last common pin: sdr_clk Path Group: SD_DDR_CLK Path Type: max Min Clock Paths Derating Factor : 0.9000 Point, Incr Path clock SDRAM CLK (fall edge) 3.7500 3.7500 clock source latency 0.0000 3.7500 sdr_clk (in) 0.0000 3.7500 £ sd_DQ{6] (inout) 4.4006 8.1506 £ data arrival time 8.1506 clock SD_DDR_CLK (rise edge) 7.5000 7.5000 clock network delay (propagated) 2.9149 10.4149 clock reconvergence pessimism 0.0000 10.4149 output external delay -0.7500 9.6649 data required time 9.6649 data required time 9.6649 data arrival time 8.1506 slack (MET) 2.5243 Lab 4-20 Constraining Multiple Clocks ‘Synopsys PrimeTime WorkshopLab Duration: 30 minutes ‘Additional Constraints ‘Synopsys 10-1-034-SL6-015 Additional Constraints After completing this lab, you should be able to: © Apply user specified annotated delays to explore time borrowing with latches ‘© Debug PTE-070 messages regarding non-unate cells, on the clock path Lab 5-1,Lab 5 Overview Relevant Files and Directories All files for this lab are located in the Lab11_speci fic directory under your home directory. labS_additional/ Current working directory orca_savesession/ Saved session for ORCA, RUNitel Script to create orca_savesession logs/ Log fites from run seript _synopsys_ptsetup PT setup file Lab 5-2 Additional Constraints, ‘Synopsys PrimeTime WorkshopLab 5 Instructions Task 1. Debug PTE-070 Information Messages 1. Invoke PrimeTime from the lab5_additional Unix directory. Restore the session saved under . /orca_savesession. 2. Shown below is the full message regarding a non-unate path on the clock network. In the next step, you will be asked to generate a timing report through this pin. In order to copy and paste and avoid typos — either find this message in the log file from another terminal window or use the Unix command grep from within PrimeTime as shown below. # Fron ./logs/run. log Information: A non-unate path in clock network detected. Propagating both inverting and noninverting senses of clock ‘SDRAM CLK! from pin *T_ORCA_TOP/I_SDRAM IF/sd_mux_dq_out_0/Z'. (PTE-070) pt_shell> sh grep -A 1 -B 1 PTH-070 logs/run.log Note: The command sh (or alternatively exec) allows you to execute Unix commands from within the PrimeTime shell. 3. Generate a timing report for setup through the above pin and answer the following questions. The following alias has been created in the PrimeTime setup file and will generate a timing report in a pop-up window with a scroll bar using the view utility found on SolvNet, Doc Id 014947. pt_shell> vrt -through Question 1. Which lines in the timing report did you use to validate it is for setup and the timing path start point is the source for the clock SDRAM_CLK? Additional Constraints Lab 5-3 Synopsys PrimeTime WorkshopLabs Lab 5-4 Question 2. How does this timing report confirm that the pin in the warming above is on a data path (i.e. a clock source being used and constrained as a data path) and not on a clock path? Question 3. Which sense is propagated through the above pin (ie. positive unate or negative unate)? Look for a smalll arrow in the timing report which will locate the specitie pin of interest. 4. Generate at least one additional timing report to show the use of a negative unate timing arc through the pin of interest. Question 4, Which lines in the timing report did you use to validate it is, for setup, the timing path start point is the source for the clock SDRAM_CLK and that the timing arc is negative unate for the pin of interest? Question 5. Explain why this warning can be ignored (and suppressed) for these timing paths? 5. Donot quit PrimeTime. Task 2. Explore Time Borrow and Latches There is only one latch in this design. 1 Use the following commands to find it: Take advantage of command and option completion with the tab key. pt_shell> all registers -level_sensitive pt_shell> !! -clock pin pt_shell> all_registers -level_sensitive -data pins Question 6. What is the name of the clock pin for this latch? Additional Constraints ‘Synopsys PrimeTime WorkshopLab 5 Question 7. What are the names of the three data pins? 2. — Generate a timing report starting at the latch for setup time (be specific by using the clock pin as the start point and not just the cell name!) This Iab will refer to this timing report as “path segment #2”. ‘The function of this latch in the ORCA design is to generate a clock gating signal to turn on and off the clock S¥S_CLK. Question 8. Describe how you know this latch is not experiencing time borrow from the previous stage? 3. Generate a timing report for the previous stage (this lab will refer to this timing report as “path segment #1”). Use the D input pin of the latch as the end point of this timing path. Question 9. How much more time can path segment #1 take before it ‘would start borrowing time from path segment #2? 4, Force path segment #1 to borrow time from path segment #2 by annotating a net delay of dns as shown below: # Use cut and paste to avoid typos on the pin name pt_shell> set_annotated delay -net 4 \ “to 1_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D 5. Generate the timing report for path segment #1 again (take advantage of the up and down arrows to scroll through the history event list). Question 10. How much time is path segment #1 borrowing from path segment #2? Question 11. What is the slack for path segment #1? Additional Constraints Lab 5-5 ‘Synopsys PrimeTime WorkshopLab5 6 Re-generate the timing report for path segment #2. Before you can do that, you have to perform a full timing update! pt_shell> update timing -ful1 Note: The start point of the timing path will now be the D pin of the latch (not the clock pin as used before) because you are interested in reporting the timing path that includes time borrow. pt_shell> report_timing -from \ T_ORCA_TOP/T_BLENDER/latched_clk_en_reg/D Question 12, Does the time given to path segment #1 now match your expectations? 7. Change the latch behavior for transparency; that is, make it transparent when data arrives between the opening and closing edges of the clock. set_app_var timing enable through paths true 8. Repeat your timing report to the latch D pin, Notice that, even though the latch is transparent, you can still specify the D pin as an endpoint, report_timing -to \ ‘"“I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D" Question 13. What is the startpoint? 9. Doatiming report FROM the startpoint you just identified. xeport_timing -from \ I_ORCA_TOP/I_PARSER/blender_clk_en_reg/CP Question 14. What is the path endpoint?. Question 15. What are the transparency open and close edges?. Lab 5-6 Additional Constraints ‘Synopsys PrimeTime WorkshopLab 5 Question 16. Did data arrive between them?. Question 17. Was there time borrowing? Question 18, Was slack positive?. 10. Quit PrimeTime. This completes Lab 5. Return to lecture. ‘Additional Constraints Lab 5-7 ‘Synopsys PrimeTime WorkshopLab5 Answers / Solutions Answers / Solutions Question 1. Which lines in the timing report did you use to validate it is for setup and the timing path start point is the source for the clock SDRAM_CLE? pt_shell> report_timing -through T_ORCA_TOP/T_SDRAM_IF/sd_mux_dq_out_0/2 Startpoint: sdr_clk (clock source ‘SDRAM CLK') Endpoint: sé_pQ{0] (output port clocked by SD_DDR Path Group: SD_DDR_CLK Path Type: max , CLK) Question 2, How does this timing report confirm that the pin in the ‘warning above is on a data path (jc. a clock source being used and constrained as a data path) and not on a clock path? If no report was generated (“path is unconstrained”), this pin is ona clock path. Because a timing report was generated, this pin is on a data path Question 3. Which sense is propagated through the above pin (ic. positive unate or negative unate)? Look for a small arrow in the timing report which will locate the specific pin of interest. A positive unate timing arc (fall to fall) is reported through, this pin. # Shown are the relevant lines in the data path T_ORCA_T 1_SDRAM_IF/buffa765B2136/% (bufta7) 0.1634 & 4.8748 £ _ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/Z (mxo2d4) <- 0.5431 & 5.4179 £ Question 4, Which lines in the timing report did you use to validate it is for setup, the timing path start point is the source for the clock SDRAM_CLX and that the timing arc is negative unate for the pin of interest? Lis pt_shell> report_timing \ srise_through I_ORCA_T0P/Z_SDRAM_IF/sd_mux_dq_out_0/z Startpoint: sdr_clk (clock source ‘SDRAM_CLK') Endpoint: sd_OT0} (output port clocked by SD_DDR_CLK) Path Group: SD_DDR_CLE Path Type: max Lab 5-8 Additional Constraints ‘Synopsys PrimeTime WorkshopAnswers | Solutions Lab5 T_ORCA_TOP/Z_SDRAM_IF/bufta7G582136/2 (buf£a7) 0.1634 & 4.8748 £ T_ORCA_TOP/I_SDRAM_IF/sd_mux_dq_out_0/2 (mx02d4) <- 0.4928 & 5.3676 x Question 5. message can be ignored for these timing The message indicates that both senses of the clock will be used when propagating the clock through this mux ~ this is the default behavior. However, because the clock is being used as data, PrimeTime actually propagates both senses (both positive and negative unate), even in older versions of PrimeTime. This is what is desired and therefore this information message can be ignored. Question 6. What is the name of the clock pin for this latch? pt_shell> all_registers -level_sensitive -clock pins {"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/EN"} Question 7, What are the names of the three data pins? pt_shell> all_registers -level_sensitive -data pins {"I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D", *I_ORCA_TOP/T_BLENDER/latched_clk en _zeg/SC", "I_ORCA_TOP/T_BLENDER/latched_clk_en_reg/sD"} # For step 2, generate a timing report for path segment 2 pt_shell> report_timing -from I_ORCA _TOP/T BLENDER/latched clk en _reg/EN ‘Additional Constraints Lab 5-9 ‘Synopsys PrimeTime WorkshopLab5 Answers / Solutions Question 8. Describe how you know this latch is not experiencing time borrow from the previous stage? If this latch were experiencing time borrow, there would be a line in the report stating the amount of time given to the start point (i. to the previous stage). This line is not present in this timing report. # For step 3, generate a timing report for path segment 1 pt_shell> report_timing -to _ORCA_TOP/I_BLENDER/latched_clk_en reg/D Question 9. How much more time can path segment #1 take before it would have to start borrowing time from path segment #27 It can take 3.465ns more before it would start borrowing time from path segment #2 (equivalent to the positive slack). Question 10. How much time is path segment #1 borrowing from path segment #2? Path segment #1 is borrowing 0.5306ns from path segment #2. This is noted in the data required time section of the timing report. Question 11. What is the slack for path segment #1? ‘The slack is zero. PrimeTime borrows exactly as much as is needed to make the slack equal zero. Does the time given to path segment #1 match your expectations? ‘Yes ~ the time given to start point in the timing report for path segment #2 will match the time borrowed in the timing report for path segment #1. pt_shell> report_timing -from I ORCA_TOP/I_BLENDER/latched clk en reg/D pt_shell> report timing -to T_ORCA_TOP/I_BLENDER/latched_clk_en_reg/D lLab 5-10 Additional Constraints ‘Synopsys PrimeTime WorkshopAnswers / Solutions Question 13. Question 14. Question 15. Question 16. Question 17. Question 18. ‘Additional Constraints Synopsys PrimeTime Workshop Lab 5S What is the startp LORCA_TOP/_PARSER/blender_clk_en_reg/CP What is the path endpoint? 1_ORCA_TOP/I_BLENDER/U794/A (a gating check) ‘What are the transparency open and close edges? 6.6454 and 10.4433 Did data arrive between them? yes—at time 7.1759 ‘Was there time borrowing? no ‘Was slack positive?. yes The timing report through the transparent latch is on the next page: Lab 5-11Lab5 Answers / Solutions pt_shell> report_timing -from 1 ORCA_TOP/I_PARSER/blender_clk_en_reg/CP Startpoint: T_ORGA_T0P/1_PARSER/blender_clk_en_reg (rising edge-triggered flip-flop clocked by s¥8_cLK) Endpoint: I_ORCA_TOP/1_BLENDER/U794 (rising clock gating-check end-point clocked by SYS_CLK) Last common pin: T_CLK_SOURCE_SYS_CLK/Z Path Group: *#clock gating default** Path Type: max Min Clock Paths Derating Factor : 0.9000 Point Ince Path clock SYS_CLK (rise edge) 0.0000 0.0000 clock network delay (propagated) 21139 2.7139 T_ORCA_TOP/2_PARSER/blender_clk_en_reg/CP (sdcrb1) 0.0000 2.7139 x TLORCATOP/1_PARSER/blender_clk_en_reg/Q (sdcrbi) 0.4621 & 3.1759 x TLORCATOP/T_BLENDER/latched_clken_reg/D (sinlqi) 4.0000 * 7.1759 x transparency window #1 clock SYS_CLK (fall edge) 4.0000 clock latency 2.3280 6.3250 clock reconvergence pessimism 0.3203 6.6454 transparency open edge 6.6454 clock SYS_CLE (rise edge) 8.0000 clock latency 2.3596 10.3596 clock reconvergence pessimism 0.3203 10.6800 library setup time 0.2367 10.4433 transparency close edge 10.4433 available borrow at through pin 3.2674 T_ORCA_TOP/T_BLENDER/latched_clk_en_reg/D (sInlgl) 0.0000 7.1759 r T_ORCAWOP/1_BLENDER/latched_clk_en_reg/Q (slnigi) 0.3164 H 7.4924 r T_ORCA_TOP/T_BLENDER/U794/B1 (oraz1ds) 0.0263 & 7.5186 F data arrival time 7.5186 clock SYS_CLK (rise edse) 8.0000 8.0000 Clock network delay (propagated) 1.6428 9.6425 Glock reconvergence pessimism 0.2160 9.8585 J_ORCA_TOP/T_BLENDER/U794/A (oraz1é4) 9.8585 x clock gating setup time 0.2000 9.6585 data required tine 9.6585 data required time 9.6585 data arrival time 7.5186 slack (MET) 2.1398 Lab 5-12 ‘Additional Constraints ‘Synopsys PrimeTime Workshop