B Helios Ecl XCL
B Helios Ecl XCL
UART
2
Serial Tx /
2 LVDS
Serial Rx /
8 Buffers PSG #1
MDR26 Camera Control /
8
Data / 28-bit
24
TM
Serial Tx
2
/
LUTs
Oasis (up to 5.3 GB/s) SDRAM
2 LVDS
Serial Rx /
8 Buffers PSG #2 LINK 0
Aux. In (4) /
(up to 1 GB/sec) 64-bit (up to 1 GB/sec)
8
Aux. Out (4) /
8
Aux. In (4) / Opto-couplers
UART
2
Serial Tx /
2 LVDS
Serial Rx /
8 Buffers PSG
Camera Control /
MDR26
8
Data / 28-bit
24
TM
2 ChannelLink
Clock / Receiver /
8 Video
Data / 28-bit 16 64 4 x 256 x 8-bit 64 64
ChannelLink
TM
/ / and
/ to /
2 4 x 4K x 12-bit PCI-X
LINK 1
Clock / Receiver LUTs
Bridge
MDR26
8 Matrox 128
/
up to 512 MB
DDR
Data /
2
28-bit
ChannelLink
TM
24
/ Oasis (up to 5.3 GB/s) SDRAM
Clock / Receiver
LINK 0
6 TTL
Aux. I/O (6) /
Transceivers 64
/
(up to 1 GB/s)
4
Clock (2) /
4
DB-44 Hsync (2) / PCI-X to PCIe (eCL)
® TM
and 4 LVDS
Vsync (2) / or PCI-X (XCL) Bridge
®
DB-9* 8 Transceivers
Aux. In (4) /
8
Aux. Out (4) /
8
Aux. In (4) / Opto-couplers
x4 PCIe (eCL) TM
5V/3.3V PCI/PCI-X (XCL) ®
2
State-of-the-art Matrox Oasis ASIC Field-proven application development software
The Matrox Imaging designed Oasis ASIC is the pivotal component Matrox Helios eCL/XCL is supported by the Matrox Imaging
of the Matrox Helios eCL/XCL. A high-density chip, the Matrox Library (MIL), a comprehensive collection of software tools for
Oasis integrates a Links Controller, main memory controller developing industrial imaging applications. MIL features
and Pixel Accelerator. interactive software and programming functions for image
capture, processing, analysis, annotation, display and
Pixel Accelerator archiving. These tools are designed to enhance productivity,
The Pixel Accelerator (PA) is a parallel processor core, which thereby reducing the time and effort required to bring your
considerably accelerates neighborhood, point-to-point and LUT solution to market. Refer to the MIL datasheet for more infor-
mapping operations. It consists of an array of 64 processing mation.
elements all working in parallel. Each processing element has a
multiply-accumulate (MAC) unit and an arithmetic-logic unit (ALU). MIL’s image processing module, when used with the Matrox
Helios eCL/XCL, comes with royalty-free redistribution rights.
The MAC unit is capable of performing a single 16-bit by The image processing module, which includes functions for basic
16-bit, two 8-bit by 16-bit or four 8-bit by 8-bit multiplies arithmetic, logic, LUT mapping, per pixel gain and offset, morphol-
with 40-bit accumulation per cycle for convolution operations. ogy, spatial filtering, statistics, temporal filtering and threshold, is
The 40-bit accumulator guarantees no overflow situation for a fully optimized for the PA4. Support for custom PA functions is also
16 by 16 kernel with 16-bit coefficients and data. In addition, the available on demand and upon evaluation.
PA architecture allows symmetrical kernels to be processed
four times faster. The MAC unit can perform up to four minimum Specifications
or maximum operations per cycle for grayscale morphology
operations. Hardware
®
• x4 PCIe card or PCI/PCI-X card with universal 64-bit card
TM
The ALU can execute a wide variety of arithmetic and logical edge connector (64-bit 33/66 MHz 5/3.3V PCI and 64-bit
operations. It can be programmed to execute a sequence of 256 66/100/133 MHz PCI-X)
instructions per pixel at one instruction per cycle reducing the • up to 512 MB of 167 MHz DDR SDRAM main memory
amount of memory accesses and further accelerating memory • two factory configured versions
I/O-bound sequences. The PA can accept up to four source buf- - two independent Camera Link® Base ports1 (dual-Base)
fers3 and output to four destination buffers allowing several oper- - single Camera Link® Base/Medium/Full port1 (single-Full)
ations to be performed at once or in a single pass (e.g., four • Channel Link speed of up to 85 MHz
images can be averaged in one pass). Operating at a core fre- • supports frame and line-scan video sources
quency of 167 MHz enables the PA to carry out up to 100 BOPS2 • full reconstruction from multi-tap sources
(i.e., process over two billion pixels per second). • four 256 x 8-bit and four 4K x 12-bit LUTs
• six TTL configurable auxiliary I/Os
Memory controller • four LVDS configurable auxiliary inputs
The Matrox Oasis includes a very efficient main memory control- • four LVDS configurable auxiliary outputs
ler for managing the 128-bit wide interface to DDR SDRAM • two separate LVDS pixel clock, hsync and vsync outputs
memory. Operating at 167 MHz, the DDR SDRAM memory and • four opto-isolated configurable auxiliary inputs
controller combine to deliver a memory bandwidth in excess • serial communication ports that can be mapped
of 5 GB as PC COM ports
per second. Such ample memory bandwidth allows the Matrox • internal video generator for diagnostics
Helios eCL/XCL to comfortably handle demanding video I/O
while maintaining PA performance even for memory I/O- Dimensions and environmental information
bound operations. • 18.75 L x 10.7 H x 1.73 W cm (7.38” x 4.2” x 0.68”) from
bottom edge of goldfinger to top edge of board and without
Links Controller bracket and retainer
The Links Controller (LINX) is the router that manages all data • power consumption (typical): 1.2A @ 3.3V or 3.96W, 1.1A @ 5V
movement within the Matrox Helios eCL/XCL. It oversees the or 5.5W, 0.02A @ 12V or 0.24W, or 9.7W total
transfer of image data from the frame grabber section to onboard • operating temperature: 0°C to 55° C (32° F to 131° F)
memory for pre-processing and from onboard memory to the • ventilation requirements: 50 LFM (linear feet per minute)
host PC including display. Image data can be subject to various over board(s)
formatting operations including plane separation on input and • relative humidity: up to 95% (non-condensing)
merging on output, input cropping, input and output sub-sampling • FCC class B (XCL), class A (eCL)
(1 to 16), and independent control of horizontal and vertical • CE class B (XCL), class A (eCL)
scanning direction. The latter is particularly useful for • RoHS-compliant
reconstructing a proper image from a camera whose readout
requires multiple taps, each with different scanning directions.
Software drivers
• Matrox Imaging Library (MIL) drivers for 32/64-bit Microsoft®
Windows® XP/Vista®/7
• MIL drivers for 32/64-bit Linux®
3
Ordering Information Notes:
grabber with 512 MB DDR SDRAM and MimMorphic(M_DILATE, M_ERODE, M_THICK, M_THIN, M_MATCH),
MimConvolve(M_SMOOTH, M_SHARPEN, M_VERT_EDGE, M_HORIZ_EDGE,
cable adapter board. M_LAPLACIAN_EDGE, M_EDGE_DETECT), MimLutMap(8-bit), MimShift(),
MimBinarize(), MimClip(), MimConvert(M_YUV16_TO_RGB,
HEL 5M DBCL* PCI-X® dual-Base Camera Link® frame M_RGB_TO_YUV16, M_RGB_TO_L, M_L_TO_RGB, M_RGB_TO_Y), MimFlip(),
grabber with 512 MB DDR SDRAM and MimFindExtreme(), MimCountDifference() and ActiveMIL equivalents.
cable adapter board.
Software
Refer to MIL datasheet.
Cables
Camera Link® cables available from camera manufacturer,
3M Interconnect Solutions (www.3m.com), Intercon1 (www.
nortechsys.com/intercon) or other third parties.
Cables for cable adapter boards available from third parties.
Corporate headquarters:
Matrox Electronic Systems Ltd.
1055 St. Regis Blvd.
Dorval, Quebec H9P 2T4
Canada
Tel: +1 (514) 685-2630
Fax: +1 (514) 822-6273
For more information, please call: 1-800-804-6243 (toll free in North America) or (514) 822-6020
or e-mail: [email protected] or http://www.matrox.com/imaging
All trademarks by their respective owners are hereby acknowledged. Matrox Electronic Systems, Ltd. reserves the right to make changes in specifications at any time and without notice. The information furnished by Matrox
Electronic Systems, Ltd. is believed to be accurate and reliable. However, no responsibility license is granted under any patents or patent rights of Matrox Electronic Systems, Ltd. Windows and Microsoft are trademarks of
Microsoft Corporation. © Matrox Electronic Systems, 2002-2011. Printed in Canada, 2010-11-20. $IE-5294-D