VIT

Vellore Institute of Technology

School of Electronics Engineering

Fall Semester 2022-23
Continuous Assessment Test-0I
Programme Name & Branch:M.Tech -VLSI Design Duration: 90 Min

Course Code: MVLDS03L Coutse Name: Digital Design with FPGA

Maximum Marks: 50 Marks Slot: C2 Class Number: VL2022230106514

Answer alo the Questions (5 X 10=s0. Marks)

SNO Ouestion CO BL Marks

Tabulate the value of outputs ofthe following Verilog codeat

time t 20, 50, 100 150, 200,250 300,350 units Assume
the clock periot ts T00 me unitsand 50% duty cyclewith
initially LOW.

initial a-0, x-0, p-0;

initial
begin
#29a K 1'bl;
INhi #20 + 1'bX
#10o <= #40-616
3 L2 10
end
always @posedge clk) begin
#10y <= #0 x+1bl; )
Nz=40y:t1bl;
end
always @(posedge clk) begin
#20 p=1bl; ~
#104=p+ lb1;
r=#40 q + 1b1;
end.

error to obtain the

2. Construct the following HDLeode without
optimised hardware.

modslMy. circuit (A, Y); 3 L2 10

input [3:0] Y;
output [3:0) A;
 always@ (Y)
begin
if (YO) : A= 2b' 00;
elseif (Y1) : A= 2b' 01;
elseif (Y2) : A = 2b'11;
elseif (Y3) : A= 2b'
Non-Blokuy 2Bloh
default : A=2b' XX# 11;
end module

3. Develop aVerilog HDL fot the application used to control an

automatic packing machine in an industty. Each lot need to be
paoked with three balls of which first two are red colour and
the third one is green. The output goes to "1' if the lot is full
in the order of specified colout, otherwise 0'. Assumè, green
and red coloured balls are randomly coming one by one in the 3 L3 10
conveyor for packing.
Note: You can empty the lot at any time but you can't
discard the ball
4. You want to build a Mealy based finite state machine using
Verilog HDL that will recognize the sequence X = 1011.
Allow overlapof sequences. Add the test bench module in the 3 L6 10
design
5. Wite a Verilog HDL n behavioural modelling to get the
following waveform as shown in Fig.l. (Hint fis the
control signal)

8 Data in(2a.

L6 10

dk

2d2e30C
Sout
Fig. 1
 VIT
Vellore lnstitute of Technology

SCHOOL OF ELECTRONICS ENGINEERING

CAT -II (15/12/2022)
Fall Semester 2022 - 2023
M.Tech- VLSI Desiga
Class Number: VL20222301065 15
Time :10.00 A.M-11.30 A.M
Course Name: MVLD504L Analog [C Design Max. Marks :50
Faculty-In-Charge: Dr. Lakshumi NS Slot : E2 + TE2

Answer ALL Questions

Sectioa-A
SNo. Question Max. CO BL
Marks
Given Let 200uA(WIL)k=S0um/0. 18um, Determine WiL
ratio of Mi, Ma, Ma,My such that Lousr600 A, Lou800 4A, 10 BLS
Loute 400 jA Assume all.devices are matched and overdrive
voltages iare same, 12un Suggest and drawa cifcuit that
can mptove the accuracy of a current miftor configuration:
Give the reason for improved accuracy.

2 Estimate the poles of the circuit 10 BL4

Voo
Rs -oVout

3. Draw the bode plot for high frequency response of a single

stage CS amplifier with resistive load with input resistance Rs 10 BL2
 and DC gain of
at the input port, identifying the poles, zeros amplifier, Cs
CG
he circuit. Assume yl0. Compared to applications.
Amplifier is not prefered for broad bànd Give
the reason for the above statement based on the
high
requency esponse ofCS and CG stag.

10 2 'BL1
4. Acomnon-soure stage incorporates aS0-ui/0.5-jum NMOS
device biased at lo=2 mA along with a load resistor of 2KO.
What is the total input-referred thermal noise voltage in a200
MHz bandwidth? Given y=23, ke1.38 x 10" J/K,
H-Cor 50uAN, T=300K.
10 3 BL3
S. For the given fcedback network, calculate the input
impedance, output impedance voltage gain and -loop gain
Voo

oVot
Rs

Zin
 VIT
Vellors Institute of Technology

SCHOOL OF ELECTRONS ENGINEERING SNS;

Coursecode & MED601L :& Còmputer Aidd Deaign for VLSIs SLOF:D2
Title

Time :90:Mie FAlF2022-23 CAT:2 ' Max.Marks:50

Answer ALLequesic.;
.Pettom Stockmrigorithm.on the slicing floorplan that is representedby42.". 10M
.*6VH2VBHKto tid the digmensión hstiateach: intermal node. The dimension cf the
ihòduls'lthrough 8 areM3): (43),(6,3; (3,5), (6;2),; ($;1), (3,8), (2,3)}.
tcisad 2.FromthedimensionAist thatare derived.in quesion1; fnd the optimized orientation 10M:
..fihe-blocks and dYaw thé loorplan afterthe.orientation optimization.
3. Cofisidr the folloing sequente-pair SP l.=
of the:modiles 1through7 are {(2,3): (2,6).(7651243,6127534). The (width;height) 10M
(4,4). (L6), (03), (43) (13)}.
a.. Draw the horizontal añd vertical constraiatgraphs.
h. What is the minimum area of the oon slicing
ioorplan?
c. Draw the corresponding non-slicing fioorplan: Find the location of the
left cormer of each module. lower
4 ider e sevr.r,;n u iin tigcow. Assume eavirid edge has u.i
iPngth. Estimate ue wii ngth using foiiuw nethods
a. Half perirmeter
b. Clique
C. Rectilinear minimum spanning tree (Use Prim's algorithm)

5. A placenent with three fixed points pl(50, 250) p2150,0) and p3(250, 300), three 10M
fixed blocks ai, änd the nets N1, N2 and N3 such that NIPlaPl-6), NZ(P: 5.P2-t
bc), and N3(c-P3). Where NI (Pl-a, Pl-b) indicates that the net NI has connections:
Plto blocka and Plto block b. The weights of the nets N1, N2 and N3 are 2, land 4
respectively. Use quadratic placement to ind the co-ordinates of the blocks a, band c.
 VIT
Vellore Itstitute of Trchnaogy

Continuous Assessment Test-I

P'rogram Name &Branch: M.Tech VLSI Deslgn
Course Name &Code: MVLD s01L PHYSICS OFVLSI DEVICES
Semester: Fall-2022-23 Slot; A2+TA2 Exam Duration: 90 Min Maximum Marks: 50
General instructian(s):
Assume constants whenever it is needed
Answer all Questions
S.No Question Mar BL
ks 0
a) A p-n junction operating in the fofward bias region with a current I = 10 L3
0.5mA is found to have a iffusion capacitarnce of 3 pF. What is the charge
störage time for this junction? What diffusion capacitance do you expect
this junctionto have at I=0.2 mA?
) The reverse saturation cuent of ap-nAunction diode is lha10 A
2
Determine the diÝde cürent for ode voltagesofO.2V andTV,
Ki) With neat diagrams, distinguish the
nechanisms that occur in a reverse biased p-ndifferent types of breakdown 10
junction diode.
3 L3

(ii) For stable and reliable opcration, the

diode should not exceed 2 x 10° V/cm. electric the field inside a P-N junction
Design
(can safely operate up to 12 of reverse bias. The P-N junction so that it
10° cm. The selection of design acceptor concentration is
resistance. parameters should minimiz the parasitid
3 i) Consider an MOS capacitor fabricated on
doping of 5x I0° cm with oxide thicknessP-type Si substrate with a
of 10 nm and N poly-gate.
10 4 L4
Find Co Va and V.
(ii) The threshold and the flat-band voltages of a
MOS capacitor are V,=
Fi0V and Vg-0.5 V, respectively. Is this capacitor created on an N
type or P-type semiconductor? What is the density of minority
carriers (in
Clm) at the semiconductor surface when the voltage applied between
metal änd semiconductor eleçtrods is Vo=-0,75 V? the

4. Find the maximum epletion width, minimum capacitänce, and

voltage for an ideal MOS capacitor with a 5-Fm gate oxide (Si02 ) threshold
on p-type
10 4 L4
Si with NA=10 cm'.
S. Determine the region of operation forthe transistorand te drain urrent. 10 LA
NMOS: Ba= 11S LAV, N=043V, A=0.06 V,

Vos(V) Vos (V) Vsa ()

Case 1 3.3 22 0
Case21.2 12
Case 3 12 0.2:

***.
 VIT
Vellore Instltnte of Teehnology

SCHOOL OF BLECTRONICS ENGINBERING

CAT-2
Course: MVLDS02L- Digital 1C Design Programme: M.Tech. (VLSIDesign)
Time: 1.5 hours Max. Marks: 50
Slot: F2+TF2 Sem: Pall 2022-23

Ansyer ALL Questlons

1) Findthe largest as well as contamination dolays for both 0->1 and 1->0 transitions (10)
8t output for the circuit below, The widths of the transistors are given. Assume uia
aminimum width transistor will have an on-resistance ofR and gate
capacia
SOurce capacitance and drain capacitances of C. Also consider sharing of diffusio
and shared contacts. Give the input combinations which produce the respecve
delays.

D-6
F

2) Find the sizes of the transistors for the circuit below for the least delay
from the
input to the output. Label the sizes in the boxes for the simple gates and besides the (10)
transistors in the figure for the compound AO121 gate.

P: 2
G3
P:
P

Scanned with CamScanner

 is designed ina l V, 90 (5)
3) i) An embedded hardware accelerator in a system-on-chip average width of 122, The
nm process, and has Imillion logic transistors with an
gate capacitance, C= 2Fhum. The gates have an activity factor of 0,2.
(a) What is the maximum clock fhequency If the dynamic power should not exceed
20 mW?
o) Ir the subthreshold leakage is 20nA/m and the gate leakage is 2nA/um, what
is the leakage power?
i) Suppose you designed a unit inverter in a 0.1p CMOS process. The inverter is (5)
designed in static CMOS, the nmos dovico with minimum length and width, and the
pmos device with minimum length and 2xminimum width. The manufacturing
process can result upto a 10% variation in the width and a 25% variation in the
length for the actual device that is fabricated. Assume that the supply voltage is 1
Volt and|Vr = Vn=0.2 Vfor both nmos and pmos devices. In the absence of
variation, the inverter switching threshold voltage is VoD2. In the presence of
variation within the ranges above, what is the minimum and maximum switching
threshold?
4 i)A four-level circuit has been designed to have the least delay, D, from input to (5)
output, which can be written as the sum of the path effort delay and the path
parasitic delay, D = D+P.
(a) If the output capacitance is now 2 times the original capacitance, with all other
parameters remaining the same, what will be the increase in delay of the circuit as
amultiple of the original path effort delay, D?
(b) What will be the increase in delay if the output capacitance is the same, but the
parasitic delay is now2 times the original?
(c) If the original circuit is designed using 3-input NAND gates, what will be the
increase in delay, as a fraction of DE, if each gate is replaced with a 3-input NOR
gate (with the output capacitance remaining the same)?
ii) Consider the circuit shown below. From the plot of Vout VS. time, estimate the (5)
effective resistance of the NMOS transistor. (Assume that all the capacitance seen
on the output of the inverter is lumped into C. time scale in ns)
Ioverter /O waveforns

-
12V
Vdd=1.2V
output

C=100fF
12V

input
 (5)
5) ) Wite the functions Fand Gimplemented by following the circutt below.
VDD

-0.2mAN', Bp
n) A CMOS inverter with minimum sized transistors has B,
0.ImA/V and VuVg0.6V.Assume VbD-3.3V.
a) What is the inverter gate switching threshold (midpoint) voltage VM?
What is the resistance for each transistors using general expression?
c) What is the rise and fall delay of this circuit, if the parasitic capacitance at the
output is 9 fF and load capacitance CL is 25 fF.
 VIT
Vellore Institute of Technology

Continuous Assessment Test- II

Program Name &Branch: M.Tech VLSI Design
Course Name &Code: MVLD507L1C Technology
Max.marks: 50
Semester: Winter sem-2022-23 Slot: C1 Exam Duration: 90Min

Answer all Questions

Mar |C B
S.No. Question ks L
he follöwing dry and wet oxidàtion datá afe available for thermal oxidation of 10 L3
k100> Si wafers
Fm
Rate constancs for Dry Oxldation
<100> SI in <t0> stioodl
thickness 1300C

ITemp (C B(tmh)BJA (tm) 10005C

1200 0.045 a657
Oxide
.027 00;C

1000 00117 0.042

Ka)A Si wafer has an initial thickness of 0.5urm with wet-oxidation at

1000°C.What is the required oxidation timë tó obtain a total thickness of
1um?
Kb) The oxidized wafer of part(a) is further subjected to dry-oxidation at
1000°C.What is the oxidation rate (in um/hr) when the oxide has a total
thickness of 2um.
2 Phosphorous is uniformly doped into p-type silicon with oiginal doping 10 L4
concentration of the sample being 10cm' at 1100°C.Given that the solid
solubility limit of phosphorqus in silicon at 1100°C is 10cm and
kiffusion co-efficient at this temperature is 2x 1o" cmls.
(a) Calculate the number of phosphorous atoms per unit area of silicon
surface area after pre-deposition of 1hour.
(b)If after part (a), drive-in is carried out for 2 hours at the same
temperature. What will be final junction depth and surface
concentration?
Describe about () Channeling, (i) annealing systems which repair the 10 4 L3
material's lattice damage by having high ramping rate (>20°C/min)
4 Bxplain with neat sketch, the principle of operation of the deposition 10 4 L4
technique used to coat contormal 10 nm silicon nitride layer at low
temperature. Justify your choice of technique.
5 Desoribe atechnique to deposit high aspect ratio (1:100) AlumiFum oxide. 10 4 L5
Mention the working principle of the system with its Pros. And Cons.
 School of Electronics Engineering, VIT Vellore
Programme: M. Tech. VLSI Design
Subject:Computer Aided Design for VLSI (ECES019)
Examination: CAT2, Slot: D2
Date: 26.09.2018, Time:9.30-11.00 p.m., Total Marks: S0
Quadratic Placement 15
Given:1) Aplacement with three fixed points p1(75, 200) p2(100,0) and p3(250, 350)
and 2)Three fixed blocks a,b,c and 3) the nets N1, N2, N3 and N4 such that
N1(P1,a,b),
N2(P2,b,c), N3(a, b, c), and N4(c, P3). Use quadratic placement to find the co-ordinates
of the blocksa,b,andc. Assume all the nets have weight unity.
Use the Dijkstras Algorithm to find the minimum cost path from the source
node S=A 20
to the target node T = 0.
(16,13) (4,2) (3,2)

(2,2) (4,2) (13,16) (8,2)

3,1) (3,6) (3,8)

(20,13) (5,4) (12,13) (3,5)

(13,6) (4,2) (1,2) 2C

(2,2) (2.5) (9,8) (1,2)

T
(6,3) (2,3) (4,3)

Left-Edge Algorithm 15
Given a channel with the following pin connections (from left to right)
TOP=[A0D0E0C00EGBCOO]and BOTTOM =[O FDAOFODGO000GBI
Find S(col) for columns a-o and the minimum number of routing tracks.
b Draw the HCG and VCG
Use the left edge algorithm to route this channel. Draw the channel with the
fully routed nets.
-X-X-X
 VIT
Vellore lnstitute of Technology

SCHOOL OF ELECTRONICS ENGINEERING

CONTINUOUS ASSESMENT TEST - II

Course: Digital Design with FPGA Course Code: ECE 5017

Max. Marks: 50 Max. Time: 90 Min

Branch: M.Tech (VLSI Design) Slot: F1

1. Fillin the table showing the values for the four registers at the given times. Legal (5]
answers are 0, 1, x, z, and indeterminate.
reg q, r, S, (;
initial
begin
q=1'b0;
t<= # I'b0:
t X
q #I i'bi;
S=l'bl;
end
always
begin
r=l'bl;
s=1'b0;

q=1'b0;
r=l'b0:
q< #10 1'b1:
end

Signal Value at the end of time 0 Value at the end of timel

1

IndatesM0 1

Andat
t

2 List the changes (values and times) to a and b in the module below.
module assg0; ab
reg [15:0/ 4, b; 2
initial 2
begin t:o 2 41
a=1; b=2;
a 2
a<= b; b<= a; t too rt4
5
a <-b+ 10; t: 2 be
b<= #5 b + 20; #I;

2t:
 3;
b <= 4;
b<= #2
b <= #10 6:
b=7;
#20;
end
endmodule
3 Write behavioralverilog description for full subtractor by using function call for
obtaining it's outputs.
4. Write behavioral Verilog code to count the sequence 0001, 0010, 0100, 1000, 0001,
[10]
0010, 0100..... use if-else construct only to realize the logic. Also write test bench to
generate clock with duty cycle of 10 t.u and display the output in decimal form.
5 Re-write the module in behavioral form. The delays can be assumed to be inertial (10])
delays.
module expl _str(x,y,a,b,c);
input a, b, c;
output y;
wie a, b, c, x, y;
wire na, nb, nc, 13, t5, 16;
not nl(na,a);
not n2(nb,b);
not n3(nc,c);
and #1 al (13,na,b, c);
and a2(5,a,nb,c);
and a3(t6,4,b,nc);
or ol(x,13,16);
or #3 o2(,a,15);
endmodule
6. Write Verilog behavioral description so that it operates as follows. [15]
Compute 32-bit output eq_time so that it is the number of consecutive positive edges
of input clk for which 32-bit inputs siga and sigb remain equal. The counting should
start on the first positive edge of clk after siga becomes equal to sigb; the count starts
at zero at the moment they become equal, and while they remain equal the count is
incremented at each positive edge. The count should go back to zero at the first
positive edge of clk after siga becomes unequal to sigb.The count goes to zero even if
siga and sigb become equal again before the positive edge. Write the test bench to
verify the same.

Page 2
 VIT
Vellore Institute of Technology SLOT-C,

SCHOOL OF ELECTRONICS ENGINEERING

CAT-1|FALL 2018-19

Course Name PHYSICSOF VLSI DEVICES Duration: 90 MINUTES

Course Code ECE 50 18 Max. Marks :50

Assume missing data if any.

Q4-An abrupt PN junction in Sihas Na = 10' cm and NÍ = 106 cm'.The temperature is

300K.Compute the contact potential, Nand P-type depletion region widths, maximum
electric field, maximum potential differences between the junctions,charge stored in each
depletion region per square centimeter ofjunction interface. [10 marks|

A. Consider apn junction in equilibrium at room temperature (T =300 K) for which the doping
concentrations are NA = 10ccm and No =10cm and the cross-sectional area A = 10
cm. Calculate p, npo, Na, Pno, Vo, W, Xns X, and Q. Use n= 1.5 X 10°cm. [10 Marks]

Qs Two diferent MOS capacitors, with different gate-oxide thicknesses (3 nm and 15 nm) have
the same density of positiveoxide charge (Noe5x 1o° cm) close to the oxide
semiconductor interface. Find the flat-band voltage shifts due to this positive oxide charge for
these two MOS capacitors. What arethe threshold voltage shifts ?
Assume N,=1 X 10'cm [10 Marks]

Aa. A PN junction has NA = 10!8 cm and Ny = 10 cm'. (a) With V =0, What are the minority
carrier densities at the depletion region edges ?. (b) Assume V= 0.8 V, What are the minority
carrier densities at the depletion region edges. (c) What are the excess minority carrier
densities. (d) What are majority carrier densities. (e) Under the reverse bias of 1.5 V, What
are the minority carrier concentration at the depletion region edges. (10 Marks|

Os. Consider an ideal MOSCAP with N- Poly Si gate tox =10 nm, N¡ =2.5 x10" cm.
Calculate a) Flat-band voltage b) The threshold voltage for strong inversion c) The voltage
drop in the semiconductor at V =V, d) The voltage drop in the oxide at V,-V, (10 Marks|

&&&&&&&&&&
 Continuous Assessment Test - 11
VIT Programme Name & Branch:
Vellore Institute of Technology M.Teh (VLSI Design)

Course Name & Code: Physics of VLSI Devices - ECE5018

Class Number: VL2018195006581 Slot: W21+W22+Z21 Exam Duration:90 mins

Maximum Marks: 50

General instruction(s):
Data: At 300K: n, = 1.5x10l cm, kT = 25.86 meV, Ne = 2.8 x 10 cm, Ny = L.04 x 10" cm.
Assume missing data if any.

Section -A(2 x5= 10 Marks)

S.No
Question

1 A long-base Si PN-diode has P-side, N, =3.7 x 10 cm and N-side, No =

6.3 X 10 cm. Given that, on P-side D, = 13.4 cm sec and on the N-side
D, = 6.2S cm'sec. Assume t,= tn = I, = 10 sec. Calculate the reverse bias
current for an applied reverse bias of -1.25 V. Assume the area of cross
section is 15 um.
An ideal rectifying contact is formed by depositing gold (O = 5.12 eV) on
2 an No = 5 X 10 cm doped silicon substrate maintained at room
temperature. Calculate (a) s (b) Vsi (c) Wunder equilibrium condition (d)
IElmax in the semiconductor under equilibrium condition.

Section -B(4x 10 =40 Marks)

S.No
Question

1
Consider a P'N junction diode with No = 10" cm in the N-region. (a)
Determine the diffusion length Lon the N-type side. (b) What are the
excess hole density andexcess electron density at the depletion layer edge
on the N-type side under (a) equilibrium and (b) forward bias V=0.5 V
2 Two silicon p'n step junction diodes maintained at 300 Kare physicaly
identical except for the n-side doping. In diode#1, No = 10" cm; in diode
#2, No =10*° cm". Compare the operation of the two diodes by answering
the questions that follow
Diode 1 Diode 2

-Np= 10%cm

(a) Which diode willexhibit the larger built-in voltage (Vb) ? Explain
(b) Which diode willexhibit the larger breakdown voltage (Va) Explain
(c) Which diode willexhibit the larger junction capacitance (C) at a given
reverse bias voltage when |VAl >> Vb Explain
 Three different MOS capacitors, with different gate-oxide thicknesses (3, 7
3 and 12 nm) have the same density of positive oxide charge (Noe =5 x 10
cm) close to the oxide-semiconductor interface. Find the flat-band
voltage shifts due to this positive oxide charge for (i) MOS cap 1 and 3 (ii)
MOS cap 2and 3
AMOSCAP has polysi gate with No = 3 × 10" cm", the oxide is SiO, with
tor =S0 nm and the substrate is P-type with N, 5 x 10" cm. Calculate
(a) For Ve =VeB, voltage drop in the P-type semiconductor
(b) For VG =0, voltage drop in the P-type semiconductor
(c) For V, =0.3 V, voltage drop in the P-type semiconductor
 VIT SLOT-C
Vellore Institute of Technology

SCHOOL OF ELECTRONICS ENGINEERING

CAT-|FALL 2018-19
Course Name PHYSICS OF VLSI DEVICES Duration: 90 MINUTES

Course Code ECE 5018 Max. Marks :50

Assume missing data if any.

. The doping levels and neutral-region widths of N- and P-type layers to be utilized for
designing adiode are as follows. No = 10 cm', NA =10" cm', and W, = W, =2 um.
Determine the area of the PN -junction so that turn-on voltage of the designed diode will be
0.7 Vif the current rating of the diode is to be specified as l mA at room temperature.
(10 marks|
Q2
N-type P-type
Np =lx 10" cm N =5x 108 cm
D, = 16 cm'/s D, = 12 cm/s

A 0.8Vforward bias is applied to the diode. (a) What are the diffusion lengths on the Nand
P-side. (b) What are the injected excess minority carrier concentrations at the junction edge.
(c) sketch the excess carrier densities p'(%) and n'). [5 Marks)

Qs. Ametal semiconductor contact is formed with a metal having work function m =5.1 eV
and Sihaving Ng =3x 10 cm' donor atoms. Sketch the lat-band energy band iagram and
determinewhether the contact is ohmic or rectifying. Also sketch the energy band diagram
when the contact is (i)forward biased (ii) reverse biased [10 Marks]

Q4. Technological parameters of aMOS capacitor are given. N,=8x 10 cm, tox 10 nm, Nge
10° cm", P+- polysilicon,n, = 1.5 x 10" cm, E= 1.12 eV, V= 0.026 V, Eor =3.45 x 10!!
F/m, [= 1.04 x10*" F/m.

a) Determine the value of flat-band voltage

b) calculate the charge density at the onset of strong inversion. ldentify the type and origin of
this charge
c) Calculate the body factor
d) Calculate the threshold voltage value
e) calculate the charge density in the inversion layer at VG =5 V. [15 Marks
Os. Determine the flatband and threshold votlage for an MOS device that has a siliconP
substrate with NA 10° cm and uses aluminum for the gate. Given Q, =5x 100gC/cm.
Eoy =3.9 x8.85 x10"Flcm, tox= 200 Angstroms ande = 11.8 x 8.85 x 104 Flcm. use
n = Ix 10" cm', E, = 1.12 eV and Xs =4.15 eV. (10 Marks

&&&&&&&&&&
 VIT
Vellore Institute of Tech nology
S s 0eemed o be t'niverity nder ection t ofUGc Act, 1956)

SCHOOL OF ELECTRONICS ENGINEERING

CONTINUOUS ASSESSMENT TEST-II (FALL- 2018)

Discipline :M.Tech.-VLSIDesign Semester: FALL2018

Subject :ECES015 Digital IC Design Max. Marks : 50

+++++

PART-A5x10=50
Answer all questions

1) a)Design a CMOS logic circuit for the following function and find out the worst case rise
and fall delay.

Y=A+{C+D) BE (7)

b) A four-input nor gate drives identical gates, as shown in Figure below. What is the
delay in the driving nor gate? (3)

2) Implement the function = ABC + ABC + AB C + ABC, which gives the sum oftwo
inputs with a carry bit, using NMOS pass transistor logic. Design a DCVSL gate which
implements the same function. Assume A, B, C, and their complements are available as
inputs. (10)

3) A) Determine Vo for each of the circuits shown. Assume that Vm = |Vpl = 0.5V, that
there is no subthreshold conduction, that the capacitor is initially discharged and that
there are no body effects. (6)
 OV
OV 2.5V
2.EM
25V
2.5V I
function
b)Sketch a pseudo -nMOS gate that implements the

F=(A(B +C+ D) +E" F*G) (4)

circuit.
4) a) Detemine x,y,z for minimum delay for the following
(7)
Assume for a static inverter, WP:WN=2:1 gives equivalent pull-up and pull-down resistance.

Cou=24/5

b)When the data in a circuit switches once for every two clock cycles, where the clock frequency
is 100MHz, the power supply and output capacitance are 5v and 100pF respectively. Calculate
switching power dissipation in the circuit. (3)

5) a) In the transfer characteristics of ainverter, P(1.2V, 2.6V) &Q(1.4, 0.4V) are the points
at which the slope is -1. Calculate the Noise Margins (NM, & NME). (4)

b) The following circuit operates at 1.2Volts and having CL=79nF.Find out the Dynamic
Power considering the Critical path Delay. Delay values are mentioned inside the logic
gates (6)

Cn

Assume allthe delay values in nano

values are mentioned)
seconds (lnside the gate Delay
 VIT
Veliore Institute of Technology

SCHO0L OF ELECTRONICSENGINEERING
CAT-I1 (24/09/2018)
Fall Semester 2018 - 19
M.Tech - VLSI Design
Course Code :ECE 5016 Time :9.30 - 11.00 A.M
Course Name: Analog 1C Design Max. Marks :50
Faculty-In-Charge: S.KUMARAVEL Slot : B2 + TB2

Answer Allthe Questions

I. Due to manufacturing defect a resistor Re has appeared between source and ground of
Mi transistor. Determine the expression for Re in the circuit shown in Fig. 1such that
I,= IRE/2. (10 Marks)

Voo
Vpe R. Rp
REF
M RL
X oVout
Rs Vout Vin Rs
MREF Rp
C

Fig. I Fig. 2 Fig. 3

2. In the CS stage shown in Fig. 2, Rs = 2002, RL =1kl, lpy =1 mA,CGs = 50 fF, CGp
= 10fF, CpB= 15 fF and VGs - VTH=200 mV. Determine the transfer function of the
circuit and sketch the Bode plot. (10Marks)

3. Identify the amplifier whose input impedance realizes anegative resistance. Derive the
expression for the negative resistance. (10 Marks)

4. Realize the transfer function for the circuit shown in Fig. 3and sketch the voltage gain
w.rto frequency. (10 Marks)

5. Consider a MOS differential amplifier with current source load shown in Fig. 4.
Assume that for all transistors W/L= 10 umlum. CGs = 20 fF, CGo = S fF and CDB
= 5fF. Also, let unCox = 400 AV', HpCox = 200 uA/V', =do= 0.1 V. The bias
current|=1mA and the bias curent source has an output resistance Rss = 30 k2 and
an output capacitance Css = 0.5 pF. In addition to the capacitances introduced by the
transistors at the output node, there is a capacitance CL of 100 fF. It is required to
determine the low frequency values of ApM, ACM, and CMRR. It is also required to find
the poles and zeros of AoM and sketch the bode plot. (10 Marks)
VoD
M3 M4

oVout

Vin M2

Iss
+
Fig.4
 VIT
Vellore Institute of Technology

SCHOOL OFELECTRONICS ENGINEERING

CAT-I| (10/05/2022) - OPENNOTEBOOK
Winter Semester 2021 - 22
M.Tech - VLSIDesign
Course Code ECE50 16 Time :09.30 A.M - 11.00 A.M
Course Name: Analog IC Design Mas. Marks :50
Faculty-In-Charge: Nithishkumar V Slot : C1+ TCI

Answer All the Questions

Assume data wherever necessary.
No Question Max Marks CO BL
Answer all questions: Total Marks: 50

T
Ro
o Vout
R

Fig. 1 10 CO3 BLI

Identify the type of the feedback of the circuit shown in Fig. 1. Evaluate the
open-loop and closed-loop gains. Also evaluate the closed-loop input and output
impedances.
2.
Vop
Ro

Rf oVout
R

Fig. 2
Identify the type of the feedback of the circuit shown in Fig. 2. Evaluate the
open-loop and closed-loop gains. Also evaluate the closed-loop input and output
impedances.
CO3 BLS

Page 1 of 2
 10 CO2 BL5
3. Estimate the poles and zeros of differential amplifier with active load. Find tne
gain as a function of frequency.
10 CO2 BLS
4. Consider the CD stage with the following parameters: Vop =SV. Io =400 A:
VIN2.5 V, VouL207 V. R_ = 5 ks), R = S k). let uCoy = 50 pAN. A*
0.1 V, y- 0.6 V'?. 20, =0.8 v. Vn (with body effec) =0.893 V. Assune
Cgs 203 fF. Cpo $0 F. Cah = $4.3 F, Cah = 50 F. Deternine the poles and
zeros.
10 CO2 BLS
5. Detemine the input referred noise of CMOS inverter.