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Design and analysis of FPGA based 32 bit ALU using reversible gates

Conference Paper · April 2017

DOI: 10.1109/ICEICE.2017.8191959

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2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)

Design and Analysis of FPGA Based 32 Bit

ALU Using Reversible Gates
S.M.Swamynathan[1], V.Banumathi[2],
Dept. of ECE, Dept. of ECE,
SNS College of Technology, Anna University Regional Centre,
Coimbatore. India Coimbatore. India
[email protected] [email protected]

Abstract— An Arithmetic logic Unit (ALU) is used in of this work is to address the design of the
arithmetic, logical function in all processor. It is also functional blocks. An Arithmetic Logical Unit is
an important subsystem in digital system design. the very important subsystem in the digital system
Arithmetic Logic Unit (ALU) is one of the most design. It is an integral part of a computer
important components of any system and is used in
processor and a combinational logic unit that
many appliances like calculators, cell phones, and
computers .A 32-bit ALU was designed using Verilog performs its arithmetic and logic operations. ALUs
HDL with the logical gates such as AND and OR for of various fixed bit-widths and full precision bit
each one bit ALU circuit. The design was width are frequently required in very large-scale
implemented in Xilinx. It can work fast than the ALU integrated circuits (VLSI) from processors to
processor using less power. The design of an ALU and application specific integrated circuits (ASICs).
a Cache memory for use in a high performance nowadays ALU is getting smaller and more
processor was examined. Reversible logic vital in complex to enable the development of a more
recent years because it has ability to reduce the powerful but smaller computer and processors. The
power dissipation which is main requirement in low
need for high speed, less power consumption and
power design. ALU which are designed using non
reversible logic gates consume more power. So there compatible processors has been increasing as a
is a need for lesser power consumption and the result of computer, digital signal processing and
reversible logic has been playing vital role during networking applications. Arithmetic operations
recent years for low power VLSI Design techniques. such as multiplication, addition, division and
This technique helps in reducing power consumption subtraction and logical operations such as AND,
and power dissipation. This paper presents an OR,NOT,XOR are using all type of processors
implementation of ALU based on reversible logic used in various applications.
while comparing it to an ALU architecture with the
normal logic gates. All the modules are simulated in
modelsim SE 6.4c and synthesised using Xilinx ISE
II. ALU WITH IRREVERSIBLE LOGIC
14.5. ALU which is designed using non reversible GATES
logic gates consume more power of about 0.312 mw
and the implementation of ALU based on reversible The 16 bit ALU is designed which allows the
logic reduces the power consumption during computer to add, subtract, multiplication and
operations to about 5.1 percentages. division and to perform basic logical operations
such as AND, OR, XOR, XNOR, NAND and
Keywords—Reversible gate, Verilog Hardware inverter etc. Since every computer needs to be able
Description Language, Feynman gate, Peres to do these functions, they are always included in a
gate, Toffoli gate, Fredkin gate, Arithmetic CPU these functions. An ALU is a combinational
Logic Unit. logic circuit that can have more inputs and only one
output.
I. INTRODUCTION

Due to wide spread use of microprocessors and

signal processors, implementation of high
performance arithmetic hardware has always
remained an attractive design problem. Arithmetic
and Logic Unit (ALU) is the workhorse of
microprocessors and determines the speed of
operation of the processor. All modern processors
include stand alone hardware for computation of
basic arithmetic operations. In addition to fast
arithmetic hardware, processors are also equipped
with on-chip memory (cache) to achieve significant
performance improvement by avoiding delay due to
data access from main memory. The key objective
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)
Table 1 Function of 1-bit ALU

S1 S0 FUNCTION
0 0 xi OR yi ORci-1
0 1 xi AND yi
1 0 xi OR yi
1 1 xi

Basically AND operation is performed

using an AND gate, the OR operation is performed
using an OR gate and the addition of two numbers
is carried out by the one bit full adder circuit as
shown in fig 2. A One Bit ALU will perform AND,
OR, and ADD operations as shown in the table
above.

III. ALU WITH REVERSIBLE GATES

In ALU architecture, a high performance

arithmetic hardware with minimum possible clock
cycles capable of computing square, square root
and inverse in addition to basic arithmetic
operations. Design of ALU was undertaken in this
thesis in the context of high performance and
testability. Architectures with high degree of
Fig. 1 Functional diagram of ALU architecture parallelism were explored for design of high speed
arithmetic unit. For simplicity, functional units
A low power 16 bit ALU is designed using were designed with 8 bit capability. Due to
Verilog HDL. Verilog HDL is an industry standard architectural parallelism, increase in operand size
language for the description, modelling and would only require replication of hardware parallel
synthesis or simulate of digital circuits and to existing circuitry. The ALU has stand alone
systems. hardware for performing basic integer arithmetic
operations and is capable of computing square,
square root and inverse as well. A logic unit
performing 8 bit logic operations was built using
logic cells available in the IC cell library and was
found to have a high operating frequency close to
1GHz. Hardware for addition and subtraction was
implemented as a combined ADD/SUB unit.
Subtraction is generally performed using two’s
complement addition. Two’s complement of a
number is obtained by negation of the operand
followed by an increment-by-1. The XOR gate
inverts the other input if the CTRL input is ‘High’.
The CTRL signal is applied to Cin to perform the
increment needed to complete two’s complement
calculation. When CTRL signal is ‘Low’, the unit
performs addition.

A) FEYNMAN Gate

Feynman gate is also known as 2X2 reversible

Fig. 2 Functional block diagram of one bit ALU gate. The input and output vectors for Feynman
gate is In (A, B) and Out (P, Q) respectively. The
Addition is the most commonly used outputs of FEYMAN gate are denoted as P=A,
arithmetic operation and hence the performance of Q=A XOR B and Quantum cost of a Feynman gate
an ALU is greatly dependent on the performance of is one. The application of this gate is used in many
its adder. A variety of choices exists for addition circuits because of low cost of the FEYMAN gates
depending on speed and area requirements.
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)

Fig. 3 Feynman Gate Fig. 7 Fredkin gate

B) PERES Gate IV. SIMULATION OUTPUT

It is also called as 3X3 reversible gate. The A. ALU using logical gates
input and output vector for PERES gate is In (A, B,
C) and Out (P, Q, R) respectively. The output is The figure 8 shows the arithmetic operations. The
defined as P = A, Q = A XOR B and R=AB XOR Control inputs for these operations are M = ‘0’ and
C and the Quantum cost of Peres gate is 4. Because Cin= ‘1’ and output is F and Cout. The Figure 10
of its lowest quantum cost in many designs Peres shows logical operations. The control inputs for
gate is used. half adder is designed by Single Peres these operations are M = ‘1’ and Cin= ‘0’ and
gate . outputs are F and Cout.

Fig. 4 Peres gate

C) TOFFOLI Gate

Let IPv and OPv be the input and output

vector of a 3*3 Toffoli Gate (TG) respectively, Fig 8 Output wave form of irreversible gate ALU
where IPv =(A, B, C) and OPv=(P=A, Q=B,
R=AB⊕ C). Fig 6 shows the 3*3 Toffoli gate. B. ALU using reversible gates
(Quantum Cost = 5).
Fig 9 shows the output waveform
configuration of 16 bit irreversible
adder/subtractor. The 16bit data A, B are the
module inputs and M is a control signal. If the
control input is “0‟, the addition operation is
performed and if the control input is “1‟
subtraction operation is taken. “Cin‟ indicates the
carry in, “Cout” indicates the carry out or borrow
out obtained from the circuit.

Fig. 6 Toffoli gate

D) FREDKIN Gate:

Let us consider IPv and OPv be the input and

output vector of a 3*3 Fredkin Gate respectively,
where IPv=(A,B,C) and OPv=(X=A,Y=A’B XOR
AC , Z=A’C XOR AB). Fig 7 shows the Functional
block diagram of 3*3 Fredkin gate. (Quantum Cost
= 5)
2017 International Conference on Electrical, Instrumentation and Communication Engineering (ICEICE2017)
of RISC, which will increase the speed of the
processor. The paper may also be expanded by
making it application specific integrated circuit.
The delay generated by using irreversible logic gate
has decreased drastically as the bit size increased in
the input side in compare with normal logic gates.
The implementation and design using different
FPGA families can also be done as a future work.

References

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Future work in this paper may extend to
include pipelined reconfigurable FPGA architecture

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