Article

Common‐Mode Voltage Reduction Algorithm for Photovoltaic

Grid‐Connected Inverters with Virtual‐Vector Model
Predictive Control
Hui Hwang Goh 1,*, Xinyi Li 1, Chee Shen Lim 2, Dongdong Zhang 1, Wei Dai 1, Tonni Agustiono Kurniawan 3
and Kai Chen Goh 4

1 School of Electrical Engineering, Guangxi University, Nanning 530004, China; [email protected]

(X.L.); [email protected] (D.Z.); [email protected] (W.D.)
2 School of Electronics and Computer Science, University of Southampton Malaysia, Iskandar Puteri 79200,

Malaysia; [email protected]
3 College of Environment and Ecology, Xiamen University, Xiamen 361102, China; [email protected]

4 Department of Technology Management, Faculty of Construction Management and Business,

University Tun Hussein Onn Malaysia, Parit Raja 86400, Johor, Malaysia; [email protected]
* Correspondence: [email protected]

Abstract: Model predictive control (MPC) has been proven to offer excellent model‐based, highly
dynamic control performance in grid converters. The increasingly higher power capacity of a PV
inverter has led to the industrial preference of adopting higher DC voltage design at the PV array
(e.g., 750–1500 V). With high array voltage, a single stage inverter offers advantages of low compo‐
Citation: Goh, H.H.; Li, X.; Lim, C.S.; nent count, simpler topology, and requiring less control tuning effort. However, it is typically en‐
Zhang, D.; Dai, W.; Kurniawan, T.A. tailed with the issue of high common‐mode voltage (CMV). This work proposes a virtual‐vector
Common‐Mode Voltage Reduction model predictive control method equipped with an improved common‐mode reduction (CMR)
Algorithm for Photovoltaic
space vector pulse width modulation (SVPWM). The modulation technique essentially subdivides
Grid‐Connected Inverters with
the hexagonal voltage vector space into 18 sub‐sectors, that can be split into two groups with differ‐
Virtual‐Vector Model Predictive
ent CMV properties. The proposal indirectly increases the DC‐bus utilization and extends the over‐
Control. Electronics 2021, 10, 2607.
all modulation region with improved CMV. The comparison with the virtual‐vector MPC scheme
https://doi.org/10.3390/
electronics10212607
equipped with the conventional SVPWM suggests that the proposed technique can effectively sup‐
press 33.33% of the CMV, and reduce the CMV toggling frequency per fundamental cycle from 6 to
Academic Editors: Gabriele Grandi, either 0 or 2 (depending on which sub‐sector group). It is believed that the proposed control tech‐
Jung‐Min Kwon and Kris Campbell nique can help to improve the performance of photovoltaic single‐stage inverters.

Received: 3 August 2021 Keywords: common‐mode voltage; delay; inverters; multi‐step model predictive control; non‐zero
Accepted: 20 October 2021 vector; space vector pulse width modulation
Published: 25 October 2021

Publisher’s Note: MDPI stays neu‐

tral with regard to jurisdictional
1. Introduction
claims in published maps and institu‐
tional affiliations. Solar photovoltaic (PV) energy generation, wind energy generation, and other new
energy technologies are constantly being developed. Control and modulation techniques
of voltage source inverter (VSI), which is the main physical interface between renewable
energy sources and the power grid, have garnered considerable research attention [1]. In
Copyright: © 2021 by the authors. Li‐ standard MPC schemes, the use of all actual voltage vectors inherently results in elevated
censee MDPI, Basel, Switzerland. CMV. On the other hand, MPC schemes with SVPWM uses virtual vector vectors and the
This article is an open access article CMV performance depends primarily on the modulation design. High peak CMV and
distributed under the terms and con‐ frequent toggling of CMV of converters may reduce the system reliability, posing poten‐
ditions of the Creative Commons At‐ tial safety concerns [2,3].
tribution (CC BY) license (https://cre‐ Numerous research works on CMV suppression have been reported to date. In gen‐
ativecommons.org/licenses/by/4.0/). eral, these solutions on CMV performance can be categorized into hardware‐based and

Electronics 2021, 10, 2607. https://doi.org/10.3390/electronics10212607 www.mdpi.com/journal/electronics

Electronics 2021, 10, 2607 2 of 15

software‐based techniques. In the hardware‐based solutions, CMV is typically mitigated

by incorporating a passive filter or optimizing the voltage source inverter topology [4,5].
However, this approach necessitates additional hardware, resulting in higher mainte‐
nance effort and costs. On the other hand, software‐based CMV suppression methods can
be subdivided further into those based on direct control scheme and those based on pulse
width modulation (PWM). In the direct control group, e.g., direct MPC with actual voltage
vectors, it is common to augment the cost objective into considering CMV as a cost com‐
ponent [6,7]. These approaches necessitate the design of a suitable weight factor to balance
the various cost components in the cost function. L. Guo et al. suggests an MPC scheme
with preselected voltage vectors having low CMV [8,9]. However, the preselection has
limited the amount of voltage vectors available, and therefore results in a higher harmonic
distortion. MPC‐based CMV suppression methods have been studied in conjunction with
various inverter topologies [10–12].
PWM modulation techniques can be modified to restrain CMV. For example, the
CMV can be suppressed by only using either odd or even voltage vectors [13]. However,
the corresponding DC‐bus utilization factor is very poor. In addition, non‐zero voltage
vector modulation approaches, such as active zero‐state switch PWM [2], near‐state PWM
[14,15], and remote‐state PWM [16] have been reported in the past. Moreover, [17,18] com‐
pare the performance indices of various modulation schemes, in terms of e.g., CMV am‐
plitude, output THD. Table 1 summarizes the advantages and disadvantages of the pro‐
posed techniques. Moreover, other CMV‐related works have attempted to improve other
inverter efficiency indicators, such as switching losses [15,19], restraining common‐mode
electromagnetic interference [20], or leakage current in photovoltaic grid‐connected in‐
verter [21,22]. Furthermore, [23] suggests a hybrid modulation based on the modulation
magnitude, resulting in varying CMV performance. Another hybrid modulation is stud‐
ied in [24] but it requires a common‐mode inductor, which increases the system cost and
design complexity. In [25], an enhanced discontinuous modulation is proposed to reduce
the line switching loss while suppressing CMV. However, if the switching sequences in
the subdivided sectors of the hexagonal voltage vector space can be ordered more opti‐
mally, further improvement may be achieved. There are other simplified PWM techniques
[26–28], each with respective merits and demerits. Similarly, PWM‐based CMV improve‐
ment have been studied in conjunction with different inverter topologies [29–32].
This paper’s contribution is as follows: (1) In the proposed improved common‐mode
reduction space vector pulse width modulation (CMRSVPWM) with 18 sub‐sectors or‐
ganizes the switching sequences in each sub‐sector into resulting lower CMV amplitude
and oscillation frequency; (2) MPC uses a large amount of virtual voltage vectors, such
that all the 18 subsectors can be fully utilized. By combining the virtual vector MPC and
CMRSVPWM, the CMV performance of the single‐stage inverter can be improved.
The following is the structure of the article: Section 2 introduces the mathematical
model and MPC for a three‐phase two‐level photovoltaic inverter, together with the
standard SVPWM and its CMV property. Section 3 proposes the virtual vector MPC with
the improved CMRSVPWM modulation, where the details of division, vector selection,
and CMV amplitude and frequency are described. Section 4 compares the performance
with the standard SVPWM and the proposed CMRSVPWM method using simulation
studies. Section 5 summarizes and concludes the overall findings. Section 6 provides pro‐
poses directions for future work. The Appendix A contains two tables. Table A1 shows
the definition of acronym. Meanwhile, Table A2 shows the definition of notations in this
paper.

Table 1. Advantages and disadvantages of different modulations.

Advantages Disadvantages
SVPWM Lower switching losses [33] Potentially high calculation burden [33]
High modulation index range, high DC‐bus
AZSPWM Line‐to‐line voltage pulse reversal [34]
utilization [22]
Electronics 2021, 10, 2607 3 of 15

Low CMV amplitude, less switching losses Higher in ripple and switching losses
NSPWM
[34] [33]
RSPWM Theoretically non‐changing CMV [16] Low DC‐bus utilization [16]

2. Virtual‐Vector MPC
2.1. Three‐Phase PV VSI Model
Figure 1 shows the topology of the three‐phase two‐level single‐stage photovoltaic
inverter that is connected to a three‐phase grid (emulated using ideal three‐phase source).
As described, this topology is relevant to photovoltaic application with high DC array
voltage (e.g., 750 V to 1500 V).

Figure 1. Model of the grid connected PV system.

In Figure 1, 𝑉 is the output voltage of PV array, 𝑉 , 𝑉 and 𝑉 are the inverter out‐
put voltages, 𝐿 and 𝑅 are filter inductor and its internal resistance, and 𝑒 , 𝑒 , and 𝑒
are the emulated AC grid voltages. Point 𝑂 is the grounded neutral of the AC grid. The
plant under control can be represented by the set of Equation (1):
𝑑𝑖
⎧𝑉 𝐿 𝑅𝑖 𝑒
⎪ 𝑑𝑡
𝑑𝑖
𝑉 𝐿 𝑅𝑖 𝑒 (1)
⎨ 𝑑𝑡
⎪ 𝑑𝑖
𝑉 𝐿 𝑅𝑖 𝑒
⎩ 𝑑𝑡
Through Clarke transformation, the circuit voltage equations are transformed from
the three‐phase coordinate to the 𝛼𝛽 two‐phase stationary coordinate, giving Equation
(2):
𝑑𝑖
𝐿 𝑉 𝑅𝑖 𝑒
𝑑𝑡 (2)
𝑑𝑖
𝐿 𝑉 𝑅𝑖 𝑒
𝑑𝑡
Each symbol in Equation (2) has the same meanings as defined above, but now the
𝛼𝛽 coordinate. Since the PV inverter contains three sets of switches, they are capable of
producing a total of eight switching states. The relationship between the output voltages
and the switching states can be described by Equation (3), where parameter 𝑎 defines the
unit vector that introduces 120° phase difference among phases:
2
⎧𝑉 𝑉 𝑆 𝑎𝑆 𝑎 𝑆
3
𝑖 0,1 ⋯ 7 (3)
⎨ 1 √3
⎩𝑎 𝑒
2
𝑗
2
where 𝑉 represents the output voltage obtainable from different switching stats, 𝑆 , 𝑆 ,
and 𝑆 represent, respectively, the states of each switch, and 𝑉 is the DC‐bus voltage.
The combination of these eight switching states corresponds to eight actual/basic voltage
Electronics 2021, 10, 2607 4 of 15

vectors that can be denoted as 𝑉 ~𝑉 . 𝑉 and 𝑉 are zero voltage vectors, and the other
six are non‐zero voltage vectors, with the same amplitude, but different phase angles.

2.2. Model Predictive Control of VSI

Using forward‐Euler method to discretize the grid current model [9]:
1
⎧𝑖 𝑘 1 𝐿𝑖 𝑘 𝑇𝑉 𝑘 𝑇𝑒 𝑘
𝑅𝑇 𝐿
(4)
⎨𝑖 𝑘 1
1 𝐿𝑖 𝑘 𝑇𝑉 𝑘 𝑇𝑒 𝑘
⎩ 𝑅𝑇 𝐿
where 𝑖 𝑘 1 and 𝑖 𝑘 1 are the predicted values of 𝛼𝛽‐axis currents at (k+1)th time
instant, 𝑖 𝑘 and 𝑖 𝑘 are the 𝛼𝛽-axis current feedback at kth sampling instant, 𝑇 is the sam‐
pling period in seconds, and 𝑒 𝑘 and 𝑒 𝑘 are the 𝛼𝛽‐axis grid voltage at kth sampling
instant.
Standard single‐vector MPC analyzes only eight actual voltage vectors per control
cycle to identify the switching state with the lowest cost value. If the control sampling
frequency is insufficiently high, three‐phase currents will suffer from higher harmonics.
To improve this aspect, virtual voltage vectors, or sub‐voltage vectors, are considered in
this study.
It has been well‐established that the inherent digital implementation delay has to be
compensated in MPC implementation in conjunction with power electronic application.
Two‐step ahead prediction technique is utilized to compensate the inherent delay [6].
With this two‐step MPC, the cost function can be written as Equation (5):
∗ ∗
𝑔 |𝑖 𝑖 𝑘 2 | 𝑖 𝑖 𝑘 2 (5)
∗ ∗
where 𝑖 and 𝑖 are the reference values of the 𝛼𝛽‐axis currents that can be obtained
from inverse‐Clarke transformed of synchronous‐axis current. 𝑖 𝑘 2 and 𝑖 𝑘 2
are the 𝛼𝛽‐axis currents at (k+2)th instant.

2.3. CMV of Basic Voltage Vectors

Equation (6) is used to calculate the PV inverter’s CMV without regard for the DC
side’s midpoint voltage fluctuation [35]:
𝑉 𝑉 𝑉 𝑉 /3 (6)
where 𝑉 (𝑉 and 𝑉 ) is the voltage between the phase‐A (phase‐B and phase‐C) output
of the inverter and the DC neutral point. Table 2 summarizes the CMV induced by the
switching combinations. CMV has four values, 𝑉 /2 and 𝑉 /6, where the two of the
zero voltage vectors have the highest peak CMV.

Table 2. Common‐mode voltage of the space vectors.

Voltage Vectors 𝐕𝐜𝐦𝐯 Voltage Vectors 𝐕𝐜𝐦𝐯

V 0,0,0 V /2 V 0,1,1 V /6
V 1,0,0 V /6 V 0,0,1 V /6
V 1,1,0 V /6 V 1,0,1 V /6
V 0,1,0 V /6 V 1,1,1 V /2

2.4. Conventional Modulation Method

In the conventional SVPWM, six non‐zero vectors naturally divide into six equilateral
triangular sectors 𝑆 ~𝑆 in the 𝛼𝛽‐plane, which is shown in Figure 2a. Using the first sec‐
tor as an example, Figure 2b illustrates how a voltage vector can be synthesized from the
actual voltage vectors.
Electronics 2021, 10, 2607 5 of 15

 

V3  010 V2 110 V2 110

S2

S3 S1
V4  011 V1 100
S2
V0  000
S1
V7 111 

S4 S6 Vref
S5
V1 100
V5  001 V6 101 
(a) Sectors of SVPWM (b) Composition in the first sector
Figure 2. Conventional SVPWM.

Under the sector 𝑆 , the action times of each vector can be calculated according to
the volt‐second principle, as in Equation (7) [35]:
𝑇 𝑉 𝑇𝑉 𝑇𝑉 𝑇𝑉 𝑇𝑉
(7)
𝑇 𝑇 𝑇 𝑇 𝑇
where 𝑇 is the sampling time of one control/PWM cycle, 𝑉 is the reference voltage
vector, 𝑉 , 𝑉 , 𝑉 , and 𝑉 are the voltage vectors selected for synthesis, and 𝑇 , 𝑇 , 𝑇
and 𝑇 are the corresponding action time periods. 𝑇 and 𝑇 are typically equal.
In Table 2, the highest CMV is 𝑉 /2 because SVPWM employs zero voltage vectors.
In what follows, we introduce AZSPWM [2], NSPWM [14], and RSPWM [16]—these PWM
techniques share the common feature of suppressing the CMV amplitude and toggling
frequency. Figure 3 illustrates an example of synthesized switching waveforms for each
of the aforementioned modulation techniques and the associated CMV.

(a) SVPWM (b) AZSPWM

Electronics 2021, 10, 2607 6 of 15

(c) NSPWM (d) RSPWM

Figure 3. Synthesis and the corresponding CMV.

3. Proposed CMRSVPWM Methods for VSI

3.1. Sectors of CMRSVPWM
In order to reduce the amplitude and toggling frequency of CMV and increase the
DC‐bus utilization, CMRSVPWM is proposed in this work.
It begins with subdividing the basic six sectors, then divides each basic sector into
three parts. The two sections vertex at the origin have the same modulation index range,
so they are combined into the first component of CMRSVPWM (CMRSVPWM I), which
forms the hexagonal star shape. The remaining six triangular areas are the second portion
of CMRSVPWM (CMRSVPWM II). Modulation index determines which of the regions
should be used. Note that since each of the six sub‐regions of CMRSVPWM I contains two
basic sectors, it is important to determine the precise location of the reference voltage vec‐
tor. Figure 4 shows that the angle between two sector boundaries that can be used to de‐
cide whether odd or even voltage vectors are used in the synthesis process.

 

V3  010 V2 110 V3  010 V2 110

S1‐1 S' 1

V4  011 V1 100 V4  011 V1 100

S1‐2

 

V5  001 V6 101 V5  001 V6 101

(a) CMRSVPWM I (b) CMRSVPWM II

Figure 4. Sectors of CMRSVPWM.
Electronics 2021, 10, 2607 7 of 15

SVPWM that uses only odd or even vectors for synthesis will result in a very‐low
DC‐bus utilization rate. Figure 5a shows that the DC‐bus utilization rate, which is essen‐
tially equal to the radius 𝑟 𝑉 /3) of the inner tangent circle of the middle‐side trian‐
gle. CMRSVPWM I in this work intends to improve this aspect. Figure 5b shows the max‐
imum linear output voltage is now increased to radius 𝑟 ( 2√3𝑉 /9), which is the inner
tangent circle of the hexagonal star shape. The DC‐bus utilization of CMRSVPWM I is
increased by 15.47%, as compared to the scheme with either odd or even vectors, while
continuing to suppress the CMV peak amplitude.

 

V3  010 V3  010 V2 110

V1 100 V4  011 V1 100

 

V5  001 V5  001 V6 101

(a) Odd Vectors SVPWM (b) CMRSVPWM I

Figure 5. DC‐bus utilization.

3.2. CMRSVPWM I
The action times of voltage vector can be solved using the volt‐second principle.
Modulation index 𝑀 is introduced in Equation (8) [35]:
𝜋𝑉
𝑀 (8)
2𝑉
The action times corresponding to the voltage vector 𝑉 ~𝑉 are 𝑇 ~𝑇 . The general
equations that solve for the action times are shown in Equation (9).
𝑇 1/3 2𝑀 𝑐𝑜𝑠𝜃/𝜋 𝑇
⎧
⎪ 𝑇 1/3 𝑀 𝑐𝑜𝑠𝜃/𝜋 √3𝑀 𝑠𝑖𝑛𝜃/𝜋 𝑇
⎪
𝑇 1/3 𝑀 𝑐𝑜𝑠𝜃/𝜋 √3𝑀 𝑠𝑖𝑛𝜃/𝜋 𝑇
(9)
⎨𝑇 1/3 𝑀 𝑐𝑜𝑠𝜃/𝜋 √3𝑀 𝑠𝑖𝑛𝜃/𝜋 𝑇
⎪𝑇 1/3 2𝑀 𝑐𝑜𝑠𝜃/𝜋 𝑇
⎪
⎩𝑇 1/3 𝑀 𝑐𝑜𝑠𝜃/𝜋 √3𝑀 𝑠𝑖𝑛𝜃/𝜋 𝑇
Table 3 summarizes the switching sequences in each sector (clockwise direction is
assumed).

Table 3. Voltage vector action sequences under CMRSVPWM I.

Sectors Sequences Sectors Sequences

S1‐1 𝑉𝑉𝑉𝑉𝑉 S4‐1 𝑉𝑉𝑉𝑉𝑉
S1 S4
S1‐2 𝑉𝑉𝑉𝑉𝑉 S4‐2 𝑉𝑉𝑉𝑉𝑉
S2‐1 𝑉𝑉𝑉𝑉𝑉 S5‐1 𝑉𝑉𝑉𝑉𝑉
S2 S5
S2‐2 𝑉𝑉𝑉𝑉𝑉 S5‐2 𝑉𝑉𝑉𝑉𝑉
S3‐1 𝑉𝑉𝑉𝑉𝑉 S6‐1 𝑉𝑉𝑉𝑉𝑉
S3 S6
S3‐2 𝑉𝑉𝑉𝑉𝑉 S6‐2 𝑉𝑉𝑉𝑉𝑉
Electronics 2021, 10, 2607 8 of 15

3.3. CMRSVPWM II
Another main contribution of this work is to propose on the use of both CMRSVPWM
I and CMRSVPWM II modes to address the problem of limited usable modulation index
range in CMRSVPWM I alone, therefore improving the DC‐bus utilization. This scheme
that combines CMRSVPWM I and CMRSVPWM II into suppressing CMV is known as
CMRSVPWM in what follows. With CMRSVPWM II mode, the DC‐bus utilization is fur‐
ther increased from 2√3𝑉 /9 (in CMRSVPWM I) to 2𝑉 /3 as Figure 6 shows. The
modulation index 𝑀 decides on which modes, I or II, to be used. Odd‐even vectors mix‐
ing modulation is used to synthesize the reference voltage vector in CMRSVPWM II. Table
4 details the switch action sequences for each sector in the CMRSVPWM II.



V3  010 V2 110
V3  010 V2 110

V4  011 V1 100
V4  011 V1 100



V5  001 V6 101
V5  001 V6 101

(a) CMRSVPWM I (b) CMRSVPWM II

Figure 6. DC‐bus utilization.

Table 4. Voltage vector action sequences under CMRSVPWM II.

Sectors Sequences Sectors Sequences

S1 𝑉𝑉𝑉𝑉𝑉 S4 𝑉𝑉𝑉𝑉𝑉
S2 𝑉𝑉𝑉𝑉𝑉 S5 𝑉𝑉𝑉𝑉𝑉
S3 𝑉𝑉𝑉𝑉𝑉 S6 𝑉𝑉𝑉𝑉𝑉

Again, using the first sector for illustration, Figure 7 shows the synthesis of the both
CMRSVPWM modes and the corresponding CMV. In theory, CMRSVPWM I has no CMV
fluctuation, i.e., zero voltage toggling frequency, within a modulation cycle. CMRSVPWM
II, on the other hand, manifests twice voltage change/toggling. Note that the CMV peak
voltages in both modes are 𝑉 /6.
Electronics 2021, 10, 2607 9 of 15

(a) CMRSVPWM I (b) CMRSVPWM II

Figure 7. Synthesis of CMRSVPWM and the corresponding CMV.

4. Experimental Result and Discussion

The proposed MPC and CMRSVPWM methods are investigated using Matlab‐Sim‐
ulink. Figure 8 depicts the control loop. A 380 V 50 Hz AC grid is assumed. The DC‐bus
voltage is chosen to be 750 V, but it is noted that single‐stage voltage source inverter typ‐
ically have higher varying DC voltage, e.g., in the range of 750 V to 1500 V.

Figure 8. Overall structure of simulation.

4.1. Virtual‐Vector MPC

To fully utilize the entire voltage vector space, virtual vector MPC is used in this
work. First, a range of selection of virtual vectors is investigated. Virtual voltage vectors
are chosen at the angular phase angle intervals of 30, 45, and 60 degrees within the mod‐
ulation limit. Then, each selected voltage vector is divided into 1, 2, 5, 10, and 20 sub‐
Electronics 2021, 10, 2607 10 of 15

voltage vectors based on the magnitude length. The resulted THDs of these combinations
are summarized in Figure 9.

Figure 9. Model of the grid connected PV system.

When the interval angle is the same, selecting more sub‐voltage vectors results in a
lower THD value. When the same number of sub‐voltage vectors (in each phase angle
value) is used, the THD value decreases as the angle interval decreases. As shown in Fig‐
ure 9, there is only a small different of 0.01% for the selections of 10 and 20 sub‐voltage
vectors. With the consideration of computational burden, the virtual voltage vectors with
a 30‐degree angle interval (around the hexagonal voltage vector space, as show in Figure
10) and ten sub‐voltage vectors (equal, for each phase angle) are used in this work.

Figure 10. Hexagonal voltage space with 120 sub‐vectors(points)—used by the virtual vector model
predictive control.

4.2. CMV Simulation

Table 5 describes the parameters used by the simulation model, and the inverter con‐
trol part adopts the standard two‐step ahead MPC method.
Electronics 2021, 10, 2607 11 of 15

Table 5. Simulation Parameters.

Parameters Values Parameters Values

DC side voltage 𝑉 750𝑉 DC side capacitance 𝐶 5 10 𝜇𝐹
Current reference 𝐼 10𝐴 Switching frequency 𝑓 5𝑘𝐻𝑧
Filter inductance 𝐿 4𝑚𝐻 MPC sampling time 𝑇 2 10 𝑠
Filter resistance 𝑅 0.01𝛺 Modulated sampling time 𝑇 2 10 𝑠
Predictive horizon (first step to
Grid voltage 𝑒 380𝑉 2
overcome digital delay)
Grid frequency 𝑓 50𝐻𝑧 Control horizon 1

The comparison in Figure 11a,b shows that the simulation results are consistent with
the theoretical analysis. The peak and valley values of CMV in conventional SVPWM are
375𝑉( 𝑉 /2), while the peak and valley values of CMRSVPWM are 125𝑉 ( 𝑉 /6),
representing a decrease of 66.67%. Notably, CMRSVPWM has fewer CMV frequency
jumps per fundamental cycle.

(a) SVPWM local magnification of CMV. (b) CMRSVPWM local magnification of CMV.
Figure 11. CMV under different strategies.

Phase‐A current and its THD values for SVPWM and CMRSVPWM are shown in
Figure 12a,b. Both have a period of 0.02 s and an amplitude of 9.994 A. Next, phase‐A
output voltages are compared in Figure 13a,b. The amplitudes of 311.4 V of the phase‐A
voltages are comparable for both.

(a) SVPWM (b) CMRSVPWM

Figure 12. Outputs current of inverter.
Electronics 2021, 10, 2607 12 of 15

(a) Phase‐A voltage in SVPWM. (b) Phase‐A voltage in CMRSVPWM.

Figure 13. Outputs phase‐A voltage of inverter.

Characteristics of several PWM techniques targeting CMV improvement, and that of

the proposed CMRSVPWM I and CMRSVPWM II, are listed in Table 6. All techniques
with improved CMV property can reduce the peak CMV to Vdc/6. Th proposed
CMRSVPWM has the best combination of DC‐bus utilization and CMV frequency (which
is either 0 or 2, due to the two modes). For current THD (where only that for SVPWM,
AZSPWM, NSPWM and CMRSVPWM are measured; all four modulation schemes have
the same DC‐bus utilization), and they have practically the same value, agreeing with
theoretical expectation.

Table 6. Characteristic of different PWM modulation techniques targeting CMV improvement.

CMRSVPWM (I and
SVPWM AZSPWM NSPWM RSPWM CMRSVPWM I
II)
Peak CMV V /2 V /6 V /6 V /6 V /6 V /6
CMV frequency 6 6 4 0 2 0 or 2
CMV frequency at
0 1 1 0 1 1
changing sectors
DC bus utilization 2𝑉 /3 2𝑉 /3 2𝑉 /3 𝑉 /3 2√3𝑉 /9 2𝑉 /3
Phase‐A current
0.61% 0.74% 0.64% 0.75%
THD
Electronics 2021, 10, 2607 13 of 15

5. Conclusions
Space vector modulation is enhanced to reduce the property of the single‐stage volt‐
age source inverter. The following results are taken from the simulation experiment:
(1) In comparison to the SVPWM, the enhanced CMRSVPWM strategy decreases the
CMV amplitude from 𝑉 /2 to 𝑉 /6, a reduction of 66.67%. The CMV toggling fre‐
quency is reduced to either 0 or 2.
(2) In comparison with the PWM techniques with either three odd or three even vectors,
the proposed CMRSVPWM I will increase the utilization rate of the DC bus by
15.47%, reaching 2√3𝑉 /9 . The utilization rate is increased further through
CMRSVPWM II, up to the maximum available rate as that of SVPWM.
(3) Through virtual‐vector MPC with 120 sub‐vectors, the entire range of CMRSVPWM
can be utilized to output switching harmonic performance.

6. Deficiencies and Prospects

In actual implementation, a dead zone will manifest itself during the modulation
phase. However, since the focus of this article is on the use of the proposed CMRSVPWM
in conjunction with virtual‐vector MPC, the dead zone is not considered. Future work will
explore this issue in greater detail.

Author Contributions: Conceptualization, H.H.G. and X.L.; methodology, X.L. and C.S.L.; software,
X.L.; validation, C.S.L.; formal analysis, D.Z. and W.D.; investigation, Goh Hui Hwang; writing—
original draft preparation, X.L.; writing—review and editing, H.H.G., T.A.K. and K.C.G. All authors
have read and agreed to the published version of the manuscript.
Funding: This research was funded by Guangxi University grant number A3020051008.
Conflicts of Interest: The authors declare that they have no known competing financial interests or
personal relationships that could have appeared to influence the work reported in this paper.

Appendix A

Table A1. Definition of acronym in paper.

VSI voltage source inverter SVPWM Space Vector Pulse Width Modulation
MPC Model Predictive Control AZSPWM Zero‐State Switch Pulse Width Modulation
CMV Common‐Mode Voltage NSPWM Near‐State Pulse Width Modulation
PWM Pulse Width Modulation RSPWM Remote‐State Pulse Width Modulation
THD Total Harmonic Distortion CMRSVPWM Common‐Mode Reduction Space Vector Pulse Width Modulation

Table A2. Definition of notations in paper.

𝑉 Output voltage of PV 𝑖 𝑘 2 Currents in 𝑘 2 𝑇

∗
𝑉 Inverter output voltages 𝑖 Reference current values on αβ axis
𝑖 Inverter output currents 𝑇 Sampling time
𝑒 Grid voltages 𝐿 Filter value
Output currents on 𝛼𝛽 coordi‐
𝑖 𝑅 Filter’s internal resistance
nate system
Output voltage from different
𝑉 𝑖 0,1 ⋯ 7 𝑉 Common‐mode voltage value
switching states
Voltage between the phase‐A output of the in‐
𝑎 Phase difference of 120° 𝑉
verter and the DC neutral point
𝑆 States of switch 𝑇 Sampling time of one cycle
Feedback values of 𝛼𝛽 axis cur‐
𝑖 𝑘 𝑇 𝑖 0,1 ⋯ 7 Corresponding action times of voltage vectors
rents at the current time
Electronics 2021, 10, 2607 14 of 15

Grid voltage values of 𝛼𝛽 axis

𝑒 𝑘 𝑀 Modulation index
at the current moment
Predicted values of αβ axis cur‐
𝑖 𝑘 1
rents at the next moment

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