See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/322411740

Heuristic Algorithm for a WIP Projection Problem at Finite Capacity in

Semiconductor Manufacturing

Article in IEEE Transactions on Semiconductor Manufacturing · January 2018

DOI: 10.1109/TSM.2018.2792312

CITATIONS READS

2 809

5 authors, including:

Emna Mhiri Fabien Mangione

University of Grenoble Grenoble Institute of Technology
6 PUBLICATIONS 31 CITATIONS 31 PUBLICATIONS 168 CITATIONS

SEE PROFILE SEE PROFILE

Philippe Vialletelle Guillaume Lepelletier

STMicroelectronics, Crolles, France kheoos
60 PUBLICATIONS 478 CITATIONS 10 PUBLICATIONS 65 CITATIONS

SEE PROFILE SEE PROFILE

All content following this page was uploaded by Guillaume Lepelletier on 29 May 2018.

The user has requested enhancement of the downloaded file.

 Heuristic algorithm for a WIP projection problem at
finite capacity in semiconductor manufacturing
Emna Mhiri, Fabien Mangione, Mireille Jacomino, Philippe Vialletelle,
Guillaume Lepelletier

To cite this version:

Emna Mhiri, Fabien Mangione, Mireille Jacomino, Philippe Vialletelle, Guillaume Lepelletier. Heuris-
tic algorithm for a WIP projection problem at finite capacity in semiconductor manufacturing. IEEE
Transactions on Semiconductor Manufacturing, Institute of Electrical and Electronics Engineers, 2018.
<hal-01682760>

HAL Id: hal-01682760

https://hal.archives-ouvertes.fr/hal-01682760
Submitted on 12 Jan 2018

HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est

archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents
entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non,
lished or not. The documents may come from émanant des établissements d’enseignement et de
teaching and research institutions in France or recherche français ou étrangers, des laboratoires
abroad, or from public or private research centers. publics ou privés.
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 1

Heuristic algorithm for a WIP projection problem at

finite capacity in semiconductor manufacturing
Emna Mhiri, Fabien Mangione, Mireille Jacomino, Philippe Vialletelle, and Guillaume Lepelletier

Abstract—In this paper, we propose a heuristic approach for products at different stages of their fabrication. This also
fixing work-in-progress (WIP) projection issues in the semi- means that according to the decisions taken on the production
conductor industry especially for High Mix Low Volume (HMLV) line, products may experience various cycle times depending
facilities. The considered problem consists of estimating the start
and end dates for each remaining process step of the production on the priority given either to a given product, to satisfy
lots in the WIP and anticipating the fab loading taking into customer demand, or to a certain technological level for the
account the constraints of the maximum throughput of machines purpose of line balancing. Hence, the capacity planning issue
considered as capacity constraints and customer delivery com- is difficult to solve and it is particularly more complex than
mitments. The objective being to guarantee on-time delivery, we in other industries [1].
focus on minimizing the total weighted tardiness (TWT). We have
formulated the problem into a mixed-integer programming (MIP) Semiconductor manufacturing is composed of four major
and we have empirically shown its computational intractability. phases: wafer fabrication (fab), wafer probe, assembly, and fi-
Due to the computational intractability using actual production nal test. Wafer fabrication, often referred to as ”front end”, rep-
data, a heuristic algorithm is proposed. It is an iterative finite resents the most complicated, expensive and time-consuming
capacity planning system that considers as inputs lots due dates phase of all four stages [2]. In this phase, hundreds of circuits
and equipment capabilities and capacities. The performance of
the heuristic is assessed using industrial instances. It turns out are layered through successive operations on a silicon wafer.
that it achieves targeted objectives with satisfactory results in The manufacturing process in wafer fabs involves a highly
terms of quality of the solution and computation time. complex sequence of processing operations which can be
Index Terms—WIP projection; finite capacity planning; semi- classified into various types, as for example: oxidation and
conductor industry; mixed integer programming; iterative algo- thermal treatment, film deposition, planarization, photolithog-
rithm. raphy, etching and ion implantation. These operations are
repeated for each layer of circuitry on the wafer. Figure 1
I. I NTRODUCTION presents a simplified view of the wafer fabrication process.

W ORK-in-progress (WIP) projection is a mid-term ca-

pacity planning activity. The objective is to compute a
mid-term target schedule in order to drive factory execution,
to anticipate production issues and to calculate net demand
and net resource capacities. In our study, the outcome is a
weekly-released schedule that depicts the start and end dates
of each remaining processing step as well as the expected
workload accumulated on each equipment per time bucket over
the planning horizon.
In this study, the WIP projection problem is considered
in one of the most dynamic industries in the world, the
semiconductor industry. The semiconductor manufacturing
process is extremely complex and constantly innovating. The
considered wafer production plant is a High Mix Low Vol-
ume (HMLV) production line: there are several hundreds of Fig. 1: Wafer fabrication Process. [1]
products, different technologies and heterogeneous toolsets i.e.
collections of nonidentical multi-purpose parallel machines (or Each operation shown in Figure 1 can include multiple
tools). Moreover, typical semiconductor fabrication processes elementary steps (cleaning, process, measurement). The total
require several hundreds of different steps. As, for obvious number of steps per flow typically ranges between 400 and
reasons, HMLV fabs cannot multiply machines, their pro- 800 for current production technologies and up to 1200 steps
duction flows are re-entrant: the same machine can process for latest generations. Some of the processing steps in a flow
E. Mhiri is with Univ. Grenoble Alpes, CNRS, G-SCOP, 38 000 Grenoble, are performed on individual wafers, others on groups of wafers
France (e-mail: [email protected]). (lots), and still others on groups of lots (batches).
F. Mangione and M. Jacomino are with Univ. Grenoble Alpes, CNRS, G- Steps performed on individual wafers or lots of wafers are
SCOP, 38 000 Grenoble.
P. Vialletelle and G. Lepelletier are with STMicroelectronics, F-38926 referred to as serial steps, while those performed on groups
Crolles Cedex, France. of lots are called batch steps. A lot is generally composed of
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 2

25 wafers, while a typical batch contains up to six lots. In II. P REVIOUS RELATED WORK
the considered case study, the lot requires 8 to 10 weeks to
be processed. Steps are executed on more than one hundred As the semiconductor industry is considered as one of
workstations called ”toolset” [1]. Due to flow re-entrance, lots the most complex manufacturing processes, many researchers
visit the same toolset more than once during the manufacturing have paid attention to the capacity planning problems encoun-
process. tered in this environment.
The various problems investigated have considered different
For each step, the wafer has to be processed on various phases of the manufacturing process of integrated circuits,
types of tools using a well-defined recipe. The recipe contains different constraints, different methods and techniques used
the detailed instructions to be used at the machine level in for capacity planning and different performance measures.
order to proceed the intended physical transformations or Mönch et al. [1], Uzsoy et al. [2], [4] and Gupta et al. [5]
measurements. The identification of the candidate tools to be have mentioned in their reviews different capacity planning
used is made through qualification of recipes on the tools. techniques used in the semiconductor environment which can
However, in HMLV fabs, because of multiple differences be classified in infinite and finite capacity planning techniques.
in hardware and software configurations, hence variety of They can also be divided, according to the length of the plan-
recipes to be used, it is not possible to qualify all recipes ning horizon, into long-term (strategic), mid-term (tactical)
on every machine. Qualification is one of the characteristics and short-term (operational) planning tools.
of the HMLV semiconductor manufacturing. It determines the
Among the methods used for capacity planning, classical
processing authorization of a product on a machine. It acts
techniques were successfully used in many industries espe-
like an eligibility constraint that allows production volume
cially for tactical and operational production planning, such as
allocation of a product to a machine. It is known also as the
Material Requirement Planning (MRP) developed by Orlicky
process capability constraint [3].
[6], Manufacturing Resource Planning (MRPII) [7], Just In
Besides, each toolset has an identified throughput consid- Time (JIT) [8] and Theory Of Constraints (TOC) [9]. The
ered as its capacity which refers to its upper loading threshold application of these traditional techniques for capacity plan-
under a given product mix condition. To establish a feasible ning in semiconductor industry presents some shortcomings.
production schedule over a planning horizon of several weeks, Indeed, it is proven that MRP method can be inefficient and
thus requires to consider capability and capacity constraints. may produce unrealistic production schedules when used in
Moreover, as for other industries, semiconductor manufactur- field applications. It ignores capacity constraints and assumes
ing facilities must respect customers delivery commitments fixed cycle times ([10], [11], [12], [13]). However, in semi-
to survive in competitive business environments. For HMLV conductor facilities, cycle times depend on many factors, such
fabs, actual cycle time is widely spread and skewed due to as machine utilization rate, lot size, inventory and dispatching
large variability of numerous sources: equipment heterogene- rules, and are thus variable. Either shortcoming above leads
ity, product priorities, low redundancy, steps qualifications, etc. to infeasible production schedules, fluctuating workloads over
It is then crucial to consider also variable cycle times while time and significant users effort to adjust the plans. The JIT
defining a production plan. In practice, fab’s historical data technique proves its strengths [14]; however, it presents some
and various applications of the queuing theory are often used. limitations in the high-mix low-volume production systems.
It seems to be more suitable for a repetitive production
In this paper, a mixed integer program (MIP) and a heuristic
environment with stable demand and low product mix [15].
algorithm are proposed to project current inventory and new
The TOC seems an efficient capacity planning technique in
wafer starts throughout the remaining processing sequence,
semiconductor industry [16] but it considers only bottleneck
taking into account all the cited constraints. The objective is
resources and it can not deal with changes in the bottlenecks.
to establish a feasible midterm schedule, in a fast execution
In addition to these classical industrial methods, authors
time (less than 5 minutes, the required computation time of
use discrete event simulation models, queueing theory, linear
capacity planners of the industrial partner), while minimizing
programming and heuristics for capacity planning applied to
lots delivery delays and optimizing workload balance among
semiconductor industry. Discrete event simulation is often
all toolsets. This study is applied to the Crolles 300 mm wafer
used for capacity planning decisions in wafer fabs [17] in
fab of STMicroelectronics. Thus, data from actual production
order to evaluate the performance of production planning
process are collected and used to evaluate the performance of
strategies ([18], [19], [20], [21], [22]). Indeed, discrete-event
the developed approaches.
simulation is considered as the only practical method that
This paper is organized as follows. This section introduces explicitly calculates the cycle time as a function of resource
the main characteristics of the considered industrial envi- availability and production rate. The simulation model can
ronment. In section 2, some background on existing related be used also to determine bottlenecks under a given product
capacity planning problems is provided. In section 3, the mix and to make strategic decisions concerning equipment
problem is stated and the MIP formulation is presented. The purchase [23]. However, simulation models used for capacity
proposed iterative heuristic algorithm is explained in section 4. planning in the semiconductor industry present some severe
Next, in section 5, experiments conducted and analyses carried limitations. Their set-up is very time-consuming due to the
out are discussed. Finally, section 6 draws conclusions and volume and often complexity of the data required for the
provides suggestions for future work. models involved. Moreover, these models do not provide a
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 3

means for optimization of the plan ([24], [25]). Chua et al. [44] developed an intelligent multi-constraint
Concerning queueing network models, Shanthikumar et al. finite capacity-based lot release system. This system has been
[26] presented a survey of the different applications of queue- designed, developed and implemented to solve the lot release
ing theory for semiconductor manufacturing systems. They problems in a discrete manufacturing environment with a huge
recognized that in spite of fast computing time compared with product mix and multiple capacity constraints.
simulation models, the accuracy of classical queueing models In this study, we are interested in operations research related
is not satisfactory due to the complexity of the semiconductor (or mathematical) optimization approaches and we consider a
manufacturing process. medium-term finite capacity planning problem, applied to a
The linear programming (LP) approach is widely applied semiconductor production line. So far, the literature review has
to specific issues encountered in capacity planning for the pointed out that the debate about this problem is still open, and
semiconductor industry. Mixed-integer programming (MIP) the proposed approaches by several authors still have some
models are developed for strategic planning in order to maxi- limits. Table II presents a taxonomy of studies considering
mize the profit ([27], [28], [29]) or to minimize the machine the same problem and using operations research solving tools.
tool operating costs, new tool acquisition costs, and inventory Steps cycle time can be either defined as a fixed input by
holding costs taking into account capacity constraints [30]. the proposed approach or a variable output of the procedure.
A good source of previous work related to more strategic Capability constraints are relevant, since they can be embedded
capacity planning is provided by Geng and Jiang [31]. or not in the proposed procedure. Lots due dates, relevant as
LP (sometimes in combination with discrete-event sim- well, can be considered as input parameters or not. Finally, the
ulation) is also used to solve medium-term finite capacity model can be tested via data generated by authors (random
planning problems. The work of Hung and Leachman [32] instances) or through data from real-life production systems
is an example of such an approach. Leachman [33] used (real case).
LP for production planning and presents a corporate capacity Whilst capacity and cycle time are tightly linked one another
planning model, which includes multiple facilities integrated through the Little’s law [45], cycle time is considered by
with the production process. Habla et al. [34] suggested a most approaches as a fixed input parameter. Moreover, some
MIP formulation to determine completion time targets for methods ignore capability constraints thus leading to infeasible
the lots on bottleneck steps. Bermon et al. [35] introduced production plans. Finally, the applicability in field to real-life
a linear programming model to analyze the capacity of large companies has not been reported for all the anterior studies.
and complex manufacturing production lines. Furthermore, Table II presents, for each study, its algorith-
Due to the intractability of LP models, they are generally mic and operational objectives. As one can notice, the main
combined with heuristics such as genetic algorithms [36] issues treated in the existing studies are generally limited to
or decomposition techniques as Benders [37] or Lagrangian dispatching rules and release control policies which are outside
relaxation ([30], [34]) to reduce execution time. Besides, the scope of this paper.
approximate methods have also been widely used to develop In the literature, there are few studies considering the WIP
either infinite or finite capacity planning systems for the projection problem in the semiconductor industry ([46], [47],
semiconductor industry. [48]). In these works, authors consider different objectives and
Infinite capacity planning systems are developed to estimate do not take into account all the cited constraints.
the future loading of equipment in order to identify bottleneck Kim and Leachman [46] proposed a LP formulation and
resources and to balance the loading of each production a decomposition heuristic method to determine net demand
resource over the planning horizon ([38], [39], [40]). and net resource capacities taking into account capacity con-
Bearing in mind the importance of capacity constraints, straints. They tested their approaches using random data.
many authors developed finite capacity planning systems using Lee et al. [47] employed deterministic linear programming
algorithmic approaches. Fargher et al. [41] used a beam-search techniques for the WIP projection problem in the wafer
algorithm in combination with backtracking steps for lot fab, that explicitly considers the variable cycle time. Govind
release and for the determination of schedules in an aggregated and Fronckowiak [48] consider WIP projection problem to
sense. measure production performance at IBM’s 300 mm wafer fab
Horiguchi et al. [42] proposed an algorithm that estimates by computing productivity and WIP targets at infinite capacity.
the start and finish date of each job scheduled on each critical As one can see, even if some papers tackle similar planning
resource: their algorithm considers the available time for all problems, none of the already proposed models explicitly
the feasible combinations of time bucket and critical resource, address our specific problem.
and it reduces the available time whenever a new production The research work outlined here tried to overcome some
order is added to the schedule. This approach, due to the of the limits above: the proposed finite capacity planning
high aggregation level in modeling resources and relationships, algorithm does not consider fixed steps cycle time, it takes
might lead to orders overlapping on the same resource in the into account lots due dates and it has been tested in a real-life
same time bucket (i.e. infeasible plans). industrial context. Furthermore, it meets the key requirement
Habenicht and Mönch [43] used also a beam-search algo- of semiconductor industrials, consisting on fast computing of
rithm to determine planned start and completion dates for the feasible production plans (in five minutes at most on a personal
macro operations (sets of consecutive process steps) of a lot. computer) to facilitate ”what-if” analysis.
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 4

III. M ATHEMATICAL FORMULATION OF THE PROBLEM TABLE I: Summary of problem notation

Indices Description
L Number of lots
l = 1..L Lot index
A. Problem description Sl Number of remaining steps of lot l
sl = 1..Sl Lot’s step index
I Number of toolsets
The WIP projection problem may be defined as follows. i = 1..I Toolset index
A set of lots l ∈ {1, . . . , L}, composed of Ql wafers each, T Number of time buckets
t = 1..T Period index
is considered. For each lot l, it remains an identified number Parameters Description
of steps Sl to be processed on a time horizon discretized in Pt Length of period t
T periods t ∈ {1, . . . , T } of equal length Pt . Each lot of a Ql Quantity of wafers of lot l
rl Release date of lot l
weight wl indicating its priority, has a release date rl and a wl Weight of lot l
due date dl . dl Due date of lot l
psl ,l,i Unit processing time of step sl of lot l on qualified
The performance measurement to be minimized in this toolset i, 0 on non-qualified toolset i
problem is total weighted tardiness TWT. TWT is a measure Ci,t Capacity of toolset i in period t
that incurs a penalty for each lot that finishes processing asl ,l,i Quantity of wafers of lot l in step sl processed by
the toolset i
after its promised delivery date. This penalty increases with Decision variables Description
the magnitude of the tardiness, and therefore schedules that ssl ,l Start date of step sl of lot l
minimize the weighted (by lot priority) sum of penalties esl ,l End date of step sl of lot l
Cl Completion date of lot l
provide good on-time delivery performance, whereas higher Tl Tardiness of lot l
values of total weighted tardiness indicate that many important Li,t Loading of toolset i in period t
lots are not being delivered on time. Indeed, a processing ysl ,l,t = ssl ,l if the step sl of lot l is released in period
t, 0 otherwise
schedule will provide a completion time, Cl , for each lot. The xsl ,l,t =1 if step sl of lot l is processed in period t, 0
tardiness, Tl , of lot l is then defined as Tl = max(0, Cl − dl ). otherwise
The weighted tardiness of the lot l (W Tl ) is defined as W Tl
= (wl × Tl ). Total weighted tardiness P computes the weighted
sum of tardiness values: T W T = l W Tl . notation presented above, the MIP is as follows:
Each remaining step sl ∈ {1, . . . , Sl } of the lot l is processed X
min wl Tl (1)
on one or several qualified toolsets i ∈ {1, . . . , I}. The
l
quantity of wafers of a lot l assigned to the toolset i, processing
s.c. s1,l ≥ rl l = 1, . . . , L (2)
the step sl during the period t, is denoted asl ,l,i,t . It has a X
waiting time wtsl ,l and it consumes a unit processing time ssl ,l + psl ,l,i × asl ,l,i,t × xsl ,l,t = esl ,l
psl ,l,i on each of its qualified processing toolsets. It also has a i
start date ssl ,l and an end date esl ,l (Figure 2). Each toolset i sl = 1, . . . , Sl , l = 1, . . . , L (3)
has a finite capacity Ci,t , which gives the maximal loading ssl ,l ≥ esl −1,l sl = 2, . . . , Sl , l = 1, . . . , L (4)
Li,t over a period t. X
ysl ,l,t = ssl ,l sl = 1, . . . , Sl , l = 1, . . . , L (5)
Table I summarizes the notation. t
X
xsl ,l,t = 1 sl = 1, . . . , Sl , l = 1, . . . , L (6)
t
Cl = eSl ,l l = 1, . . . , L (7)
Tl ≥ Cl − dl l = 1, . . . , L (8)
Tl ≥ 0 l = 1, . . . , L (9)
Fig. 2: Problem description. t × Pt × xsl ,l,t ≤ ysl ,l,t sl = 1, . . . , Sl ,
l = 1, . . . , L, t = 1, . . . , T (10)
(t + 1) × Pt × xsl ,l,t > ysl ,l,t sl = 1, . . . , Sl ,
l = 1, . . . , L, t = 1, . . . , T − 1 (11)
XX
Li,t = psl ,l,i × xsl ,l,t × asl ,l,i,t
l sl
B. Mixed-Integer Program i = 1, . . . , I, t = 1, . . . , T (12)
Li,t ≤ Ci,t i = 1, . . . , I, t = 1, . . . , T (13)
In this subsection, an appropriate MIP formulation is pre- xsl ,l,t = {0, 1} sl = 1, . . . , Sl , l = 1, . . . , L,
sented for the multi-product, multi-period and multi-resource
t = 1, . . . , T (14)
capacity planning problem. The proposed MIP is similar to
LP capacity planning models that can be found in standard
textbooks, with some variations and extensions. Using the
 TABLE II: Taxonomy of the literature of finite capacity planning approaches applied to semiconductor industry.

Objectives Constraints and assumptions

Approach Reference Test
Capacity Capability Variable
Algorithmic Operational Due dates
constraints constraints cycle times
Hung and
Linear
Leachman Determine wafer release
programming Maximize the profit X X Real case study
[32], Bermon quantities
based
et al. [35]
Generate capacity-
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

Leachman [33] Maximize the profit feasible start and out X X X X Real case study
schedules
Determine completion
Habla et al. Minimize total weighted
time targets for the X X Example
[34] tardiness
bottleneck steps
Algorithms Determine the work to
Fargher et al. Reduce cycle time and
/heuristics release into the factory at X X X Real case study
[41] the variance of cycle time
based any time
Estimate the start and
Improve delivery
Horiguchi et finish date of each job
performance and system X X Example
al. [42] scheduled on each critical
predictability
resource
Determine the start date
Habenicht and Establish a feasible
and the end date of each X X X Example
Mönch [43] production plan
operation of the lot
Compute orders release
Chua et al. [44] dates for semiconductor Solve lot release problem X Real case study
back end assembly
Minimize total weighted Establish a feasible target
Our study X X X X Real case study
tardiness production plan
5
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 6

The objective function (1) minimizes the total weighted TABLE III: Summary of tests parameters
tardiness (TWT). The MIP constraints can be classified in Problem parameter Values used
two kinds: temporal constraints ((2). . .(11)) and cumulative Number of lots (L) 2, 3, 10, 20, 30, 40, 50, 60, 70,
80, 90, 100, 200, 240, 1000, 1700,
constraints (constraints (12)-(13)). Constraints (2) define the 2000
start date of the first remaining step for each lot. The end date Maximum number of remaining 1, 2, 5, 6, 8, 10, 20, 30, 40, 50, 60,
of each remaining step of each lot is computed using con- steps of lot l (max Sl ) 100, 150, 200, 250, 680
Number of toolsets (I) 3, 5, 10, 20, 100, 300
straints (3). Constraints (4) present precedence constraints of Number of time buckets (T ) 24
processing steps. Constraints (5) guarantee that each remaining Weight per lot (wl ) Uniform (0,1)
step of each lot is released once. Constraints (6) verify that Lots release dates (rl ) 0
Lots due dates (dl ) rl +[1..210]
each remaining step of each lot is processed once during the Lots quantity of wafers (Ql ) 25
planning horizon. Constraints (7) define the lots completion Steps unit processing times [0.0005..0.5]
date. Constraints (8) and (9) compute the tardiness for each (psl ,l,i )
lot. Constraints (10) and (11) indicate that each remaining
step of each lot is processed in one period. Constraints (12)
calculate the workload accumulated by each toolset over each
period taking into account the qualification of the toolset
to the processed step and the quantity of wafers assigned
to the considered toolset. Constraints (13) are the capacity
constraints. Constraints (14) are the binary constraints for the
decision variable.
The mathematical model presented above has been solved
by ILOG CPLEX solver. Experiments were run on an
Intelr CoreTM i5 PC running a 2.7 GHz processor and
4 GB of RAM. Tests have been performed on 30 randomly Fig. 3: Limits of MIP resolution.
generated instances of the problem in order to highlight the
main characteristics of the industrial data and to maintain
a certain degree of generality in order to preserve all the From the empirical evidence on the computational difficul-
difficulty of the problem. Indeed, based on the observation ties in getting optimal schedule considering lots due dates and
made in the literature, we identified seven important problem capacity constraints, it is obvious that the problem of WIP pro-
parameters which could affect the performance of the proposed jection applied to the real case study will be computationally
approach: number of lots (L), maximum number of remaining intractable. Furthermore, Garey and Johnson [49] highlighted
steps for each lot (max Sl ), number of toolsets (I), length in their study that production planning, capacity planning and
of the planning horizon (T ), lots steps unit processing times scheduling problems in complex job shops like semiconductor
(psl ,l,i ), lots due dates (dl ) and machines capacities (Ci,t ). manufacturing are known as strongly NP-hard problems. This
We consider the cases of 3, 5, 10, 20, 100 and 300 parallel has motivated us to develop a heuristic algorithm for the
toolsets with a fixed capacity corresponding to the maximum research problem considered in this study to provide near
equipment utilization rate which is equal to 100%. The lots optimal solutions and/or efficient solution in a reasonable time.
weights wl are chosen from a uniform distribution over (0,1). The proposed heuristic algorithm is presented in the next
The lots release dates rl and lots quantity of wafers Ql are section.
supposed equal to 0 and 25 for all lots, respectively. The range
of lots due dates dl and steps unit processing times psl ,l,i is IV. H EURISTIC ALGORITHM
extracted from real data. dl are ranging from 1 to 210 days An alternative methodology for the above problem should
relative to the release date and psl ,l,i range between 0.0005 and be accurate and, at the same time, fast and small enough to
0.5 hours. The planning horizon is set to 24 periods (weeks). be stored and implemented in a mainframe or work station
Table III presents the different tests parameters generating 30 computer system. Bearing this in mind, a heuristic approach
instances. for WIP projection problem in HMLV semiconductor manu-
Optimal results were obtained in reasonable execution time facturing line has been developed. It is an iterative algorithm
while testing the MIP on instances of reduced size. Further composed of three main modules: (i) WIP projection at infinite
increasing the size of the tested instances (up to about 4000 capacity, (ii) workload accumulation and capacity analysis
steps plan), the resolution of MIP was halted as it required a and (iii) workload and capacity balancing. The algorithm is
very large amount of time and computer memory (Figure 3). executed by iterations on periods of the planning horizon. The
Indeed, the whole real problem presents 70 742 400 constraints principle of iterative running of the algorithm is inspired from
and 69 371 200 variables. It corresponds to a WIP composed of the literature [50] and the detailed scheduling in the com-
2000 lots, each lot having a maximum of 680 remaining steps mercial ERP/APS. For each defined period, WIP projection
to process on 300 toolsets over a planning horizon composed module estimates the evolution of the WIP, lot by lot, based
of 24 periods (weeks). Thus, the size of real instances is on lots due dates. Then, workload accumulation module calcu-
obviously too large to be solved using the proposed MIP lates the expected equipment loading. In case of toolsets over-
(Figure 3). saturation i.e. the loading of toolsets exceeds their maximal
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 7

capacity, workload and capacity balancing module is employed target cycle time, extracted from historical data. It is
to reduce toolsets loading by shifting their affected steps to defined as the step mean cycle time divided by the step
subsequent periods. The following sections will detail the three raw processing time RPT [51].
major modules. Figure 4 depicts the flow of the developed WIP projection module includes three steps. Step 1 computes,
system. for each lot, from its position in the route, four parameters
which are remaining process time RemP Tl , remaining refer-
ence cycle time RemRef CTl , remaining expected cycle time
RemExpCTl and cycle time coefficient CT Coef fl .
RemP Tl is equal to the sum of lot remaining steps unit
process time multiplied by lot quantity of wafers Ql .
Sl X
X I
RemP Tl = psl ,l,i × Ql (15)
sl =1 i=1

RemRef CTl corresponds to the sum of the reference cycle

times of lot remaining steps Ref CTsl ,l .
Sl
X
RemRef CTl = Ref CTsl ,l (16)
sl =1

In the industrial context considered, each step has a reference

cycle time, extracted from historical data, named Ref CTsl ,l .
Ref CTsl ,l corresponds to the product of the unit step process
time with the quantity of lot wafers Ql and the flow factor
Xf actorsl ,l . It is the maximum amount of time that a lot
would spend at that step, including waiting and processing
times.
I
X
Ref CTsl ,l = psl ,l,i × Ql × Xf actorsl ,l (17)
i=1

RemExpCTl is equal to the maximum between the difference

between the due date and the current time t and RemP Tl .
RemExpCTl = max(dl − t, RemP Tl ) (18)
The lot cycle time coefficient CT Coef fl identifies the nec-
essary and sufficient speed for lots to achieve their due date
according to the reference cycle time. It is equal to the ratio
between lot remaining expected cycle time RemExpCTl and
lot remaining reference cycle time RemRef CTl :
RemExpCTl
Fig. 4: Finite Capacity Planning Algorithm Flow. CT Coef fl = (19)
RemRef CTl
In step 2, the RemExpCTl is split on the elementary steps
A. WIP projection module of each lot l to compute an expected cycle time per step
ExpCTsl ,l which is equal to the product of ObjCTsl ,l and
The objective of this module is to push lots, one by one,
CT Coef fl .
forward along their routes, from their current positions up to
their due dates. It also aims to compute over a period the ExpCTsl ,l = Ref CTsl ,l × CT Coef fl (20)
activity required by step to ensure the delivery plan.
For each selected time bucket t of the planning horizon, this Equation (20) gives a rough estimation of queuing time at each
module requires the following data input: step. Hence, waiting time by step wtsl ,l can be computed:
1) WIP status and wafer starts at the beginning of the I
X
considered projection period (position rl , quantity Ql ), wtsl ,l = ExpCTsl ,l − psl ,l,i × Ql (21)
2) Routing information, including a partition of each route i=1

into consecutive steps, In step 3, having the waiting time by step, start dates and end
3) Steps unit processing times psl ,l,i , dates for all lots remaining steps, decision variables xl,sl ,t ,
4) Lots due dates dl and weights wl , lots completion date and tardiness are computed.
5) Flow factor Xf actorsl ,l that reflects possible waiting Figure 5 illustrates an example of 2 lots with different due
times between consecutive process steps to achieve the dates, having 3 remaining steps each. The first one has an
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 8

TABLE IV: Data for simple instance

Lot l Weight Number RemP Tl Rem- Rem- CT-
wl of re- in Ref CTl ExpCTl Coef fl
maining days in days in days
steps Sl
Lot 1 0.33 6 1.1 1.6 5 3.125
Lot 2 1 4 0.8 1.1 0.5 0.45
Lot 3 0.5 2 0.25 0.41 1.5 3.65
Lot 4 0.5 8 1.7 2.3 1.5 0.65
Lot 5 0.5 6 1 1.4 1.5 1.07
Lot 6 0.33 4 0.75 1.02 5 4.9
Lot 7 0.5 8 0.86 1.05 1.5 1.43
Lot 8 1 4 0.8 1.05 0.5 0.48
Fig. 5: Principle of cycle time computation for each processing Lot 9 0.5 4 0.8 1.05 1.5 1.43
step of a lot. Lot 10 0.5 6 1.4 1.9 1.5 0.79

earlier due date i.e. a higher priority and less RemExpCTl

than the second.
Using the classical projection based on historical data, the
two lots have the same distribution of remaining steps waiting
times over the planning horizon, independently of their due
dates, because they have the same remaining process time
RemP Tl . However, the proposed projection module allocates
steps expected cycle times taking into account lots priorities
i.e. due dates. Indeed, there are multiple priority levels of
production lots. Production priorities can be divided into two
levels according to the urgency of delivery: hot and standard.
So, to respect these priorities, the projection module shrinks
steps waiting times in order to satisfy the hot lot’s due date.
However, for a standard lot, it extends steps waiting times Fig. 6: Simple instance: Production schedule at infinite capac-
respecting the lot due date. ity.
To further explain the concept of WIP projection, a simple
random instance is tested. The considered WIP consists of 10
lots of 25 wafers each, following different routes, and having that have same qualifications and share same recipes. This
different due dates. Table IV presents, for each lot, the number approach enables to decompose the problem into small sub-
of remaining steps, RemP Tl , RemRef CTl , RemExpCTl problems. It is a linear program used to optimize workload
and CT Coef fl . balancing of toolsets, belonging to the same balancing group,
Figure 6 illustrates projection results of the 10 lots during over a selected time bucket. The formulation of the linear
the first period of the planning horizon. For some lots, a program, for each balancing group and over each period, is
sequence of steps is repeated twice (lots 1,4,5,7,8,9) i.e. lots as follows:
visit the same toolset twice which illustrates the re-entrant Notations
flows. Figure 6 shows start and end dates, waiting time and
processing time for each remaining process step during the Indices:
considered period. Some steps (step 4.5 and step 10.4) start B Number of balancing groups
in the first period and finish in the subsequent periods of the b = 1..B Balancing group index
planning horizon. This figure demonstrates that the projection Rb Number of recipes related to the balancing
engine allows the extension of steps waiting times for lots group b
having a far due date which is the case of lots 1 and 6 and r = 1..Rb Recipe index
it shrinks steps cycle times in case of close due date for lots Ib Number of toolsets of the balancing group
2, 4 and 8. Lots 2, 4 and 8 are not delivered on time. Their Ir Number of toolsets qualified for recipe r,
due dates are not reachable so their fab-out dates are equal to Ir ⊆ Ib
the sum of the current date (t = 0) and the remaining process i = 1..Ib Toolset index
time RemP Tl .

B. Workload accumulation and capacity analysis module

After WIP projection, the loading of toolsets, over each
considered period Li,t , is computed based on the assumption
of infinite capacities.
To optimize the computation time, toolsets are distributed
in balancing groups. A balancing group is a set of toolsets
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 9

Parameters: For the example cited above, the remaining steps of

10 lots are considered to be processed by 6 toolsets
xsl ,l,t Decision variables values, results of WIP pro- {M 1, M 2, M 3, M 4, M 5, M 6}. These toolsets are classified
jection module in period t into 4 balancing-groups {M 1, M 6}, {M 2, M 4}, {M 3} and
vsl ,l,r =1 if recipe r corresponds to step sl of lot l, {M 5}. Figure 7 illustrates the saturation percentage of toolsets
0 otherwise i.e. the ratio of the loading to the available capacity during
asl ,l,i Quantity of wafers of lot l in step sl processed L
the first period of the planning horizon ( Ci,1 , i = 1..6) while
i,1
by the toolset i processing the remaining steps ordered in increasing order of
pr,i Processing time of recipe r on toolset i the start date.
Ql Quantity of wafers of lot l In this example, the capacity of all the considered toolsets
(Ci,1 , i = 1..6) is equal to 24 hours/day. Figure 7 shows
Decision variables:
that there are two over-saturated toolsets (M 2 and M 6) which
Li,t Loading of toolset i over period t workloads exceed saturation threshold.
Wr,i Quantity of wafers produced by toolset i
qualified for recipe r
Lmax Workload of the most loaded toolset in the
balancing group
Lmin Workload of the least loaded toolset in the
balancing group
Lmaxr Loading, for a given recipe r, of the most
loaded toolset among those on which r is
qualified
Lminr Loading, for a given recipe r, of the least
loaded toolset among those on which r is
qualified

Using the above parameters, and decision variables, the linear

program formulation can be represented as follows:

 Minimize
P
α · Lmax − β · Lmin + γ · r Lmaxr Fig. 7: Workload accumulation at infinite capacity for the first

 P P I
−δ · r Lminr + δ · ( i b Li,t − Lmin) period of the planning horizon.


with α = Ib2 , β = Ib , γ = 1, δ = 1/Ib


C. Workload/Capacity Balancing Module

s.t.
X As a result of the workload accumulation module, loading
Li,t = pr,i × Wr,i i = 1, . . . , Ib (22)
of some toolsets may exceed their maximal capacities i.e.
r
Ir
constraints (13) are not satisfied. In this case, the toolset is
X
Wr,i =
XX
xsl ,l,t × vsl ,l,r × asl ,l,i unable to process all its affected steps during the considered
i=1 l sl
period so its loading should be balanced over subsequent
periods. The principle of this module is to postpone additional
r = 1, . . . , Rb (23)
lots in order to bring back workload of over-saturated toolsets
below their maximal saturation and to smooth the activity over
Li,t ≥ Lminr r = 1, . . . , Rb , i = 1, . . . , Ir (24) the planning horizon. The algorithm for workload/capacity
Li,t ≤ Lmaxr r = 1, . . . , Rb , i = 1, . . . , Ir (25) balancing module is as follows:
Li,t ≥ Lmin i = 1, . . . , Ib (26) 1) Sort toolsets in decreasing order of saturation.
Li,t ≤ Lmax i = 1, . . . , Ib (27) 2) Select lots executed on over-saturated toolsets.
3) Sort selected lots in increasing order of a computed rank-
The linear program seeks to : ing coefficient (rankingCoef fl ). The rankingCoef fl
• Minimize the workload of the most loaded toolset in the illustrates the priority of the lot in terms of its position
balancing group Lmax. in the process sequence of the considered toolset and the
• Maximize the workload of the least loaded toolset in the urgency of delivery. The position of a lot in the process
balancing group Lmin. PIb sequence of a toolset is determined by the processing
• Minimize the total workload of toolsets i Li and date of its last remaining step treated by the considered
maximize the
P total workload of the least loaded toolset toolset denoted sSl ,l,t .
per recipe r Lminr , with the same degree of priority. The urgency of delivery is defined by the lot cy-
• Minimize the total workload of the most loaded toolsets
P cle time coefficient (CT Coef fl ). To compute the
per recipe r Lmaxr . rankingCoef fl , the lot position in the process se-
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 10

quence is normalized by the period length Pt . Hence,

the rankingCoef fl is equal to :
1 sS ,l,t
rankingCoef fl = + l (28)
CT Coef fl Pt
4) For the first selected lot in the sorted list, shift the last
step executed in the considered over-saturated toolset
and its successors to the next period.
5) Remove the processing time of shifted steps s0l from
the loading of its qualified processing toolsets while
considering the quantity of wafers as0l ,l0 ,i processed
by each toolset. The new value of the loading of the
considered toolsets L0i,t is, then, equal to :
XX
L0i,t = Li,t − (as0l ,l0 ,i × ps0l ,l0 ,i × xl0 ,s0l ,t ) (29)
l0 s0l

6) Repeat steps 2, 3, 4 and 5 for all toolsets until the Fig. 8: Workload accumulation at finite capacity.
saturation criterion is satisfied for all toolsets over the
TABLE VI: WIP parameters in the beginning of the second
period t.
period
Hence, this module modifies steps projection at period t as
well as the WIP for the beginning of period t + 1. Lot l Weight Number RemP Tl Rem- Rem- CT-
wl of re- in Ref CTl ExpCTl Coef fl
For instance, to balance the capacity and the workload of the maining days in days in days
over-saturated toolsets M 2 and M 6 in the considered example, steps Sl
the balancing module selects M 2 as the most over-saturated Lot 1 0.33 6 1.1 1.6 4 2.5
L Lot 3 0.5 2 0.25 0.41 0.5 1.22
toolset ( C2,1
2,1
= 109.3%). Then, it selects lots 2, 4, 5, 7, 8 and Lot 4 0.5 3 0.58 0.76 0.7 0.92
10 processed by this resource (Figure 7). These lots are sorted Lot 5 0.5 4 0.6 0.83 0.5 0.6
in increasing order of rankingCoef fl as it is mentioned in Lot 6 0.33 4 0.75 1.02 4 3.92
Lot 7 0.5 7 0.76 0.91 0.5 0.55
Table V. Lot 9 0.5 4 0.8 1.05 0.5 0.47
Lot 10 0.5 2 0.3 0.41 0.5 1.22
TABLE V: Order of lots processed on M 2 according to
rankingCoef fl
Lot l CTCoeffl Step sl sSl ,l,t RankingCoeffl Clearly, the shorter the length of the period, the more accurate
Lot 5 1.07 Step 5.3 0.68 1.25 the results of the approach. The final obtained schedule for this
Lot 7 1.43 Step 7.2 0.265 1.43 instance is illustrated in Figure 9. For this instance, the TWT
Lot 10 0.79 Step 10.2 0.23 2.04 is equal to 1.46 days and we have five delayed lots.
Lot 4 0.65 Step 4.2 0.2 2.34
Lot 8 0.48 Step 8.1 0 3.08
Lot 2 0.45 Step 2.1 0 3.22

In order to decrease the loading of the toolset M 2, steps 5.3

and 7.2 and its successors are shifted to the next period of the
planning horizon. Hence, the loading of M 2 becomes less than
L
its maximum capacity: C6,1 6,1
= 96.4%. M 4 is also qualified for
step 5.3, so its loading decreases by 5.06%. Step 5.4 projected
in the first period is also postponed as it is the successor of
the shifted step 5.3. Thus, the loading of M 1 processing step
5.4 becomes equal to 58.83%. Shifting the successors of step
7.2 (steps 7.3, 7.4 and 7.5) leads to decreasing the loading of
toolsets M 1, M 4 and M 5. The same algorithm is applied to
the toolset M 6 by shifting step 9.1 and its successor step 9.2.
So, its loading decreases to 72%. Fig. 9: The obtained schedule using heuristic approach.
The toolsets workload obtained after steps shifting is il-
lustrated in Figure 8. Table VI presents the WIP and the
computed parameters (RemP Tl , RemObjCTl , RemExpCTl V. R ESULTS AND DISCUSSION
and CT Coef fl ) in the beginning of the next period. The proposed algorithm is coded in Java and it is tested on
The proposed approach is tested over a five-day planning a 4 GigaOctet RAM and 2.7 GigaHertz processor computer.
horizon. Indeed, as mix variations were present in industrial We conducted two types of experiments to evaluate the perfor-
dataset used for this study, it was decided to focus on a very mance of the proposed approach. The first type corresponds
short planning horizon to evaluate the proposed approach. to a comparison between the exact method and the heuristic
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 11

using a set of randomly generated instances. In the second type

of experiment, we compare the projected schedule obtained by
the proposed approach using real data with what is really going
on in the wafer fab following this schedule.

A. Evaluation of the proposed heuristic algorithm in compar-

ison with optimal solution
For this evaluation, random instances were generated and
solved using the MIP and the proposed heuristic algorithm.
The parameter, number of lots (L), assumes only five levels
(L=10, 15, 20, 50 and L=100). The parameters generated
for the proposed instances are presented in Table VII. So,
three random problem instances for each fixed parameter
combination are obtained, giving a total of 270 test problems.
Each of the 270 problem instances generated has been solved
using the ILOG CPLEX solver and the proposed heuristic
algorithm. Fig. 10: Comparaison between the optimal and the approxi-
mate solution.
TABLE VII: Test data parameters
Problem Parameter Values used Total
values
size equal to 10000 (L=100, max Sl =10, I=10) which
Number of lots (L) 10, 15, 20, 50, 100 5 has an absolute deviation equal to 79 days and a relative
Maximum number of remain- 10, 20, 30, 40, 50, 100 6 deviation equal to 0.36. This instance has an optimal
ing steps of lot l (max Sl )
Number of toolsets (I) 5, 10, 20 3
solution TWT equal to 218 days. The important value
Number of time buckets (T ) 24 1 of the absolute deviation is thus not significant because
Weight per lot wl uniform (0,1) 1 of high values of TWT.
Lots release dates rl 0 1
Lots due dates dl uniform(1,30) 1
• The third zone (corresponding to absolute deviation val-
Lots quantity of wafers Ql 25 1 ues ∈ [0..30] days and relative deviation values >1): 14
Steps unit process times psl ,l,i 0.0001× uniform(5,50) 1 instances (' 5% of the total of tested instances) are
Total parameter combina- 90
tions
located in this zone. We can cite the example of the
Number of problem in- 3 instance with a size equal to 15000 (L=50, max Sl =30,
stances I=10), a low value of absolute deviation equal to 2.23
Total problems 270
days and a high value of relative deviation equal to 4.74.
For this instance, both of the optimal and the approximate
The results on TWT obtained for each instance using MIP solutions present a low value of TWT. Hence, in this
model and using the proposed iterative algorithm are recorded. zone, the importance of the relative deviation has no
Based on these results, the heuristic solution matched exactly significance.
with the optimal solution 53 times. • The fourth zone (corresponding to absolute deviation
Furthermore, for each instance with a size L × max Sl × I, values > 30 days and relative deviation values >1): No
we compute: instance is located in this zone characterized by high
• The absolute deviation= |TWT value from a heuristic values of absolute and relative deviations.
algorithm - optimal TWT value|
absolute deviation value
• The relative deviation= optimal TWT value
Figure 10 shows the relative deviation over 270 instances B. Experimental tests on real fab data
plotted against the absolute deviation. The aim of this section is to evaluate the ability of the
In this figure, we can define four zones or classes according proposed approach to tackle real world problems. The test of
to the size of the instance: the real instance (L=2000, max Sl =680, I=300, T =24), un-
• The first zone (corresponding to absolute deviation values solved in reasonable execution time using the MIP approach in
∈ [0..30] days and relative deviation values ≤ 1): Around Section 3, is treated. The execution time of this instance with
92% of the tested instances are situated in this zone. the proposed algorithm is around 30 seconds. In the calculated
Hence, for most of the instances, the heuristic solution production schedule, 80 % of projected lots are delivered on
is close to the optimal one. time. Furthermore, the saturation of toolsets is kept below
• The second zone (corresponding to absolute deviation the pre-defined saturation threshold while minimizing lots
values ∈]30..140] days and relative deviation values ≤ 1): lateness. Figure 11 illustrates the obtained weekly saturation
The 8 instances (' 3% of the total of tested instances) at infinite and finite capacity of a photo-lithography toolset
belonging to this category are instances of large size considered as a bottleneck. In semiconductor fabs, several
(≥ 10000). For example, we find the instance with a indicators are used to measure performance [52]. Jointly with
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 12

Fig. 12: Number of moves comparison actual versus forecast.

Fig. 11: Weekly saturation of a photo-lithography toolset at
infinite and finite capacity.
between the total number of completed steps processed by
two types of bottleneck usages (photolithography and etching).
managers of the fab, we identified three relevant indicators for For this indicator also, we observe a convergence between the
our study, as described below: planning and the real process for the first 6 periods with an
• Number of moves: This corresponds to the number of
average of the average relative deviations over these periods
completed steps on each period of the planning horizon, equal to 6.5% for the usage of photolithography and 12.3% for
which can be compared to the real number in the pro- the usage of etching. Therefore, the heuristic provides good
duction line. estimations of the tools loading close to the real workload
• Number of moves by usage: It is the number of processed
while respecting capacity constraints.
steps by set of toolsets belonging to the same area named
”usage” in each period of the planning horizon.
• Total Weighted Tardiness TWT: This indicator is used to
evaluate the waiting times of lots for processing.
In this section, we compare the cited indicators of performance
of the heuristic solution with the indicators determined in
the real production line. To ensure this experiment, six tests
have been performed on actual instances issued over four
months of production: September, October, November and (a) Photolithography usage
December 2015. We have made projections in six different
periods (week1, week2, week3, week4, week5 and week6) and
we have determined the three indicators for each projection.
For confidential reasons, we are not allowed to provide the
real values of the fab. This is why, we compute the relative
deviation between the predicted value and the real one for each
period of the planning horizon:
Relative deviation = |Estimatedreal
value−real value|
value
1) Analysis based on the performance measure: number (b) Etching usage
of moves: Figure 12 shows relative deviations of number of
Fig. 13: Total number of moves processed by photo-
moves over 15 time buckets (weeks) of the planning horizon. It
lithography and etching usages comparison actual versus fore-
illustrates that in the first 6 periods for the different instances,
cast.
the relative deviation between the real number of processing
steps and the calculated value is low. The average of the
3) Analysis based on the performance measure: TWT:
average relative deviations over six periods for the different
To compare between the real total weighted tardiness and
tests is equal to 12.7%, reflecting a small difference between
the obtained value of this indicator using the iterative
the estimated number of moves and the achieved one. Further
algorithm for the six tests, absolute and relative deviations
being away from the beginning of the projection, the relative
are computed and reported in Table VIII. From Table VIII,
deviation between the obtained solution and the real number
we note that the estimated value of TWT is close to the
of moves increases which is explained by the variability of
real tardiness while respecting lots due dates. Indeed, the
the process. Hence, there is a convergence between what is
average of relative deviations over six instances is equal to 4%.
estimated and what is achieved in terms of periodic activity
for a short-term planning horizon.
2) Analysis based on the performance measure: number
of moves by usage: To evaluate how the heuristic solution VI. C ONCLUSIONS AND PERSPECTIVES
anticipates the fab loading, we compute the absolute deviation This paper has examined the problem of WIP projection
of the number of moves by set of toolsets sharing the same at finite capacity to minimize the TWT, and has proven
qualifications named ”usage” over the six instances for each empirically the computational complexity in obtaining optimal
period of the planning horizon. Figure 13 shows the difference solution and suggested a simple, fast and efficient heuristic.
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 13

TABLE VIII: TWT comparison actual versus forecast [3] M. Rowshannahad and S. Dauzère-Pérès, “Qualification management
with batch size constraint,” in Proceedings of the 2013 Winter Simulation
Instance Absolute deviation Relative deviation
Conference, (Washington, United States), pp. 3707–3718, 2013.
(days) (%) [4] R. Uzsoy, C.-Y. Lee, and L. Martin-Vega, “A review of production
Instance 1 228.255 6 planning and scheduling models in the semiconductor industry part II:
Instance 2 98.305 2.62 shop-floor control,” IIE Transactions, vol. 26, no. 5, pp. 44–55, 1994.
Instance 3 108.86 3.39 [5] J. N. D. Gupta, R. Ruiz, J. W. Fowler, and S. J. Mason, “Operational
Instance 4 47.77 1.83 planning and control of semiconductor wafer fabrication,” Production
Instance 5 50.13 2.08 Planning and Control, vol. 17, no. 7, pp. 639–647, 2006.
Instance 6 146.23 7.92 [6] J. Orlicky, Material requirements planning. McGraw-Hill Professional,
1975.
[7] P. J. Rondeau and L. A. Litteral, “Evolution of manufacturing planning
and control systems: from reorder point to enterprise resource planning,”
The motivation for this research is to compute a feasible Production and Inventory Management Journal, vol. 42, no. 2, p. 17,
production plan to drive the execution of wafer fabs. This 2001.
problem is of considerable practical value because the heuris- [8] D. Y. Golhar and C. L. Stamm, “The just-in-time philosophy: a literature
review,” International Journal of Production Research, vol. 29, no. 4,
tic, proposed in this paper, can be used in planning of a large pp. 657–676, 1991.
number of production lots while respecting lots due dates and [9] E. M. Goldratt, Theory of constraints: What is this thing called Theory
capacity and capability constraints. of Constraints and how should it be implemented. North River Press,
1990.
The computational tests, made on real production instances, [10] T. Rossi and M. Pero, “A simulation-based finite capacity mrp proce-
showed that acceptable solutions are obtained in reasonable dure not depending on lead time estimation,” International Journal of
execution time. Indeed, the TWT could be minimized and the Operational Research, vol. 11, no. 3, pp. 237–261, 2011.
[11] H. Jodlbauer and S. Reitner, “Material and capacity requirements
average tool utilization rate could be balanced significantly planning with dynamic lead times,” International Journal of Production
by using the developed system. Besides, the computation for Research, vol. 50, no. 16, pp. 4477–4492, 2012.
real instances is achieved in around 30 seconds which is [12] L. Sun, S. S. Heragu, L. Chen, and M. L. Spearman, “Comparing
efficient for planning problems with a horizon of weeks up dynamic risk-based scheduling methods with mrp via simulation,”
International Journal of Production Research, vol. 50, no. 4, pp. 921–
to months in real situations. Hence, this decision support tool 937, 2012.
outperforms simulation and analytic models for establishing a [13] T. Aouam and R. Uzsoy, “Zero-order production planning models with
feasible production schedule rapidly. Finally, it is observed (as stochastic demand and workload-dependent lead times,” International
Journal of Production Research, vol. 53, no. 6, pp. 1661–1679, 2015.
well as statistically verified) from the results of the comparison [14] M. E. Levitt and J. A. Abraham, “Just-In-Time methods for semiconduc-
of the different criteria (total number of moves, number of tor manufacturing,” in Proceedings of the 1990 Advanced Semiconductor
moves by usage and TWT) an obvious convergence between Manufacturing Conference, (Danvers, MA), pp. 3–9, 1990.
what is predicted using the developed approach and what is [15] J. G. Carlson and A. C. Yao, “Mixed model assembly simulation,” Inter-
national Journal of Production Economics, vol. 26, no. 1-3, pp. 161–167,
achieved in the real process over a short-term planning hori- 1992.
zon. These results show that the implementation of the finite [16] C. Rippenhagen and S. Krishnaswamy, “Implementing the theory of
capacity planning system in real fabs seems very interesting to constraints philosophy in highly reentrant systems,” in Proceedings
of the 1998 Winter Simulation Conference, (Piscataway, New Jersey),
minimize lots lateness and to establish a feasible production pp. 993–996, 1998.
schedule. There are a number of interesting extensions of [17] M.-G. Resende, “A program for simulation of semiconductor wafer
the problems that can be pursued. The first important issue fabrication,” tech. rep., University of California, Berkeley, Operations
Research Center, 1985.
would be to perform a more thorough multi-criteria analysis [18] B. Tullis, V. Mehrotra, and D. Zuanich, “Successful modeling of
while shifting lots to balance toolsets loadings. Besides, it is a semiconductor R & D facility,” in Proceedings of the 1990
necessary to implement the developed finite capacity planning IEEE/SEMI International Semiconductor Manufacturing Science Sym-
posium, (Burlingame, California, United States), pp. 26–32, 1990.
system in the production plant to guarantee the performance of
[19] M. Thompson, “Using simulation-based finite capacity planning and
the solution. Considering other specificities of semiconductor scheduling software to improve cycle time in front end operations,” in
industry such as batching or sequence dependent setup times Proceedings of 1995 IEEE/SEMI Advanced Semiconductor Manufactur-
may be interesting to enhance the accuracy of the developed ing Conference Workshop, pp. 131–135, 1995.
[20] J. Fowler, H. Brown, S.and Gold, and A. Schoemig, “Measurable im-
system. provements in cycle-time-constrained capacity,” in Proceedings of IEEE
International Symposium On Semiconductor Manufacturing Conference,
(San Francisco, United States), pp. 21–24, 1997.
ACKNOWLEDGMENT [21] A. J. Weintraub, A. Zozom Jr, T. J. Hodgson, and D. Cormier, “A
simulation-based finite capacity scheduling system,” in Proceedings of
This work is supported by the ENIAC European Project the 29th conference on Winter simulation, pp. 838–844, IEEE Computer
INTEGRATE. The authors also gratefully acknowledge STMi- Society, 1997.
croelectronics for their support on the knowledge of the [22] N. Grewal, A. Bruska, T. Wulf, and J. Robinson, “Integrating targeted
semiconductor industry. cycle-time reduction into the capital planning process,” in Proceedings
of the 1998 Winter Simulation Conference– WSC 1998, (Washington,
United States), pp. 1005–1010, 1998.
R EFERENCES [23] K. Potti and S. J. Mason, “Using simulation to improve semiconductor
manufacturing,” Semiconductor International, vol. 20, no. 8, pp. 289–
[1] L. Mönch, J. Fowler, and S. Mason, Production planning and control for 292, 1997.
semiconductor wafer fabrication facilities. Springer New York, 2013. [24] A. A. B. Pritsker and K. Snyder, “Production scheduling using FAC-
[2] R. Uzsoy, C.-Y. Lee, and L. Martin-Vega, “A review of production TOR,” in The Planning and Scheduling of Production Systems, pp. 337–
planning and scheduling models in the semiconductor industry part I: 358, Springer US, 1997.
system characteristics, performance evaluation and production planning,” [25] J. P. Ignizio and H. Garrido, “Fab simulation and variability,” Future
IIE Transactions, vol. 24, no. 4, pp. 47–60, 1992. Fab International, vol. 41, pp. 41–45, 2012.
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING 14

[26] J. G. Shanthikumar, S. Ding, and M. T. Zhang, “Queueing theory for [49] M. Garey and D. Johnson, Computers and Intractability: A Guide to the
semiconductor manufacturing systems: A survey and open problems,” Theory of NPCompleteness. New York, NY, USA: W. H. Freeman &
IEEE Transactions on Automation Science and Engineering, vol. 4, Co., 1979.
no. 4, pp. 513–522, 2007. [50] T. Winkler, P. Barthel, and R. Sprenger, “Modeling of complex decision
[27] S. Bermon and S. Hood, “Capacity optimization planning system making using forward simulation,” in Proceedings of the 2016 Winter
(CAPS),” Interfaces, vol. 29, no. 5, pp. 31–50, 1999. Simulation Conference, pp. 2982–2991, IEEE Press, 2016.
[28] J. Swaminathan, “Tool capacity planning for semiconductor fabrication [51] D. Martin, “Key factors in designing a manufacturing line to maxi-
facilities under demand uncertainty,” European Journal of Operational mize tool utilization and minimize turnaround time,” in Semiconductor
Research, vol. 120, no. 3, pp. 545–558, 2000. Manufacturing Science Symposium, 1993. ISMSS 1993., IEEE/SEMI
[29] F. Barahona, S. Bermon, O. Günlük, and S. Hood, “Robust capacity International, pp. 48–53, 1993.
planning in semiconductor manufacturing,” Naval Research Logistics [52] J. Montoya-Torres, “Manufacturing performance evaluation in wafer
(NRL), vol. 52, no. 5, pp. 459–468, 2005. semiconductor factories,” International Journal of Productivity and
[30] B. Çatay, c. Erengüç, and A. Vakharia, “Tool capacity planning in semi- Performance Management, vol. 55, no. 3/4, pp. 300–310, 2006.
conductor manufacturing,” Computers & Operations Research, vol. 30,
no. 9, pp. 1349 – 1366, 2003.
[31] N. Geng and Z. Jiang, “A review on strategic capacity planning for
the semiconductor manufacturing industry,” International Journal of
Production Research, vol. 47, no. 13, pp. 3639–3655, 2009.
[32] Y.-F. Hung and R. C. Leachman, “A production planning methodology
for semiconductor manufacturing based on iterative simulation and Emna Mhiri is PhD student in G-SCOP Laboratory (www.g-scop.grenoble-
linear programming calculations,” IEEE Transactions on Semiconductor inp.fr). She received industrial engineering degree from engineering school of
Manufacturing, vol. 9, no. 2, pp. 257–269, 1996. Tunisia, in 2012 and completed her masters degree in industrial engineering
[33] R. C. Leachman, “Modeling techniques for automated production from the University of Grenoble, France in 2013. Her research interests
planning in the semiconductor industry,” in Optimisation in Industry: include capacity planning in semiconductor industry. Her email address is
Mathematical Programming and Modeling (T. Ciriani and R. Leachman, [email protected].
eds.), (Wiley, New York), pp. 1–30, 1993.
[34] C. Habla, L. Mönch, and R. Drissel, “A finite capacity production plan-
ning approach for semiconductor manufacturing,” in Proceedings of the
3rd Annual IEEE Conference on Automation Science and Engineering,
(Scottsdale, United States), pp. 82–87, 2007.
[35] S. Bermon, G. Feigin, and S. Hood, “Capacity analysis of complex
manufacturing facilities,” in Decision and Control, 1995., Proceedings Fabien Mangione is assistant professor in G-SCOP Laboratory. He received
of the 34th IEEE Conference on, vol. 2, pp. 1935–1940, 1995. the Ph.D. degree in industrial engineering from the University of Grenoble,
[36] Y. Hsiung, M.-C. Wu, and H.-M. Hsu, “Tool planning in multiple France and works on production planning, particularly on industrial case
product-mix under cycle time constraints for wafer foundries using ge- studies. His research also deals with lot sizing problems on supply chain
netic algorithm,” Journal of the Chinese Institute of Industrial Engineers, modeling. His email address is [email protected].
vol. 23, no. 2, pp. 174–183, 2006.
[37] J. Bard, Y. Deng, R. Chacon, and J. Stuber, “Midterm planning to
minimize deviations from daily target outputs in semiconductor manu-
facturing,” IEEE Transactions on Semiconductor Manufacturing, vol. 23,
no. 3, pp. 456–467, 2010.
[38] J. C. Chen, C. W. Chen, C. J. Lin, and H. Rau, “Capacity planning with
capability for multiple semiconductor manufacturing fabs,” Computers Mireille Jacomino is professor in G-SCOP Laboratory. She is carrying out
and Industrial Engineering, vol. 48, no. 4, pp. 709–732, 2005. her research in combinatorial optimization of systems. Her application fields
[39] J. C. Chen, Y.-C. Fan, and C.-W. Chen, “Capacity requirements planning are manufacturing and energy systems, used particularly in execution context
for twin fabs of wafer fabrication,” International Journal of Production of systems. Her works aim at computing control decisions that guaranty
Research, vol. 47, no. 16, pp. 4473–4496, 2009. performance during execution. Robust control and robust decision are the
[40] J. C. Chen, L.-H. Su, C.-J. Sun, and M.-F. Hsu, “Infinite capacity key research interests of professor Jacomino to address the uncertainties. Her
planning for IC packaging plants,” International Journal of Production email address is [email protected].
Research, vol. 48, no. 19, pp. 5729–5748, 2010.
[41] H. E. Fargher, M. A. Kilgore, P. J. Kline, and R. A. Smith, “A planner
and scheduler for semiconductor manufacturing,” IEEE Transactions on
Semiconductor Manufacturing, vol. 7, no. 2, pp. 117–126, 1994.
[42] K. Horiguchi, N. Raghavan, R. Uzsoy, and S. Venkateswaran, “Finite-
capacity production planning algorithms for a semiconductor wafer fab-
rication facility,” International Journal of Production Research, vol. 39, Philippe Vialletelle is principal staff engineer at the Industrial Engineering
no. 5, pp. 825–842, 2001. department of STMicroelectronics Crolles300. He is in charge of the definition
[43] K. Habenicht and L. Mönch, “A finite-capacity beam-search-algorithm and follow-up of collaborative projects in Manufacturing Sciences. His fields
for production scheduling in semiconductor manufacturing,” in Simula- of interest cover production planning and management techniques, process
tion Conference, 2002. Proceedings of the Winter, vol. 2, pp. 1406–1413, control and Big data. His email address is [email protected].
IEEE, 2002.
[44] T. J. Chua, M. W. Liu, F. Y. Wang, W. J. Yan, and T. X. Cai,
“An intelligent multi-constraint finite capacity-based lot release sys-
tem for semiconductor backend assembly environment,” Robotics and
Computer-Integrated Manufacturing, vol. 23, no. 3, pp. 326–338, 2007.
[45] J. D. Little, “A proof for the queuing formula: L= λ w,” Operations
research, vol. 9, no. 3, pp. 383–387, 1961. Guillaume Lepelletier is senior project leader at STMicroelectronics. He
[46] J. S. Kim and R. C. Leachman, “Decomposition method application received Engineering degree in Operations and Production Management from
to a large scale linear programming wip projection model,” European INSA de Lyon, France and Master of Science in ”Advanced Modeling
Journal of Operational Research, vol. 74, no. 1, pp. 152–160, 1994. Systems” from Brunel University, Uxbridge, UK in 1997. He has 15 years
[47] Y. Lee, S. Kim, S. Yea, and B. Kim, “Production planning in semi- of professional experience in Industrial Engineering in the semiconductor
conductor wafer fab considering variable cycle times,” Computers & industry. He is working on capacity planning, cycle time management, discrete
Industrial Engineering, vol. 33, no. 3-4, pp. 713–716, 1997. event simulation, industrial reporting and equipment performance tracking.
[48] N. Govind and D. Fronckowiak, “Setting performance targets in a His email address is [email protected].
300mm wafer fabrication facility,” in Proceedings of Advanced Semi-
conductor Manufacturing Conference and Workshop, pp. 75–79, 2003.

View publication stats