Automated Design of Analog Circuits using

Machine Learning Techniques

Devi S Gourav Tilwankar Rajesh Zele
[email protected] [email protected] [email protected]

Department of Electrical Engineering, IIT Bombay, Mumbai, India

2021 25th International Symposium on VLSI Design and Test (VDAT) | 978-1-6654-1992-5/21/$31.00 ©2021 IEEE | DOI: 10.1109/VDAT53777.2021.9601131

Abstract—This work presents methodology for an automated a reasonable solution requiring large SPICE simulations. The
design of analog circuits using global Artificial Neural Net- advantage of the GA-based optimization technique is that the
work (ANN) for an optimised dataset. The optimised dataset population used for evaluations are independent of each other
is generated using simulation based gm /Id technique, which
reduces the dataset size and also the time required for data enabling parallel computations. Some of these above-said
collection and analysis. Automated analog circuit design is algorithms work along with local minimum search techniques
implemented using ANN based supervised learning technique to reach the optimum solution.
for a common source amplifier and a two stage single-ended In this paper, the different techniques of automated design
opamp. The results obtained are compared with unsupervised of analog circuits using Machine Learning (ML) methods are
(Reinforcement Learning algorithm) and supervised learning
technique (Genetic Algorithm based local ANN). The comparison analyzed. We propose a new gm /Id method of data collection
results shows that the proposed gm /Id technique based ANN which reduces the overall time for analysis. The previous
model gives a better accuracy in terms of score and mean square work done in [1] uses ANN which can determine a functional
error (MSE). mapping with a certain precision using a dataset. The time
Index Terms—Machine Learning, Reinforcement learning required for the evaluation of the model and to attain the
(RL), Artificial Neural Networks (ANN), Genetic Algorithm
(GA), Python design specifications is much less than the equation-based or
the simulation-based methods. The ANN model provides a
I. I NTRODUCTION global optimum solution, requiring a huge dataset resulting in
a large number of SPICE simulations. The paper is organized
Analog circuits play an important role in processing real as follows: Section II describes the unsupervised learning
world signals and interfacing them with digital signal process- technique using reinforcement learning. Forward propagation
ing units. The design of analog circuits is challenging as the and backward propagation techniques using supervised learn-
parameters of the analog circuits are interrelated and difficult ing method are given in Section III. Proposed model using
to tune to achieve the desired performance. Optimizing one global ANN with optimized dataset is detailed in Section IV
parameter can result in the degradation of another. Designers followed by conclusions in Section V.
are always trying to achieve an optimum trade-off between
the performance metrics. Analog circuits have non-linearities
associated with their components. Hence, the final optimum
design of a circuit takes a large number of iterations for the
fine-tuning of the circuit parameters. The previous works in
the automated design of analog circuits starts with a particular
topology and tries to optimize the parameters such as transis-
tor width and bias current based on some cost function, which
further depends on the performance metrics. The two main
optimization approaches are equation-based and simulation-
based design. Equation based approach utilizes analytical
Fig. 1. L2DC Method [2]
design equations to optimize the performance metrics. These
equations have to go through a large design space to reach
an optimum solution. The accuracy of these solutions will be II. UNSUPERVISED LEARNING TECHNIQUE
limited as the equations considered for the optimization will The automated design of analog circuits using ML tech-
not account for the device non-linearities. The simulation- niques is introduced in [2]. It explains the method L2DC
based approach works in conjunction with the SPICE simu- (Learning to Design Circuits), which uses the RL algorithm
lations, to reach the global optimum solution. However, this for the design of circuit parameters as shown in Figure 1. In
process requires high computational cost due to large number this work, the author have demonstrated the simulation results
of SPICE runs. There are various other techniques that make for trans-impedance amplifiers.
use of nonlinear data space exploration like GA, simulated The technique starts to train the RL agents without any
annealing, and particle swarm intelligence. The simulated specific rules or constraints. In each step, the agent obtains
annealing method and the swarm-based method sometimes observation from the environment, producing an action for the
gets stuck at a local optimum solution rather than finding a environment (values for design parameters), and then deter-
global optimum solution requiring a longer time to converge. mines the reward as a function of gain, power, bandwidth,
In the case of GA, a large population is required to achieve area, etc. The observations from the environment include

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.
 Fig. 2. Flowchart of Machine Learning Model

DC operating points, AC magnitude, and phase response iteration. This output is then fed back to one of the hidden
which are obtained from the SPICE simulator. The reward layer which then works on minimizing the error between
is given in terms of the figure of merit (FoM). The optimum two outputs. This is done by adjustment of weights and bias
circuit parameters for particular design specifications can be values of hidden layers. Finally, the output specifications are
achieved by maximizing the reward. As shown in Figure 1, achieved after a stated number of iterations/loops. As an
the method starts with certain hard design constraints and example, a common source amplifier with resistive load as
optimizing targets. We will have a x, y where x and y are shown in Figure 3 was analyzed. The parameter values taken
vectors, x defines the parameters of the components and y into consideration are Rd , W0 , L0 , W1 , L1 and output values
denote the design constraints. In the RL algorithm the agent achieved as specification are gain (dB) and power (mW).
is trying to find f:x → y by maximizing the reward which The circuit was designed and simulated in 65nm CMOS
is defined as the ratio qc (x) = fc (x)/yc , if performance technology in Cadence Virtuoso environment. A few sample
metric larger than specification, otherwise qc (x) = yc /fc (x). points were generated and the dataset obtained was then
A Deep Deterministic Policy Gradient (DDPG) agent which interpolated as well as extrapolated to get more than 2500
uses an encoder-decoder network is also employed for the sample points. The technique applied in this circuit is ANN
conversion of observations to actions. The steps in the DDPG with multiple activation functions used in series as a means
can be broken into four steps, namely experience replay, to achieve negligible loss value.
actor and critic network updates, target network updates, and
exploration. In each iteration, the four states, state, action,
reward, and next state are stored in the replay buffer. The
mini-batches out of it are sampled to update the reward. With
the help of the experience replay, the uncorrelated data can
be generated for running each iteration. The actor and value
network will compute the current value and find the MSE
from the actual value and attempting to minimize this MSE.
The critic network is working on the basis of the multi-layer
perceptron technique. Once the MSE is minimized, the target
network values will be reached and soft updating is done at
this stage. In RL for discrete action spaces, a study is done
by probabilistically picking an arbitrary action such as epsilon
greedy or Boltzmann exploration [7]. Although the amount of
dataset required is reduced compared to supervised learning Fig. 3. Common Source Amplifier
technique the time required for reaching at the optimum
solution based on bandwidth and gain at the expense of power In the above circuit, for a set of input parameters, value
remains same as the simulation tools are also involved in the of Id is taken as base value and gain is calculated in first
each iteration for calculating the reward. row of Table I. The parameters are then varied so as to
III. SUPERVISED LEARNING TECHNIQUE change the Id value and hence changing the gain value. The
comparison of manual calculation, SPICE output and machine
A. Forward Propagation Technique learning model output is given in Table I by varying the
The supervised learning techniques requires us to train values of Id . It can be seen that the values of gain of com-
the model on some data points that includes both input and mon source amplifier circuit predicted, are very close to the
output values. Figure 2 shows the algorithm based on forward manual calculation results as well as to the Cadence/SPICE
propagation technique implemented for creating Machine output. This model operates on dataset containing more than
Learning Model coded in Python Language. Initially the input 2500 values and gets trained in less than two minutes. This
layer takes circuit parameters as input, calculates the first layer technique is based on both equation-based and simulation-
output and after series of steps gives the final output of first based approaches, which make it difficult for application on

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.
large circuits. Also, as mentioned above, giving parameters as to select the best candidate. The training dataset for the ANN
inputs and taking specifications as outputs can be done with model is generated from the local neighbourhood using OA-
the help of SPICE softwares in nearly same time, hence this based LHS. Inside the ANN model, Local Minimum Search
method may be used for the purpose of illustration. (LMS) is carried out and the optimum solution is verified
using the SPICE simulations. A two-stage rail-to-rail Opamp
TABLE I and active-RC Chebyshev band-pass filter (CBPF) are used
O UTPUT C OMPARISON FOR G AIN VALUES IN dB FROM VARIOUS as examples. This method employing the Local-ANN using
SOURCES
the parallel simulations generates an optimal circuit solution
Gain Value four times faster than the Global-ANN technique. A genetic
Id Manual Cadence Machine Learning algorithm based optimization is also needed in order to reduce
value Calculation Output Model
100% 4.10 4.05 4.09 the range of dataset over which the Local-ANN need to be
200% 7.57 7.59 7.4 trained.
250% 10.0 10.2 10.07
300% 12 11.95 12.02

Fig. 4. Model MSE Plot as a function of Iterations Fig. 5. Algorithm for Local ANN [3]

n
1X IV. P ROPOSED MODEL USING GLOBAL ANN
M SE = (|actual − predicted|2 ) (1)
n n=1
In this section, we propose a new ML Model using global
Various combinations of activation functions, namely, Lin- ANN. It consists of the input layer, an output layer, and
ear, ReLu and Softmax were used and best results in terms of hidden layers. The number of input neurons in the input layer
MSE (can be calculated by Equation 1) obtained are shown depends on the input parameters of the ANN model. For
in Figure 4. As shown in the figure, MSE value decreases example, for the design of an amplifier, the input parameters
by increasing the number of iterations for both training and can be the performance metrics like DC gain, current (Idd ),
validation dataset. The MSE value at 0th iteration is near -1dB gain-bandwidth product (GBW), etc. The number of output
and decreases to -4dB after 100 iterations with the stopping neurons depends upon the number of design parameters that
criterion of iterations as 0.1% of initial MSE value. we need to estimate, for example, the transistor widths,
lengths, resistances, etc. Since there are multiple input and
B. Backward Propagation Technique - Local ANN using GA output parameters, we use a multi-layer perceptron (MLP)
based global optimization Technique ANN model. The number of hidden layers and the number
The supervised learning technique [3] combines the GA of neurons in each hidden layer in the architecture is a
and ANN techniques to achieve an automated analog circuit hyper-parameter that can be optimized through the validation
design flow. Instead of training the ANN on a very large process. The representative diagram for the ANN model is as
dataset, the paper proposes the training on a filtered dataset shown in Figure 6.
obtained as the output of GA. The algorithm is shown in Each layer of neurons is connected to other layer neurons
Figure 5. A comparison of the GA-ANN model with other through a fully connected network. The weights and bias
ML models namely, K-Nearest Neighbours (KNN), Decision represent the relation between each layer of data. These
Trees (DTs), Support Vector Machine (SVM), etc is per- parameters are determined by minimizing the objective func-
formed. The algorithm in [3] starts with the global and local tion which is the averaged error. The weights and biases
optimizations running alternatively until the performance met- are determined through the back propagation method. In
rics are reached or the maximum iteration limit is reached. the forward pass, the network will save all the intermediate
The initial population of the GA-based algorithm is generated derivatives. The optimum parameters for the ANN model are
using the orthogonal array (OA) based Latin Hypercube obtained by minimizing the loss function with respect to each
Sampling (LHS). Parallel SPICE simulations are performed weight and bias values using chain rule.

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.
 Fig. 6. ANN Network Model for Multi-Input Multi-Output System [4]

Figure 7 shows the flowchart of newly proposed ML imple-

mentation of the ANN algorithm. The input to the algorithm
will be the desired specifications and output will be the set of
design parameters. For the initial training of the ANN model
the dataset collection is done using two different methods,
W, L variation and Id /W variation. In the first method, the
width and the length of each transistor are varied between a
range of maximum and minimum in nonlinear step size to
get an independent dataset. This method gives a large dataset
requiring a filtering step to remove all unwanted data which
is similar prcedure to the previous works in [3]. For example,
the cases of non satisfying region of operation leading to a
random behaviour of the response can be ignored. The second
method proposed in this work generates the dataset based on
the Id /W values. These Id /W values need to be varied in a
small range only (as shown in Table II) as this range is chosen
based on the simulations. This has an advantage of working Fig. 7. Flowchart of ML Implementation of the ANN Algorithm
with a smaller dataset which eliminates the filtering step.
Once the dataset is obtained from the above two methods,
80% of data is used for training the ANN model and the rate, gain, unity gain frequency, phase margin, and power
remaining 20% is used for testing the accuracy of the trained from the test data are given as input to the trained ANN
model. To reduce the number of simulations for the initial model, and the output values namely Ibias , Vincm and Id /W
analysis, the length of all the transistors is taken as the same. or width and length are predicted. As the predicted data is
To train the ANN model, slew rate, gain, unity gain frequency, in the normalized form, to bring back to the original range
phase margin, and power is taken as the input parameters, and inverse transformations are applied to the predicted data. The
Ibias , Vincm and Id /W or width and length values are taken predicted values are then compared with the actual values
as output parameters. The first step in training the ANN model from the test data followed by the score and MSE calculation.
is data visualization and pre-processing of the data values. A two-stage single ended Opamp as shown in Figure 8, is
Some of the data values show a skewed pattern which can implemented in 65nm CMOS process. The transistor widths,
be simplified into a more evenly distributed dataset using the lengths, resistances, and capacitances are chosen as design
log and power transforms. If the ANN model is trained using parameters for optimization. The dataset for training the ANN
these data values directly, it will not converge to a solution model is generated using the gm /Id variation method and
set as the data values are in different ranges. Hence, we need W, L variation method. Considering the matching criteria
to normalize these data values before training of the ANN there will be a total of 13 independent parameters (W0 , W5 ,
model. The operations performed on the training data has to W7 , W1 , W3 , W6 , L0 , L1 , L3 , Rz , Cz , Vincm , Ibias ). For
be performed for the testing data as well. The MLP regressor example, the input transistors (M1 , M2 ) and (M3 , M4 ) are
model is used for the multi-input multi-output system. The fully matched pairs so their W, L values are the same. The
MLP regressor is implemented using three hidden layers with length of the transistors (M0 , M5 , M7 ) and (M3 , M4 , and M6 )
ReLu activation function, adaptive learning rate, and Adam are taken to be L0 and L3 respectively. In the W, L varying
solver. The MLP regressor fits the model by minimizing method all the above said 13 parameters are varied to obtain
the squared error objective function. The accuracy of the a dataset of the performance metrics. The design parameters
model is evaluated using the test data. The parameters slew are varied from a minimum value to a maximum value with

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.
 optimised data generated using the gm /Id technique performs
the simulation on a two stage single ended Opamp. The score
was obtained as 93.44% and an MSE of 0.055. The score
values for W, L method and proposed gm /Id method show
that the trained ANN model accurately predicts the data with
greater than 90% accuracy. Comparison between the proposed
global ANN using gm /Id method and W,L varying method
shows that the time required to generate the dataset using
cadence simulations is substantially less. Though the dataset
size is very small, the proposed method gives accurate results
as the parameters which are varied to generate the dataset are
simulation based.

TABLE III
C OMPARISON TABLE OF D IFFERENT ML T ECHNIQUES
Fig. 8. Two-Stage Single-Ended Opamp
Method Dataset Score(%)
Unsupervised [2] 40000 - 50000 -
Global ANN
a nonlinear step size. In the case of the gm /Id method - Supervised [3] 45583 30.2
the transistor sizes are determined from the current density Local ANN
(Id /W ) plots obtained from the Cadence simulations for - Supervised [3] 632 75.8
This work - W, L - Supervised 65534 90
different lengths. The overdrives of the transistors are chosen This work - gm /Id - Supervised 7361 93
such that they operate in a strong inversion region, then the
corresponding Id /W values are taken. For the generation of
the dataset to train the ANN model, the parameter varied
V. C ONCLUSION
in the gm /Id method is the current density (Id /W ). Since
the overdrives of the transistors M0 , M5 , M7 are the same This paper analyses two methods of automated analog
their Id /W values are changing in a similar manner. M1 , circuit design using machine learning techniques, namely
M2 and M3 , M4 , M6 combinations follow the same pattern. the forward propagation method and backward propagation
Ibias is kept as a variable to change the current through these method. In forward propagation we are able to predict the ex-
transistors. The operational amplifier tail current is decided pected performance metrics for the given design parameters,
as a scaled factor of Ibias . The current through the input while in the backward propagation method we are predicting
transistors is taken as half of the tail current and the output the design values for a given specifications. The backward
branch (M6 , M7 ) is taken as 10 times the current of input propagation method uses a novel data acquiring technique
transistors. Thus the total number of independent variables in using the gm /Id method which reduces the dataset size and
this case are 11 (Id /W0 , Id /Wn , Id /Wp , Ibias , Itail , Vincm , time for analysis significantly. The new technique proposed
Rz , Cz , L0 , L1 , L3 ). The range of Id /W values is given in in this paper shows that the global ANN model operates on
Table II. The other parameters are varied from a minimum to smaller dataset size efficiently. It trains the ANN model with
a maximum with a nonlinear step size. fewer hidden layers and the number of neurons to produce
optimum design parameters. In the (W, L) variation method,
TABLE II
the simulation time to generate the training data for the ANN
Id /W RANGE OF NMOS AND PMOS TRANSISTORS FOR DIFFERENT model is quite long. In gm /Id supervised method, the dataset
LENGTHS size is effectively limited as the simulations are done only
L(µm) Id /Wn Id /Wp Id /W0
for the selected region of operation. The time taken, dataset
0.165 [24.4, 51.6] [3.685, 10.74] [20.3, 88.58] size and the efficiency is higher for the gm /Id method as
0.565 [4.661, 13.35] [1.061, 3.158] [4.661, 24.72] it considers the simulation-based sample space for dataset
1.056 [2.56, 7.34] [0.61, 1.77] [2.56, 13.67] generation. This method can be extended further for design
5.056 [0.5, 1.512] [0.113, 0.34] [0.5, 3.27]
of complex analog circuits.
R EFERENCES
In the unsupervised learning technique mentioned in
[2], the simulations are performed for a three-stage trans- [1] G. Wolfe and R. Vemuri, “Extraction and use of neural network models
in automated synthesis of operational amplifiers,” IEEE Trans. Comput.-
impedance amplifier and a two-stage trans-impedance am- Aided Design Integr. Circuits Syst., vol. 22, no. 2, pp. 198–212, Feb.
plifier. The dataset size used in training the ML model is 2003
given in Table III. The data samples required is larger than [2] H.Wang, J.Yang, H.S.Lee, S.Han, ”Learning to design circuits,” 32nd
Conference on Neural Information Processing Systems , Montr´eal,
human expert model. Comparing with the human expert Canada, 2018.
model the three-stage trans-impedance amplifier and two- [3] Y. Li, Y. Wang, Y. Li, R. Zhou and Z. Lin, ”An Artificial Neural
stage trans-impedance amplifier gives a sample efficiency of Network Assisted Optimization System for Analog Design Space
Exploration,” in IEEE Transactions on Computer-Aided Design of
250 and 25 respectively. In the supervised learning technique Integrated Circuits and Systems, vol. 39, no. 10, pp. 2640-2653, Oct.
[3], the simulations are performed for two-stage rail-to-rail 2020, doi: 10.1109/TCAD.2019.2961322.
Opamp and active-RC CBPF. It uses filtered data from the [4] J.Rosa, D.Guerra, N.Horta, M. F. Martins, N.Lourenco, ”Using Ar-
tificial Neural Networks for Analog Integrated Circuit Design Au-
GA algorithm to generate training data for the local ANN tomation”, Springer Briefs in Applied Sciences and Technology,
model. In the proposed model of global ANN, which uses an https://doi.org/10.1007/978-3-030-35743-6.hed.

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.
[5] M. Kotti, M. Fakhfakh and E. Tlelo-Cuautle, ”Effect of the design space
sampling on the design performances,” 2018 IEEE 9th Latin American
Symposium on Circuits & Systems (LASCAS), 2018, pp. 1-4, doi:
10.1109/LASCAS.2018.8399926.
[6] Ethem Alpaydın, ”Introduction to Machine Learning” Second Edition,
The MIT Press, 2010.
[7] https://towardsdatascience.com/deep-deterministic-policy-gradients-
explained-2d94655a9b7b
[8] M. I. Dieste-Velasco, M. Diez-Mediavilla and C. Alonso-
Trist´an, “Regression and ANN Models for Electronic Circuit
Design”, Hindawi Complexity Volume 2018, Article ID 7379512,
doi.org/10.1155/2018/7379512.
[9] Engin Afacan, Nuno Lourenc¸o, Ricardo Martins, G¨unhan D¨undar,
“Review: Machine learning techniques in analog/RF integrated circuit
design, synthesis, layout, and test”, INTEGRATION, the VLSI journal
77 (2021) 113–130 ELSEVIER

Authorized licensed use limited to: Bharati Vidyapeeth's New Delhi. Downloaded on September 27,2023 at 08:21:13 UTC from IEEE Xplore. Restrictions apply.