t

1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Design, Analysis and Simulation of Synchronous

Reference Frame based Phase Lock Loop for Grid
Connected Inverter

Yash P. Bhattl and Mihir C. Shah2

1,2Department of Electrical Engineering, Institute of Technology, Nirma University, Ahmedabad, India
E-mail: [email protected]@nirmauni.ac.in

Abstract-With the increases in demand of energy, the the power to the far end user with low power loss without
non renewable energy sources have depleted and also there is adding and instability in power system. Grid
a concern of global warming with the use of non renewable synchronization is one of the main important issue in grid
source of energy. So there arises a need to find new energy connected system. In grid feeding solar PV systems,
resources which are in bulk and also does not affect the
electricity generated by solar PV is fed to the grid without
environment. Solar is one of the best solution among all the
storage. For large power solar PV system, three phase
renewable source of energy available today. Nowadays
photovoltaic (PV) system are mostly recognized and widely
central inverters feeding to grid are popular. In the PV
used for different types of power system applications. Solar power conditioning system, the maximum power point
panels convert solar energy into electricity, if DC load is tracking control technique is required to get the maximum
there it can be fed directly by panel through DC-DC possible power from the PV array to achieve maximum
converter and if alternating current (AC) load is there, which operating efficiency, the current control is required to
is mostly in residential and industrial applications, inverter is control the active and reactive power. In addition, the
connected to DC-DC converter. As demand has rise phase-Iocked loop (PLL) is also essential to collect the
maximum utilization of power is also a major concern, the
grid voltage and current data, such as the frequency, phase
power generated by solar should be fully utilized for the
angle and amplitude, for controlling overall system.[I][2]
extra power generated is fed to grid by synchronizing solar
inverter with grid. This paper presents simulation of Phase
11. SYSTEM DESCRIPTION
Lock Loop (PLL) with grid connected inverter using
Synchronous Reference Frame (SRF) method and close loop Usually the power converter acts as bridge between
boost converter. dc source to the load and/or to the grid consists of a two
Keywords-Phase Lock Loop; Grid Connected Inverter; stage converter: the dc-dc converter and the dc-ac
Boost Converter; Synchronous Reference Frame
converter. An alternative solution could be the use of a
I. INTRODUCTION
single-stage converter directly without dc-dc converter
and in order to achieve the required dc voltage level the
Utilization of renewable energy resources have been PV array are arranged in series parallel combination. In
the most important and futuristic field for meeting the the c1assical solution with two-stage converter, the dc-dc
rising demand in power all over the world specially in a converter requires several additional devices producing a
developing country like India. Grid-connected PV systems large amount of conduction losses, sluggish transient
may provide a viable technology for producing electrical response and high cost while the advantages of the single­
energy by using renewable energy resources. Important stage converters are good efficiency, a lower price and
design consideration for this system are high power easier implementation. As shown in Fig. 1, PV array
density, high efficiency and reliability along with control generates dc power which is fed to boost converter or dc­
objectives like grid synchronization, islanding detection dc converter which stabilizes the dc voltage and then fixed
and prevention, sinusoidal current injection into the grid, dc voltage is feed to the inverter which converts dc to ac
maintaining the THD within certain permissible limit. PV and then this ac voltage is fed to grid by ac filter and
system present now days can be broadly c1assified into isolation transformer. For synchronization of grid and
two types: inverter. PLL is used using the synchronous reference
• Stand alone frame method.
,....-----,
• Grid Connected
Standalone systems are used mainly in small scale
ISOLAnON GRIO
power requirement application and moreover the power TRANSFORME
R
cannot be transmitted over in long distance, thus this is
used in rural where the power is used in the place where it
Fig. I: Block Diagram of Grid Connected PV System
is generated. Grid connected system are used to transmit

978-1-4673-8587-9/16/$31.00 ©2016 IEEE [1]

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III. PHASE LOCK LOOp(PLL) have less information, more advanced systems are
required. The orthogonal signals are then further
Phase-Iocked loop (PLL) is a grid voltage phase
transferred from PI controller and voltage controlled
detection that makes use of dq reference frame which
oscillator from which e or sin is generated which is used
transfers three phase voltages to orthogonally separated dq
for SPWM comparision.
voltage to lock the grid phase.PLL uses dq reference
Three phase voltages can be given as:
frame for generating orthogonally separated dq voltage
Va Vm COS Wgrid t (1)
from three phase voltages to lock the grid phase. In =

practical applications, the grid voltage is distorted due to Vb Vm COS ( Wgridt - 2n/3)
= (2)
various factors such as nonlinearities of load and Vc Vm cOS ( Wgridt + 2n/3)
= (3)
measurement devices and the signal conversion errors, Where, Wgridt egrid =

which results in the harmonics, unbalancing of phase and

offset. Various error occurs in PLL due to this distorted
utility. The distorted utility causes various types of the v.
error in the PLL system. Phase Detection and loop filter v.
are two main parts of PLL.The PLL consists of two major v,
parts, the phase detecting device and loop filter. The phase
detecting consists of transformation from three phase to
two phase i.e abc to dq. The design parameters of the loop
filter are the damping ratio and the natural frequency
Fig. 3: Block Diagram of Three Phase SRF-PLL
which determine the dynamic characteristics. The
bandwidth of the loop filter is a trade-off between the
filtering performance and response time. While the higher
bandwidth offers the faster dynamic responses, the
tracking error is increased under the distorted utility
conditions. The errors caused by the phase unbalancing
f;:r:� C[:'kTj11�j 2 2 c

Substituting the values of Va' Vb' Vc in equation 4

(4)

[�ßH[: f ��lml
and harmonics have the frequency components of
multiples of cu, respectively, and can be considerably

[\I:ß] [ ]
reduced by using the loop filter with the low bandwidth. (5)
The error caused by the voltage offset is of the same
frequency as that of the utility voltage. To reduce this cos egrid
Vm (6)
error by the loop filter, the extremely low bandwidth is V =
- sinegrid
required. However, this degrades the dynamic Applying Parks transformation
performance and is not acceptable.[3][4]
[�] [���; �
n e
Rafe.rence = (7)
Input Phase error ��� e ][ ]
Here aß is the stationary two dimensional reference
frame and the dq is rotating reference frame which is
rotating at some angular frequency. For grid
synchronization dq axis and three phase voltages of grid
should synchronize. Grid voltages are rotating at angular
speed Wgrid'
Fig. 2: Block Diagram of Phase Lock Loop
Simplifying parks transformation we get
There are various PLL techniques available Vd Vm cos (egrid - e )
= (8)
Synchronous reference frame Vq Vm si n (egrid - e )
= (9)
Second order generalized integrator (SOG!)
When egrid e inverter voltage frequency and grid
=
Enhanced PLL (EPLL)
frequency get synchronized.[l] Thus
Quadrature PLL (QPLL)
Vd=Vm (10)
Out of this SRF-PLL is used for its sirnplicity and
ease of implementation and QPLL for its high filtering Vq 0 = (11)
capabilities and performance. [4]
IV. FILTER D ESIGN
A. Synchronous Reference Frame PLL (SRF PLL) The output of inverter is not pure and we cannot feed
Here in SRF initially the three phase voltages are this voltage directly to grid, for feeding this voltage to grid
sensed and they are transformed to two phase and then to it has to be filtered frrst. Either the inductance of
d-q axis. This method is suitable for both single and three transformers is used as a filter otherwise LC, LCL etc.
phase systems, although in single-phase, because they filter is to be designed.

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There are three types of filters that ean be eonneeted V. SIMULATION RESULTS
at the inverter outputs:
The MATLAB/SIMULINK model of grid eonneeted
• Sine filter or the LC filter
inverter with PLL is as shown in Fig 5. Here instead of
• Common mode filter
solar panel DC souree is eonneeted. This de souree is
• dv/dt filter. eonneeted to dose loop boost eonverter, output of dose
The inverter output filter that has been designed and loop boost eonverter is shown in Fig. 6 whieh aet as a de
shown in this paper is LC filter. The strueture of the filter link voltage of inverter. The inverter is eontrolled by
is shown in FigA. The seleetion of LC filter parameters is unipolar SPWM teehnique. The output voltage of inverter
deeided by assuming aeeeptable level of output voltage is shown in Fig. 7. To generate unipolar PWM signals sine
drop, maximum allowable voltage drop in the filter and wave is used as a referenee wave whieh is obtained from
switehing frequeney of the power switehes of the inverter. the eontrol bloek i.e. PLL shown in Fig.12. The harmonie
The ehoiee of the filter parameters requires eompromise analysis of two level inverter voltage output is shown in
between the total harmonie distortion in the voltage, eost Fig. 8 whieh is 92.87%. To feed this voltage into grid it is
of the filter, dimensions, weight and the eurrent of the to be filtered out. For this purpose LC filter is designed.
inverter. Fig. 4 shows the element response for smoothing output voltage of inverter after filter and its FFT analysis
the eurrent mainly is the induetor [5]. is as shown in Fig. 9 and Fig. 10 respeetively. As shown
A. Design Steps in Fig. 10 the THD improves to 4.00%.

Vdc = DC link voltage of inverter

fsw = switehing frequeney of switehes
Ll Is = ripple of induetor eurrent
fresonance = resonanee frequeney
fout = maximum first harmonie from the inverter
• Find value of induetanee from below equation
12.
2Vdc
1I
I

L= (12)
2,firrfsw3Ms
• To avoid the resonanee phenomena the maximum 11
I • I
I
first harmonie should be less than the fresonance i.e.
eondition in equation 13 is to be followed and
then ealculate value of eapaeitor (C) using
equation 140r 15.
� �i �i
10 *!out < fresollGllce < 0.5 */sw (13)
1 Fig. 5: Simulink Model of Grid Connected Inverter
fresonance = 2rr,[LC (14)
1 BO,-----�--�---�-�
C - 4flesonanceL (15)
-
60
• Now the damping resistor is to be ealculated
from Equation 17 where Zo is the natural
frequeney offilter and Q is quality faetor.
40 _
Zo= � (16)
20

R=
Zo
(17) °0L---�
0 .5--��--,�
.5--�--�2�
.5 --�
Time(Seconds)
- Q-

er Fig. 6: Close Loop Boost Converter Output

w
�
g:: I CI
�
C)
:>
� I
I

W I !
Fig. 4: Inverter Output Filter for Three Phase Grid Connection Fig. 7: Inverter Output Voltage without Filter

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

Fundamentat 150Hz): 27.95. THO: 92.87% VI. HARDWARE RESUL TS

t
Three phase IGBT based inverter is implemented
.
0.8 using SPWM switching techniques. The switching pulses
"
�0.6 required for switching of inverter are provided by
0
'"
� 0 .4
TMS320t28027 picoolo controller. The hardware setup of
three phase inverter with piccolo controller is as shown in

I I
0.2
Fig 13. The pulses required to trigger IGBTs of one leg
0
0 5 10 15 20 25 30 35 40
are as shown in Fig 14, both the pulses are
Hannonic order complementary. The output of inverter is as shown in Fig
15. Inverter output voltage with L filter is as shown in Fig
Fig. 8: % THD Analysis oflnverter without Filter
16, here the value of L is 5mH. Now the implementation
30 ,---,---,----,--� of PLL will be carried out.
20

·20

"-----"----'--"---'---'
·30
1.5 1.51 1.52 1.53 1.54 1.55 1.56 1.57 1.58 1.59 1.6
Time(Seconds)

Fig. 9: Inverter Output Voltage with Filter

Fundamental 150Hz) : 16.57 , THO: 4.00%

G:I 0.8 Fig. 13: Hardware Setu p of Three Phase SPWM Inverter
"
RIGOL STOP � � 00.00ulJ
�O,6
3'
'"
�O.4
l'ü 846 100Hz
� •

. ' 1'.:_: L...: ,;,..:..: r-:.: ..:...:. '

0.2

�
0
0 5 10 15 20 25 30 35 40
Hannonie order

Fig. 10: % THD Analysis oflnverter Output Voltage with Filter

_ .h
,-" �""""
If<---;" Ir--.
"",,, �
u...... L...-
. '---: -": I'-
I-.. r"- -- �
L.,;,- '-
_ I'- • .

40

�
20

g
w
1.-: - ..;...... '---: -
0: 0
.... CH1= 5.00lJ [!G!!I!!!I 5.00lJ Time 2.000ms �-476.8us
....
Q.

·20 Fig. 14: Switching Pulses for One Leg oflnverter (X axis:- 2ms/Div, Y
axis:- 5 V/Div)
..0
0 1 2 3 4 5 6 7 8 9 10 3' 0 6.00lJ
Time(Seconds)

Fig. I I: Error Generated by PLL PI

1.S

.1.S "-----�--�-----'
U = � � � u � � � � V
Time [!GI)!!!! 10.0lJ Time 10.00ms �279.6ms

Fig. 12: Sine Wave Generated by PLL. Fig. 15: Output oflnverter (X axis:- 10ms/Div Y axis: - 10V/Div)

[4]

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1s IEEE International Conference on Power Electronics. Intelligent Control and Energy Systems (ICPEICES-2016)

RIGOL STOP f 8 -32.8U

that by using LC passive filter the harmonie speetrum of
inverter output voltage is improved. Hardware result
shows results of three phase IGBT based SPWM inverter.
The inverter output voltage with and without filter are
same as the simulation results.

VIII. REFERENCES

[I] Dr. Saibal Chanerjee Mr. Shantanu Chanerjee. "Simulation of

Synchronous Reference Frame PLL based Grid Connected Inverter

Ur-m:6l:2) =: 12.8U
for Photovoltaic App lication". IEEE Press.

� 10.0U Time 10.00ms 1Ü+0.0000s [2] S.P.Srivastava Aurobinda Panda, M.K.Pathak. "Grid Tie Inverter
Control for Rooftop Photovoltaic System ". IEEE Press, 2012.
Fig. 16: Inverter Output Voltage with L=5mH (X axis:- 10ms/Div Y
[3] S.K.Chung. "Phase-Iocked loop for grid-connected three-phase
axis: - 10V/Div)
power conversion systems ". IEEE Proc-Electr. Power Appl, Vol.
147, No. 3, 2000.
VII. CONCLUSION
[4] Min Chen Wei Yao Zhaoming Qian Mingzhi Gao, Baohong Li.
The paper presented the detailed study of grid "Analysis and Implementation of a PLL Structure for Single-Phase
Grid-Connected Inverter System". IEEE Press, 2009.
eonneeted three phase two level inverter using PLL. PLL
[5] J.A. Peas Lopes R. J. Ferreira, R. E. Arajo. "A Com parative
has to be implemented for synehronizing solar inverter Analysis and Im plementation of Various PLL Techniques App lied
with grid. SRF-PLL is widely used beeause of its to Single phase Grids ". IEEE Press.
simplieity and out of different PWM teehniques unipolar [6] Ahmad A. AI-Abduallah, Atif Iqbal, Senior Member IEEE, Abdul
have advantage over bipolar, as in unipolar seheme the Aziz AI Hamadi, Khalel A1awi, Mohammed Saleh." Five-Phase
Induction Motor Drive System with Inverter Output LC Filter"
harmonies are shifted to twiee the switehing frequeney, so
2013 IEEE GCC Conference and exhibition, November 17-20,
by using unipolar seheme with filter we get sinusoidal Doha, Qatar.
voltage whieh ean be feed to the grid. FFT analysis shows

[5]

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