Arm Cortex-A Processor Comparison Table

The Cortex-A series of applications processors provide a range of solutions for devices undertaking complex compute tasks, such as hosting a rich operating system (OS) platform, and supporting multiple software applications.

Feature Cortex-A5 Cortex-A7 Cortex-A9 † Cortex-A15 † Cortex-A17 †

Architecture Armv7-A Armv7-A Armv7-A Armv7-A Armv7-A

Main Extensions LPAE Virtualization LPAE Virtualization LPAE Virtualization

Pipeline In order In order Out of order Out of order Out of order

Superscalar No Partial Yes Yes Yes

Physical Addressing (PA) 32-bit 40-bit 32-bit 40-bit 40-bit

TrustZone for Cortex-A Yes Yes Yes Yes Yes

Neon and Floating Point Unit Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Included

Floating Point Unit only Optional Optional Optional Optional Included

Optional Integrated GIC v1 (MP only)

Interrupt Controller Optional Integrated GIC v2 Internal Integrated GIC v1 (MP only) Optional Integrated GIC v2 Optional Integrated GIC v2
Integrated GIC v1 (MP only)

Bus Protocol AXI ACE AXI ACE or CHI ACE

32kB/ 32-64kB/
L1 I-Cache/D-Cache 4-64kB 8-64kB 16-64kB
32kB 32kB
Feature Cortex-A5 Cortex-A7 Cortex-A9 † Cortex-A15 † Cortex-A17 †

L2 Cache External L2C-310 Up to 1MB External L2C-310 512kB-4MB 256kB-8MB

L3 Cache N/A N/A N/A N/A N/A

Dual Core Lock-Step (DCLS) No No No No No

Functional Safety Support No No No No No

Cryptography Unit No No No No No

Error Code Correction (ECC)/Parity No No Optional Optional Yes

Accelerator Coherency Port (ACP) Optional No Optional Optional Optional

Peripheral Port No No No No No

Generic Timer No Yes Yes Armv8-A Armv8-A

Non-intrusive debug (trace) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable) Supported (separately licensable)
 Cortex- Cortex- Cortex-
Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 † Cortex-A65 Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A77 Cortex-A78
A65AE A76AE A78AE

Armv8-A Armv8-A Armv8.2-A Armv8.2-A Armv8.2-A Armv8.2-A Armv8.2-A Armv8.2-A Armv8.2-A

Architecture (AArch32 (AArch64 Armv8-A Armv8-A Armv8.2-A Armv8-A (AArch64 (AArch64 Armv8-A Armv8-A Armv8.2-A (AArch32 at (AArch32 at (AArch32 at (AArch32 at (AArch32 at
only) only) only) only) EL0 only) EL0 only) EL0 only) EL0 only) EL0 only)

Armv8.1 Armv8.1 Armv8.1 Armv8.1 Armv8.1 Armv8.1 Armv8.1 Armv8.1 Armv8.1

extensions extensions extensions extensions extensions extensions extensions extensions extensions
Armv8.2 Armv8.2 Armv8.2 Armv8.2 Armv8.2 Armv8.2 Armv8.2 Armv8.2 Armv8.2
extensions extensions extensions extensions extensions extensions extensions extensions extensions
Armv8.3 Armv8.3 Armv8.3 Armv8.3 Armv8.3 Armv8.3 Armv8.3 Armv8.3 Armv8.3
(LDAPR (LDAPR (LDAPR (LDAPR (LDAPR (LDAPR (LDAPR (LDAPR (LDAPR
Main instructions instructions instructions instructions instructions instructions instructions instructions instructions
Extensions only) only) only) only) only) only) only) only) only)
Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot Armv8.4 Dot
Product Product Product Product Product Product Product Product Product
Cryptography Cryptography Cryptography Cryptography Cryptography Cryptography Cryptography Cryptography Cryptography
extensions extensions extensions extensions extensions extensions extensions extensions extensions
RAS exten- RAS exten- RAS exten- RAS exten- RAS exten- RAS exten- RAS exten- RAS exten- RAS exten-
sions sions sions sions sions sions sions sions sions

Pipeline In order In order In order In order In order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order Out of order

Superscalar Partial Partial Partial Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

Physical
Addressing 40-bit 40-bit 40-bit 40-bit 40-bit 40-bit 44-bit 44-bit 44-bit 40-bit 44-bit 40-bit 40-bit 40-bit 40-bit 48-bit
(PA)

TrustZone for
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Cortex-A

Supported
(separately Included with Included with Included with Included with Included with Included with Included with Included with
Neon and Supported Supported Supported Supported
licensable) Dot Product INT8 Dot INT8 Dot INT8 Dot INT8 Dot INT8 Dot INT8 Dot INT8 Dot
Floating (separately (separately (separately (separately Included Included Included
Point Unit with Dot and IEEE Product and Product and Product and Product and Product and Product and Product and
licensable) licensable) licensable) licensable)
Product, and FP16 IEEE FP16 IEEE FP16 IEEE FP16 IEEE FP16 IEEE FP16 IEEE FP16 IEEE FP16
IEEE FP16

Floating
Point Unit N/A N/A N/A N/A Optional Included Included Included Included Included Included Included Included Included Included Included
only

Interrupt External External External External External External External External External External External External External External External External
Controller GICv3 GICv3 GICv3 GICv3 GICv4 GICv3 GICv4 GICv4 GICv3 GICv3 GICv3 GICv4 GICv4 GICv4 GICv4 GICv4
 Cortex- Cortex- Cortex-
Feature Cortex-A32 Cortex-A34 Cortex-A35 Cortex-A53 Cortex-A55 Cortex-A57 † Cortex-A65 Cortex-A72 Cortex-A73 Cortex-A75 Cortex-A76 Cortex-A77 Cortex-A78
A65AE A76AE A78AE

Bus Protocol ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI ACE or CHI

L1 I-Cache/ 48kB/ 48kB/32- 32kB/32-

8-64kB 8-64kB 8-64kB 8-64kB 8-64kB 16-64kB 16-64kB 64kB 64kB 64kB 64kB 64kB 64kB
D-Cache 32kB 64kB 64kB

L2 Cache 128kB-1MB 128kB-1MB 128kB-1MB 128kB-2MB 64-256kB 512kB-2MB 64-256kB 64-256kB 512kB-4MB 256kB-8MB 256-512kB 128-512KB 128-512KB 256-512kB 256-512kB 256-512kB

Optional Optional Optional Optional Optional Optional Optional Optional Optional

L3 Cache N/A N/A N/A N/A N/A N/A N/A
256kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB 512kB-4MB

Dual Core Yes (in Lock- Yes (in Lock-

Lock-Step No No No No No No No No No No No No No Yes
(DCLS) mode) mode)

ASIL D ASIL D ASIL D

Functional ASIL D ASIL D Systematic1 ASIL D ASIL D Systematic1 ASIL D Systematic1
Safety Yes Yes Yes Yes Yes Yes No No
Support Systematic1 Systematic1 and ASIL D Systematic1 Systematic1 and ASIL D Systematic1 & ASIL D
Diagnostic2 Diagnostic2 Diagnostic2

Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported Supported
Cryptography (with (with (with (with (with (with (with (with (with (with (with (with (with (with (with (with
Unit cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography cryptography
extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions) extensions)

Error Code
Correction Optional Optional Optional Optional Optional Optional Optional Yes Optional Yes Optional Optional Yes Optional Optional Yes
(ECC)/Parity

Accelerator
Coherency Optional Optional Optional Optional Optional Yes Optional Optional Optional Yes Optional Optional Optional Optional Optional Optional
Port (ACP)

Peripheral
No No No No Optional No Optional Optional No No Optional Optional Optional Optional Optional Optional
Port

Generic
Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A Armv8-A
Timer

Non- Supported Supported Supported

intrusive (separately (separately (separately Included Included Included Included Included Included Included Included Included Included Included Included Included
debug (trace) licensable) licensable) licensable)
Feature Cortex-A520 Cortex-A720

Architecture Armv9.2 Armv9.2

Up to Armv8.7 extensions
Up to Armv8.7 extensions
QARMA3 extensions QARMA3 extensions
SVE2 extensions SVE2 extensions
Main Extensions
Memory Tagging Extensions (MTE) (Including Asymmetric MTE) Memory Tagging Extensions (MTE) (Including Asymmetric MTE)
Cryptography extensions Cryptography extensions
RAS extensions
RAS extensions

Pipeline In order Out of order

Superscalar Yes Yes

Physical Addressing (PA) 40-bit 40-bit

Security TrustZone, Secure-EL2 Included TrustZone, Secure-EL2 Included

Neon, Floating Point Unit and SVE Included Included

Floating Point Unit only Included Included

Interrupt Controller External GICv4.1 External GICv4.1

Bus Protocol AMBA AXI5 or CHI.E AMBA AXI5 or CHI.E

L1 I-Cache/D-Cache 32KB or 64KB 32KB or 64KB

L2 Cache Optional, 128KB, 192KB, 256KB, 384KB, 512KB 128KB, 256KB, 512KB

L3 Cache Optional, 256KB to 32MB Optional, 256KB to 32MB

Dual Core Lock-Step (DCLS) No No

Functional Safety Support No No

Cryptography Unit Optional Optional

Error Code Correction (ECC)/Parity Yes Yes

Accelerator Coherency Port (ACP) Optional Optional

Peripheral Port Optional Optional

Generic Timer Armv9.2-A Armv9.2-A

Non-intrusive debug (trace) Included Included

†
Arm products undergo continual development and improvement. These Cortex-A processors are no longer available to license and are included here for comparison purposes only.
1
Suitable for up to ASIL D systematic development
2
Contributes towards up to ASIL D hardware diagnostic metrics

For more information, contact your Arm account manager today or explore the processors in more detail here: developer.arm.com/ip-products/processors/cortex-a

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