DP3773C

Quasi-Resonant PSR CC/CV PWM Power Switch

FEATURES GENERAL DESCRIPTION

 Low Cost Solution Built-in 800V power BJT DP3773C is a high performance Quasi Resonant
 Quasi-Resonant Primary Side Regulation (QR) Primary Side Regulation (PSR) PWM power
(QR-PSR) Control with High Efficiency switch with high precision CV/CC control ideal for
 Multi-Mode PSR Control charger applications.
 Fast Dynamic Response
 Built-in Dynamic Base Drive In CV mode, DP3773C adopts Multi Mode QR
 Audio Noise Free Operation
Control which uses the hybrid of AM (Amplitude
 ±4% CC and CV Regulation
Modulation) mode and (Frequency Modulation)
 Low Standby Power <70mW
FM mode to improve system efficiency and
 Programmable Cable Drop Compensation
reliability. In CC mode, the IC uses PFM control
(CDC) in CV Mode
with line and load CC compensation. The IC can
 Built-in AC Line & Load CC Compensation
 Build in Protections: achieve fast dynamic response. The built-in Cable
 Short Load Protection (SLP) Drop Compensation (CDC) function can provide
 Cycle-by-Cycle Current Limiting excellent CV performance.
 Leading Edge Blanking (LEB)
 Pin Floating Protection DP3773C integrates functions and protections of
 VDD OVP & UVP & Clamp Under Voltage Lockout (UVLO), VDD over Voltage
 Over temperature protection(OTP) Protection (VDD OVP), Cycle-by-cycle Current
 Available with DP3773C Versions in SOP-7 Limiting (OCP), Short Load Protection (SLP), On-
Package Chip Thermal Shutdown, VDD Clamping, etc.

APPLICATIONS

 Battery Chargers for Cellular Phones

 AC/DC Power Adapter and LED Lightings

TYPICAL APPLICATION CIRCUIT

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

Pin Configuration

Marking Information

DPXXXX for product name;

CXXXXXX The C represents the version; The first X reresents the last year,2014 is 4; The second X
represents the month, in A-L 12 letters;The third and fourth X on behalf of the date, 01-31 said; The
last two X represents the wafer batch code.

Pin Description (DP3773C)

Pin Pin
I/O Description
Number Name
System feedback pin which regulates both the output voltage in CV
1 FB I mode and output current in CC mode based on the flyback voltage of
the auxiliary winding.
2 CS I Current Sense Input Pin.
3 VDD P Power Supply Pin of the Chip.
4 E O The Power BJT Emitter
5,6 HV O The Power BJT Collector
7 GND P The Ground of the IC

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

Block Diagram

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

Absolute Maximum Ratings (Note 1)

Parameter Value Unit
HV PIN Maximum Voltage 800 V
HV PIN DC Current @DP3773C 1300 mA
VDD DC Supply Voltage 30 V
VDD DC Clamp Current 10 mA
CS, BASE voltage range -0.3 to 7 V
FB voltage range -0.7 to 7 V
RJA (℃/W) (SOP7) 90 o
C/W
Maximum Junction Temperature 150 o
C
Operating Temperature Range -40 to 85 o
C
Storage Temperature Range -65 to 150 oC

Lead Temperature (Soldering, 10sec.) 260 o

C
ESD Capability, HBM (Human Body Model) 3 kV
ESD Capability, MM (Machine Model) 250 V

Recommended Operation Conditions (Note 2)

Parameter Value Unit
Supply Voltage, VDD 7 to 24 V
Operating Ambient Temperature -40 to 85 C
o

Maximum Switching Frequency @ Full Loading 70 kHz

Minimum Switching Frequency @ Full Loading 35 kHz

ELECTRICAL CHARACTERISTICS (TA = 25OC, VDD=20V, if not otherwise noted)

Symbol Parameter Test Conditions Min Typ. Max Unit

Supply Voltage Section(VDD Pin)

IVDD_st Start-up current into VDD pin 3 20 uA

IVDD_Op Operation Current 0.8 1.5 mA

IVDD_standby Standby Current 0.5 1 mA

VDD Under Voltage Lockout

VDD_ON 10.5 12 13.5 V
Exit
VDD Under Voltage Lockout
VDD_OFF 5.5 6.5 7 V
Enter

VDD_OVP VDD OVP Threshold 24 26.5 29 V

VDD_Clamp VDD Zener Clamp Voltage I(VDD ) = 7 mA 26 28 30 V

Control Function Section (FB Pin)

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Quasi-Resonant PSR CC/CV PWM Power Switch

Internal Error Amplifier (EA)

VFBREF 1.97 2.0 2.03 V
Reference Input
Short Load Protection (SLP)
VFB_SLP 0.65 V
Threshold
Short Load Protection (SLP) (Note 3)
TFB_Short 36 ms
Debounce Time
Demagnetization Comparator
VFB_DEM 25 mV
Threshold

Toff_min Minimum OFF time (Note 3) 2 us

Ton_max Maximum ON time (Note 3) 20 us

Toff_max Maximum OFF time 5 ms

Maximum Cable Drop

ICable_max 60 uA
Compensation(CDC) Current
Ratio between Switching
TSW /TDEM Period and Demagnetization 7/4
Time in CC Mode

Current Sense Input Section (CS Pin)

CS Input Leading Edge
TLEB 500 ns
Blanking Time

Vcs(max) Current limiting threshold 490 500 510 mV

Over Current Detection and

TD_OC 100 ns
Control Delay

On-Chip Thermal Shutdown

TSD Thermal Shutdown (Note 3) --- 155 -- °C

TRC Thermal Recovery (Note 3) 140 -- °C

BJT Section (HV Pin)

VCEO Collector-Emitter voltage 450 V

VCBO Collector-Base voltage 800 V

Note1. Stresses listed as the above "Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to maximum rating conditions for extended periods may
remain possibility to affect device reliability.
Note2. The device is not guaranteed to function outside its operating conditions.
Note3. Guaranteed by the Design.

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

CHARACTERIZATION PLOTS

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

In Primary Side Regulation (PSR) control, the

PERATION DESCRIPTION output voltage is sensed on the auxiliary winding
during the transfer of transformer energy to the
DP3773C is a high performance, multi mode, highly secondary. Fig.2 illustrates the timing waveform of
integrated Quasi Resonant Primary Side CV sampling signal, demagnetization signal (DEM)
Regulation (QR-PSR) power switch. The built-in and quasi-resonant (QR) trigger signal in
high precision CV/CC control with high level DP3773C. When the CV sampling process is over,
protection features makes it suitable for offline the internal sample/hold (S&H) circuit captures the
small power converter applications. error signal and amplifies it through the internal
Error Amplifier (EA). The output of EA is sent to the
 System Start-Up Operation Quasi Resonant PSR CV Modulator (QR-CVM) for
CV regulation. A valley is selected to trigger new
Before the IC starts to work, it consumes only PWM cycle by the output of the QR-CVM bock,
startup current (typically 3uA) which allows a large which is determined by the load. The internal
value startup resistor to be used to minimize the reference voltage for EA is trimmed to 2V with high
power loss and the current flowing through the accuracy.
startup resistor charges the VDD hold-up capacitor
from the high voltage DC bus. When VDD reaches
UVLO turn-on voltage of 12V (typical), DP3773C
begins switching and the IC operation current is
increased to be 0.8mA (typical). The hold-up
capacitor continues to supply VDD before the
auxiliary winding of the transformer takes the
control of VDD voltage.

Fig.1 Fig.2

Once DP3773C enters very low frequency FM During the CV sampling process, an internal
(Frequency Modulation) mode, the operating variable current source is flowing to FB pin for
current is reduced to be 500uA typically, which Cable Drop Compensation (CDC). Thus, there is
helps to reduce the standby power loss. a step at FB pin in the transformer
demagnetization process, as shown in Fig.2.
 Quasi Resonant PSR CV Modulation Fig.2 also illustrates the equation for
“demagnetization plateau”, where Vo and VF is
(QR-CVM)
the output voltage and diode forward voltage; R1
and R2 is the resistor divider connected from the

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 DP3773C
Quasi-Resonant PSR CC/CV PWM Power Switch

auxiliary winding to FB Pin, Ns and Na are Side Constant Current Modulator (PSR-CCM) block,
secondary winding and auxiliary winding the IC operates in pulse frequency modulation
respectively. (PFM) mode to control the output current at any
output voltage at or below the voltage regulation
When heavy load condition, the Mode Selector target as long as the auxiliary winding can keep
(as shown in “Block Diagram”) based on EA VDD above the UVLO turn-off threshold.
output will switch to CC Mode automatically.
In DP3773C, the ratio between Tdem and Tsw in
 PSR Constant Current Modulation CC mode is 4/7. Therefore, the average output
(PSR-CCM) current can be expressed as:

Timing information at the FB pin and current 2 500mV

I CC_OUT mA    N
information at the CS pin allow accurate regulation 7 Rcs 
of the secondary average current. The control law
dictates that as power is increased in CV regulation In the equation above,
and approaching CC regulation the primary peak
current is at Ipp(max), as shown in Fig.3. N----The turn ratio of primary side winding to
secondary side winding.

Rcs--- the sensing resistor connected between the

power BJT emitter to GND.

 Multi Mode Control in CV Mode

To meet the tight requirement of averaged system

efficiency and no load power consumption, a hybrid
of frequency modulation (FM) and amplitude
modulation (AM) is adopted in DP3773C which is
shown in the Fig 4.

Around the full load, the system operates in FM

mode. When normal to light load conditions, the IC
operates in FM+AM mode to achieve excellent
regulation and high efficiency. When the system is
near zero loading, the IC operates in FM again for
Fig.3 standby power reduction. In this way, the no-load
consumption can be less than 70mW.
Referring to Fig.3 above, the primary peak current,
transformer turns ratio, secondary demagnetization
time (Tdem), and switching period (Tsw)
determines the secondary average output current
Iout. Ignoring leakage inductance effects, the
equation for average output current is shown in
Fig.3. When the average output current Iout
reaches the regulation reference in the Primary

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Quasi-Resonant PSR CC/CV PWM Power Switch

Fig.4

 Programmable Cable Drop

Compensation (CDC) in CV Mode

In smart phone charger application, the battery is

always connected to the adapter with a cable wire
which can cause several percentages of voltage
drop on the actual battery voltage. In DP3773C, an Fig.5
offset voltage is generated at FB pin by an internal
current source (modulated by CDC block, as shown  Optimized Dynamic Response
in Fig.5) flowing into the resistor divider. The
current is proportional to the switching period, thus, In DP3773C, the dynamic response performance is
it is inversely proportional to the output power Pout. optimized to meet USB charge requirements.
Therefore, the drop due the cable loss can be
compensated. As the load decreases from full  On Chip Thermal Shutdown (OTP)
loading to zero loading, the offset voltage at FB pin
will increase. By adjusting the resistance of R1 and When the IC temperature is over 155 oC, the IC
R2 (as shown in Fig.), the cable loss compensation shuts down. Only when the IC temperature drops to
can be programmed. The percentage of maximum 140 oC, IC will restart.
compensation is given by
 Audio Noise Free Operation
V(cable) Icable_max  R1//R2 
  100% As mentioned above, the multi-mode CV control
Vout VFB_REF
with a hybrid of FM and AM provides frequency
modulation. An internal current source flowing to
For example, R1=3K Ω , R2=18K Ω , The CS pin realizes CS peak voltage modulation. In
percentage of maximum compensation is given by: DP3773C, the optimized combination of frequency
modulation and CS peak voltage modulation
V(cable) 60uA  3K//18K  algorithm can provide audio noise free operation
  100%  7.7%
Vout 2V from full loading to zero loading.

 Dynamic BJT Base Drive

DP3773C drives a power BJT with dynamic base

drive control to optimize efficiency. The BJT base

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Quasi-Resonant PSR CC/CV PWM Power Switch

drive current ranges from 12mA to 35mA (typical),  Short Load Protection (SLP)
and is dynamically controlled according to the
power supply load change. The higher the output In DP3773C, the output is sampled on FB pin and
power, the higher the based current. Specifically, then compared with a threshold of UVP (0.65V
the base current is related to CS peak voltage, as typically) after an internal blanking time (10ms
shown in Fig.6 typical).

In DP3773C, when sensed FB voltage is below

0.6V, the IC will enter into Short Load Protection
(SLP) mode, in which the IC will enter into auto
recovery protection mode.

 VDD Over Voltage Protection (OVP) and

Zener Clamp

When VDD voltage is higher than 26.5V (typical),

the IC will stop switching. This will cause VDD fall
down to be lower than VDD_OFF (typical 6.5V) and
Fig.6 then the system will restart up again. An internal
28V (typical) zener clamp is integrated to prevent
the IC from damage.

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Quasi-Resonant PSR CC/CV PWM Power Switch

Package Dimension

Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min
A 1.350 1.750 A 1.350
A1 0.100 0.250 A1 0.100
A2 1.350 1.550 A2 1.350
b 0.330 0.510 b 0.330
c 0.170 0.250 c 0.170
D 4.700 5.100 D 4.700
e 1.270（BSC） 0.050（BSC） e 1.270（BSC）
E1 5.800 6.200 E1 5.800
E 3.800 4.000
L 0.400 1.270 L 0.400
θ 0º 8º θ 0º

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