Analog VLSI Circuits

E3 238
MOSFET small signal model

❑ References:
• G-H-L-M: Analysis and design of Analog Integrated Circuits by Gray, Hurst, Lewis, Meyer
 Load line of
Motivation for resistor R VG=1.75V

Small signal model

VG=1.50V
Input

VG=1.25V

VG=1.00V
VG=0.75V

𝑽𝑫𝑺 𝑽𝑹

Signal gain in Saturation region

IISc, Analog VLSI Circuits E3 238 Output 2

 • Transconductance 𝑔𝑚 at quiescent
Transconductance 𝑔𝑚 (operating) point (VGS0, ID0)
ID0+𝑖𝐷 𝑖𝐷 𝜕𝐼𝐷
𝑔𝑚 = = ቤ
𝑣𝐺𝑆 𝜕𝑉𝐺𝑆 𝑉 =𝑉𝐺𝑆
𝐺𝑆 0

• Ignoring channel length modulation

𝜇𝑛𝐶𝑜𝑥 𝑊
𝐼𝐷 = 𝑉𝐺𝑆 − 𝑉𝑇 2
2 𝐿

𝑊
𝑔𝑚 = 𝜇𝑛𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇
𝑣𝐺𝑆 𝐿 1ൗ
𝑊 2
= 2𝜇𝑛𝐶𝑜𝑥 𝐼𝐷
𝐿
2𝐼𝐷
=
𝑉𝐺𝑆 − 𝑉𝑇
IISc, Analog VLSI Circuits E3 238 3
MOSFET Small signal model (intermediate 1)
• Analysis of small signal (ac) gain,
frequency response, noise all done
around quiescent (dc) operating point
• Only AC sources are considered
̶ DC sources are essentially shorted
̶ VDD and ground are same!!

𝑉𝑜𝑢𝑡 = −𝑔𝑚𝑉𝑖𝑛𝑅
“-” sign denotes phase reversal
of ac (sinusoid) signal
IISc, Analog VLSI Circuits E3 238 4
 Signal Gain Large “good to
VG=1.75V

have” resistor (?)

VG=1.50V Input

• Signal gain 𝐴
𝑉𝑜𝑢𝑡 VG=1.25V
= −𝑔𝑚𝑅
𝑉𝑖𝑛 VG=1.00V
VG=0.75V

• We need large resistance

for high gain 𝑽𝑫𝑺 𝑽𝑹
̶ Large conventional resistor
requires large voltage drop
across it
→ large supply voltage,
huge power loss
IISc, Analog VLSI Circuits E3 238 Output 5
 PMOS load (resistor)
VGp=-1.1V VGn=1.12V Input
VGn=1.08V

• PMOS provides large dynamic

(differential) resistance for large
gain with small dc voltage (VDSp)
drop
Output
IISc, Analog VLSI Circuits E3 238 6
Output resistance (Intermediate model 2)
• Output resistance (differential) at
quiescent point
𝜕𝑉𝑑𝑠 1 Extremely important parameter
𝑟𝑑𝑠 = = that determines gain of amplifiers
𝜕𝑖𝑑 𝜕𝑖𝑑 Τ𝜕𝑉𝑑𝑠

1 1
= ≈
𝜇𝑛𝐶𝑜𝑥 𝑊
𝑉𝐺𝑆 − 𝑉𝑇 2𝜆 𝜆𝐼𝐷
2 𝐿

IISc, Analog VLSI Circuits E3 238 7

Gain of PMOS load amplifier

Simplified small signal

equivalent circuit
Small signal equivalent circuit

𝑉𝑜𝑢𝑡
• Gain of the amplifier: = −𝑔𝑚𝑛 𝑟𝑑𝑠𝑛||𝑟𝑑𝑠𝑝
𝑉𝑖𝑛

IISc, Analog VLSI Circuits E3 238 8

 Source-body modulation
Body/substrate/well

VSS VDD B

Isolated P-well
N-well

P-substrate

• Source is shorted to P-well • Source is modulated, p-type substrate grounded

→ No source-body modulation → Source-body modulation
• Need isolated P-well (not native p-type substrate) • Device in native p-type substrate
× May not be available in basic CMOS flow
IISc, Analog VLSI Circuits E3 238 9
 Second order effect: Body Effect

VSB

• Reverse bias (P substrate and N source) VSB

increases barrier potential for electrons
• Larger gate voltage needs to be applied to bring the
barrier down → VT increases
IISc, Analog VLSI Circuits E3 238 10
Change in VT
• With reverse bias VSB applied between channel and substrate, depletion
layer width and space charge increase
2𝜖𝑠𝑖 1
̶ 𝑄𝑑′ = −𝑞𝑁𝑠𝑢𝑏𝑊 ′ = −𝑞𝑁𝑠𝑢𝑏 2𝜙𝐹 + 𝑉𝑆𝐵 = − 2𝑞𝜖𝑠𝑖 2𝜙𝐹 + 𝑉𝑆𝐵 𝑁𝑠𝑢𝑏
𝑞 𝑁𝑠𝑢𝑏
𝑄𝑑′ 𝑄𝑖
• New VT wrt channel potential: 𝑉𝑇′ = Φ𝑚𝑠 − − + 𝜙𝐹 + 𝜙𝐹 + 𝑉𝑆𝐵
𝐶𝑜𝑥 𝐶𝑜𝑥
𝑄𝑑′ 𝑄𝑖
• New VT wrt source: 𝑉𝑇′ = Φ𝑚𝑠 − − + 2𝜙𝐹
𝐶𝑜𝑥 𝐶𝑜𝑥
𝑄𝑑′ −𝑄𝑑
• Change in Δ𝑉𝑇′ =−
𝐶𝑜𝑥

1
Δ𝑉𝑇′ = 2𝑞𝜖𝑠𝑖 2𝜙𝐹 + 𝑉𝑆𝐵 𝑁𝑠𝑢𝑏 − 2𝑞𝜖𝑠𝑖 2𝜙𝐹 𝑁𝑠𝑢𝑏 2𝑞𝜖𝑠𝑖 𝑁𝑠𝑢𝑏
𝐶𝑜𝑥 𝛾=
=𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹 𝐶𝑜𝑥

IISc, Analog VLSI Circuits E3 238 11

 Source body modulation (Full DC model)
𝜇𝑛𝐶𝑜𝑥 𝑊
• Start with 𝐼𝐷 = 𝑉𝐺𝑆 − 𝑉𝑇 2
2 𝐿
𝜕𝐼𝐷
→ 𝑔𝑚𝑏 =
𝜕𝑉𝐵𝑆

𝑊 𝜕𝑉𝑇 𝜕𝑉𝑇
= 𝜇𝑛𝐶𝑜𝑥 𝑉𝐺𝑆 − 𝑉𝑇 = −𝑔𝑚
𝐿 𝜕𝑉𝐵𝑆 𝜕𝑉𝐵𝑆

• Start with 𝑉𝑇 = 𝑉𝑇0 + 𝛾 2𝜙𝐹 + 𝑉𝑆𝐵 − 2𝜙𝐹

𝜕𝑉𝑇 −1
→ =𝛾 = −𝜒
𝜕𝑉𝐵𝑆 2 2𝜙𝐹 +𝑉𝑆𝐵

• Hence 𝑔𝑚𝑏 = 𝜒𝑔𝑚

̶ Typical value of 𝜒 is 0.1 to 0.3
IISc, Analog VLSI Circuits E3 238 12
Source follower with body effect
𝑉𝑜𝑢𝑡 𝑔𝑚
=
𝑉𝑖𝑛 𝑔𝑚 + 𝑔𝑚𝑏 + 1Τ𝑟𝑑𝑠

̶ Loss of gain due to body effect

IISc, Analog VLSI Circuits E3 238 13

Remember…..
• Small signal model and analysis are valid only when transistors are in
the saturation region. When any transistor tends to go close to the
linear region, the design starts falling apart. Making all transistors
happy at all conditions within the limited voltage supply is analog IC
designer’s first and foremost job.

• Conditions for operating in saturation region:

̶ NMOS: 𝑉𝐺𝐷 < 𝑉𝑇𝑛 or (𝑉𝐷𝑆 > 𝑉𝐺𝑆 − 𝑉𝑇𝑛 = 𝑉𝑜𝑑 )
̶ PMOS: 𝑉𝐷𝐺 < |𝑉𝑇𝑝 | or (𝑉𝑆𝐷 > 𝑉𝑆𝐺 − 𝑉𝑇𝑝 = 𝑉𝑜𝑑 )

IISc, Analog VLSI Circuits E3 238 14

Small signal model for AC simulation
• MOS working principle gives 𝑔𝑚 and 𝑟𝑑𝑠 - the desired parameters
• Device design gives 𝑔𝑚𝑏 and other parasitic capacitances
• Parasitic capacitances limit the speed of operation
• In linear region, channel exists
• Total capacitance from gate to channel
= 𝐶𝑜𝑥 𝑊𝐿
• Using engineering judgement, this is
represented by two lumped capacitance
1
𝐶𝑔𝑠 = 𝐶𝑜𝑥 𝑊𝐿
2
1
𝐶𝑔𝑑 = 𝐶𝑜𝑥 𝑊𝐿
2
IISc, Analog VLSI Circuits E3 238 15
Small signal 𝐶𝑔𝑠 and 𝐶𝑔𝑑 in saturation region
• In saturation, channel is pinched off before drain region
→ drain voltage does not change gate or channel charge
̶ 𝐶𝑔𝑑 = 0
𝜕𝑄𝑇
• Small signal 𝐶𝑔𝑠 = [why?]
𝜕𝑉𝑔𝑠
2
̶ 𝐶𝑔𝑠 = 𝑊𝐿𝐶𝑜𝑥
3
𝐿𝑒𝑓𝑓
𝑄𝑇 = 𝑊 න 𝑄𝐼 (𝑦)𝑑𝑦 𝑸𝑻
0
▪ 𝐼𝐷 𝑑𝑦 = 𝑊𝜇𝑛𝑄𝐼 𝑦 𝑑𝑣 𝑦
▪ 𝑄𝐼 𝑦 = 𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑣 𝑦 − 𝑉𝑇

𝑉𝑔𝑠 −𝑉𝑇
𝜇𝑛 𝑊 2 𝐶𝑜𝑥
2
2
2
𝑄𝑇 = න 𝑉𝑔𝑠 − 𝑣 − 𝑉𝑇 𝑑𝑣 = 𝑊𝐿𝐶𝑜𝑥 𝑉𝑔𝑠 − 𝑉𝑇
𝐼𝐷 0 3
IISc, Analog VLSI Circuits E3 238 16
Other parasitic capacitances

IISc, Analog VLSI Circuits E3 238 Ref: G-H-L-M 17

Full MOS transistor small signal equivalent circuit

IISc, Analog VLSI Circuits E3 238 Ref: G-H-L-M 18

MOSFET frequency response
𝑖0 𝜔
• We want to calculate
𝑖𝑖 𝜔
̶ Note that at dc, 𝑖𝑖 = 0
• Using Laplace transform formalism,
▪ 𝑖𝑖 = 𝑠 𝐶𝑔𝑠 + 𝐶𝑔𝑏 + 𝐶𝑔𝑑 𝑣𝑔𝑠
▪ 𝑖0 = 𝑔𝑚 𝑣𝑔𝑠 − s𝐶𝑔𝑑 𝑣𝑔𝑠
𝑖0 𝑔𝑚 −s𝐶𝑔𝑑 𝑔𝑚
▪ = ≈
𝑖𝑖 𝑠 𝐶𝑔𝑠 +𝐶𝑔𝑏 +𝐶𝑔𝑑 𝑠 𝐶𝑔𝑠 +𝐶𝑔𝑏 +𝐶𝑔𝑑

𝑖0 𝑔𝑚
≈
𝑖𝑖 𝑠 𝐶𝑔𝑠 + 𝐶𝑔𝑏 + 𝐶𝑔𝑑 𝑣𝑠𝑏 , 𝑣𝑑𝑠 are zero →
IISc, Analog VLSI Circuits E3 238
𝑟𝑑𝑠 , 𝐶𝑠𝑏 , 𝐶𝑑𝑏 , 𝑔𝑏 have no effect 19
Concept of 𝑓𝑇
• 𝑓𝑇 : Frequency at which short-circuit current gain is one.
• To find frequency response 𝑠 = 𝑗𝜔 = 𝑗2𝜋𝑓 𝑔𝑚
𝑓𝑇 =
𝑖0 𝜔 2𝜋 𝐶𝑔𝑠 + 𝐶𝑔𝑏 + 𝐶𝑔𝑑
• At 𝜔 = 𝜔 𝑇 = 2𝜋𝑓𝑇 , =1
𝑖𝑖 𝜔
𝑊
𝑔𝑚 𝜇𝑛𝐶𝑜𝑥 𝑉𝐺𝑆−𝑉𝑇
• Typically, 𝐶𝑔𝑠 ≫ 𝐶𝑔𝑏 + 𝐶𝑔𝑑 , hence 𝑓𝑇 = = 𝐿
2
2𝜋𝐶𝑔𝑠 2𝜋 3𝑊𝐿𝐶𝑜𝑥

3𝜇𝑛
• Significance of 𝑓𝑇 𝑓𝑇 = 𝑉𝐺𝑆 − 𝑉𝑇
4𝜋𝐿 2
̶ It is the frequency capability of the MOSFET
̶ Smaller L → higher frequency capability
• Push for smaller process node (up to a point for analog circuits)
̶ Higher mobility → higher frequency capability
• HEMT – high electron mobility transistor
IISc, Analog VLSI Circuits E3 238 20
Design Implications – trade-offs
A lot of times an analog circuit designer faces the problem of designing high gain and high
bandwidth circuits (e.g., amplifiers) with power (current) constraints. Choosing the right device
size and knowing the required current involves knowing the trade-off between gm and fT

• Overdrive voltage 𝑉𝑜𝑣 = 𝑉𝐺𝑆 − 𝑉𝑇 • Ways to increase 𝑓𝑇

𝑊 2 ̶ Use minimum 𝐿 of process node
• 𝐼𝐷 = 𝜇𝑛𝐶𝑜𝑥 𝑉𝑜𝑣 ̶ 𝑉𝑜𝑣 ↑
𝐿
𝑊
• 𝑔𝑚 = 𝜇𝑛𝐶𝑜𝑥 𝑉𝑜𝑣
𝐿
𝑊
1ൗ
2 2𝐼𝐷 • Ways to increase 𝑔𝑚
𝑊
= 2𝜇𝑛𝐶𝑜𝑥 𝐼𝐷 = ̶ ↑, 𝑉𝑜𝑣 ↑, but that implies 𝐼𝐷 ↑
𝐿 𝑉𝑜𝑣 𝐿 𝑊
3𝜇𝑛 ̶ For fixed 𝐼𝐷 , ↑ → 𝑉𝑜𝑣 ↓ → 𝑓𝑇 ↓
𝐿
• 𝑓𝑇 = 𝑉𝑜𝑣
4𝜋𝐿2

IISc, Analog VLSI Circuits E3 238 21

Topics left out…
• Short channel effects

• Drain induced barrier lowering

• Weak inversion or subthreshold operation

IISc, Analog VLSI Circuits E3 238 22