5-

CHAPTER 5

Combinational Circuit Design

VLSI Design Chih-Cheng Hsieh

 Outline 5- 2

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Static CMOS 5- 3

• Bubble Pushing
• Compound Gates
• Logical Effort Example
• Input Ordering
• Asymmetric Gates
• Skewed Gates
• Best P/N ratio

VLSI Design Chih-Cheng Hsieh

 Example 1 5- 4

module mux(input s, d0, d1,

output y);

assign y = s ? d1 : d0;
endmodule

1) Sketch a design using AND, OR, and NOT gates.

D0
S
Y
D1
S

VLSI Design Chih-Cheng Hsieh

 Example 2 5- 5

2) Sketch a design using NAND, NOR, and NOT gates.

Assume ~S is available.

D0
S
Y
D1
S

VLSI Design Chih-Cheng Hsieh

 Bubble Pushing 5- 6

• Start with network of AND / OR gates

• Convert to NAND / NOR + inverters
• Push bubbles around to simplify logic
– Remember DeMorgan’s Law

A B  A  B A  B  A B

VLSI Design Chih-Cheng Hsieh

 Bubble Pushing 5- 7

• Y = AB + CD

A A
B B
Y Y
C C
(a) D (b) D

A A
B B
Y Y
C C
D
(c) D (d)

VLSI Design Chih-Cheng Hsieh

 Example 3 5- 8

3) Sketch a design using one compound gate and

one NOT gate. Assume ~S is available.

D0
S
Y
D1
S

VLSI Design Chih-Cheng Hsieh

 Compound Gates 5- 9

• Logical Effort of compound gates

unit inverter AOI21 AOI22 Complex AOI

YA Y  A B  C Y  A B  C  D Y  AB  C  D  E
D
A A E
Y
B B A
A Y Y Y
C C B
D C

A 4 B 4 A 4 B 4 B 6
2 C 4 C 4 D 4 C 6 A 3
A Y Y Y
1 A 2 A 2 C 2 D 6 E 6
C 1 Y
B 2 B 2 D 2 E 2 A 2
D 2 B 2 C 2

gA = 3/3 gA = 6/3 gA = 6/3 gA = 5/3

p = 3/3 gB = 6/3 gB = 6/3 gB = 8/3
gC = 5/3 gC = 6/3 gC = 8/3
p = 7/3 gD = 6/3 gD = 8/3
p = 12/3 gE = 8/3
p = 16/3

VLSI Design Chih-Cheng Hsieh

 Example 4 5- 10

• The multiplexer has a maximum input capacitance

of 16 units on each input. It must drive a load of
160 units. Estimate the delay of the NAND and
compound gate designs.
D0 D0
S S
Y Y
D1
D1 S
S

H = 160 / 16 = 10
B=1
N=2
VLSI Design Chih-Cheng Hsieh
 NAND Solution 5- 11

P  22  4 D0
G  (4 / 3)  (4 / 3)  16 / 9 S
Y
F  GBH  160 / 9
D1
S

fˆ  N F  4.2 DeMorgan’s Law

D  Nfˆ  P  12.4 D0
S
Y
D1
S

VLSI Design Chih-Cheng Hsieh

 Compound Solution 5- 12

P  4 1  5
AOI22 + INV
G  (6 / 3)  (1)  2
F  GBH  20 D0
S
Y
D1
fˆ  N F  4.5 S

D  Nfˆ  P  14

VLSI Design Chih-Cheng Hsieh

 Example 5 5- 13

• Annotate your designs with transistor sizes that

achieve this delay.
NAND solution Compound solution
8 8

8 10 10

8 25 25 10 10 24
Y Y
25 6 6 12
8 8 25 6 6
8

8
16 160 * (4/3) / 4.2 = 50 16 160 * 1 / 4.5 = 36

VLSI Design Chih-Cheng Hsieh

 Input Order 5- 14

• Our parasitic delay model was too simple

– Calculate parasitic delay for Y falling
• If A arrives latest? 2
• If B arrives latest? 2.33

2 2 Y
A 2 6C

B 2x 2C

VLSI Design Chih-Cheng Hsieh

 Inner & Outer Inputs 5- 15

• Outer input is closest to rail (B)

• Inner input is closest to output (A)

2 2 Y
A 2
B 2

• If input arrival time is known

– Connect latest input to inner terminal
VLSI Design Chih-Cheng Hsieh
 VTC is Data-Dependent 5- 16

• The threshold voltage of M2 is higher than M1 due to body effect ()

VTn1 = VTn0 VTn2 = VTn0 + ((|2F| + Vint) - |2F|)
since VSB of M2 is not zero (when VB = 0) due to the presence of Cint
0.5/0.25 NMOS
0.75 /0.25 PMOS

A M3 B M4

F= A • B
D weaker
A M2 PUN
VGS2 = VA –VDS1 S
D
Cint
B M1
VGS1 = VB S

VLSI Design Chih-Cheng Hsieh

 Symmetric Gates 5- 17

• Inputs can be made perfectly symmetric

2 2
Y
A 1 1
B 1 1

VLSI Design Chih-Cheng Hsieh

 Asymmetric Gates 5- 18

• Asymmetric gates favor one input over another

• Ex: suppose input A of a NAND gate is most critical
– Use smaller transistor on A (less capacitance)
– Boost size of noncritical input A
Y
reset
– So total resistance is same
– gA = 10/9 2 2
Y
– gB = 2 A 4/3
4
– gtotal = gA + gB = 28/9 reset

• Asymmetric gate approaches g = 1 on critical input

• But total logical effort goes up
VLSI Design Chih-Cheng Hsieh
 Skewed Gates 5- 19

• Skewed gates favor one edge over another

• Ex: suppose rising output of inverter is most critical
– Downsize noncritical nMOS transistor
HI-skew unskewed inverter unskewed inverter
inverter (equal rise resistance) (equal fall resistance)

2 2 1
A Y A Y A Y
1/2 1 1/2

• Calculate logical effort by comparing to unskewed

inverter with same effective R on that edge.
– gu = 2.5 / 3 = 5/6
– gd = 2.5 / 1.5 = 5/3
VLSI Design Chih-Cheng Hsieh
 HI- and LO-Skew 5- 20

• Def: Logical effort of a skewed gate for a particular

transition is the ratio of the input capacitance of
that gate to the input capacitance of an unskewed
inverter delivering the same output current for
the same transition.
• Skewed gates reduce size of noncritical transistors
– HI-skew gates favor rising output (small nMOS)
– LO-skew gates favor falling output (small pMOS)
• Logical effort is smaller for favored direction
• But larger for the other direction
VLSI Design Chih-Cheng Hsieh
 Catalog of Skewed Gates 5- 21

Inverter NAND2 NOR2

2 2 B 4
Y
2 A 4
A 2
unskewed A Y Y
1 gu = 1 B 2 gu = 4/3 1 1 gu = 5/3
gd = 1 gd = 4/3 gd = 5/3
gavg = 1 gavg = 4/3 gavg = 5/3

2 2 B 4
Y
2 A 4
A 1
HI-skew A Y Y
1/2 gu = 5/6 B 1 gu = 1 1/2 1/2 gu = 3/2
gd = 5/3 gd = 2 gd = 3
gavg = 5/4 gavg = 3/2 gavg = 9/4
1 1 B 2
Y
1 A 2
A 2
LO-skew A Y Y
1 gu = 4/3 B 2 gu = 2 1 1 gu = 2
gd = 2/3 gd = 1 gd = 1
gavg = 1 gavg = 3/2 gavg = 3/2

VLSI Design Chih-Cheng Hsieh

 Asymmetric Skew 5- 22

• Combine asymmetric and skewed gates

– Downsize noncritical transistor on unimportant input
– Reduces parasitic delay for critical input

A
Y
reset

1 2
Y
A 4/3 10/9 100/99 ~1
reset 4 10 100 ∞

VLSI Design Chih-Cheng Hsieh

 Best P/N Ratio 5- 23

• We have selected P/N ratio for unit rise and fall

resistance ( = 2-3 for an inverter).
• Alternative: choose ratio for least average delay
• Ex: inverter
– Delay driving identical inverter P
A
– tpdf = (P+1) 1
– tpdr = (P+1)(/P)
– tpd = (P+1)(1+/P)/2 = (P + 1 +  + /P)/2
– Differentiate tpd w.r.t. P
– Least delay for P = 
VLSI Design Chih-Cheng Hsieh
 P/N Ratios 5- 24

• In general, best P/N ratio is sqrt of that giving

equal delay.
– Only improves average delay slightly for inverters
– But significantly decreases area and power

Inverter NAND2 NOR2

fastest
P/N ratio
A
1.414

1
Y
gu = 1.15
A
B
2 2

2
2
Y ?
gu = 4/3
B
A

1
2
2

1
Y
?
gu = 2
gd = 0.81 gd = 4/3 gd = 1
gavg = 0.98 gavg = 4/3 gavg = 3/2

VLSI Design Chih-Cheng Hsieh

 Observations 5- 25

• For speed:
– NAND vs. NOR
– Many simple stages vs. fewer high fan-in stages
– Latest-arriving input
• For area and power:
– Many simple stages vs. fewer high fan-in stages

VLSI Design Chih-Cheng Hsieh

 Outline 5- 26

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Introduction 5- 27

• What makes a circuit fast?

– I = C dV/dt -> tpd  (C/I) DV B 4
– low capacitance A 4
Y
– high current 1 1
– small swing
• Logical effort is proportional to C
• pMOS are the enemy!
– High capacitance for a given current
• Can we take the pMOS capacitance off the input?
• Various circuit families try to do this…
VLSI Design Chih-Cheng Hsieh
 Pseudo-nMOS 5- 28

• In the old days, nMOS processes had no pMOS

– Instead, use pull-up transistor that is always ON
• In CMOS, use a pMOS that is always ON
– Ratio issue, Make pMOS about 1/3~1/6 effective
strength of pulldown network
load 1.8

P/2 1.5

Ids 1.2
P = 24
Vout Vout 0.9

16/2
0.6
Vin P = 14
0.3
P=4

0
0 0.3 0.6 0.9 1.2 1.5 1.8
Vin

VLSI Design Chih-Cheng Hsieh

 Pseudo-nMOS Gates 5- 29

• Design for unit current on output

to compare with unit inverter. Y

• Choose pMOS size between 1/3 inputs

f
~ 1/6 the effective width (pick 1/3)
Inverter NAND2 NOR2

gu = 4/3 gu = 8/3 gu = 4/3

gd = 4/9 2/3 gd = 8/9 gd = 4/9
gavg = 8/9 Y g = 16/9 gavg = 8/9
2/3 avg 2/3
pu = 6/3 A 8/3 pu = 10/3
Y Y pu = 10/3
A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9
pavg = 12/9 pavg = 20/9 pavg = 20/9

Inverter : Iu = (1/3)I, Cinv-u = 1, gu = (4/3)/1, pu = (2/3+4/3)/1

Id = I, Cinv-d = 3, gd = (4/3)/3, pd = (2/3+4/3)/3
VLSI Design Chih-Cheng Hsieh
 Pseudo-nMOS Design 5- 30

• Ex: Design a k-input AND gate using INV+ seudo-

nMOS NOR. Find the delay driving a fanout of H
Pseudo-nMOS
In1
• G = 1 * 8/9 = 8/9 1
Y

• F = GBH = 8H/9 Ink 1

H

• P = 1 + (4+8k)/9 = (8k+13)/9
• N =2
4 2 H 8k  13
• 1/N
D = NF + P = 
3 9

VLSI Design Chih-Cheng Hsieh

 Pseudo-nMOS Power 5- 31

• Pseudo-nMOS draws power whenever Y = 0

– Called static power P = I•VDD
– A few mA / gate * 1M gates would be a problem
– This is why nMOS went extinct!
• Use pseudo-nMOS sparingly for wide NORs
• Turn off pMOS when not in use

en
Y
A B C

VLSI Design Chih-Cheng Hsieh

 Outline 5- 32

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Cascode Voltage Switch Logic 5- 33

• Differential Cascode Voltage Switching Logic (DCVS,

DCVSL)
– Seeks the performance of ratioed circuits without the static
power consumption
– Use both true and complementary input signals and compute
both true and complementary outputs

1 0 ON OFF OFF ON 01

OFF ON ON OFF

VLSI Design Chih-Cheng Hsieh

 Cascode Voltage Switch Logic 5- 34

2-input AND/NAND gate 4-input XOR/XNOR gate

VLSI Design Chih-Cheng Hsieh

 Outline 5- 35

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Dynamic CMOS 5- 36

• In static circuits at every point in time (except when

switching) the output is connected to either GND or VDD
via a low resistance path.
– fan-in of N requires 2N devices

• Dynamic circuits rely on the temporary storage of signal

values on the capacitance of high impedance nodes.
– requires only N + 2 transistors
– takes a sequence of precharge and conditional evaluation
phases to realize logic functions

VLSI Design Chih-Cheng Hsieh

 Dynamic Logic 5- 37

• Dynamic gates uses a clocked pMOS pullup

• Two modes: precharge and evaluate

2 2/3  1
A Y Y Y
1 A 4/3 A 1

Static Pseudo-nMOS Dynamic

 Precharge Evaluate Precharge

VLSI Design Chih-Cheng Hsieh

 The Foot 5- 38

• What if pulldown network is ON during precharge?

• Use series evaluation transistor to prevent fight.

precharge transistor  
 Y Y
Y
inputs inputs
A
f f
foot

footed unfooted

VLSI Design Chih-Cheng Hsieh

 Logical Effort 5- 39

Inverter NAND2 NOR2

 1
Y
 1  1
A 2
unfooted Y Y
A 1 B 2 A 1 B 1
gd = 1/3 gd = 2/3 gd = 1/3
pd = 2/3 pd = 3/3 pd = 3/3

 1
Y
 1  1
A 3
Y Y
footed A 2 B 3 A 2 B 2
gd = 2/3 gd = 3/3 gd = 2/3
2 pd = 3/3 3 pd = 4/3 2 pd = 5/3

VLSI Design Chih-Cheng Hsieh

 Conditions on Output 5- 40

• Once the output of a dynamic gate is discharged, it

cannot be charged again until the next precharge
operation.
• Inputs to the gate can make at most one transition
during evaluation.
• Output can be in the high impedance state during and
after evaluation (PDN off), state is stored on CL

VLSI Design Chih-Cheng Hsieh

 Properties of Dynamic Gates 5- 41

• Logic function is implemented by the PDN only

– number of transistors is N + 2 (versus 2N for static complementary CMOS)
– should be smaller in area than static complementary CMOS
• Full swing outputs (VOL = GND and VOH = VDD)
• Nonratioed - sizing of the devices is not important for
proper functioning (only for performance)
• Faster switching speeds
– reduced load capacitance due to lower number of transistors per gate (Cint)
so a reduced logical effort
– reduced load capacitance due to smaller fan-out (Cext)
– no Isc, so all the current provided by PDN goes into discharging CL
– Ignoring the influence of precharge time on the switching speed of the gate,
tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
VLSI Design Chih-Cheng Hsieh
 Properties of Dynamic Gates, con’t 5- 42

• Power dissipation should be better

– consumes only dynamic power – no short circuit power consumption since
the pull-up path is not on when evaluating
– lower CL- both Cint (since there are fewer transistors connected to the drain
output) and Cext (since there the output load is one per connected gate, not
two)
– by construction can have at most one transition per cycle – no glitching
• But power dissipation can be significantly higher due to
– higher transition probabilities
– extra load on CLK
• PDN starts to work as soon as the input signals exceed
VTn, so set VM, VIH and VIL all equal to VTn
– low noise margin (NML)
• Needs a precharge clock
VLSI Design Chih-Cheng Hsieh
 Dynamic Behavior 5- 43

CLK
Out Evaluate
In1
In2

In3
In &
In4 CLK
Out Precharge
CLK

Time, ns

#Trns VOH VOL VM NMH NML tpHL tpLH tp

6 2.5V 0V VTn 2.5-VTn VTn 110ps 0ns 83ps

VLSI Design Chih-Cheng Hsieh

Gate Parameters are Time Independent 5- 44

• The amount by which the output voltage drops is a strong

function of the input voltage and the available evaluation time.
– Noise needed to corrupt the signal has to be larger if the evaluation time is
short – i.e., the switching threshold is truly time independent.

CLK
Vout (VG=0.45)

Vout (VG=0.55)
Vout (VG=0.5)
VG

VLSI Design Chih-Cheng Hsieh

Power Consumption of Dynamic Gate 5- 45

CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

VLSI Design Chih-Cheng Hsieh

 Dynamic Power is Data Dependent 5- 46

Dynamic 2-input NOR Gate

Assume signal probabilities
A B Out
PA=1 = 1/2
0 0 1
PB=1 = 1/2
0 1 0
1 0 0
Then transition probability
P01 = Pout=0 x Pout=1
1 1 0
= 3/4 x 1 = 3/4

Switching activity can be higher in dynamic gates!

P01 = Pout=0

VLSI Design Chih-Cheng Hsieh

 Issues 1: Charge Leakage 5- 47

CLK
4
3
CLK Mp
Out
1

A=0 CL
2
VOut Evaluate
CLK Me
Precharge
Leakage sources

Minimum clock rate of a few kHz

VLSI Design Chih-Cheng Hsieh

 Impact of Charge Leakage 5- 48

• Output settles to an intermediate voltage determined by a

resistive divider of the pull-up and pull-down networks
– Once the output drops below the switching threshold of the fan-out logic
gate, the output is interpreted as a low voltage.

CLK

Out

VLSI Design Chih-Cheng Hsieh

 A Solution to Charge Leakage 5- 49

• Keeper compensates for the charge lost due to the pull-

down leakage paths.
Keeper

CLK Mp Mkp

!Out
A
CL
B

CLK Me

Same approach as level restorer for pass

transistor logic
VLSI Design Chih-Cheng Hsieh
 Summary: Leakage 5- 50

• Dynamic node floats high during evaluation

– Transistors are leaky (IOFF  0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
 1 k
X
H Y
A 2
2

VLSI Design Chih-Cheng Hsieh

 Issues 2: Charge Sharing 5- 51

• Charge stored originally on CL is redistributed (shared) over CL and

CA leading to static power consumption by downstream gates and
possible circuit malfunction.

CLK Mp
Out
A CL

B=0 Ca

CLK Me Cb

• When DVout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough
to be below the switching threshold of the gate it drives causing a
malfunction.
VLSI Design Chih-Cheng Hsieh
 Charge Sharing 5- 52

• Dynamic gates suffer from charge sharing

 

Y
A x CY A

B=0 Cx Y
Charge sharing noise

CY
Vx  VY  VDD
Cx  CY

VLSI Design Chih-Cheng Hsieh

 Charge Sharing Example 5- 53

What is the worst case voltage drop on y? (Assume all inputs are
low during precharge and that all internal nodes are initially at 0V.)

Load
CLK inverter
y=ABC

A !A Cy=50fF
a

B b
Ca=15fF !B B !B
c d Cb=15fF

Cc=15fF !C C Cd=10fF

CLK

VLSI Design Chih-Cheng Hsieh

 Charge Sharing Example 5- 54

What is the worst case voltage drop on y? (Assume all inputs are
low during precharge and that all internal nodes are initially at 0V.)
Load
CLK inverter
y=ABC

A !A Cy=50fF
a

B b
Ca=15fF !B B !B
c d Cb=15fF

Cc=15fF !C C Cd=10fF

CLK

DVout = - VDD ((Ca + Cc)/((Ca + Cc) + Cy)) = - 2.5V*(30/(30+50)) = -0.94V

VLSI Design Chih-Cheng Hsieh
 Solution to Charge Redistribution 5- 55

CLK Mp Mkp CLK

Out
A

CLK Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)

VLSI Design Chih-Cheng Hsieh

 Secondary Precharge 5- 56

• Solution: add secondary precharge transistors

– Typically need to precharge every other node
• Big load capacitance CY helps as well

secondary
 precharge
Y transistor
A x
B

VLSI Design Chih-Cheng Hsieh

 Issues 3: Backgate Coupling 5- 57

• Susceptible to crosstalk due to 1) high impedance of the

output node and 2) backgate capacitive coupling
‒ Out2 capacitively couples with Out1 through the gate-source
and gate-drain capacitances of M4

CLK Mp M6 M5
Out1 =1
Out2 =10
A=0 M1 M4
CL1 CL2

B=0 M2 M3 In

CLK Me

Dynamic NAND Static NAND

VLSI Design Chih-Cheng Hsieh
 Backgate Coupling Effect 5- 58

• Capacitive coupling means Out1 drops significantly so

Out2 doesn’t go all the way to ground
Clock Feedthrough
3

2
Out1
1
CLK

0
In Out2

-1
0 2 Time, ns 4 6

VLSI Design Chih-Cheng Hsieh

 Issues 4: Clock Feedthrough 5- 59

• A special case of backgate capacitive coupling between

the clock input of the precharge transistor and the
dynamic output node

Coupling between Out and CLK

CLK Mp input of the precharge device due
Out to the gate-drain capacitance. So
A CL voltage of Out can rise above VDD.
The fast rising (and falling edges)
B
of the clock couple to Out.
CLK Me

VLSI Design Chih-Cheng Hsieh

 Clock Feedthrough 5- 60

Clock feedthrough
CLK
Out
In1
In2

In3 In &
CLK Out
In4
CLK

Time, ns
Clock feedthrough

VLSI Design Chih-Cheng Hsieh

 Issues 5: Cascading Gates 5- 61

CLK
CLK Mp CLK Mp
Out2
Out1 In
In
VTn
Out1
CLK Me CLK Me
DV
Out2

t
Only a single 0  1 transition allowed at the
inputs during the evaluation period!
VLSI Design Chih-Cheng Hsieh
 Monotonicity 5- 62

• Dynamic gates require monotonically rising inputs

during evaluation

– 0 -> 0
A
– 0 -> 1
– 1 -> 1
– But not 1 -> 0 violates monotonicity
during evaluation
A

 Precharge Evaluate Precharge

Output should rise but does not

VLSI Design Chih-Cheng Hsieh
 Monotonicity Woes 5- 63

• But dynamic gates produce monotonically falling

outputs during evaluation
• Illegal for one dynamic gate to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X

VLSI Design Chih-Cheng Hsieh

 Monotonicity Woes 5- 64

• But dynamic gates produce monotonically falling

outputs during evaluation
• Illegal for one dynamic gate to drive another!

A=1

  Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

VLSI Design Chih-Cheng Hsieh

 Domino Gates 5- 65

• Follow dynamic stage with inverting static gate

– Dynamic / static pair is called domino gate
– Produces monotonic outputs
 Precharge Evaluate Precharge
domino AND

W
W X Y Z
A X

B C
Y

Z
dynamic static
NAND inverter  
 
A W X A X
H Y =
B H Z B Z
C C

VLSI Design Chih-Cheng Hsieh

 Domino Optimizations 5- 66

• Each domino gate triggers next one, like a string of

dominos toppling over
• Gates evaluate sequentially, precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic


S0 S1 S2 S3
D0 D1 D2 D3
Y
H


S4 S5 S6 S7
D4 D5 D6 D7

VLSI Design Chih-Cheng Hsieh

 Dual-Rail Domino 5- 67

• Domino only performs noninverting functions:

– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs

sig_h sig_l Meaning

0 0 Precharged Y_l  Y_h

0 1 ‘0’ inputs
f f
1 0 ‘1’ 
1 1 invalid

VLSI Design Chih-Cheng Hsieh

 Example: AND/NAND 5- 68

• Given A_h, A_l, B_h, B_l

• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements

Y_l  Y_h
= A*B A_h = A*B
A_l B_l B_h

VLSI Design Chih-Cheng Hsieh

 Example: XOR/XNOR 5- 69

• Sometimes possible to share transistors

Y_l  Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

VLSI Design Chih-Cheng Hsieh

 Noise Sensitivity 5- 70

• Dynamic gates are very sensitive to noise

– Inputs: VIH  Vtn
– Outputs: floating output susceptible noise
• Noise sources
– Capacitive crosstalk
– Charge sharing
– Power supply noise
– Feedthrough noise
– And more!

VLSI Design Chih-Cheng Hsieh

 Domino Summary 5- 71

• Domino logic is attractive for high-speed circuits

– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
• Widely used in high-performance microprocessors

VLSI Design Chih-Cheng Hsieh

 Outline 5- 72

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Pass Transistor Circuits 5- 73

• Use pass transistors like switches to do logic

• Inputs drive diffusion terminals as well as gates
• CMOS + Transmission Gates:
– 2-input multiplexer
– Gates should be restoring
S S

A A
S Y S Y
B B

S S
VLSI Design Chih-Cheng Hsieh
 NMOS Transistors in Series/Parallel 5- 74

• Primary inputs drive both gate and source/drain

terminals
• NMOS switch closes when the gate input is high
A B
X = Y if A and B
X Y
A

B X = Y if A or B
X Y

• Remember - NMOS transistors pass a strong 0

but a weak 1
VLSI Design Chih-Cheng Hsieh
 PMOS Transistors in Series/Parallel 5- 75

• Primary inputs drive both gate and source/drain

terminals
• PMOS switch closes when the gate input is low
A B
X = Y if A and B = A + B
X Y
A

B X = Y if A or B = A  B
X Y

• Remember - PMOS transistors pass a strong 1 but

a weak 0
VLSI Design Chih-Cheng Hsieh
 Pass Transistor (PT) Logic 5- 76

B
B
A A
F= A  B B
B
0 F= A  B
0

• Gate is static – a low-impedance path exists to both

supply rails under all circumstances
• N transistors instead of 2N
• No static power consumption
• Ratioless
• Bidirectional (versus undirectional)
VLSI Design Chih-Cheng Hsieh
 VTC of PT AND Gate 5- 77

B
1.5/0.25

0.5/0.25
B=VDD, A=0VDD

Vout, V
A
0.5/0.25
B A=VDD, B=0VDD
F= AB
A=B=0VDD
0
0.5/0.25

• Pure PT logic is not regenerative - the signal gradually

degrades after passing through a number of PTs (can fix
with static CMOS inverter insertion)
VLSI Design Chih-Cheng Hsieh
 NMOS Only PT Driving an Inverter 5- 78

• Vx does not pull up to VDD, but VDD – VTn

In = VDD
VGS M2
A = VDD
D S
B M1

Vx = VDD-VTn

• Threshold voltage drop causes static power consumption

(M2 may be weakly conducting forming a path from VDD
to GND)
• Notice VTn increases for pass transistor due to body effect
(VSB)
VLSI Design Chih-Cheng Hsieh
Voltage Swing of PT Driving an Inverter 5- 79

• Body effect – large VSB at x - when pulling high (B is tied

to GND and S charged up close to VDD)
• So the voltage drop is even worse
Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
In
In = 0  VDD =2.5V
1.5/0.25 x = 1.8V
x Voltage, V
S
D
VDD Out
0.5/0.25 Out
0.5/0.25
B

Time, ns

VLSI Design Chih-Cheng Hsieh

 Cascaded NMOS Only PTs 5- 80

B = VDD B = VDD C = VDD

G
M1 x M2 y
M1 A = VDD Out
A = VDD S x = VDD - VTn1
G
M2 y
C = VDD Out
S

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1

• Pass transistor gates should never be cascaded as on
the left
• Logic on the right suffers from static power dissipation
and reduced noise margins
VLSI Design Chih-Cheng Hsieh
 Solution 1: Level Restorer 5- 81

• Full swing on x (due to Level Restorer) so no static power

consumption by inverter
• No static backward current path through Level Restorer
and PT since Restorer is only active when A is high
• For correct operation Mr must be sized correctly (ratioed)
Level Restorer
on
Mr
B off
A=1 M2 Out=0
Mn
x= 0
A=0 Out =1
1
A M1

VLSI Design Chih-Cheng Hsieh

 Restorer Circuit Transient Response 5- 82

• Restorer has speed and power impacts: increases the capacitance

at x, slowing down the gate; increases tr (but decreases tf)

Mr

M2
node x never goes below VM x
of inverter so output never Mn
switches M1
Voltage, V

W/Lr=1.75/0.25
W/Ln=0.50/0.25

W/Lr=1.50/0.25 W/L2=1.50/0.25

W/L1=0.50/0.25
W/Lr=1.25/0.25
W/Lr=1.0/0.25

Time, ps

VLSI Design Chih-Cheng Hsieh

 Solution 2: Multiple VT Transistors 5- 83

• Technology solution: Use (near) zero VT devices for the NMOS PTs to eliminate
most of the threshold drop (body effect still in force preventing full swing to VDD)

low VT transistors
In2 = 0V A = 2.5V
on

Out
off but
leaking
In1 = 2.5V B = 0V

sneak path

• Impacts static power consumption due to subthreshold currents flowing through

the PTs (even if VGS is below VT)
VLSI Design Chih-Cheng Hsieh
 Solution 3: Transmission Gates (TGs) 5- 84

• Most widely used solution

• Full swing bidirectional switch controlled by the gate
signal C, A = B if C = 1
C C

A B A B

C C

C = GND C = GND

A = VDD B A = GND B

C = VDD C = VDD
VLSI Design Chih-Cheng Hsieh
 Solution 4: CPL 5- 85

• Complementary Pass-transistor Logic

– Dual-rail form of pass transistor logic
– Avoids need for ratioed feedback
– Optional cross-coupling for rail-to-rail swing
S
A
S L Y
B
S
A
S L Y
B
VLSI Design Chih-Cheng Hsieh
 Outline 5- 86

1. Static CMOS
2. Ratioed Circuits
3. Cascode Voltage Switch Logic
4. Dynamic Circuits
5. Pass-Transistor Circuits
6. Circuit Pitfalls

VLSI Design Chih-Cheng Hsieh

 Introduction 5- 87

• Circuit Pitfalls
– Detective puzzle
– Given circuit and symptom, diagnose cause and
recommend solution
– All these pitfalls have caused failures in real chips
• Noise Budgets
• Reliability

VLSI Design Chih-Cheng Hsieh

 Threshold Drop 5- 88

• Circuit • Symptom
– 2:1 multiplexer – Mux works when
S selected D is 0 but
D0 X
not 1.
Y
D1 – Or fails at low VDD.
S – Or fails in SF corner.
 Principle: Threshold drop
– X never rises above VDD-Vt
– Vt is raised by the body effect
– The threshold drop is most serious as Vt becomes a greater
fraction of VDD.
 Solution: Use transmission gates, not pass transistors
VLSI Design Chih-Cheng Hsieh
 Leakage 5- 89

• Circuit • Symptom
– Latch  – Load a 0 into Q
D
X
Q
– Set  = 0
– Eventually Q

spontaneously flips to 1
 Principle: Leakage
– X is a dynamic node holding value as charge on the node
– Eventually subthreshold leakage may disturb charge
 Q

 Solution: Stabilize node with feedback D

X


– Or periodically refresh node (requires fast clock, 

not practical processes with big leakage) 

VLSI Design Chih-Cheng Hsieh

 Leakage 5- 90

• Circuit • Symptom
– Domino AND  – Precharge gate (Y=0)
X
gate Y – Then evaluate
0
– Eventually Y
1
spontaneously flips to 1

 Principle: Leakage

– X is a dynamic node holding value Y
0 X
as charge on the node
– Eventually subthreshold leakage 1
may disturb charge
 Solution: Keeper
VLSI Design Chih-Cheng Hsieh
 Ratio Failure 5- 91

• Circuit • Symptom
– Pseudo-nMOS OR – When only one input is
true, Y = 0.
X – Perhaps only happens in
Y SF corner.
A B

 Principle: Ratio Failure

– nMOS and pMOS fight each other.
– If the pMOS is too strong, nMOS cannot pull X low enough.
 Solution: Check that ratio is satisfied in all corners

VLSI Design Chih-Cheng Hsieh

 Ratio Failure 5- 92

• Circuit • Symptom
– Latch 
– Q stuck at 1.
D X Q – May only happen for
certain latches where
 weak input is driven by a small
gate located far away.
 Principle: Ratio Failure (again)
– Series resistance of D driver, wire 
resistance, and tgate must be much
D Q
less than weak feedback inverter.
 Solutions: Check relative strengths  weak
– Avoid unbuffered diffusion inputs stronger
where driver is unknown
VLSI Design Chih-Cheng Hsieh
 Charge Sharing 5- 93

• Circuit • Symptom
– Domino AND 
– Precharge gate while
Y
gate Z A = B = 0, so Z = 0
A
B
X – Set  = 1
– A rises
– Z is observed to
 Principle: Charge Sharing sometimes rise
– If X was low, it shares charge with Y

 Solutions: Limit charge sharing Y
Z
CY A X CY
Vx  VY  VDD
Cx  CY B Cx

– Safe if CY >> CX
– Or precharge node X too
VLSI Design Chih-Cheng Hsieh
 Charge Sharing 5- 94

• Circuit • Symptom
– Dynamic gate – Precharge gate while
+ latch 
X
transmission gate latch
Y
0
is opaque
– Evaluate
– When latch becomes
transparent, X falls

 Principle: Charge Sharing

– If Y was low, it shares charge with X
 Solution: Buffer dynamic nodes before driving
transmission gate

VLSI Design Chih-Cheng Hsieh

 Diffusion Input Noise 5- 95

• Circuit • Symptom
– Latch – Q changes while latch
is opaque
– Especially if D comes
from a far-away driver

 Principle: Diffusion Input Noise Sensitivity

– If D < -Vt, transmission gate turns on
0
– Most likely because of power
VDD Q
supply noise or coupling on D D

 Solution: Buffer D locally VDD

weak

VLSI Design Chih-Cheng Hsieh

 Hot Spot 5- 96

• Nonuniform power dissipation (even within overall power

budget)

VLSI Design Chih-Cheng Hsieh

 Minority Carrier Injection 5- 97

• Minority injection caused by forward biased p-n junction

• Solution: Use guard ring to collect the excess minority

VLSI Design Chih-Cheng Hsieh

 Back-Gate Coupling 5- 98

• Dynamic gates drive multiple-input static CMOS gates

• Solution : Drive input closer to the rail

VLSI Design Chih-Cheng Hsieh