Module-I

1. Differentiate between Computer Architecture and Organization. Out of CA and CO.

which one has undergone more change with respect to time? What may be the reason for this?
2. What is the cycle? Show the state diagram for it with and without interrupts. instruction
3. What is interrupt? How is it executed? Show the program flow with interrupts?
4. Draw and explain the interrupt cycle.
5. Using 2’s complement perform the following operations: (-7)+(+5),(-7)-(-6).
6. If Computer A runs a program in 10 seconds & Computer B runs the same program in 15
seconds, how much faster is A than B?
7. Our favorite program runs in 10 seconds on computer A, which has a 4 GHz clock. We
are trying to help a computer designer build a computer B, that will run this program in 6
seconds. The designer has determined that a substantial increase in the clock rate is possible,
but this increase will affect the rest of the CPU design, causing computer B to require 1.2 times
as many clock cycles as computer A for this program. What clock rate do we tell the designer to
target?
8. Suppose we have two implementations of the same instruction set architecture.
Computer A has a clock cycle time of 250 ps and a CPI of 2.0 for some programs, and computer
B has a clock cycle of 500 ps and a CPI of 1.2 for the same program. Which is faster for this
program, and by how much?
9. A compiler is trying to decide between two code sequences for a particular computer.
The hardware designer has supplied the following facts:

CPI for this Instruction class

A B C
CPI 1 2 3

For a particular high-level-language statement, the compiler writer is considering two

code sequences that require the following instruction counts:

Code sequence Instruction counts for Instruction class

A B C
1 2 1 2
2 4 1 1

Which code sequence executes the most instructions? Which will be faster?
What is the CPI for each sequence?

10. Show the IEEE 754 binary representation of the number – 0.7510 in single & double
precision.

11. Convert the following floating-point number (represent in IEEE 754 floating-point format)
to their equivalent decimal number.
11000000100000000000000000000000
12. Add 9.99910 X 101 x 1.61010 x 10 -1 using floating-point addition .
13. Explain Booth’s algorithm for multiplication.

14. Multiply using Booth’s Multiplication algorithm:

i) 7X3
ii) 7x-3
15. Describe the Von-Neumann Architecture.
16. Explain Moore’s law. What are the consequences of Moore’s law?

Answers

1.)

S.NO Computer Architecture Computer Organization

Architecture describes
The Organization describes
1. what the computer
how it does it.
does.

Computer Architecture
Computer Organization
deals with the
2. deals with a structural
functional behavior of
relationship.
computer systems.

In the above figure, it’s

In the above figure, it’s also
clear that it deals with
3. clear that it deals with
high-level design
low-level design issues.
issues.
 Architecture indicates its Where Organization
4.
hardware. indicates its performance.

For designing a computer,

For designing a computer,
an organization is
5. its architecture is fixed
decided after its
first.
architecture.

Computer Architecture is Computer Organization is

6. also called instruction frequently called
set architecture. microarchitecture.

Computer Architecture
comprises logical
Computer Organization
functions such as
consists of physical units
7. instruction sets,
like circuit designs,
registers, data types,
peripherals, and adders.
and addressing
modes.

Architecture coordinates
Computer Organization
between the hardware
8. handles the segments of
and software of the
the network in a system.
system.
Throughout whole generational changes, Computer Organization goes through more
amendments than Computer Architecture. At an abstract level, we make reference to Moore’s
Law then transistor density is doubling every 2 years. Increased density simply results in faster
computing. Moreover, transistors shrank over this period which results in faster clock speeds. As
hardware-level computing has ramped up, allocation of resources is also required to be tunned
over the period. Therefore many reforms have been compensated in Computer Architecture
over the period to keep account of these radical changes at the hardware level.

2.) A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through
a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instructions from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

A program residing in the memory unit of a computer consists of a sequence of

instructions. These instructions are executed by the processor by going through a cycle
for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instructions from memory.

2. Decode the instruction.

3. Read the effective address from memory.

4. Execute the instruction.

https://www.javatpoint.com/instruction-cycle
 Interrupt Cycle:
https://www.ques10.com/p/19373/explain-instruction-cycle-with-interrupts-exec
utio/#:~:text=Interrupt%20Cycle%3A&text=It%20is%20the%20process%20by,the
%20computer%20is%20shut%20down.

3.) The interrupt is a signal emitted by hardware or software when a process or an event
needs immediate attention. It alerts the processor to a high-priority process requiring
interruption of the current working process. In I/O devices one of the bus control lines is
dedicated for this purpose and is called the Interrupt Service Routine (ISR).
When a device raises an interrupt at let’s say process i, the processor first completes the
execution of instruction i. Then it loads the Program Counter (PC) with the address of the
first instruction of the ISR. Before loading the Program Counter with the address, the
address of the interrupted instruction is moved to a temporary location. Therefore, after
handling the interrupt the processor can continue with process i+1. While the processor
is handling the interrupts, it must inform the device that its request has been recognized
so that it stops sending the interrupt request signal. Also, saving the registers so that the
interrupted process can be restored in the future, increases the delay between the time
an interrupt is received and the start of the execution of the ISR. This is called Interrupt
Latency.

https://www.geeksforgeeks.org/interrupts/

4.) Interrupt Cycle

https://www.brightways.org/computer-organization-interrupt-cycle.php

5.) Addition and Subtraction Using 2’s Compliment

https://www.javatpoint.com/addition-and-subtraction-using-2s-complement-i
n-digital-electronics

6.) The performance ratio is 15 10 = 1.5, so A is 1.5 times faster than B.

7.) We denote x as clock cycle on computer A, y as clock rate on computer

B.
x = 10 × 4 × 10^9 , 1.2x = 6 × y. → y = 8 × 109 = 8 GHz.
8.) Assume each computer executes I instructions, so
CPU time = I × 2.0 × 250 = 500 × I ps
CPU time = I × 1.2 × 500 = 600 × I ps
A is faster by the ratio of execution times:
performance A/ performance B = execution time B /execution time A =
(600 × I) / (500 × I) = 1.2

9.)
Sequence 1 : executes 2+1+2 = 5 instructions.
Sequence 2 : executes 4+1+1 = 6 instructions.

Use Formula: Sigma(i=1 to n) CPIi x i

Sequence 1 : (2x1) + (1x2) + (2x3) = 10 cycles

Sequence 2 : (4x1) + (1x2) + (1x3) = 9 cycles.

Sequence 2 is faster even after executing more instructions

CPI = CPU clock cycle / Instruction count

Seq 1 = 10/5 = 2.0

Seq 2 = 9/6 = 1.5

Since Seq 2 takes fewer overall cycles clock but has more instructions it
must have a lower CPI.

10.)

Concept:

IEEE 754 Single Precision has 3 basic components:

Sign:

It takes one bit. 0 represents a positive number while 1 represents a negative number.
Exponent:

It takes 8 bits (signed exponent in excess-127 representation). The exponent field

needs to represent both positive and negative exponents. A bias is added to the actual
exponent in order to get the stored exponent.

Mantissa:

It takes 23 bits. The mantissa is part of a number in scientific notation or a floating-point

number, consisting of its significant digits.

Standard representation for IEEE 754 Floating-Point Standard single precision:

Format:

Single precision like= (-1)s x (1.M)2 x 2E-127

Calculation:

The given number is = -0.75

Take the positive number = 0.75

Binary representation of a (0.75)10= (0.11)2

Normalized form (0.75)10 = (0.11)2 = 1.1 × 2-1

Here, exponent = -1

Excess 127 form of,

E-127 = -1

E=127-1 = (126)10 = (0111 1110)2

Sign= 1 because negative number.

Exponent= (0111 1110)2

Mantissa = 1 ( From normalized number )

Normalized mantissa = 100 0000 0000 0000 0000 0000

IEEE 754 Single Precision (Binary32) Format : 1 01111110

10000000000000000000000

Hence the correct answer is 1 0111 1110 1000 0000 0000 0000 0000 000.

12.)

https://people.utm.my/nur-haliza/files/2021/09/Module-2-Data-Representation-in-CS-v2b
-4-Mac-2021Lstudent-1.pdf

13.)

https://www.javatpoint.com/booths-multiplication-algorithm-in-coa

14.)

https://www.geeksforgeeks.org/computer-organization-von-neumann-architecture/

15.)

Moore's law is the observation that the number of transistors in a dense integrated circuit (IC)
doubles about every two years. Moore's law is an observation and projection of a historical trend.
Rather than a law of physics, it is an empirical relationship linked to gains from experience in
production.

Mathematically, Moore's Law predicted that transistor count would double every 2 years due to
shrinking transistor dimensions and other improvements. As a consequence of shrinking
dimensions, Dennard's scaling predicted that power consumption per unit area would remain
constant.

Microprocessor architects report that since around 2010, semiconductor advancement has slowed
industry-wide below the pace predicted by Moore's law. As a result, much of the semiconductor
industry has shifted its focus to the needs of major computing applications rather than
semiconductor scaling.
Module-II
1. Which addressing mode is used for accessing data stored in an array in memory?
2. “Instruction set of a system is dependent on its system architecture”. Comment.
3. What is the difference between Big-endian and little-endian representation.
4. What are different addressing modes? Explain the working principle with a suitable
example.
5. What are the advantages and disadvantages of register mode.
6. What is instruction sequencing?
7. Differentiate between Pseudo- instruction(directives) and Instructions with examples.
8. How the loops are formed using instructions? Explain with suitable examples.
9. What are subroutines? How subroutines are defined using instructions? State using
examples.
10. What is word length? How the word size is associated with the particular architecture of
a system?
11. Give some examples of (i) Data Transfer (ii) Arithmetic (iii) Logical (iv) Program Control
and(v) I/O operations Instructions

1.) The address of the operand is obtained by adding to the contents of the general register
(called index register) a constant value. The number of the index register and the
constant value is included in the instruction code. Index Mode is used to access an array
whose elements are in successive memory locations. The content of the instruction code
represents the starting address of the array and the value of the index register, and the
index value of the current element. By incrementing or decrementing the index register
different elements of the array can be accessed.

Example: SPIM/SAL - Accessing Arrays

.data
array1: .byte 1,2,3,4,5,6
.text
__start:
move $3, $0 # $3 initialize index register with 0
add $3, $3,4 # compute the index value of the fifth element
sb $0, array1($3) # array1[4]=0
# store byte 0 in the fifth element of the array
# index addressing mode
Done
 2.) An instruction can vary in length depending on the architecture. In x86 systems, the length of
the instruction is typically 1 to 3 bytes (for the opcode), plus a number of bytes needed for
the operands, depending on the addressing mode. additionally, shorter instructions do not
always mean faster instructions. Sometimes a short instruction hides a lot of machine cycles
We can see in the variation in RISC and CISC style processors where the complexity of
instructions is also determined by the architecture.

3.)All computers do not store the bytes that comprise a multi-byte value in the same
order. Consider a 16-bit internet that is made up of 2 bytes. Two ways to store this value
−
● Little Endian − In this scheme, the low-order byte is stored on the starting
address (A) and the high-order byte is stored on the next address (A + 1).
● Big Endian − In this scheme, the high-order byte is stored on the starting
address (A) and the low-order byte is stored on the next address (A + 1).
To allow machines with different byte order conventions to communicate with each
other, the Internet protocols specify a canonical byte order convention for data
transmitted over the network. This is known as Network Byte Order.
By these definitions, a 32-bit data pattern is regarded as a 32-bit unsigned integer. The
"high- Order" byte is the one for the largest powers of 2: 231, ..., 224. The "low-order"
byte is the one for the smallest powers of 2: 27, ..., 20.

Example
0x12674592 in 32-bit representation can be stored as −
4.)
The operands of the instructions can be located either in the main memory or in the
CPU registers. If the operand is placed in the main memory, then the instruction
provides the location address in the operand field. Many methods are followed to
specify the operand address. The different methods/modes for specifying the operand
address in the instructions are known as addressing modes.

Types of Addressing Modes

There are various types of Addressing Modes which are as follows −
Implied Mode − In this mode, the operands are specified implicitly in the definition of
the instruction. For example, the instruction "complement accumulator" is an
implied-mode instruction because the operand in the accumulator register is implied in
the definition of the instruction. All register reference instructions that use an
accumulator are implied-mode instructions.
Instruction format with mode field

Opcode Mode Address

Immediate Mode − In this mode, the operand is specified in the instruction itself. In
other words, an immediate-mode instruction has an operand field instead of an address
field. The operand field includes the actual operand to be used in conjunction with the
operation determined in the instruction. Immediate-mode instructions are beneficial for
initializing registers to a constant value.
Register Mode − In this mode, the operands are in registers that reside within the CPU.
The specific register is selected from a register field in the instruction. A k-bit field can
determine any one of the 2k registers.
Register Indirect Mode − In this mode, the instruction defines a register in the CPU
whose contents provide the address of the operand in memory. In other words, the
selected register includes the address of the operand rather than the operand itself.
A reference to the register is then equivalent to specifying a memory address. The
advantage of a register indirect mode instruction is that the address field of the
instruction uses fewer bits to select a register than would have been required to specify
a memory address directly.
Autoincrement or Autodecrement Mode &minuend; This is similar to the register
indirect mode except that the register is incremented or decremented after (or before)
its value is used to access memory. When the address stored in the register defines a
table of data in memory, it is necessary to increment or decrement the register after
every access to the table. This can be obtained by using the increment or decrement
instruction.
Direct Address Mode − In this mode, the effective address is equal to the address part
of the instruction. The operand resides in memory and its address is given directly by
the address field of the instruction. In a branch-type instruction, the address field
specifies the actual branch address.
Indirect Address Mode − In this mode, the address field of the instruction gives the
address where the effective address is stored in memory. Control fetches the instruction
from memory and uses its address part to access memory again to read the effective
address.
Indexed Addressing Mode − In this mode, the content of an index register is added to
the address part of the instruction to obtain the effective address. The index register is a
special CPU register that contains an index value. The address field of the instruction
defines the beginning address of a data array in memory.

5.)
Advantages of Register Mode.
1. By using addressing modes we can reduce the number of bits in the
addressing field of the instruction.
2. Most addressing modes modify the address field of the instruction.
3. The implied and immediate models need no address field at all.
4. It allows a variety of data processing and data movement instructions to be
designed.

5. It is flexible to access data as per the user's requirements

REGISTER INDIRECT
REGISTER MODE
MODE
Operand is placed in a The operand’s offset is
general-purpose placed in one of the
register. registers.

In register mode, the In register indirect mode,

address field contains the address field contains
the effective address of a reference of effective
the operand. address.

It requires only one It requires two registers

register reference to references to access
access data. data.

No further calculation is Require further

required to perform the calculation to find the
operation. effective address.

Register addressing register indirect

mode is fast. addressing mode is slow.

It is easier to access It is a bit complex to

the data in register access the data in
mode. register indirect mode.
 It uses temporary
variables.

6.)

The order in which the instructions in a program are

carried out. Normally the sequence proceeds in a linear
fashion through the program, and the address of the
instructions is obtained from the program counter in the
control unit. This sequence is interrupted when a branch
instruction is executed; at such a time the address field
of the branch instruction is inserted into the program
counter and the process continues. In the case of an
indirect branch instruction, the memory content referred
to by the address field of the instruction is inserted into
the program counter
7.)
Pseudo Instructions are special commands to the assembler about the positioning of the program,
the address the program should presume to be assembled at, the name of the module, data
declarations, the title and printing options for the program, defining and calling macros, macro
looping and test, and end of source code. Unless a machine instruction is issued, these do not
generate executable code.
The pseudo instructions varied from version to version of the assembler, and higher-level and more
powerful assemblers provided for all of the instructions. All pseudo instructions are 2-5 letters in
length. The following lists the general pseudo instructions available. Some pseudo instructions are
used for conditional assembly or macro processing, and some are only available while processing a
macro.
Computer instruction is a binary code that determines the micro-operations in a
sequence for a computer. They are saved in the memory along with the information.
Each computer has its specific group of instructions.
They can be categorized into two elements as Operation codes (Opcodes) and
Addresses. Opcodes specify the operation for specific instructions. An address
determines the registers or the areas that can be used for that operation. Operands are
definite elements of computer instruction that show what information is to be operated
on.
It consists of 12 bits of memory that are required to define the address as the memory
includes 4096 words. The 15th bit of the instruction determines the addressing mode
(where direct addressing corresponds to 0, indirect addressing corresponds to 1).
Therefore, the instruction format includes 12 bits of address and 1 bit for the addressing
mode, 3 bits are left for Opcodes.

8.)
https://www.educative.io/edpresso/what-are-loops-in-assembly-language
9.)
https://www.geeksforgeeks.org/subroutine-subroutine-nesting-and-stack-memory/
Example -> Stack Memory.
10.)
In computer science, the word length can be defined as the length in bits of the
processors working registers. this usually corresponds to the number of data
inputs/outputs (aka the data bus) that the processor uses in its normal operations(i.e.
the number of bits that a MOV operation affects). The total memory location required to
feed the instruction in memory is called instruction word size. The memory location of
the 8085 microprocessor can accommodate 8-bits of data. To store 16-bits data, they
are stored in two consecutive memory locations (i.e. 2 Bytes).

11.)
Data Transfer Instruction
MOV: Moves value at B to A; Operands (Rd, M); MOV(A, B)
PUSH: Pushes R.P to the stack; PUSH H
POP: Pops the stack to r.p. ; POP H
Logical Instructions
ANA: Performs AND operations; ANA B ⇒ A AND B.
ORA : Performs OR operations; ORA B ⇒ A OR B
Arthematic Instructions
ADD : A= A+R ; ADD B
SUB: A=A-R; SUB B
Program Control Instructions

CMP: Compare two registers; CMP R1,R2

RESET: Reset the processor
TRAP: Highest priority interrupt
INTR: Lowest priority interrupt

12.)
https://www.geeksforgeeks.org/computer-organization-instruction-formats-zero-one-two-
three-address-instruction/

Module – III

1. Explain the difference between Horizontal and Vertical micro-programmed Control Unit.
2. What are the differences between the Hardwired and microprogram control unit.
3. Explain in detail about different instruction types and instruction sequencing.
4. What is Pipelining? What are the major characteristics of a Pipeline?
5. What are the various stages in a Pipeline execution? Explain the various types of
pipeline 2hazards?
6. Why we need an instruction buffer in a pipelined CPU? What are the problems faced in
instruction pipeline and how they are resolved?
7. Define stall .
8. Illustrdo ate the behaviour of four segment instruction pipeline using space-time
diagram.
9. the A non-pipeline system takes 50ns to process a task. The same task can be processed
in a 4– segment pipeline with a clock of 10 ns. Determine speedup ratio of the pipeline
for 100 tasks.
10. Explain how parallel processing improves the performance of multiprocessing
environment?
11. What are the registers necessary to fetch decode and execute an instruction ?

1.)
https://www.geeksforgeeks.org/difference-between-horizontal-and-vertical-micro-progra
mmed-control-unit/
2.)
Set 01 :
https://www.geeksforgeeks.org/difference-between-hardwired-and-microprogrammed-co
ntrol-unit/?ref=rp
Set 02 :
https://www.geeksforgeeks.org/difference-between-hardwired-and-micro-programmed-c
ontrol-unit-set-2/?ref=lbp
3.)
https://educatech.in/instructions-and-instruction-sequencing-in-computer-organization/

4.)
https://www.javatpoint.com/pipelining
5.)
https://www.javatpoint.com/execution-stages-and-throughput-in-pipeline
Pipeline hazards :
https://www.geeksforgeeks.org/computer-organization-and-architecture-pipelining-set-2-
dependencies-and-data-hazard/
6.) Covered in Ques 5
7.)
https://www.geeksforgeeks.org/computer-organization-and-architecture-pipelining-set-3-
types-and-stalling/

8.)

https://www.slideshare.net/prithvisharma9083/pipeline-processing-and-space-time-diagr
am
9.)
https://testbook.com/question-answer/a-non-pipeline-system-takes-50ns-to-process-a-ta
sk--604eedb859d8c471da980409
10.)
https://www.tutorialspoint.com/what-is-parallel-processing
11.)
http://theteacher.info/index.php/fundamentals-of-cs/1-hardware-and-communication/topi
cs/2599-registers-and-the-fetch-decode-execute-cycle#:~:text=The%20way%20register
s%20are%20used,that%20is%20all%20it%20does.

Module -IV

1. Describe the Memory Hierarchy. Compare them in terms of size, speed and cost.
2. Differentiate between SRAM and DRAM.
3. Explain locality of reference with example.
4. Define mapping . What are the three mapping Techniques used in caches?
5. What are the various replacement algorithms.
6. Define auxiliary memory, seek time, rotational time, access time and transfer time.
7. How does the locality of reference help in faster access of memories .
8. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block
size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB.
The number of bits for the TAG field is _____

9. Consider a 4-way set associative cache consisting of 128 lines with a line size of 64
words. The CPU generates a 20-bit address of a word in main memory. The number of
bits in the TAG, LINE and WORD fields are ?
10. Differentiate between auxiliary memory and Cache memory.
1.)
https://www.geeksforgeeks.org/memory-hierarchy-design-and-its-characteristics/
2.)
https://www.geeksforgeeks.org/difference-between-sram-and-dram/
3.)
https://www.geeksforgeeks.org/locality-of-reference-and-cache-operation-in-cache-me
mory/
4.)
https://www.geeksforgeeks.org/cache-memory-in-computer-organization/
5.)
 6.)
Auxiliary Memory
https://www.javatpoint.com/coa-auxiliary-memory
https://www.geeksforgeeks.org/difference-between-seek-time-and-rotational-latency-in
-disk-scheduling/
https://www.geeksforgeeks.org/difference-between-seek-time-and-transfer-time-in-disk
-scheduling/

7.)
Simply put, it increases the likelihood that when the CPU goes to fetch something it will
already be in the cache (a “hit”) as opposed to it not being in the cache and having to take
the “miss,” and therefore the delay, to go to main memory or the next level of cache to
retrieve the content.

The assumption is that when you access some arbitrary memory, locality presumes that
future access will be nearby, and therefore the retrieval logic should go get more than just
the one specified address at a lower cost for retrieving an entire cache line, in hopes that it’s
saving itself additional delay to go back later to get the other nearby data (or instructions,
same thing.)

8.)
https://testbook.com/question-answer/a-4-way-set-associative-cache-memory-unit-wit
h-a-c--5f009fde83ab5c07edbc5ef0
9.)
https://www.geeksforgeeks.org/gate-gate-cs-2007-question-10/
10.)
https://www.geeksforgeeks.org/difference-between-primary-and-secondary-memory/

Module -V

1. What is the importance of I/O interface? Compare the features of SCSI and PCI
Interfaces.
 2. Explain the use of vectored interrupts in processes. Why is priority handling desired in
interrupt controllers? How does the different priority scheme work?
3. What is the difference between a subroutine and an interrupt-service routine? Explain
with suitable example.

4. What is the difference between isolated I/O and memory mapped I/O? What are the
advantages and disadvantages of each?
5. What is cache coherency and how is it eliminated?
6. The approaches of shared memory and message passing both support simultaneous
execution of tasks that interact with each other. Which of these two approaches can
emulate the action of the other more easily? Justify your answer.
7. Give an overview of parallel priority interrupt hardware. Write about two different
approaches for bus arbitration
8. Explain the importance of handshake control for data transfer in asynchronous bus?
9. Explain Flynn’s classification of computers.
10. Explain the term exception. What is Synchronous Bus? Explain.
11. Explain the usage of daisy chains and priority in simultaneous interrupt handling?

12. Discuss the implementation of nested interrupts to handle multiple devices with suitable
example.
13. Explain the method of enabling and disabling Interrupts.
14. With suitable block diagram describe the types of shared memory multiprocessor
architecture and also discuss their major differences.

1.)
https://www.geeksforgeeks.org/io-interface-interrupt-dma-mode/#:~:text=The%20method%20
that%20is%20used,connected%20to%20any%20computer%20system.
https://stackoverflow.com/questions/17339640/difference-between-scsi-and-pci
2.)
In computer science, a vectored interrupt is a processing technique in which the interrupting device
directs the processor to the appropriate interrupt service routine. This is in contrast to a polled
interrupt system, in which a single interrupt service routine must determine the source of the
interrupt by checking all potential interrupt sources, a slow and relatively laborious process.

https://www.geeksforgeeks.org/priority-interrupts-sw-polling-daisy-chaining/

https://cvbl.iiita.ac.in/sks/coa-files/lectures/Lec_12_IO[2].pdf
3.)

Subroutine is a portion of code within a larger program, which performs a specific task and
is relatively independent of the remaining code.

Interrupt Service Routines (ISRs) are to handle hardware interrupts. These routines are not
independent threads, but more like signals. ISR is called if any thread is suspended by an
interrupt

Subroutine runs when you call it. ISR runs whenever a certain signal occurs. (The signal can
be generated by software or hardware.) The big difference is that you know where the
subroutine runs (because you call it). But you do not know when the ISR will be executed.
Your code may run normally when a hardware interrupt occurs and your program jumps to
the ISR. This can happen anywhere in your code (in between two statements or even in the
middle of a complete statement, remember a statement is compiled into multiple assembly
instructions).

Therefore, care must be taken when ISR accesses global variables. A race condition may
occur if ISR and a normal thread touch the same global variable at the same time.