6.

976
High Speed Communication Circuits and Systems
Lecture 13
High Speed Digital Circuits

Michael Perrott
Massachusetts Institute of Technology

Copyright © 2003 by Michael H. Perrott

 High Speed Digital Design in Wireless Systems
Zin
From Antenna PC board Mixer
and Bandpass trace RF in IF out
Filter Zo Package LNA To Filter
Interface

LO signal
VCO
Reference Frequency
Frequency Synthesizer

ƒ Primary application areas

- Divider within frequency synthesizer
- High speed A/D’s and D/A’s in future wireless systems
ƒ Design Issues
- Speed – want it to be fast
- Power – want low power dissipation
- Noise – need to be careful of how it impacts analog circuits
M.H. Perrott MIT OCW
 High Speed Digital Design in High Speed Data Links
Zin
PC board Data
trace
From Broadband In Clock and
Zo Package Amp Data
Transmitter Clk
Interface Recovery

Data Out

Data In Phase Loop Clk Out

Detector Filter
VCO

ƒ Primary application areas

- Phase detector within CDR
- High speed A/D’s and D/A’s in future systems
ƒ Design Issues
-
M.H. Perrott
Same as wireless, but dealing with non-periodic signals
MIT OCW
Note: much of the material to follow can be found in

J. Rabaey, “Digital Integrated Circuits: A Design

Perspective”, Prentice Hall, 1996
 The CMOS Inverter As An Amplifier (From Lecture 5)

vout
M2 M4
vout vin
Rf
(gm1+gm2)(ro1||ro2)
vin
Cfixed
M1 M3
slope = -20 dB/dec
Vbias
(gm1+gm2)Rf

1 f
Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + CRf /2 + Cfixed 1 gm1+gm2
(+Cov1+Cov2) Miller multiplication factor 2πCtotRf 2πCtot

ƒ Small signal assumption allows linearized modeling

ƒ Key metric for speed: gain-bandwidth product (= ft )
- Strive for high transconductance to capacitance ratio ( = f )
- Increase speed by lowering gain (use low valued resistors)
t

- Minimize capacitance for given level of transconductance

ƒ How does digital design differ?
M.H. Perrott MIT OCW
 The CMOS Inverter as a Digital Circuit

Vin
M2 M4
Vout
50%

Vin Cfixed t
M1 M3
Vout tpHL tpLH

Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed

50%

(+Cov1+Cov2) Miller multiplication factor t

ƒ Large signal variation prevents linearized modeling

- We must examine nonlinear behavior of devices
ƒ Key metric for speed: propagation delay
- What device parameters influence this?
- What are the tradeoffs?
M.H. Perrott MIT OCW
 Key Issue for High Speed – Fast Rise and Fall Times
Ipmos Inmos
Slope = Slope =
Ctot Ctot
M2 M2
Ipmos
Vout Vout
Vin Vin Inmos
Ctot Ctot
M1 M1

ƒ For digital circuit, propagation delays primarily set by

rise and fall times
- Rise and fall times set by slew rate
ƒ Slew rate: ratio of driving current to load capacitance
- Faster speed obtained with higher slew rates
- Key performance metric: current drive/capacitance
ƒ Compare with analog: transconductance/capacitance

M.H. Perrott MIT OCW

 Designing for High Speed
Ipmos Inmos
Slope = Slope =
Ctot Ctot
M2 M2
Ipmos
Vout Vout
Vin Vin Inmos
Ctot Ctot
M1 M1

ƒ Design parameters
- Voltage supply (and voltage swing)
- Scaling of NMOS and PMOS devices
ƒ Relative to each other
ƒ In an absolute sense
- Circuit architecture (impacts drive current/capacitance ratio)
ƒ Key focus point: how is drive current and capacitance
influenced by these parameters?
-
M.H. Perrott
Focus on voltage and sizing issues first
MIT OCW
 Impact of Voltage and Sizing on Drive Current
Ipmos Inmos
Slope = Slope =
Ctot Ctot
M2 M2
Ipmos
Vout Vout
Vin Vin Inmos
Ctot Ctot
M1 M1

ƒ Rigorous analysis is difficult

- Transistor goes through different regions of
operation as load capacitance is charged (i.e., cutoff,
triode, saturation)
- Transistor physics is changing over time
ƒ Velocity saturation is becoming an important issue
ƒ We need a simple approach for intuition
- Assume device is in saturation the entire time load
capacitor is being charged
M.H. Perrott MIT OCW
 Examine Device Current in Saturation (from Lec 5)

ƒ We classically assume that MOS current is calculated as

ƒ Which is really

-V corresponds to the saturation voltage at a given

dsat,l
length, which we often refer to as ∆V
ƒ It may be shown that

- If V gs-VT
approaches LEsat in value, then the top equation is
no longer valid
ƒ We say that the device is in velocity saturation
M.H. Perrott MIT OCW
 Analytical Device Modeling in Velocity Saturation (Lec 5)

ƒ If L small (as in modern devices), than velocity

saturation will impact us for even moderate values
of Vgs-VT

- Current increases linearly with Vgs-VT

- Current no longer depends on L!
ƒ Note: above is extreme case of velocity saturation!
- In practice, modern devices operate somewhere
between square law and extreme velocity saturation
M.H. Perrott MIT OCW
 Useful References for Velocity Saturation

ƒ For a physics approach

- See Lundstrom et.al., “Essential Physics of Carrier
Transport in Nanoscale MOSFETS”, IEEE Transactions
on Electron Devices, Jan 2002
ƒ For an engineering model
- See Toh et. al., “An Engineering Model for Short-
Channel MOS Devices”, JSSC, Aug 1988, pp 950-958

ƒ In this class
- We will simply do a quick experimental hack job at
assessing its impact

M.H. Perrott MIT OCW

 Investigate Velocity Saturation Issue for 0.18µ Device
Id versus Vgs
1.4

Id 1.2

Vgs 1
M1

Id (milliAmps)
0.8
W 1.8µ
=
L 0.18µ 0.6

0.4

0.2

0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Vgs (Volts)

ƒ Linear curve for Id versus Vgs

- Velocity saturation is indeed an issue
- How does this impact digital design?
M.H. Perrott MIT OCW
 Impact of Voltage and Sizing On Drive Current

Square Law Device Velocity Saturated Device

ƒ Voltage supply
- Drive current increases with higher drive voltage
ƒ Width
- Current scales proportionally
ƒ Length
- Current scales inversely proportional for square-law device
ƒ No dependence for purely velocity saturated device

M.H. Perrott MIT OCW

 Impact of Voltage and Sizing on Capacitance
Wp Wp
L L
Vout

Vin Wn Cfixed Wn
L L

Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed

ƒ Voltage supply (and voltage swing)

- Has no impact on capacitance (to first order)
ƒ Sizing of NMOS and PMOS devices
ƒ Input capacitance proportional to product of width and
length of transistor

ƒ Junction and overlap capacitance proportional to W

M.H. Perrott MIT OCW

 Designing For High Speed

ƒ Want the highest ratio of drive current to load

capacitance
ƒ Increased supply voltage

Drive current Capacitance

ƒ Increased transistor width

Drive current Capacitance

ƒ Increased transistor length

Drive current or Capacitance

Want high voltage supply and small length to achieve high speed

M.H. Perrott MIT OCW

 Setting of Transistor Width for High Speed

Wp Wp
L L
Vout

Vin Wn Cfixed Wn
L L

Ctot = Cdb1+Cdb2 + Cgs3+Cgs4 + K(Cov3+Cov4) + Cfixed

Ctot = WnCndevices + WpCpdevices + Cfixed

ƒ Intrinsic performance of device not influenced by W

- Current/capacitance ratio (considering only device
capacitance) is constant with changing W (to first order)
ƒ Within circuit, speed is improved by increasing W when
Cfixed is significant with respect to device capacitance
- W should be chosen such that device capacitance equals
or exceeds fixed wiring capacitance
M.H. Perrott MIT OCW
 Relative Sizing of NMOS and PMOS Devices
Ipmos Inmos
Slope = Slope =
Ctot Ctot
Wp Wp
L Ipmos L
Vout Vout
Vin Wn Vin Wn Inmos
Ctot Ctot
L L

ƒ Comparison of NMOS and PMOS current drive

Square Law Device Velocity Saturated Device

NMOS

PMOS

Primary difference – mobility values (µn versus µp)

ƒ Capacitance relationships the same for NMOS and PMOS

M.H. Perrott MIT OCW
 Relative Sizing to Match Propagation Delays
Ipmos Inmos
Slope = Slope =
Ctot Ctot
Wp Wp
L Ipmos L
Vout Vout
Vin Wn Vin Wn Inmos
Ctot Ctot
L L

ƒ Equate drive currents to get same slope when charging

and discharging load capacitance
- Assume minimum L for NMOS and PMOS for high speed
- Choose W values to accommodate difference between
NMOS and PMOS mobility values

ƒ Size PMOS devices 2.5 times larger than NMOS!

M.H. Perrott MIT OCW
 Modeling Propagation Delays with Resistance

α
R p=
µpWp
Vin
Vout
Vin
α Ctot
R n=
µnWn

ƒ We can visualize impact of relative transistor sizing

between NMOS and PMOS by using switched resistances
to represent their current drive
- Choose α parameter to match propagation times of actual
circuit (assume α has same value for NMOS and PMOS)
- We see that increasing mobility or width reduces resistance
ƒ Intuitively illustrates impact of these parameters on drive
current
ƒ To match propagation delays, set Rp = Rn
M.H. Perrott MIT OCW
 Complementary CMOS Logic

In PUN

Out

In PDN

ƒ Composed of pull-up and pull-down networks that are

duals of each other
- Each network composed of NAND (series connection)
and/or NOR (parallel connection) functions
ƒ Advantage
- No static power (except leakage)

M.H. Perrott MIT OCW

 Example: NAND Gate

A B

ƒ Boolean function

- PDN performs NAND operation

- PUN is dual of PDN

M.H. Perrott MIT OCW
 Modeling Dynamic Performance of NAND Gate

A B

ƒ Assume NMOS devices are same size and PMOS

devices are same size
ƒ Modeling of parallel devices (in PUN above) is
straightforward
- Simply represent with parallel switched resistors
ƒ Modeling of series devices (in PDN above) is not
immediately obvious
- We need to do further investigation
M.H. Perrott MIT OCW
 Equivalent Transistor Model of Stacked Transistors
Inmos
Slope = Inmos
Ctot Slope =
Ctot
Vout
Inmos
W
L Vout
Ctot Inmos
Vin W Vin W Ctot
L 2L

ƒ Drive current is created only when both devices are on

- We can hook gates together without loss of generality
- Resulting configuration is equivalent (at least to first
order) to a single device with twice the length
ƒ Issue – if device velocity saturated, what’s the impact?
Square Law Device Velocity Saturated Device (extreme)

M.H. Perrott MIT OCW

 Let’s Do A Test

ƒ In Hspice, simulate the output current of an NMOS

transistor with a given Vgs bias
- Vary the length of the transistor
- Scale the current by the length
ƒ For square law device

- Product independent of length

ƒ For velocity saturated device (extreme case)

- Product increases with length

M.H. Perrott MIT OCW
 Length Normalized Drain Current – 0.18µ NMOS Device
NMOS Drain Current (Multiplied by Normalized
Transistor Length) Versus Transistor Length
1.5

Id length Vgs = 1.8 V

Id*(transistor length)/0.18µm (mA)

0.18µ
Vgs
M1
1
Vgs = 1.5 V
W 1.8µ
=
L length

Vgs = 1.2 V
0.5

Vgs = 1.0 V

Vgs = 0.8 V

0
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
Transistor Length (microns)

ƒ Product is relatively constant – square law behavior for L

M.H. Perrott MIT OCW
 Length Normalized Drain Current – 0.18µ PMOS Device
PMOS Drain Current (Multiplied by Normalized
Transistor Length) Versus Transistor Length
0.6
W 1.8µ
=
L length Vgs = -1.8 V

Id*(transistor length)/0.18µm (mA)

M1
Vgs 0.4

Id length Vgs = -1.5 V

0.18µ

0.2 Vgs = -1.2 V

Vgs = -1.0 V

Vgs = -0.8 V

0
0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55
Transistor Length (microns)

ƒ Product is relatively constant – square law behavior for L

M.H. Perrott MIT OCW
 Back to Dynamic Modeling of Stacked Transistors
Inmos
Slope = Inmos
Ctot Slope =
Ctot
Vout
Inmos
W
L Vout
Ctot Inmos
Vin W Vin W Ctot
L 2L

ƒ Since we can assume approximately square law

behavior with respect to impact of L for 0.18 micron
CMOS

ƒ Model with two switched resistors in series

- Represents the fact that we have half the drive current
M.H. Perrott MIT OCW
 Dynamic Model of NAND Gate

α
R p= Rp Rp
A B µpWp
A B
Y Y

B A
CL
Rn
A α
R n=
µnWn B

Rn

ƒ To match worst case propagation delays

M.H. Perrott MIT OCW

 Another Example: NOR Gate

A B

ƒ Boolean function

- PDN performs NAND operation

- PUN is dual of PDN

M.H. Perrott MIT OCW
 Dynamic Model of NOR Gate

Rp
B
α
R p= B
µpWp

A
Rp
A
Y Y

A B A B
α CL
R n= Rn Rn
µnWn

ƒ To match worst case delays

M.H. Perrott MIT OCW

 Comparing the Dynamic Performance of Gates (Step 1)

NOR NAND
1 1
=
W 5
B A B
Y
1 1
= A
W 5
A
CL
Y

A B B
1 1 CL
=1 =1
W W

ƒ NOR
- Normalize performance by setting NMOS widths to 1
- PMOS widths set to 5 to match propagation delay

M.H. Perrott MIT OCW

 Comparing the Dynamic Performance of Gates (Step 2)

NOR NAND
1 1 1 1 1 1
= = =
W 5 W 2.5 W 2.5
B A B
Y
1 1
= A
W 5
1 1 CL
A
Y =
W 2
A B B
1 1 CL 1 1
=1 =1 =
W W W 2

ƒ NOR
- Normalize performance by setting NMOS widths to 1
- PMOS widths set to 5 to match NMOS propagation delay
ƒ NAND
- Match NOR by setting NMOS widths to 2
- PMOS widths set to 2.5 to match NMOS propagation delay
M.H. Perrott MIT OCW
 Comparing the Dynamic Performance of Gates (Step 3)

NOR NAND
1 1 1 1 1 1
= = =
W 5 W 2.5 W 2.5
B A B
Y
1 1
= A
A: Cin= 6Cα W 5 A: Cin= 4.5Cα
1 1 CL
B: Cin= 6Cα
A
Y B: Cin= 4.5Cα =
W 2
A B B
1 1 CL 1 1
=1 =1 =
W W W 2

ƒ Compare the input device capacitance of each gate

- Proportional to width of devices connected to a given input
- Define C as a capacitance scaling factor
α
ƒ Includes impact of Cox, L, etc.
ƒ We see that the NAND gate is faster than the NOR gate
- Ratio of current drive to capacitance is higher
M.H. Perrott MIT OCW
 Issue – Stacked PMOS Transistors Lower Performance
PUN
NOR NAND
1 1 1 1 1 1
= = =
W 5 W 2.5 W 2.5
B A B
Y
1 1
= A
A: Cin= 6Cα W 5 A: Cin= 4.5Cα
1 1 CL
B: Cin= 6Cα
A
Y B: Cin= 4.5Cα =
W 2
A B B
1 1 CL 1 1
=1 =1 =
W W W 2

ƒ Why is NOR performance worse than the NAND?

- PMOS create dominant portion of capacitive load
- Stacked PMOS require even larger devices
ƒ Can we eliminate the impact of the PMOS devices on
input capacitance (i.e. eliminate the PUN)?
- Could achieve higher speed!
M.H. Perrott MIT OCW
 Technique 1 to Eliminate PUN: Pseudo-NMOS
Example: 3 input NOR gate

Mp

Vout
Y
In PDN A B C

ƒ Benefit
- Substantial reduction in input capacitance – faster speed!
ƒ Negatives
- Static power consumption
- Asymmetric propagation delays (falling edge faster)
- Output logic levels set by ratio of NMOS to PMOS width
ƒ Rule of thumb: Set Rp/Rn to 4 (or more)
ƒ Alternate rule of thumb: Set Wp = Wn/2
M.H. Perrott MIT OCW
 Dynamic Model for Pseudo-NMOS

A: Cin= 1.0Cα 1 1
=
B: Cin= 1.0Cα W 0.5
C: Cin= 1.0Cα
Y
Y
A B C
A B C
1 1 1 CL
=1 =1 =1
W W W

ƒ Arbitrarily choose NMOS width to be 1

- Set PMOS width to be 1/2 according to rule of thumb on
previous slide
ƒ Note that negative edge transition at output is 5 times
faster than the positive edge transition at output

M.H. Perrott MIT OCW

 Comparison of Complementary CMOS vs Pseudo-NMOS
Compementary CMOS NOR Pseudo-NMOS NOR

1 1
=
W 7.5
C

1 1
=
A: Cin= 8.5Cα W 7.5 A: Cin= 1.0Cα
B 1 1
=
B: Cin= 8.5Cα B: Cin= 1.0Cα W 0.5
1 1
C: Cin= 8.5Cα = C: Cin= 1.0Cα
W 7.5
A
Y Y

A B C A B C
1 1 1 CL 1 1 1 CL
=1 =1 =1 =1 =1 =1
W W W W W W

ƒ For same negative transition propagation delay

- Pseudo-NMOS has nearly 1/10 the input capacitance
ƒ In practice, may want to scale up the pseudo-NMOS
sizes to get faster positive transition propagation delay
M.H. Perrott MIT OCW
 The Issue of Static Power Dissipation
Static power >> Dynamic Power
Y

Istatic Idynamic t
Y Static power Dynamic Power
Y
A B C CL

t
ƒ Ratio of dynamic power to static power depends on
transition activity of output
- For low transition activity, static power is dominant
ƒ Could potentially turn off PMOS during quite times?
- For high transition activity, static and dynamic power may
be similar in value
ƒ Pseudo-NMOS can save power due to reduced capacitive
loading
M.H. Perrott MIT OCW
 Sizing PDN Transistors for High Speed

PUN/Load
Y

A
CL
n2
B
Cp2
n1
C
Cp1

ƒ Diffusion capacitance exists on intermediate nodes

- Different effective cap load for each PDN transistor
ƒ Example: transistor C must discharge C , C , C
- Transistor drive compromised by the floating nodes
L p2 p1

ƒ Example: transistor A has reduced drive for Vn2 > 0

ƒ Design tips for highest speed
- Increase the width of devices farthest from output (trans. C)
- Place signals that transition last closest to output (trans. A)
M.H. Perrott MIT OCW
 Technique 2 to Eliminate PUN - DCVSL

Mp2 Mp1

Out Out

In PDN1 In PDN2

ƒ Differential Cascade Voltage Swing Logic (DCVSL)

- Employs differential logic structure
- Faster speed than complementary CMOS
- No static power dissipation
- Great for interface between power supply domains
ƒ Issues
- Slower than Pseudo-NMOS (PMOS gates load output)
- More power than complementary CMOS
M.H. Perrott MIT OCW
 Technique 3 to Eliminate PUN (or PDN): Dynamic Logic
Example: 2 input NOR gate

Φ Φ
Mp
Y
Out
PDN
A B
In PDN

Φ Φ
Me

ƒ Use a clock, Φ, to gate the load and PDN network

- Φ=0
ƒ Precharge the output node
ƒ Shut off current to PDN
- Φ=1
ƒ Turn off the precharge device
ƒ Send current to PDN so that it “evaluates” inputs
M.H. Perrott MIT OCW
 The Pros and Cons of Dynamic Logic
Example: 2 input NOR gate

Φ Φ
Mp
Y
Out
PDN
A B
In PDN

Φ Φ
Me

ƒ Benefits
- High speed (but lower speed than Pseudo-NMOS due to
precharge time requirement)
- No static power, non-ratioed, and low number of transistors
ƒ Issues
- High design complexity – cascading requires care
- Large clock load, minimum clock speed due to leakage
M.H. Perrott MIT OCW
 Increasing Speed By Reducing Voltage Swing
Vin

Vdd
50%

0 t
tpHL tpLH
Vout
Vdd
50%

0 t

ƒ The propagation delay is defined as time between input

and output crossing at 50% amplitude
ƒ We found that increased voltage is beneficial for speed
- Increased V leads to increased drive current to
gs
capacitance ratio
ƒ What if we could keep high drive current to
capacitance ratio AND reduce the swing?
M.H. Perrott MIT OCW
 Impact of Reduced Swing with Same Drive Current
Vin

Vdd
50%

0 t
tpHL tpLH
Vout
Vdd
50%

0 t

ƒ Propagation time reduced!

ƒ How do we reduce the swing AND achieve high drive
current to capacitance ratio?

M.H. Perrott MIT OCW

 Technique 4 to Eliminate PUN: Source-Coupled Logic
Basic building block: differential pair Example: 2 input OR/NOR gate

Load

Load
Load

Load
NOR OR
Vout Vout

Vin Vref A B Vref

ƒ Single-ended version – Vref set by bias network

ƒ High speed achieved through
- Small signal swings
- Leveraging of a fast amplifier structure
ƒ Load can be implemented in a variety of ways
- Resistor: highest speed, but large area
- Diode connected PMOS (or NMOS): slower, but small area
- PMOS in triode region: high speed, but complicated biasing
M.H. Perrott MIT OCW
 Logic Realization Using Differential SCL
2 input AND/NAND 2 input OR/NOR

Load

Load

Load

Load
NAND AND OR NOR

B B B B

A A A A

ƒ Employs differential signaling (no Vref)

- More robust and higher noise margin than singled-ended
version
ƒ Ordering of signals yields AND/NAND versus OR/NOR

M.H. Perrott MIT OCW

 Comparison of Differential SCL to Full Swing Logic
2 input AND/NAND 2 input OR/NOR

Load

Load

Load

Load
NAND AND OR NOR

B B B B

A A A A

ƒ Advantages
- Much faster speed (> 2X with resistor loads)
- Quieter on supplies (good when analog parts nearby)
ƒ Disadvantages
- Static current, need for biasing networks
-
M.H. Perrott
Logic implementation more clumsy
MIT OCW
Registers
 Edge-triggered Registers
Single-Ended Register Differential Register

MASTER SLAVE MASTER SLAVE

LATCH LATCH LATCH LATCH
IN S Q S Q OUT
IN D Q D Q OUT
IN R Q R Q OUT
Φ Φ Φ Φ

Φ Φ Φ Φ

ƒ Achieved by cascading two latches that are

transparent out of phase from one another
ƒ Two general classes of latches
- Static – employ positive feedback
ƒ Robust
- Dynamic – store charge on parasitic capacitance
ƒ Smaller, lower power in most cases
ƒ Negative: must be refreshed (due to leakage currents)
M.H. Perrott MIT OCW
 Static Latches

LATCH
IN Q Q
S Q OUT

IN R Q OUT
Φ Φ
Φ

S R
Φ

ƒ Classical case employs cross-coupled NAND/NOR

gates to achieve positive feedback
ƒ Above example uses cross-coupled inverters for
positive feedback
ƒ Set, reset, and clock transistors designed to have
enough drive to overpower cross-coupled inverters
ƒ Relatively small number of transistors
ƒ Robust
M.H. Perrott MIT OCW
 Dynamic Latches

MASTER SLAVE
Φ Φ
LATCH LATCH

IN D Q D Q OUT IN OUT

Φ Φ Φ Φ

Φ Φ

ƒ Leverage CMOS technology

- High quality switches with small leakage available
- Can switch in and store charge on parasitic
capacitances quite reliability
ƒ Achieves faster speed than full swing logic with fewer
transistors
ƒ Issues: higher sensitivity to noise, minimum refresh
rate required due to charge leakage
M.H. Perrott MIT OCW
 True Single Phase Clocked (TSPC) Latches

Doubled n-C2MOS latch Doubled p-C2MOS latch

LATCH
IN OUT IN OUT
D Q Φ Φ
Φ Φ
Φ IN OUT

ƒ Allow register implementations with only one clock!

- Latches made transparent at different portions of clock
cycle by using appropriate latch “flavor” – n or p
ƒ n latches are transparent only when Φ is 1
ƒ p latches are transparent only when Φ is 0
ƒ Benefits: simplified clock distribution, high speed

M.H. Perrott MIT OCW

 Example TSPC Registers
ƒ Positive edge-triggered version
SLAVE MASTER

IN OUT
Φ Φ
Φ Φ

ƒ Negative edge-triggered version

MASTER SLAVE

IN
Φ Φ
Φ Φ
OUT

M.H. Perrott MIT OCW

 A Simplified Approach to TSPC Registers

ƒ Clever implementation of TSPC approach can be

achieved with reduced transistor count
Positive-edge triggered Negative-edge triggered

Φ Φ

IN OUT
Φ Φ
Φ Φ
IN OUT

Φ Φ

ƒ For more info on TSPC approach, see

- J. Yuan and C. Svensson, “New Single-Clock CMOS
Latches and Flipflops with Improved Speed and Power
Savings”, JSSC, Jan 1997, pp 62-69

M.H. Perrott MIT OCW

 Embedding of Logic within Latches

Φ
LATCH
IN OUT OUT
Logic Function D Q
(NAND,NOR, etc.) IN Φ
Φ PDN

ƒ We can often increase the speed of a logic function

fed into a latch through embedding
- Latch slowed down by extra transistors, but logic/latch
combination is faster than direct cascade of the
functions
ƒ Method can be applied to both static and dynamic
approaches
- Dynamic approach shown above
M.H. Perrott MIT OCW
 Highest Speed Achieved with Differential SCL Latch

Load
Load
OUT OUT

LATCH
IN S Q OUT
IN IN
IN R Q OUT
Φ Φ

Φ Φ

Φ Φ

ƒ Employs positive feedback for memory

- Realized with cross-coupled NMOS differential pair
ƒ Method of operation
- Follow mode: current directed through differential
amplifier that passes input signal
- Hold mode: current shifted to cross-coupled pair
M.H. Perrott MIT OCW
 Design of Differential SCL Latch with Resistor Loads

RL RL

OUT OUT

IN IN

Ibias
Φ Φ

Ibias

ƒ Step 1: Design follower amplifier to have gain of 1.75 to

2 using simulated gm technique from Lecture 5

M.H. Perrott MIT OCW

 Design of Differential SCL Latch with Resistor Loads

RL RL

OUT OUT

IN IN

Ibias
Φ Φ

Ibias

ƒ Step 1: Design follower amplifier to have gain of 1.75 to

2 using simulated gm technique from Lecture 5
ƒ Step 2: For simplicity, size cross-coupled devices the
same as computed above (or make them slightly smaller)

M.H. Perrott MIT OCW

 Design of Differential SCL Latch with Resistor Loads

RL RL

OUT OUT

IN IN

Φ Φ

Ibias

ƒ Step 1: Design follower amplifier to have gain of 1.75 to

2 using simulated gm technique from Lecture 5
ƒ Step 2: For simplicity, size cross-coupled devices the
same as computed above (or make them slightly smaller)
ƒ Step 3: Choose clock transistors roughly 20% larger in
width (they will be in triode, and have lower drive)
M.H. Perrott MIT OCW