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Procedia Computer Science 57 (2015) 757 – 760

3rd International Conference on Recent Trends in Computing 2015 (ICRTC-2015)

Analysis of Interface Charge Using Capacitance-Voltage Method

for Ultra Thin HfO2 Gate Dielectric Based MOS Devices
N. P. Maitya*, R. R. Thakura, Reshmi Maitya, R. K. Thapab, S. Baishyac
a
Department of Electronics & Communication Engineering, Mizoram University(A Central University), Aizawl-796004, India
b
Department of Physics, Mizoram University (A Central University), Aizawl-796004, India
c
Department of Electronics & Communication Engineering, National Institute of Technology, Silchar-788010, India

Abstract

In this paper, we have calculated Flatband voltage (V fb) in terms of interface trap charges, fixed oxide charges and oxide
trapped charges for ultra thin oxide Metal Oxide Semiconductor (MOS) Devices using SiO2 and HfO2 has been
methodically investigated. The interface charges are designed using capacitance-voltage (C-V) method. It indicates that by
reducing the oxide thickness, the interface charges increases linearly. It is originated to be in good agreement with ATLAS
simulation results at p-type doping level of 1 × 1017 cm-3. It has been evaluated that with respect to SiO2 for the same oxide
thickness, HfO2 contributes less to Vfb. Numerical calculations and Analytical solutions are performed by MATLAB and we
simulate the capacitance-voltage (C-V) characteristics of the MOS devices with ultrathin oxide using ATLAS, a
commercially available TCAD tool from SILVACO. The tool has investigated the effect on C-V characteristics of different
oxide thickness of SiO2 and HfO2. Excellent agreement was observed over a wide range of oxide thickness for the
materials.

© 2015The
© 2015 TheAuthors.
Authors. Published
Published by Elsevier
by Elsevier B.V.is an open access article under the CC BY-NC-ND license
B.V. This
Peer-review under responsibility of organizing committee of the 3rd International Conference on Recent Trends in
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of organizing committee of the 3rd International Conference on Recent Trends in Computing 2015
Computing 2015 (ICRTC-2015).
(ICRTC-2015)

Keywords: High-k; MOS; ATLAS; Interface Charge.

* Corresponding author. Tel.: +91 9436353171.

E-mail address: [email protected]

1877-0509 © 2015 The Authors. Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license
(http://creativecommons.org/licenses/by-nc-nd/4.0/).
Peer-review under responsibility of organizing committee of the 3rd International Conference on Recent Trends in Computing 2015 (ICRTC-2015)
doi:10.1016/j.procs.2015.07.470
758 N.P. Maity et al. / Procedia Computer Science 57 (2015) 757 – 760

1. Introduction

Aggressive scaling of MOS devices led to the replacement of conventional silicon dioxide and hence the
integration of high-k dielectric materials into MOS devices. But, replacing SiO2 by high-k materials brought
some serious challenges. This is because, although high-k materials offer higher capacitance, high-k materials
often suffer from poor electrical quality of the dielectric-semiconductor interface and are often associated with
lower dielectric breakdown voltages and decreased lifetimes. Moreover, due to scaling, it has become very
significant to consider the effect of generated traps in Si- SiO2 junction [1]. The use of high-k gate dielectric is
apt to generate a large number of interface traps at the surface channel and oxide trap charges in the gate
dielectric bulk of MOS transistors, which would result in the degradation of device electrical characteristic.
Among the high-k dielectric materials, the charge trapping behavior of the HfO2 gate stack under constant
voltage stressing exhibits an improved interface quality and high dielectric reliability. Further, due to the
presence of the oxide charges and the work function difference that exists in practice, an ideal MOS device
does not agree with experimental results. It was shown from the early studies of the MOS devices that the
threshold voltage VThand the flat band voltage Vfb could strongly be affected by these charges. Silicon dioxide
is often treated as an ideal insulator, where there are no traps or states at the interface of silicon and silicon
dioxide. But in real devices, the silicon/silicon dioxide interface and bulk silicon dioxide is far from electrically
neutral. These may be caused by positive or negative charges at the silicon/silicon dioxide interface or by
mobile ionic charges and fixed charges trapped within the oxide and itself, which are often created during the
fabrication process. The interface states are located at or very close to the semiconductor/oxide interface with
energy distributed along the bandgap of the semiconductor [2-3]. Electrons or holes get trapped in these states
and act like charges at the interface. There are three types of oxide charges associated with the SiO 2-Si system.
They are: Fixed oxide charge, Mobile oxide charge, and Oxide trapped charge [4]. All of these charges are very
much dependent on the device fabrication process. The simplest and most widely used method for measuring
oxide charge density is to infer this density from the voltage shift of a C-V curve. The most important property
of the MOS capacitor is that its capacitance changes with an applied DC voltage. As a result, the modes of
operation of the MOS capacitor change as a function of the applied voltage. As a DC sweep voltage is applied
to the gate, it causes the device to pass through accumulation, depletion, and inversion regions [5].

2. Theoretical Analysis

When an external voltage ୋ is applied to the gate and the substrate, it is shared between the voltage across
the oxide ୭୶ the surface Potential ɔୗ  and the work function difference ‫׎‬୫ୱ  between the metal and the
substrate. Thusୋ ൌ ୭୶ ൅  ɔୗ ൅  ‫׎‬୫ୱ . Also three charges get induced in the MOS. The charge neutrality
condition requires that ୋ ൅   ୓ ൅   ୗ ൌ Ͳ. Where  ୋ is the gate charge per unit area due to ୋ applied to the
gate,  ୓ is the effective interface charge in the oxide interface and the  ୗ is the semiconductor charge induce
in the silicon under the oxide. A nonlinear relation between flat band voltage and oxide thickness is given by
[6],

ொ೑ ାொ೔೟ ሺ‫׎‬ೞ ሻ ఘ೚ೣ

ܸ௙௕ ൌ  ‫׎‬௠௦ െ  ‫ݐ‬௢௫ െ  ‫ ݐ‬ଶ (1)
ఌ೚ೣ ఌ೚ ଶఌ೚ೣ ఌ೚ ௢௫

Where,  ୤ is the fixed charge density,  ୧୲ ሺ‫׎‬ୱ ሻ is interface charge density which is a function of surface
potential, ɏ୭୶ is oxide trap charge density, – ୭୶  is oxide thickness and ε୭୶ is the permittivity of oxide material.
The relation can be made linear by removing square term of thickness because we are taking ρ ox as negligible.
Now for  ୭ ൌ ͷ ൈ ͳͲଵ଴  , ୊୆ has been calculated for different oxide thickness of 1nm to 10 nm. From our
assumption  ୭ can be calculated from the slope of graph. In the high frequency capacitance method,
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capacitance is measured as a function of gate bias with frequency fixed at high enough value so that interface
traps do not respond. At high frequency the total capacitance is given with Cit (ω) = 0 (because ω = 2πf is too
large for any ac response of interface traps). That is, capacitance at high frequencies CHF is given by, ୌ୊ ൌ
ሾୱ ୓ଡ଼ ሿΤሾୱ ൅ ୓ଡ଼ ሿ. The High Frequency Capacitance of the MOS capacitor will be same as that of an ideal
one without interface traps provided that semiconductor capacitanceǡ ୱ is the same. Where ୓ଡ଼ is the oxide
capacitance. C-V curve is measured at a constant frequency, but now a frequency so low that interface trap
response is immediate. So, ሾͳΤ୐୊ ሿ ൌ ሾͳΤ୓ଡ଼ ሿ ൅ ሾͳΤሼୱ ൅ ୧୲ ሽሿ . Where, ୐୊ is the capacitance at low
frequency measured at gate bias ୋ . Solving the equation for ୧୲ yields, ୧୲ ൌ  ሾሺͳΤ୐୊ ሻ െ ሺͳΤ୓ଡ଼ ሻሿିଵ െ
ୱ .Where, ୓ଡ଼ can be measured in strong accumulation. We know, ୱ ൌ ሾሺͳΤୌ୊ ሻ െ ሺͳΤ୓ଡ଼ ሻሿିଵ , so ୧୲ [7]
can be determined by,
ଵ ଵ ିଵ ଵ ଵ ିଵ
‫ܥ‬௜௧ ൌ ቀ െ ቁ െቀ െ ቁ (2)
஼ಽಷ ஼೚ೣ ஼ಹಷ ஼೚ೣ

Interface charge densities, ୧୲ can be measured by୧୲ ൌ ሾ୧୲ Τ“ଶ ሿ. Where q is the electronic charge. So, ୧୲
can be expressed from equation (2) is,
ଵ ଵ ିଵ ଵ ଵ ିଵ
‫ܦ‬௜௧ ൌ ൤൜ቀ െ ቁ െቀ െ ቁ ൠൗ‫ ݍ‬ଶ ൨ (3)
஼ಽಷ ஼೚ೣ ஼ಹಷ ஼೚ೣ

3. Results & Discussions

The p-substrate Silicon based MOS devices have been analyzed consisting of SiO 2 (k = 3.9) along with
high-k dielectric material, HfO2 (k = 22). These materials were considered for different oxide thickness at p-
type doping level of ͳ ൈ ͳͲଵ଻  ିଷ . The variations of magnitude of the Vfb as function of tox for SiO2 and high-
k material theoretically and by ATLAS simulation are shown in figure 1 and 2 respectively.

Fig. 1. Vfb vs. Oxide thickness for SiO2 and HfO2 materials in Fig. 2. Vfb vs. Oxide thickness for SiO2 and HfO2 materials in
MATLAB (Theoretical) ATLAS (Simulation)

The Vfb of the samples indicated negative value due to the existence of deep donor type surface states and
positive interface charges. This clearly indicates the presence of a number of parasitic charges at the interface.
The deviation of simulated result from the theoretical result was found due to the high dielectric value of the
760 N.P. Maity et al. / Procedia Computer Science 57 (2015) 757 – 760

materials. The interface charge Qit present in each of the MOS capacitor was 5 × 1010 C at the interface given in
ATLAS simulation. The interface charge Qit obtained from theoretical result is given below (see Table 1):

Table 1. Qit values for SiO2 and HfO2

Materials Qit1 Qit2 Qit3 Qit4 Qit (Average)

SiO2 5.20 × 10 10
5.23 × 1010 5.22 × 1010 5.22 × 1010 5.21 × 1010
HfO2 6.8 × 1010 9.0 × 1010 10.1 × 1010 13.4 × 1010 9.82 × 1010

After performing simulation in ATLAS and calculating the slope of the graph from Fig. 1 and Fig. 2 we find
that the interface charge was almost same as we have provided in the ATLAS simulation. But there has been
increase in interface charge as SiO2 is replaced by High-k material. The interface charge is found to be more in
case of HfO2 than SiO2 because of the larger value of dielectric constant. The increase in interface charge
reveals that introducing high-k in MOS decreases the interfacial attachment between silicon and oxide.

4. Concussions

The flatband voltage of SiO2 and HfO2 indicated negative value due to the existence of deep donor type
surface states and positive interface charges. The interface charge densities have been calculated using C-V
method and it has been found that as the thickness of the oxide is reduced, the interface trap density increases
and greater value has been found in the case of for HfO2. The increase in interface charge reveals that
introducing high-k in MOS decreases the interfacial attachment between silicon and oxide.

Acknowledgements

The authors are highly indebted to Department of Science and Technology (DST), Ministry of Science and
Technology, Govt. of India for supporting this technical work.

References

1. Stesmans A, Afanas' ev VV. Undetectability of the point defect as an interface state in thermal. J. Phys.: Condens. Matter 1998; 10:
L19-L25
2. Wilk GD, Wallace RM, Anthony JM. High-K dielectrics: Current status and materials properties considerations. J. of Applied Physics
2001; 89: 5243-5275.
3. Uren MJ, Brunson KM, Hodge AM. Separation of two distinct fast interface state contributions at the Si/SiO2 interface using the
conductance technique. Appl. Phys. Lett. 1992; 60: 624-625
4. Maity NP, Maity R, Thapa RK, Baishya S. Study of Interface Charge Densities for ZrO2 and HfO2 Based Metal Oxide Semiconductor
Devices. Advances in Material Sciences and Engineering 2014; 2014: 1-6.
5. Haneji N, Vishnubhotla L, Ma TP. Potential fluctuations due to Pb centres at the Si/SiO2 interface. Appl. Phys. Lett. 1991; 59: 3416-
3418
6. Maity NP, Kumar A, Maity R, Baishya S. Analysis of Flatband Voltage for MOS Devices Using High-k Dielectric Materials.
Procedia Material Science 2014; 5: 1198-1204
7. Nicollian EH, Brews JR. MOS (Metal Oxide Semiconductor) Physics and Technology, New York: Wiley; 1982.