A B C D E

Vinafix.com
1 1

ZZZ

PCB LA-H351PR10 REV A00 M/B

DAB0004H010
PCB@

Coffee Lake-H 45W 2

CNL PCH-H with nVIDIA N18E

REV : 1.0 (XA00)
2019.04.12

@ : Nopop Component
EMI@,ESD@,RF@ : EMI/ESD/RF part
3 3

CONN@ : Connector Component

@EMI@,@ESD@,@RF@ : Total debug Component

Layout Dell logo

4 4

COPYRIGHT 2015
ALL RIGHT RESERVED
REV: X00
PWB: XXXXX Security Classification Compal Secret Data Compal Electronics, Inc.
DATE: 1450-06 Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P001-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Wednesday, August 21, 2019 Sheet 1 of 109

A B C D E
 A B C D E

mDP
connector
P.39 DP 1.4
PEG(Gen3)x8
Block Diagram
nVIDIA GPU
GDDR5*8
port8~port15 Fan control
Max-P: NCT7718W
N18P-G1, W83L771AWG-2
HDMI2.0
HDMI
connector
P.40
Vinafix.com N18E-G1
Max-Q :
1
N18E-G2 1

, N18E-G3 Intel CPU Memory Bus

Dual Channel P.23-26 DDR4 on Board 16GB
Coffee Lake-H_R
P.27-37
1.2V DDR4
DDR4 x16 DDR4 x16 DDR4 x16 DDR4 x16
8+2
(2666) MHz
2GB 2GB 2GB 2GB
eDP 1.2 x4 Lane
eDP panel BGA 1440 DDR4 x16 DDR4 x16 DDR4 x16 DDR4 x16
45W 2GB 2GB 2GB 2GB
P.38

CIO/USB3.1 DP 1.2(DDI 1) x4 Lane

USB3.1 Thunderbolt
TypeC USB PD I2C Alpine Ridge SP DP 1.2(DDI 2) x4 Lane
connector 2 TPS65982DC USB2.0
P.50 P.06-13
P.42-43
P.50
PEG(Gen3)x4
port4~port7 DMI x 4

P.62-63
USB2.0 port4
AlienFX / ELC , STM32F070CB
PCIe re-driver
DS80PCI402
Caldera P.74
USB2.0 port7 P.38
2 2

connector
USB3.0 port8 Digital camera(with digital MIC)
USB2.0 port3
USB3.1 port4
USB Type-A *1 , left side P.73
P.74
USB2.0 port1
USB3.1(Gen1) with power share IO/B 1

PCI-E port 17~20 PCI-E X4

USB3.1 por5 P.73
USB2.0 port2
USB Type-A *2, right side
USB3.1 port6
USB3.1(Gen1) IO/B 2
USB2.0 port2
G-Sensor I2C
FUNCTION/B LSM6DSLUSTR
PCH-H
P.65

RJ45 2.5 Gigabit LAN PCI-E port15 BGA874(HM370)

IO/B 1 connector Killer E3000 P.73
USB2.0 _B

USB2.0 port9
PCI-E port16 Tobii (15&17) P.65
3
WLAN+BT 12x16 3

IO/B 2 8265 USB2.0 port14

USB2.0 port10 MCU/B
P.73
Per key KB P.64

SSD1 M.2 2280 PCI-E port 9~12 P.31 digital MIC

PCIe+SATA SATA3.0 port 4
P.68
Audio codec
Realtek Headphone/MIC Global headset
SSD2 M.2 2280 PCI-E port 21~24 HD Audio ALC3281 combo JACK
PCIe
P.68
P.14-20
P.82 P.87 P.89
SPI ROM SPI P.73
DC in dGPU 128Mbit
Battery 1.00V Core IO/B 1
P.15

P.84 P.86 P.84 I2C ESPI BUS Speaker

3V/5V 2.5V Charger
Touch pad KC3810
P.85 P.89-92 P.97-98 P.63 P.59
ENE KB9542
System CPU dGPU
4 4

1.2V Vcore 1.35V

P.58

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cable Routing Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-F551P 0.1

Date: Thursday, May 30, 2019 Sheet 2 of 109

A B C D E
 A

Board ID table HSIO USB3.1 PCIe SATA3 Function USB2 Function

NV PCB Revision
0 0 ohm EVT-1 PCH-H CM246 0 1 1 JUSB3 left side
1 12k ohm DVT-1 1 2 2 JIO right side USB2
Board ID Table for AD channel 2 15k ohm DVT-2
3 20k ohm Pilot 2 3 3 Caldera
Vcc 3.3V +/- 1%
Ra 100K +/- 1%
Vinafix.com 3 4 4 ELC
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 4 5 JIO right side USB1 5
0 0 0.000V 0.000V 0.300V 0x00 - 0x13
1 12K +/- 1% 0.347V 0.354V 0.360V 0x14 - 0x1E 5 6 JIO right side USB2 6
2 15K +/- 1% 0.423V 0.430V 0.438V 0x1F - 0x25 6 7 1 JUSB3 left side 7 Camera
3 20K +/- 1% 0.541V 0.550V 0.559V 0x26 - 0x30
4 27K +/- 1% 0.691V 0.702V 0.713V 0x31 - 0x3A 7 8 2 Caldera 8 JIO right side USB1
NVIDIA
5 33K +/- 1% 0.807V 0.819V 0.831V 0x3B - 0x45 Graphic 8 9 3 9 Tobii
6 43K +/- 1% 0.978V 0.992V 1.006V 0x46 - 0x54
7 56K +/- 1% 1.169V 1.185V 1.200V 0x55 - 0x64 9 10 4 10 Per Key
8 75K +/- 1% 1.398V 1.414V 1.430V 0x65 - 0x76 10 5 11 Thunderbolt PD
9 100K +/- 1% 1.634V 1.650V 1.667V 0x77 - 0x87
11 6 12
Voltage Rails 12 7 13
Power Plane Description S0 S3 S4 / S5
VIN Adapter power supply N/A N/A N/A 13 8 14 Bluetooth
BATT+ Battery power supply N/A N/A N/A 14 9
+19VB AC or battery power rail for power circuit N/A N/A N/A
+VCC_CORE Core voltage for CPU ON OFF OFF 15 10 JSSD3 , 2280
+VCC_GT Sliced graphics power rail SATA/PCIe x4 Symbol Note :
ON OFF OFF 16 11 0a
+0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF
+1VALW System +1VALW power rail ON ON ON* 17 12 1a
+1V_PRIM System +1VALW power rail ON ON ON* 18 13 0b
Digital Ground
+VCCIO +1.0VS IO power rail ON OFF OFF
+VGA_PCIE +1.0VS power rail for GPU ON OFF OFF 19 14 1b Analog Ground
1
+MEM_GFX +1.5VS power rail for GPU ON OFF OFF 20 15 2 LAN
1

+1.2V_VDDQ DDR-IV +1.2V power rail ON ON OFF

+1VS_VCCST +1.0V power rail for CPU ON ON OFF 21 16 3 WLAN PCIE CLK table
+1VS_VCCSTG +1.0VS power rail for CPU ON OFF OFF 22 17 4 PCIE CLK PCB Revision
+3VALW System +3VALW always on power rail ON ON ON* 0 GPU
+3VLP +19VB to +3VLP power rail for suspend power ON ON ON 23 18 5 TBT PCIE X4 1 SSD1
+3VALW_DSW +3VALW power for PCH DSW rails ON ON ON* 24 19 2 NA
+3V_LAN +3VALW power for LAN power rails ON ON ON* 3 TBT
+3VS System +3VS power rail ON OFF OFF 25 20 4 LAN
+1.8VALW +1.8VALW power rail for PCH ON OFF OFF 26 21 5 WLAN
+3VGS +3VS power rail for GPU ON OFF OFF 6 caldera
+5VALW System +5VALW power rail 27 22 7
ON ON ON* JSSD2 , 2280 SSD2
+5VS System +5VS power rail ON OFF OFF 28 23 PCIe x4
+3VL_RTC RTC power ON ON ON
+VCC_SA System Agent power rail ON OFF OFF 29 24
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF

Config
Config-X76_Memory Config-X76_Vram
LM-431AG631L01: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I5-9300H@/HM370 B@/N18EG0@/ LM-X7681531L10:MCN16G@/DDP16G@/Micron_16G@ LM-X7681531L02:Vram Micron@/MCNGD8@
LM-X7681531L09:SAM16G@/DDP16G@/Samsung_16G@ LM-X7681531L01:Vram Samsung@/SAMGD8@
LM-X7681531L11:HYX16G@/DDP16G@/Hynix_16G@ LM-X7681531L55:Vram Micron@/MCNGD6@
LM-431AG631L02: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG0@/ LM-X7681531L06:SAM8G@/SDP8G@/Samsung_8G@ LM-X7681531L54:Vram Samsung@/SAMGD6@
LM-X7681531L07:MCN8G@/SDP8G@/Micron_8G@
LM-431AG631L03: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG1@/ LM-X7681531L08:HYX8G@/SDP8G@//Hynix_8G@

LM-431AG631L04: 47@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG1@/

LM-431AG631L05: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9850H@/HM370 B@/N18EG2@/

LM-431AG631L06: 47@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG2@/

LM-431AG631L09: 47@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I9-9880H@/HM370 B@/N18EG2@/

LM-431AG631L07: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG3@/

LM-431AG631L08: 047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I9-9980HK@/HM370 B@/N18EG3@/

LM-431AG631L51:047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG0@/

LM-431AG631L52:047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I7-9750H MP@/HM370 SSPEC@/N18EG1@/

Security Classification Compal Secret Data Compal Electronics, Inc.
LM-431AG631L53:047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I9-9880H@/HM370 B@/N18EG2@/ 2017/05/15 2018/02/05 Title
Issued Date Deciphered Date
LM-431AG631L54:047@/047U@/128@/17@/PCHES@/PCB@/PERICOM@/CMC@/LCDTESTEC@/NV@/QX1@/UU5@/UT4@/EC@/BID_DVT2@/RTD3@/I9-9980HK@/HM370 B@/N18EG3@/
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P003-Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 3 of 109

A
 5 4 3 2 1

IMVP_VR_ON SIC632CDT1GE3
ISL95855HRTZ +VCC_CORE
(PU502)
(PU500) (PU503)
(PU504)

SIC632CDT1GE3
+VCCGT
(PU507)
(PU510)

D
(PU511)Vinafix.com
SIC531CDT1GE3
+VCCSA

8880mA (PJP200 PJP201) APE8937GN2

+1.2VP +1.2V_DDR +1.2V_VCCPLL_OC
SYSON
(UZ21)
RT8207MZQW
(PU200) 1470mA (PJP202)
+0.6VSP +0.6VS JDIMM1/2

PCH_PWR_EN TPS51212DSCR 9410mA (PJP300 PJP302) SYSON TPS22961

ADAPTER +1VALWP +1VALW +VCCST
(PU300) (U19)
SUSP# TPS22961
+VCCSTG
(U20)
NVVDD_EN NCP81278 58000mA
(PU6100) +NVVDD1
CHARGER
BQ24780SRUYR NVVDD2_EN NCP81278 28000mA
(PU700)
B+ (PU6200) +NVVDD2
F75305M
BQ24780S (U2407)
SUSP# SY8286RAC 3740mA (PJP505)
+VCCIOP +VCCIO
(PU509) PI6CEQ20200LIEX
(UM4)
BATTERY

+1.0VS_VGA_PGOOD
DS80PCI402
(UM8)
FBVDD/Q_EN RT8812AGQW 18200mA (PJP8201 PJP8202)
C +1.35VS_VGAP +1.35VS_VGA C
(PU8200) (R2)
+3VS_TOUCH (JPWR)

RM34 +3VS_WLAN_NGFF NGFF Conn.

(JWLAN)
Fuse +INV_PWR_SRC +3VS

KB9022QD
+EC_VCCA (RV81) JEDP Conn.
(UE5) +VDD_TOUCH
(JEDP)
KC3810
(UE6)
3/5V_B+ TPS51225CRUKR 10010mA (PJP102) PCH_PWR_EN SY6288C20AAC (J6)
+3VALWP +3VALW +3VALW_PCH +3V_PCH
(PU100) (U18)
AP2337SA-7
+3VS_DP JDP Conn.
SUSP#
(UV18)
AOZ1331 (J5)
(U17)
SKY-H-PCH
EN_W OL# (UH1H)
SY6288D20AAC +LAN_IO E2400-BL3A-R
(UL2) (UL1)
SODIMM Conn.
(JDIMM1/2)
RT53 +3VALW_PD

3V_F383_ON
SN1508014
SY6288C20AAC (UT4)
+3.3V_ELC
(UE9)
(RA5)
(RT95) +3.3V_1.8V_DVDD_IO ALC3266
+3VS_TBT ALPINE-RIDGE ALC1309
(UT1)
(RA11) (UA1, UA4)
B (RT97) +3.3V_1.8V_DVDD B
+3VS_TBT_SX

PCH_ENVDD JEDP Conn.

SY6288C20AAC +LCDVDD 3V3_SYS_EN SY6288D20AAC
(JEDP) +3V3_SYS
(UV17) (UG14)
SUSP#
TPS22961 NGFF Conn.
+3VS_SSD
(U16) (JSSD1/2/3)

(PJP1301) SY8003DFC (PJP1300)

+2.5V_MEMP +2.5V_MEM
(PU1300)

3000 mA
3/5V_B+
10770mA (PJ800) SY8286RAC (PJP801)
TPS51225CRUKR +5VALWP +1.05VS_VGAP SI3456DDV
(PU800) +PEX_VDD +5VS_TP_LED JTP Conn.
(PU100) (PJP100 PJP101) PEX_VDD_EN (Q2409)
+5VALW
USB_PW R_EN SY6288C20AAC
+5V_USB_PWR2
(UU3) APL3517AI
+5VS +HDMI_5V_OUT JHDMI Conn.
(UV22)
PWRSHARE_EN_EC# TPS2546RTER
+5V_USB_PWR1
(UU1)

USB_PW R_EN
(RA3)
TPS25810RVCR +5V_PVDD ALC3266
+5V_USBC_VBUS ALC1309
(UU7)
PQ3 B+_BIAS LA21 +PVDD
(RA8) (UA1, UA4)
+5VA
SUSP# AOZ1331
5VS_GATE (U17)
ALC1309 RT56 +5VALW _PD UT4,PD +TBTA_VBUS
A (UA4) A

1V8_AON_EN
1V8_EN RT8061AZQW (PJP803)
+1.8VGSP +1.8VALW +1V8_AON N17E-G1 GB4-256
1V8_EN
(PU802) AOZ1331
(UG9)
(UG12)
+1V8_AON +1V8_MAIN N17E-G1 GB4-256
1V8_MAIN_EN (UG9)
ALC3266
ALC1309
LA4
+CODEC_AVDD2
(UA1, UA4)
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P004-Power Map
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Siz e Document Number Re v
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 4 of 109
5 4 3 2 1
 5 4 3 2 1

+3VS PR802

+3VS PR8204

1V8_EN +1.8VALW
15 PU802 G0 +1.35VS_VGA_PGOOD

+5VALW +1.35VS_VGA
G6A +1.0VS_VGA_PGOOD PU8200
PR14 FBVDD/Q_EN G7
16 PR8212
20K RT8812A
DG5
PQ3 B+_BIAS GPU_GC6_FB_EN FBVDD/Q_EN
SI3457CDV PR8216

D
PMOS
Vinafix.com 123
H_VCCST_PWRGD
15
RH154 H13 SOC
+1.0VS_VGA_PGOOD
D

CPU1 OVERT#
DG5 +3VS PR821
10
+1.0VS_VGA_PGOOD
Will Modify 9 G6A
DGPU_PWR_EN ME_SUS_PWR_ACK 11 G5A NVVDD2_PGOOD
1 71 NVVDD1_PGOOD +PEX_VDD
BD19 DGPU_PWROK PR801 PU800
AJ44 SY8286 G6
ACIN1_AV_IN 7a AC_PRESENT PEX_VDD_EN
ACIN 110 110 BB15 17 PR823
NVVDD2_PGOOD
DG6 G5A
POK PM_SLP_SUS# 8
38 BB13 AJ39 13
NVVDD_EN NVVDD2_EN
PR6230 PU6200
+NVVDD2
GPU_GC6_FB_EN NCP81278 G5
9 AW27 BB5 G4A NVVDD1_PGOOD 1.8VS_PGOOD
PBTN_OUT# PR6201
106 AT13
ACIN G0A
12 @ +3V3_SYS
PM_SLP_S5# UE10 Will Modify PR6107
A5 B6 14 BA13 DG3 OVERT#
A1
7
14
KC3810
AC VIN 5 A2 +3VALW PM_SLP_S3# NVVDD1_PGOOD
6 AW15 G8 DG3 G4A
MODE B+ PU100 +5VALW
PU700
BQ24780SRUYR TPS51225 13
CHARGER CRUKR SUSACK# 9 +1.35VS_VGA_PGOOD NVVDD1_EN
BATT+ 97 BB19 NVVDD_EN
+3VLP,VL UE5 19 PR6131
A3 B3 EC9022QD PCH PU6100 +NVVDD1
G4
18 SYS_PWROK UH1 CLKREQ#_GPU PEX_CLKREQ#
G3 +3V3_SYS 1.8VS_PGOOD
PR6103
NCP81278
DC 74 AY1
MODE BC24 QG5 BL26 G0A
B1 @
B2 VCOUT0_PH# 7
BATT+ PQ703 PCH_DPWROK Will Modify
104 127 AV11 GPU
NMOS
C UG9 20
3V3_SYS_EN
UG14
+3V3_SYS
G3 C

EC_RSMRST # 10
A4 B5 100 BA11
G2 +1V8_MAIN 10K SY6288
112 PG515
EC_ON
19
PCIRST # TC7SH08FU PCH_PLTRST#
A6 B4 13 4 BB27 1V8_MAIN_EN +1V8_MAIN
SW1 (UH3) G2
ON/OFFBTN# G9 1V8_AON_EN UG12
+3VALW +1VALWP_PGOOD 22 +1V8_AON
PR301 DGPU_HOLD_RST # SYS_PEX_RST_MON#
BE2 G1
114 AL36
PCH_PWR_EN 9 TPS512212 +1VALW
107 UG10 G10 1V8_MAIN_EN G1A
3 (PU300) BB27 PCH_PLTRST# BE1

SY6288C20AAC +3V_PCH
(U18) +1V8_AON G1
17
PCH_PWROK
32 AW11
+1VALWP_PGOOD
122 KB_RST#
2 AT17

73 PM_SLP_S4# BD15
13 SM_PG_CT RL G0 G1 G2 G4 G5 G6 G7
+2.5V_MEMP BT13
7
SY8003DFC
(PU1300)
UC1 GPU power on
121 101 116 95 15

SYSON TPS22961DNYR +VCCST

Compal Net
(U19) 13b
15
13a G1
+1.8VS_AON
VR_PWRGD
IMVP_VR_ON

SYSON 8 +1.2VP BH29

B RT8207MZQW BH31 G2 B

SM_PG_CT RL
(PU201) +1.8VS_MAIN Compal Net
15 7 +0.6VSP BH32
15a
G1

SVID Bus
14a +3V3_SYS G3 +1.8VS_AON

SUSP# AOZ1331 +3VS

16 (U17)
+NVVDD1 G4 G2
+5VS, +3VS
+1.8VS_MAIN

SUSP# SY8286RAC +NVVDD2 G5

(PU509)
+VCCIO G3
+3V3_SYS
+PEX_VDD G6
SUSP# APE8937GN2
(UZ21)
+1.2V_VCCPLL_OC 43,44,45
+1.35VS_VGA G7 +NVVDD1 G4
SVID Bus

SUSP# TPS22961DNYR
(U20)
+VCCSTG G5
+NVVDD2

IMVP_VR_ON +VCC_CORE
PR523 48 PCH_PLTRST# +PEX_VDD G6
ISL95855 SIC632
(PU500) (PU502/503/504) UM3 CDRA_RST#
47 CALDERA_RST# 22
16 TC7SH08FU +1.35VS_VGA G7

for power down sequence VR_PWRGD

16
SIC632
+VCCGT JCDRA
(PU507/510) UE6
CALDERA_ PWRGD
Caldera
+3VS KC3810 15 2 GPU power off G7 G6 G5 G4
A @ Q7A IMVP_VR_ON PR515 A

G3
PM_SLP_S3# @ Q8A @ Q7B H_VCCST_PWRGD +VCCSA DGPU_PWROK
SIC531 19
(PU511) G2
@ Q8B SUSP#

G1
PM_SLP_S4# DMN65D8LDW SYSON
(Q9) @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P005 - Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 5 of 109
5 4 3 2 1
 5 4 3 2 1

CFL-H
UC1C
E25 B25
D25 PEG_RXP_0 PEG_TXP_0 A25
PEG_RXN_0 PEG_TXN_0

Vinafix.com E24
F24 PEG_RXP_1
PEG_RXN_1
PEG_TXP_1
PEG_TXN_1
B24
C24

E23 B23
D
D23 PEG_RXP_2 PEG_TXP_2 A23 D
PEG_RXN_2 PEG_TXN_2
E22 B22
F22 PEG_RXP_3 PEG_TXP_3 C22
PEG_RXN_3 PEG_TXN_3
E21 B21 PEG_CTX_GRX_P11 CC24 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_CTX_GRX_N11 PEG_CTX_C_GRX_P11 <74>
CC12 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N11 PEG_RXN_4 PEG_TXN_4 PEG_CTX_C_GRX_N11 <74>
E20 B20 PEG_CTX_GRX_P10 CC23 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P10 PEG_RXP_5 PEG_TXP_5 PEG_CTX_GRX_N10 PEG_CTX_C_GRX_P10 <74>
F20 C20 CC11 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N10 PEG_RXN_5 PEG_TXN_5 PEG_CTX_C_GRX_N10 <74>
PEG_CTX_GRX_P9
Caldera TX Caldera RX
E19 B19 CC22 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P9 PEG_RXP_6 PEG_TXP_6 PEG_CTX_GRX_N9 PEG_CTX_C_GRX_P9 <74>
D19 A19 CC10 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N9 PEG_RXN_6 PEG_TXN_6 PEG_CTX_C_GRX_N9 <74>
E18 B18 PEG_CTX_GRX_P8 CC21 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_P8 PEG_RXP_7 PEG_TXP_7 PEG_CTX_GRX_N8 PEG_CTX_C_GRX_P8 <74>
F18 C18 CC9 1 2 0.22U_0201_6.3V
<74> PEG_CRX_GTX_N8 PEG_RXN_7 PEG_TXN_7 PEG_CTX_C_GRX_N8 <74>
D17 A17 PEG_CTX_GRX_P7 CC20 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 PEG_CTX_C_GRX_P7 <27>
CC8 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N7 PEG_RXN_8 PEG_TXN_8 PEG_CTX_C_GRX_N7 <27>
UC1 F16 C16 PEG_CTX_GRX_P6 CC19 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P6 E16 PEG_RXP_9 PEG_TXP_9 B16 PEG_CTX_GRX_N6 PEG_CTX_C_GRX_P6 <27>
CC7 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N6 PEG_RXN_9 PEG_TXN_9 PEG_CTX_C_GRX_N6 <27>
D15 A15 PEG_CTX_GRX_P5 CC18 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P5 PEG_RXP_10 PEG_TXP_10 PEG_CTX_GRX_N5 PEG_CTX_C_GRX_P5 <27>
E15 B15 CC6 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N5 PEG_RXN_10 PEG_TXN_10 PEG_CTX_C_GRX_N5 <27>
F14 C14 PEG_CTX_GRX_P4 CC17 1 2 0.22U_0201_6.3V
I5-9300H <27> PEG_CRX_GTX_P4 PEG_RXP_11 PEG_TXP_11 PEG_CTX_GRX_N4 PEG_CTX_C_GRX_P4 <27>
GPU TX
SA0000COG6L E14 B14 CC5 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N4 PEG_RXN_11 PEG_TXN_11 PEG_CTX_C_GRX_N4 <27>
GPU RX
I5_9300H@
D13 A13 PEG_CTX_GRX_P3 CC16 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P3 PEG_RXP_12 PEG_TXP_12 PEG_CTX_GRX_N3 PEG_CTX_C_GRX_P3 <27>
UC1 E13 B13 CC4 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N3 PEG_RXN_12 PEG_TXN_12 PEG_CTX_C_GRX_N3 <27>
F12 C12 PEG_CTX_GRX_P2 CC15 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P2 E12 PEG_RXP_13 PEG_TXP_13 B12 PEG_CTX_GRX_N2 PEG_CTX_C_GRX_P2 <27>
CC3 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N2 PEG_RXN_13 PEG_TXN_13 PEG_CTX_C_GRX_N2 <27>
D11 A11 PEG_CTX_GRX_P1 CC14 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P1 E11 PEG_RXP_14 PEG_TXP_14 B11 PEG_CTX_GRX_N1 PEG_CTX_C_GRX_P1 <27>
I7-9750H CC2 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N1 PEG_RXN_14 PEG_TXN_14 PEG_CTX_C_GRX_N1 <27>
C SA0000COF7L C
I7_9750H_MP@ F10 C10 PEG_CTX_GRX_P0 CC13 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_P0 PEG_RXP_15 PEG_TXP_15 PEG_CTX_GRX_N0 PEG_CTX_C_GRX_P0 <27>
E10 B10 CC1 1 2 0.22U_0201_6.3V
<27> PEG_CRX_GTX_N0 PEG_RXN_15 PEG_TXN_15 PEG_CTX_C_GRX_N0 <27>
UC1
1 2 PEG_RCOMP G2
+VCCIO PEG_RCOMP
RC2
24.9_0402_1%

I9-9880H D8 B8
<17> DMI_CRX_PTX_P0 E8 DMI_RXP_0 DMI_TXP_0 A8 DMI_CTX_PRX_P0 <17>
SA0000COA3L
<17> DMI_CRX_PTX_N0 DMI_RXN_0 DMI_TXN_0 DMI_CTX_PRX_N0 <17>
I9_9880H@
E6 C6
<17> DMI_CRX_PTX_P1 F6 DMI_RXP_1 DMI_TXP_1 B6 DMI_CTX_PRX_P1 <17>
<17> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <17>
UC1
D5 B5
<17> DMI_CRX_PTX_P2 DMI_RXP_2 DMI_TXP_2 DMI_CTX_PRX_P2 <17>
E5 A5
<17> DMI_CRX_PTX_N2 DMI_RXN_2 DMI_TXN_2 DMI_CTX_PRX_N2 <17>
J8 D4
<17> DMI_CRX_PTX_P3 DMI_RXP_3 DMI_TXP_3 DMI_CTX_PRX_P3 <17>
J9 3 OF 13 B4
<17> DMI_CRX_PTX_N3 DMI_RXN_3 DMI_TXN_3 DMI_CTX_PRX_N3 <17>
I9-9980HK
SA0000CO83L CFL-H_BGA1440
I9_9980HK@ @

CFL-H
UC1D

K36 D29
<42> CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0_PCH <38>
K37 E29
B <42> CPU_DP1_N0 DDI1_TXN_0 EDP_TXN_0 EDP_TXN0_PCH <38> B
J35 F28
<42> CPU_DP1_P1 J34 DDI1_TXP_1 EDP_TXP_1 E28 EDP_TXP1_PCH <38>
<42> CPU_DP1_N1 DDI1_TXN_1 EDP_TXN_1 EDP_TXN1_PCH <38>
H37 A29
<42> CPU_DP1_P2 DDI1_TXP_2 EDP_TXP_2 EDP_TXP2_PCH <38>
FOR TBT DDI1 <42>
<42>
CPU_DP1_N2
CPU_DP1_P3
H36
J37
J38
DDI1_TXN_2
DDI1_TXP_3
EDP_TXN_2
EDP_TXP_3
B29
C28
B28
EDP_TXN2_PCH
EDP_TXP3_PCH
<38>
<38>
<42> CPU_DP1_N3 DDI1_TXN_3 EDP_TXN_3 EDP_TXN3_PCH <38>
D27 C26
<42> CPU_DP1_AUXP E27 DDI1_AUXP EDP_AUXP B26 EDP_AUXP_PCH <38>
<42> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN_PCH <38>
H34
<42> CPU_DP2_P0 H33 DDI2_TXP_0
<42> CPU_DP2_N0 DDI2_TXN_0
F37 A33 1
<42> CPU_DP2_P1 G38 DDI2_TXP_1 EDP_DISP_UTIL PAD~D @ T194 +VCCIO
<42> CPU_DP2_N1 DDI2_TXN_1
F34
<42> CPU_DP2_P2 DDI2_TXP_2 EDP_RCOMP
F35 D37 1 2
<42> CPU_DP2_N2 DDI2_TXN_2 DISP_RCOMP
FOR TBT DDI2 <42>
<42>
CPU_DP2_P3
CPU_DP2_N3
E37
E36 DDI2_TXP_3
DDI2_TXN_3
RC30
24.9_0402_1%

<42> CPU_DP2_AUXP
F26
DDI2_AUXP
Net : EDP_RCOMP
<42> CPU_DP2_AUXN
E26
DDI2_AUXN Trace Width/Space: 15 mil/ 20 mil
C34
D34 DDI3_TXP_0 Max Trace Length: 600 mil
B36 DDI3_TXN_0
B34 DDI3_TXP_1
F33 DDI3_TXN_1
E33 DDI3_TXP_2
C33 DDI3_TXN_2
B33 DDI3_TXP_3
DDI3_TXN_3 G27
PROC_AUDIO_CLK CPU_DISPA_BCLK <16>
A27 G25
B27 DDI3_AUXP PROC_AUDIO_SDI G29 CPU_DISPA_SDI_R 1 2 CPU_DISPA_SDO <16>
DDI3_AUXN 4 ofPROC_AUDIO_SDO
13 CPU_DISPA_SDI <16>
RC66
CFL-H_BGA1440 20_0402_5%
A @ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P006-CPU(1/8) DMI,PEG,DDI,EDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 6 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

JPCMC CMC_DEBUG_36P
+1VALW
OBS DATA JTAG/RC/HOOKS

+3V_PCH 1 22
<9> CFG0 3 DATA_0 VCCOBS_AB
<9> CFG1 5 DATA_1
XDP_SPI_SI <9> CFG2 DATA_2
1.5K_0402_1% 1 2RC9 7
C <9> CFG3 9 DATA_3 28 C
<9> CFG4 11 DATA_4 XDP_TRST* 29 CPU_XDP_TRST# <9,20>
<9> CFG5 13 DATA_5 XDP_TDI 30 XDP_TDI <9,16>
<9> CFG6 15 DATA_6 XDP_TMS 32 PCH_JTAG_TCK XDP_TMS <9,16>
<9> CFG7 DATA_7 XDP_TCK0 31 XDP_TCK PCH_JTAG_TCK <9,16>
17 XDP_TCK1 35 XDP_TCK <16>
<9> CFG17 21 DATA_CLK_1P XDP_TDO XDP_TDO <9>
<9> CFG16 DATA_CLK_1N 33
+1VALW 2 XDP_PREQ* 34 XDP_PREQ# <9,20>
<9> CFG8 4 DATA_8 XDP_PRDY* XDP_PRDY# <9,20>
<9> CFG9 6 DATA_9 27 XDP_HOOK0 RC355 1 CMC@ 2 1K_0402_1%
1 CMC@ 2 1K_0402_5% XDP_ITP_PMODE <9> CFG10 8 DATA_10 HOOK_0 25 XDP_SPI_SI EC_RSMRST# <58>
RC353
<9> CFG11 10 DATA_11 HOOK_3 26 XDP_ITP_PMODE XDP_SPI_SI <15>
<9> CFG12 12 DATA_12 HOOK_6 XDP_ITP_PMODE <16>
<9> CFG13 14 DATA_13 24 XDP_SPI_IO2 1 CMC@ 2 1K_0402_1%
RC354
<9> CFG14 16 DATA_14 XDP_PRSNT_PCH* 23 PCH_SPI_0_WP# <15>
<9> CFG15 DATA_15 XDP_PRSNT_CPU*
18 19
<9> CFG19 20 DATA_CLK_2P GND 36
<9> CFG18 DATA_CLK_2N <MT> GND
RC35 2 CMC@ 1 51_0402_1% PCH_JTAG_TCK

RC348 2 @ 1 51_0402_1% XDP_TCK

RH497 1 @ 2 51_0402_5% CPU_XDP_TRST# INTEL_CMC_PRIMARY

CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P007-CPU(2/8) CMC Connector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 7 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

CFL-H
UC1A CFL-H

Nil
UC1B
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_A_D16 BT11 AM9
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR_A_CLK0 <23,24> DDR_A_D17 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 DDR_B_CLK0 <25,26>
BT6 AG2 BR11 AN9
DDR_A_D2 BP3 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 AK2 DDR_A_CLK#0 <23,24> DDR_A_D18 BT9 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 AM7 DDR_B_CLK#0 <25,26>
<23,24> DDR_A_D[0..63] DDR_A_D3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR_A_D19 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1
BR3 AK1 BR8 AM8
<23,24> DDR_A_MA[0..13] DDR_A_D4 BN5 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 AL3 DDR_A_D20 BP11 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 AM11
<23,24> DDR_A_DQS#[0..7] DDR_A_D5 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 DDR_A_D21 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2
BP6 AK3 BN11 AM10
<23,24> DDR_A_DQS[0..7] DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR_A_D22 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2
BP2 AL2 BP8 AJ10
DDR_A_D7 BN3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 AL1 DDR_A_D23 BN8 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3 AJ11
DDR_A_D8 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_A_D24 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D9 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_A_D25 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8
DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_A_CKE0 <23,24> DDR_A_D26 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_B_CKE0 <25,26>
BL2 AT2 BL8 AT10
DDR_A_D11 BM1 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 AT3 DDR_A_D27 BJ8 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 AT7
<25,26> DDR_B_D[0..63] DDR_A_D12 BK4 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 AT5 DDR_A_D28 BJ11 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2 AT11
<25,26> DDR_B_MA[0..13] DDR_A_D13 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_A_D29 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
BK5 BJ10
<25,26> DDR_B_DQS#[0..7] DDR_A_D14 BK1 DDR0_DQ_13/DDR0_DQ_13 AD5 DDR_A_D30 BL7 DDR1_DQ_13/DDR0_DQ_29 AF11
<25,26> DDR_B_DQS[0..7] DDR_A_D15 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR_A_CS#0 <23,24> DDR_A_D31 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 DDR_B_CS#0 <25,26>
BK2 AE2 BJ7 AE7
DDR_A_D32 BG4 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 AD2 DDR_A_D48 BG11 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 AF10
DDR_A_D33 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_A_D49 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D34 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_A_D50 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D35 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_A_D51 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7
DDR_A_D36 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR_A_ODT0 <23,24> DDR_A_D52 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 DDR_B_ODT0 <25,26>
BG2 AE4 BF11 AE8
DDR_A_D37 BG1 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 AE1 DDR_A_D53 BF10 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 AE9
DDR_A_D38 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_A_D54 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D39 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_A_D55 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3 change NET
C C
DDR_A_D40 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_A_D56 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10
DDR_A_D41 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BA0 <23,24> DDR_A_D57 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_MA16 <25,26>
BD1 AH1 BC11 AH11
DDR_A_D42 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BA1 <23,24> DDR_A_D58 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_MA14 <25,26>
BC4 AU1 BB8 AF8
DDR_A_D43 BC5 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23,24> DDR_A_D59 BC8 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_MA15 <25,26>
DDR_A_D44 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_A_D60 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8
DDR_A_D45 BD4 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 AG4 DDR_A_MA16 <23,24> DDR_A_D61 BB10 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 AH9 DDR_B_BA0 <25,26>
DDR_A_D46 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR_A_MA14 <23,24> DDR_A_D62 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 DDR_B_BA1 <25,26>
BC1 AD1 BC7 AR9
DDR_A_D47 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_MA15 <23,24> DDR_A_D63 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <25,26>
BC2 BB7
DDR_B_D0 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0 DDR_B_D16 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_B_D1 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D17 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_B_D2 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D18 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_B_D3 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D19 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_B_D4 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D20 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_B_D5 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D21 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_B_D6 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D22 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_B_D7 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D23 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_B_D8 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_B_D9 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D24 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_B_D10 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D25 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_B_D11 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D26 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_B_D12 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D27 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_B_D13 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D28 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_B_D14 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_B_D29 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_B_D15 U4 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 AU3 DDR_A_BG1 <23,24> DDR_B_D30 V7 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 AR7
DDR_B_D32 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_A_ACT# <23,24> DDR_B_D31 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR_B_BG1 <25,26>
R2 V8 AT9
DDR_B_D33 P5 DDR0_DQ_48/DDR1_DQ_32 AG3 DDR_B_D48 R11 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <25,26>
DDR_B_D34 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR_A_PARITY <23,24> DDR_B_D49 DDR1_DQ_48/DDR1_DQ_48
R4 AU5 P11 AJ7 change NET
DDR_B_D35 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23,24> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PARITY <25,26>
P4 P7 AR8
DDR_B_D36 R5 DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) change NET DDR_B_D51 R8 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <25,26>
DDR_B_D37 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D52 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_B_D38 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D53 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_A_DQS#2
DDR_B_D39 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#4 DDR_B_D54 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_A_DQS#3
DDR_B_D40 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#5 DDR_B_D55 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_A_DQS#6
DDR_B_D41 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_B_DQS#0 DDR_B_D56 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_A_DQS#7
DDR_B_D42 L4 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 U3 DDR_B_DQS#1 DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#2
DDR_B_D43 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_B_DQS#4 DDR_B_D58 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#3
DDR_B_D44 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_B_DQS#5 DDR_B_D59 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
B DDR_B_D45 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D60 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7 B
DDR_B_D46 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0 DDR_B_D61 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_B_D47 L1 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_D62 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_A_DQS2
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS4 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_A_DQS3
LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS5 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_A_DQS6
BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_B_DQS0 AW11 LP3/DDR4 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_A_DQS7
BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_B_DQS1 AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS2
AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_B_DQS4 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS3
AY5 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_B_DQS5 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
BA4 NC/DDR0_ECC_4 AY3 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
AY1 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 BA3 AY7 NC/DDR1_ECC_5 AW9
AY2 NC/DDR0_ECC_6 1 OFDDR0_DQSN_8/DDR0_DQSN_8
13 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9
NC/DDR0_ECC_7 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8
CFL-H_BGA1440
@
11/28 change

RH148 1 2 121_0402_1% DDR_RCOMP0 G1 BN13

DDR_RCOMP1 DDR_RCOMP_0 DDR_VREF_CA +0.6V_VREFCA
RH149 1 2 121_0402_1% H1 BP13 @ T144
RH150 1 2 100_0402_1% DDR_RCOMP2 J2 DDR_RCOMP_1 2 OF 13 DDR0_VREF_DQ BR13
DDR_RCOMP_2 DDR1_VREF_DQ +0.6V_B_VREFDQ
CFL-H_BGA1440
@

Net : DDR_RCOMP0
Net : DDR_RCOMP1
Net : DDR_RCOMP2
Trace Width/Space: 15 mil/ 25 mil
Max Trace Length: 500 mil
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P008-CPU(3/8) DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 8 of 109

5 4 3 2 1
 5 4 3 2 1

+VCCST

CFL-H
UC1E
RH163 1 2 1K_0402_5% H_THERMTRIP#

RH156

RH164
Vinafix.com
1

1
@ 2

2
51_0402_5%

1K_0402_5%
XDP_PREQ#

H_VCCST_PWRGD
<15>
<15>
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B31
A32 BCLKP
BCLKN
CFG_0
CFG_1
BN25
BN27
BN26 CFG2
CFG0
CFG1
<7>
<7>
CFG_2 CFG2 <7>
D35 BN28
D VR_SVID_DATA <15> PCH_CPU_PCIBCLK_P PCI_BCLKP CFG_3 CFG3 <7> D
RH151 1 2 100_0402_1% C36 BR20 CFG4
<15> PCH_CPU_PCIBCLK_N PCI_BCLKN CFG_4 BM20 CFG4 <7>
CFG5
VR_SVID_ALERT# CFG_5 CFG5 <7>
RH152 1 2 56.2_0402_1% E31 BT20 CFG6
<15> CPU_24MHZ_P D31 CLK24P CFG_6 BP20 CFG6 <7>
CFG7
<15> CPU_24MHZ_N CLK24N CFG_7 CFG7 <7>
BR23
+VCCSTG CFG_8 CFG8 <7>
BR22
CFG_9 BT23 CFG9 <7>
CFG_10 CFG10 <7>
BT22
CFG_11 BM19 CFG11 <7>
CFG_12 CFG12 <7>
BR19
H_PROCHOT# CFG_13 CFG13 <7>
RH165 1 2 1K_0402_5% BP19
VR_SVID_ALERT# 1 2 220_0402_5% BH31 CFG_14 BT19 CFG14 <7>
RH153
<89> VR_SVID_ALERT# VIDALERT# CFG_15 CFG15 <7>
BH32
<89> VR_SVID_CLK VR_SVID_DATA BH29 VIDSCK BN23
<89> VR_SVID_DATA H_PROCHOT# VIDSOUT CFG_17 CFG17 <7>
RH158 1 2 499_0402_1% BR30 BP23
<58,83> H_PROCHOT# CFG16 <7>

0.1U_0402_25V6
PROCHOT# CFG_16 BP22
DDR_VTT_PG_CTRL CFG_19 CFG19 <7>

1
BT13 BN22

PCB35
DDR_VTT_CNTL CFG_18 CFG18 <7>
@ESD@

2
0926 ESD ADD BR27
BPM#_0 BT27
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS BPM#_1 BM31
H_VCCST_PWRGD RH154 1 2 60.4_0402_1% H13 BPM#_2 BT30
<58> H_VCCST_PWRGD VCCST_PWRGD BPM#_3
1: Normal Operation; Lane # definition matches
CFG2 socket pin map definition <16> H_CPUPWRGD
BT31
PROCPWRGD XDP_TDO
BP35 BT28
<14> PLTRST_CPU# BM34 RESET# PROC_TDO BL32 XDP_TDI XDP_TDO <7,16>
<14> H_PM_SYNC PM_SYNC PROC_TDI XDP_TMS XDP_TDI <7,16>
0:Lane Reversed
*
RH155 1 2 20_0402_5% BP31 BP28
<14> H_PM_DOWN BT34 PM_DOWN PROC_TMS BR28 PCH_JTAG_TCK XDP_TMS <7,16>
<14,58> H_PECI H_THERMTRIP# PECI PROC_TCK PCH_JTAG_TCK <7,16>
J31
<14> H_THERMTRIP# THERMTRIP# CPU_XDP_TRST#
BP30
1 2 1 2 0_0402_5% BR33 PROC_TRST# BL30 XDP_PREQ# CPU_XDP_TRST# <7,20>
CFG2 RH519 @
<14> PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PREQ# <7,20>
RH184 1K_0402_5% 1 2 PROC_SELECT# BN1 BP27 XDP_PRDY#
0913 change intel PROC_SELECT# PROC_PRDY# XDP_PRDY# <7,20>
RE716 0_0201_5%
+VCCST RC693 1 2 51_0402_1% H_CATERR# BM30
CATERR# BT25 CFG_RCOMP
AT13 CFG_RCOMP
C AW13 ZVM#
MSM#
Net :CFG_RCOMP C

1
AU13
RSVD1
RH59 Trace Width/Space: 4 mil/ 12 mil
Display Port Presence Strap
AY13
RSVD2 49.9_0402_1%
Max Trace Length: 600 mil
5 OF 13

2
1 : Disabled; No Physical Display Port CFL-H_BGA1440
CFG4 attached to Embedded Display Port +1.2V_DDR @
UC2
0 : Enabled; An external Display Port device is 5 1
* connected to the Embedded Display Port
1
VCC NC

A
2 DDR_VTT_PG_CTRL
4
CH197 Y 3
0.1U_0402_10V7K GND H_VCCST_PWRGD H_CPUPWRGD PLTRST_CPU#
CFG4 1 2 2 74AUP1G07GW_TSSOP5
RH185 1K_0402_5%
1 1 1
CH193 CH194 CH195
0.1U_0402_16V7K~D 0.1U_0402_16V7K~D 0.1U_0402_16V7K~D
+3VS ESD@ ESD@ ESD@
1 2 2 2

PCIE Port Bifurcation Straps RH525

330K_0402_5%
2

11: (Default) x16 - Device 1 functions 1 and 2 disabled

<85> SM_PG_CTRL
CFG[6:5] 10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
B B
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
* PCH_SYS_PWROK_XDP
RH489 1 2 1K_0402_5%
<15> PCH_SPI_0_SI_R
CFG5 1 2
RH186 1K_0402_5%

CFG6 1
RH187
2
1K_0402_5% +3V_PCH
RH489,RH493 close to UH4
RH493 1 2 2.2K_0402_5% PCH_SYS_PWROK_XDP

PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion
+VCCSTG
0: PEG Wait for BIOS for training

RH494 1 CMC@ 2 51_0402_5% XDP_TMS

CFG7 1 @ 2
RH188 1K_0402_5% RH495 1 CMC@ 2 51_0402_5% XDP_TDI

RH496 1 CMC@ 2 51_0402_5% XDP_TDO

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P009-CPU(4/8) CFG,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 9 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D
+VCC_CORE +VCC_CORE

+VCC_CORE CFL-H +VCC_CORE

UC1J
CFL-H
UC1M K14 W35
CFL-H L13 VCC1 VCC64 W36
UC1I 0913 change intel L14 VCC2 VCC65 W37
AA13 AH13 E2 N13 VCC3 VCC66 W38
AA31 VCC1 VCC64 AH14 IST_TRIG E3 RSVD_TP5 N14 VCC4 VCC67 Y29
VCC2 VCC65 TC13 @ IST_TRIG VCC5 VCC68
AA32 AH29 E1 N30 Y30
AA33 VCC3 VCC66 AH30 D1 RSVD_TP4 N31 VCC6 VCC69 Y31
AA34 VCC4 VCC67 AH31 RSVD_TP3 N32 VCC7 VCC70 Y32
AA35 VCC5 VCC68 AH32 BR1 BK28 N35 VCC8 VCC71 Y33
AA36 VCC6 VCC69 AJ14 BT2 RSVD_TP1 RSVD11 BJ28 N36 VCC9 VCC72 Y34
AA37 VCC7 VCC70 AJ29 RSVD_TP2 RSVD10 N37 VCC10 VCC73 Y35
AA38 VCC8 VCC71 AJ30 BN35 N38 VCC11 VCC74 Y36
AB29 VCC9 VCC72 AJ31 RSVD15 P13 VCC12 VCC75
AB30 VCC10 VCC73 AJ32 J24 P14 VCC13
AB31 VCC11 VCC74 AJ33 H24 RSVD28 P29 VCC14
AB32 VCC12 VCC75 AJ34 BN33 RSVD27 P30 VCC15
AB35 VCC13 VCC76 AJ35 BL34 RSVD14 P31 VCC16
AB36 VCC14 VCC77 AJ36 RSVD13 P32 VCC17
AB37 VCC15 VCC78 AK31 N29 P33 VCC18
AB38 VCC16 VCC79 AK32 R14 RSVD30 P34 VCC19
AC13 VCC17 VCC80 AK33 AE29 RSVD31 P35 VCC20
AC14 VCC18 VCC81 AK34 AA14 RSVD2 P36 VCC21
AC29 VCC19 VCC82 AK35 AP29 RSVD1 R13 VCC22
AC30 VCC20 VCC83 AK36 AP14 RSVD5 R31 VCC23
AC31 VCC21 VCC84 AK37 RH592 1 2 0_0402_5% A36 RSVD4 R32 VCC24
AC32 VCC22 VCC85 AK38 VSS_A36 R33 VCC25
C
AC33 VCC23 VCC86 AL13 RH593 1 2 0_0402_5% A37 R34 VCC26 C
AC34 VCC24 VCC87 AL29 VSS_A37 R35 VCC27
AC35 VCC25 VCC88 AL30 RH167 1 2 30_0402_5% H23 R36 VCC28
VCC26 VCC89 <20> PCH_TRIGGER PROC_TRIGIN VCC29
AC36 AL31 RH192 1 2 30_0402_5% J23 R37
VCC27 VCC90 <20> CPU_TRIGGER PROC_TRIGOUT VCC30
AD13 AL32 R38
AD14 VCC28 VCC91 AL35 F30 T29 VCC31
AD31 VCC29 VCC92 AL36 RSVD24 T30 VCC32
AD32 VCC30 VCC93 AL37 T31 VCC33
AD33 VCC31 VCC94 AL38 E30 T32 VCC34
AD34 VCC32 VCC95 AM13 RSVD23 T35 VCC35
AD35 VCC33 VCC96 AM14 T36 VCC36
AD36 VCC34 VCC97 AM29 B30 BL31 T37 VCC37
AD37 VCC35 VCC98 AM30 C30 RSVD7 RSVD12 AJ8 T38 VCC38
AD38 VCC36 VCC99 AM31 RSVD21 RSVD3 G13 U29 VCC39
AE13 VCC37 VCC100 AM32 RSVD25 U30 VCC40
AE14 VCC38 VCC101 AM33 G3 U31 VCC41
AE30 VCC39 VCC102 AM34 J3 RSVD26 C38 U32 VCC42
AE31 VCC40 VCC103 AM35 RSVD29 RSVD22 C1 U33 VCC43
AE32 VCC41 VCC104 AM36 RSVD20 BR2 U34 VCC44
AE35 VCC42 VCC105 AN13 BR35 RSVD17 BP1 U35 VCC45
AE36 VCC43 VCC106 AN14 BR31 RSVD19 RSVD16 B38 U36 VCC46
AE37 VCC44 VCC107 AN31 BH30 RSVD18 RSVD8 B2 V13 VCC47
AE38 VCC45 VCC108 AN32 RSVD9 RSVD6 V14 VCC48
AF29 VCC46 VCC109 AN33 13 OF 13 V31 VCC49
AF30 VCC47 VCC110 AN34 V32 VCC50
AF31 VCC48 VCC111 AN35 CFL-H_BGA1440 V33 VCC51
AF32 VCC49 VCC112 AN36 V34 VCC52
VCC50 VCC113 @ VCC53
AF33 AN37 V35
AF34 VCC51 VCC114 AN38 V36 VCC54
AF35 VCC52 VCC115 AP13 V37 VCC55
AF36 VCC53 VCC116 AP30 V38 VCC56
AF37 VCC54 VCC117 AP31 W13 VCC57
AF38 VCC55 VCC118 AP32 W14 VCC58
AG14 VCC56 VCC119 AP35 +VCC_CORE W29 VCC59
AG31 VCC57 VCC120 AP36 W30 VCC60
B B
AG32 VCC58 VCC121 AP37 W31 VCC61
AG33 VCC59 VCC122 AP38 W32 VCC62 10 OF 13
VCC60 VCC123 VCC63
1

AG34 K13
AG35 VCC61 VCC124 RH197 CFL-H_BGA1440
AG36 VCC62
100_0402_1% @
VCC63
2

AG37
VCC_SENSE VCCSENSE <89>
9 OF 13 AG38
VSS_SENSE VSSSENSE <89>
CFL-H_BGA1440
1

@
RH466
100_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P010-CPU(5/8) +VCC_CORE,RSVD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 10 of 109
5 4 3 2 1
 5 4 3 2 1

+VCCIO +VCCSTG +VCCST

Vinafix.com

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D

10U_0603_6.3V6M~D
D D

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1

CH102

CH103

CH104
+VCCSA +1.2V_DDR

CH105

CH106

CH107
2 2 2 2 2 2

CFL-H
UC1L

J30 AA6
K29 VCCSA1 VDDQ1 AE12
K30 VCCSA2 VDDQ2 AF5
K31 VCCSA3 VDDQ3 AF6
K32 VCCSA4 VDDQ4 AG5
K33 VCCSA5 VDDQ5 AG9
VCCSA6 VDDQ6
VCCPLL_OC is allowed to be turned off
K34 AJ12
K35 VCCSA7 VDDQ7 AL11
VCCSA8 VDDQ8
during S3 and DS3 if it is not powered directly from VDDQ
L31 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
L37 VCCSA12 VDDQ12 AT12
L38 VCCSA13 VDDQ13 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6
M32 VCCSA17 VDDQ17 K12
M33 VCCSA18 VDDQ18 K6
M34 VCCSA19 VDDQ19 L12
M35 VCCSA20 VDDQ20 L6
C M36 VCCSA21 VDDQ21 R6 C
+VCCIO VCCSA22 VDDQ22 T6
VDDQ23 W6
VDDQ24 Y12 +1.2V_VCCPLL_OC +1.2V_DDR
AG12 VDDQ25
G15 VCCIO1 RH530 1 @ 2 0_0402_5%
G17 VCCIO2
G19 VCCIO3 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13 +1.2V_DDR +1.2V_DDR
H15 VCCIO5 VCCPLL_OC2 G11 +VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 10mil +VCCSTG +VCCSA
H19 VCCIO8 VCCST
H20 VCCIO9 H29 10mil

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VCCIO10 VCCSTG2

2
H21

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M
VCCIO11 +VCCST 1 1 1 1
H26 G30 10mil RH201 1 1 1 1 1 1 1 1 1 1 1
H27 VCCIO12 VCCSTG1

CH129

CH130

CH131

CH132
VCCIO13 100_0402_1%
J15 H28 10mil

CH118

CH121

CH124

CH120

CH119

CH122

CH123

CH125

CH126

CH127

CH128
J16 VCCIO14 VCCPLL1 J28 10mil 2 2 2 2
VCCIO15 VCCPLL2 2 2 2 2 2 2 2 2 2 2 2
1
J17
J19 VCCIO16
J20 VCCIO17 M38
VCCIO18 VCCSA_SENSE VCCSA_SENSE <89>
J21 M37
VCCIO19 VSSSA_SENSE VSSSA_SENSE <89>
J26
VCCIO20
1

J27 H14
VCCIO21 VCCIO_SENSE VCCIO_SENSE <88>
J14 RH469
12 OF 13 VSSIO_SENSE VSSIO_SENSE <88>
100_0402_1%

CFL-H_BGA1440
2

B B

+1.2V_VCCPLL_OC +VCCST
1U_0201_6.3V6M

1U_0201_6.3V6M

22U_0402_6.3V6M

1 1 1
CC39

@
CC36

CC37

2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P011-CPU(6/8) +VCCSA,+VCCIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 11 of 109
5 4 3 2 1
 5 4 3 2 1

+VCCGT CFL-H +VCCGT

UC1K
AT14 BD35
VCCGT1 VCCGT80
Vinafix.com AT31
AT32
AT33
VCCGT2
VCCGT3
VCCGT4
VCCGT81
VCCGT82
VCCGT83
BD36
BE31
BE32
D AT34 BE33 D
AT35 VCCGT5 VCCGT84 BE34
AT36 VCCGT6 VCCGT85 BE35
AT37 VCCGT7 VCCGT86 BE36
AT38 VCCGT8 VCCGT87 BE37
AU14 VCCGT9 VCCGT88 BE38
AU29 VCCGT10 VCCGT89 BF13
AU30 VCCGT11 VCCGT90 BF14
AU31 VCCGT12 VCCGT91 BF29
AU32 VCCGT13 VCCGT92 BF30
AU35 VCCGT14 VCCGT93 BF31
AU36 VCCGT15 VCCGT94 BF32
AU37 VCCGT16 VCCGT95 BF35
AU38 VCCGT17 VCCGT96 BF36
AV29 VCCGT18 VCCGT97 BF37
AV30 VCCGT19 VCCGT98 BF38
AV31 VCCGT20 VCCGT99 BG29
AV32 VCCGT21 VCCGT100 BG30
AV33 VCCGT22 VCCGT101 BG31
AV34 VCCGT23 VCCGT102 BG32
AV35 VCCGT24 VCCGT103 BG33
AV36 VCCGT25 VCCGT104 BG34
AW14 VCCGT26 VCCGT105 BG35
AW31 VCCGT27 VCCGT106 BG36
AW32 VCCGT28 VCCGT107 BH33
AW33 VCCGT29 VCCGT108 BH34
AW34 VCCGT30 VCCGT109 BH35
AW35 VCCGT31 VCCGT110 BH36
AW36 VCCGT32 VCCGT111 BH37
AW37 VCCGT33 VCCGT112 BH38
AW38 VCCGT34 VCCGT113 BJ16
AY29 VCCGT35 VCCGT114 BJ17
C AY30 VCCGT36 VCCGT115 BJ19 C
AY31 VCCGT37 VCCGT116 BJ20
AY32 VCCGT38 VCCGT117 BJ21
AY35 VCCGT39 VCCGT118 BJ23
AY36 VCCGT40 VCCGT119 BJ24
AY37 VCCGT41 VCCGT120 BJ26
AY38 VCCGT42 VCCGT121 BJ27
BA13 VCCGT43 VCCGT122 BJ37
BA14 VCCGT44 VCCGT123 BJ38
BA29 VCCGT45 VCCGT124 BK16
BA30 VCCGT46 VCCGT125 BK17
BA31 VCCGT47 VCCGT126 BK19
BA32 VCCGT48 VCCGT127 BK20
BA33 VCCGT49 VCCGT128 BK21
BA34 VCCGT50 VCCGT129 BK23
BA35 VCCGT51 VCCGT130 BK24
BA36 VCCGT52 VCCGT131 BK26
BB13 VCCGT53 VCCGT132 BK27
BB14 VCCGT54 VCCGT133 BL15
BB31 VCCGT55 VCCGT134 BL16
BB32 VCCGT56 VCCGT135 BL17
BB33 VCCGT57 VCCGT136 BL23
BB34 VCCGT58 VCCGT137 BL24
BB35 VCCGT59 VCCGT138 BL25
BB36 VCCGT60 VCCGT139 BL26
BB37 VCCGT61 VCCGT140 BL27
BB38 VCCGT62 VCCGT141 BL28
BC29 VCCGT63 VCCGT142 BL36
BC30 VCCGT64 VCCGT143 BL37
BC31 VCCGT65 VCCGT144 BM15
BC32 VCCGT66 VCCGT145 BM16
BC35 VCCGT67 VCCGT146 BM17
B BC36 VCCGT68 VCCGT147 BM36 B
BC37 VCCGT69 VCCGT148 BM37
BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
BD14 VCCGT72 VCCGT151 BN17
BD29 VCCGT73 VCCGT152 BN36
BD30 VCCGT74 VCCGT153 BN37
BD31 VCCGT75 VCCGT154 BN38
BD32 VCCGT76 VCCGT155 BP15
BD33 VCCGT77 VCCGT156 BP16 +VCCGT
BD34 VCCGT78 VCCGT157 BP17
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15

2
BR15 VCCGT160 VCCGT165 BT16
VCCGT161 VCCGT166 RH203
BR16 BT17
BR17 VCCGT162 VCCGT167 BT37 100_0402_1%
VCCGT163 VCCGT168

1
AH37
11 OF VSSGT_SENSE VSSGT_SENSE <89>
13 AH38
VCCGT_SENSE VCCGT_SENSE <89>
CFL-H_BGA1440
@ 1
RH472
100_0402_1%
2

1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.
A A

3. RC1, RC2 should be placed within 2 inches (50.8 mm) of CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P012-CPU(7/8) +VCCGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 12 of 109
5 4 3 2 1
 5 4 3 2 1

CFL-H
CFL-H CFL-H UC1H

A10
A12
Vinafix.com
UC1F
VSS_1 VSS_82
AK4
AL10
AW5
AY12
UC1G
VSS_163 VSS_244
BJ15
BJ18
BN4
BN7
BP12
VSS_325 VSS_409
VSS_326 VSS_410
F15
F17
F19
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP14 VSS_327 VSS_411 F2
D A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP18 VSS_328 VSS_412 F21 D
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP21 VSS_329 VSS_413 F23
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP24 VSS_330 VSS_414 F25
A24 VSS_6 VSS_87 AL4 BA11 VSS_168 VSS_249 BJ31 BP25 VSS_331 VSS_415 F27
A26 VSS_7 VSS_88 AL7 BA12 VSS_169 VSS_250 BJ32 BP26 VSS_332 VSS_416 F29
A28 VSS_8 VSS_89 AL8 BA37 VSS_170 VSS_251 BJ33 BP29 VSS_333 VSS_417 F3
A30 VSS_9 VSS_90 AL9 BA38 VSS_171 VSS_252 BJ34 BP33 VSS_334 VSS_418 F31
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP34 VSS_335 VSS_419 F36
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP7 VSS_336 VSS_420 F4
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BR12 VSS_337 VSS_421 F5
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR14 VSS_338 VSS_422 F8
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR18 VSS_339 VSS_423 F9
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR21 VSS_340 VSS_424 G10
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR24 VSS_341 VSS_425 G12
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR25 VSS_342 VSS_426 G14
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR26 VSS_343 VSS_427 G16
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR29 VSS_344 VSS_428 G18
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR34 VSS_345 VSS_429 G20
AC3 VSS_21 VSS_102 AN5 BB5 VSS_183 VSS_264 BL14 BR36 VSS_346 VSS_430 G22
AC37 VSS_22 VSS_103 AN6 BB6 VSS_184 VSS_265 BL18 BR7 VSS_347 VSS_431 G23
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BT12 VSS_348 VSS_432 G24
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT14 VSS_349 VSS_433 G26
AC5 VSS_25 VSS_106 AP12 BC14 VSS_187 VSS_268 BL21 BT18 VSS_350 VSS_434 G28
AC6 VSS_26 VSS_107 AP33 BC33 VSS_188 VSS_269 BL22 BT21 VSS_351 VSS_435 G4
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT24 VSS_352 VSS_436 G5
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT26 VSS_353 VSS_437 G6
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT29 VSS_354 VSS_438 G8
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT32 VSS_355 VSS_439 G9
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT5 VSS_356 VSS_440 H11
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 C11 VSS_357 VSS_441 H12
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C13 VSS_358 VSS_442 H18
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C15 VSS_359 VSS_443 H22
C AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C17 VSS_360 VSS_444 H25 C
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C19 VSS_361 VSS_445 H32
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C21 VSS_362 VSS_446 H35
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C23 VSS_363 VSS_447 J10
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C25 VSS_364 VSS_448 J18
AF13 VSS_40 VSS_121 AR34 BE3 VSS_202 VSS_283 BM23 C27 VSS_365 VSS_449 J22
AF14 VSS_41 VSS_122 AR35 BE30 VSS_203 VSS_284 BM24 C29 VSS_366 VSS_450 J25
AF2 VSS_42 VSS_123 AR36 BE4 VSS_204 VSS_285 BM25 C31 VSS_367 VSS_451 J32
AF3 VSS_43 VSS_124 AR37 BE5 VSS_205 VSS_286 BM26 C37 VSS_368 VSS_452 J33
AF4 VSS_44 VSS_125 AR38 BE6 VSS_206 VSS_287 BM27 C5 VSS_369 VSS_453 J36
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C8 VSS_370 VSS_454 J4
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C9 VSS_371 VSS_455 J7
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 D10 VSS_372 VSS_456 K1
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D12 VSS_373 VSS_457 K10
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D14 VSS_374 VSS_458 K11
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D16 VSS_375 VSS_459 K2
AG7 VSS_51 VSS_132 AU11 BG14 VSS_213 VSS_294 BM5 D18 VSS_376 VSS_460 K3
AG8 VSS_52 VSS_133 AU12 BG37 VSS_214 VSS_295 BM6 D20 VSS_377 VSS_461 K38
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D22 VSS_378 VSS_462 K4
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D24 VSS_379 VSS_463 K5
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D26 VSS_380 VSS_464 K7
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D28 VSS_381 VSS_465 K8
AH36 VSS_57 VSS_138 AU8 BH11 VSS_219 VSS_300 BN14 D3 VSS_382 VSS_466 K9
AH6 VSS_58 VSS_139 AU9 BH12 VSS_220 VSS_301 BN18 D30 VSS_383 VSS_467 L29
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D33 VSS_384 VSS_468 L30
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D6 VSS_385 VSS_469 L33
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D9 VSS_386 VSS_470 L34
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 E34 VSS_387 VSS_471 M12
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E35 VSS_388 VSS_472 M13
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E38 VSS_389 VSS_473 N10
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E4 VSS_390 VSS_474 N11
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E9 VSS_391 VSS_475 N12
B AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 N3 VSS_392 VSS_476 N2 B
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N33 VSS_393 VSS_477 BT8
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N34 VSS_394 VSS_478 BR9
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N4 VSS_395 VSS_479
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N5 VSS_396 A3
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N6 VSS_397 VSS_A3 A34
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N7 VSS_398 VSS_A34 A4
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N8 VSS_399 VSS_A4 B3
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N9 VSS_400 VSS_B3 B37
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 P12 VSS_401 VSS_B37 BR38
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P37 VSS_402 VSS_BR38 BT3
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 M14 VSS_403 VSS_BT3 BT35
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M6 VSS_404 VSS_BT35 BT36
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 N1 VSS_405 VSS_BT36 BT4
VSS_81 VSS_162 VSS_243 VSS_324 F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 F13 VSS_4078 OF 13
VSS_C2 D38
VSS_408 VSS_D38
@ @
CFL-H_BGA1440
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P013-CPU(8/8) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 13 of 109

5 4 3 2 1
 5 4 3 2 1

UH1

HM370 B-0 QS
SA0000BVP1L
HM370_B@

Vinafix.com
CNP-H
D D
UH1C
AR2 G36
CL_CLK PCIE9_RXN PCIE_PRX_DTX_N9 <68>
AT5 F36
AU4 CL_DATA PCIE9_RXP C34 PCIE_PTX_DRX_N9 2 1 CH202 PCIE_PRX_DTX_P9 <68>
0.22U_0201_6.3V
CL_RST# PCIE9_TXN PCIE_PTX_DRX_P9 PCIE_PTX_C_DRX_N9 <68>
M.2 SSD Slot#3
D34 0.22U_0201_6.3V 2 1 CH203
PCIE9_TXP PCIE_PTX_C_DRX_P9 <68>
P48
GPP_K8
PCIe/SATA
V47
V48 GPP_K9 K37
W47 GPP_K10 PCIE10_RXN J37 PCIE_PRX_DTX_N10 <68>
GPP_K11 PCIE10_RXP PCIE_PTX_DRX_N10 PCIE_PRX_DTX_P10 <68>
C35 0.22U_0201_6.3V 2 1 CH204
PCIE10_TXN PCIE_PTX_DRX_P10 PCIE_PTX_C_DRX_N10 <68>
L47 B35 0.22U_0201_6.3V 2 1 CH205
L46 GPP_K0 PCIE10_TXP PCIE_PTX_C_DRX_P10 <68>
U48 GPP_K1 F44
GPP_K2 PCIE15_RXN/SATA2_RXN PCIE_PRX_DTX_N15 <73>
LAN
U47 E45
GPP_K3 PCIE15_RXP/SATA2_RXP PCIE_PRX_DTX_P15 <73>
N48 B40
GPP_K4 PCIE_15_SATA_2_TXN PCIE_PTX_DRX_N15 <73>
N47 C40
P47 GPP_K5 PCIE15_TXP/SATA2_TXP PCIE_PTX_DRX_P15 <73>
R46 GPP_K6 L41
GPP_K7 PCIE16_RXN/SATA3_RXN PCIE_PRX_DTX_N16 <73>
WLAN
M40
PCIE_PTX_DRX_P11 PCIE16_RXP/SATA3_RXP PCIE_PRX_DTX_P16 <73>
0.22U_0201_6.3V 2 1 CH206 C36 B41
<68> PCIE_PTX_C_DRX_P11 PCIE_PTX_DRX_N11 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN PCIE_PTX_DRX_N16 <73>
M.2 SSD Slot#3
0.22U_0201_6.3V 2 1 CH207 B36 C41
<68> PCIE_PTX_C_DRX_N11 F39 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP PCIE_PTX_DRX_P16 <73>
<68> PCIE_PRX_DTX_P11 PCIE11_RXP/SATA0A_RXP
PCIe/SATA
G38 K43
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN K44 PCIE_PRX_DTX_N17 <42>
PCIE17_RXP/SATA4_RXP PCIE_PTX_DRX_N17 PCIE_PRX_DTX_P17 <42>
AR42 A42 0.22U_0201_6.3V 2 1 CH218
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN PCIE_PTX_DRX_P17 PCIE_PTX_C_DRX_N17 <42>
AR48 B42 0.22U_0201_6.3V 2 1 CH219
AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP PCIE_PTX_C_DRX_P17 <42>
GPP_F13/SATA_SDATAOUT0
TBT
AU46 P41
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN R40 PCIE_PRX_DTX_N18 <42>
PCIE18_RXP/SATA5_RXP PCIE_PTX_DRX_N18 PCIE_PRX_DTX_P18 <42>
C39 C42 0.22U_0201_6.3V 2 1 CH220
PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_P18 PCIE_PTX_C_DRX_N18 <42>
D39 D42 0.22U_0201_6.3V 2 1 CH221
D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP PCIE_PTX_C_DRX_P18 <42>
C47 PCIE14_RXN/SATA1B_RXN AK48 PCH_SATADET#
PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED#
B38 AH41
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43
C45 PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 AK47 SATA_GP1 <68>
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 +3VS
C C
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46
PCIE_PTX_DRX_P12 GPP_F1/SATAXPCIE4/SATAGP4 SATA_GP4 <68>
M.2 SSD Slot#3
0.22U_0201_6.3V 2 1 CH208 E37 AM43
<68> PCIE_PTX_C_DRX_P12 PCIE_PTX_DRX_N12 PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5
0.22U_0201_6.3V 2 1 CH209 D38 AM47 TBT CHANGE 9/11
<68> PCIE_PTX_C_DRX_N12 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 PCH_SATADET#
PCIe/SATA
J41 AM48 1 2
<68> PCIE_PRX_DTX_P12 PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 TBT_RTD3_RST# <42>
H42 RH512 10K_0402_5%
<68> PCIE_PRX_DTX_N12 PCIE12_RXN/SATA1A_RXN AU48
PCIE_PTX_DRX_P20 GPP_F21/EDP_BKLTCTL BIA_PWM_PCH <38>
CH225 1 2 0.22U_0201_6.3V B44 AV46
<42> PCIE_PTX_C_DRX_P20 PCIE_PTX_DRX_N20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN ENBKL_PCH <58>
CH224 1 2 0.22U_0201_6.3V A44 AV44
<42> PCIE_PTX_C_DRX_N20 R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN ENVDD_PCH <38>
<42> PCIE_PRX_DTX_P20 PCIE20_RXP/SATA7_RXP H_THERMTRIP#_R
R35 AD3 RH79 1 2 620_0402_5%
<42> PCIE_PRX_DTX_N20 PCIE_PTX_DRX_P19 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI H_THERMTRIP# <9>
TBT
CH223 1 2 0.22U_0201_6.3V D43 AF2 RH73 1 2 12.1_0402_1%
<42> PCIE_PTX_C_DRX_P19 PCIE_PTX_DRX_N19 PCIE19_TXP/SATA6_TXP PECI H_PM_SYNC_R H_PECI <9,58>
CH222 1 2 0.22U_0201_6.3V C44 AF3 RH15 1 2 30_0402_5%
<42> PCIE_PTX_C_DRX_N19 PCIE19_TXN/SATA6_TXN PM_SYNC H_PM_SYNC <9>
N42 AG5
<42> PCIE_PRX_DTX_P19 M44 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# AE2 PLTRST_CPU# <9>
<42> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <9>
CNP-H_BGA874 Rev1.0

1
@
@
RH14
12.1_0402_1%

2
+3VS
CNP-H
UH1E
AL13 CPU_DDC1CLK
GPP_I5/DDPB_CTRLCLK AR8 CPU_DDC1DATA
B
AT6 GPP_I6/DDPB_CTRLDATA AN13 CPU_DDC2CLK PCH_DP3_CTRL_DATA 2.2K_0402_5% 2 1 RH601 B
<42> CPU_DP1_HPD AN10 GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK AL10 CPU_DDC2DATA
<42> CPU_DP2_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA PCH_DP4_CTRL_DATA RH602
AP9 AL9 2.2K_0402_5% 2 1
AL15 GPP_I2/DPPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 PCH_DP3_CTRL_DATA
GPP_I3/DPPE_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 PCH_DP4_CTRL_DATA
GPP_F23/DDPF_CTRLDATA AT49
GPP_F22/DDPF_CTRLCLK CPU_DDC1CLK 2.2K_0402_5% 2 1 RH604
AP41
EDP_HPD_CPU AN6 GPP_F14/PS_ON# PROC_DETECT# <9> CPU_DDC1DATA 2 1 RH605
2.2K_0402_5%
<38> EDP_HPD_CPU GPP_I4/EDP_HPD/DISP_MISC4
M45 CPU_DDC2CLK 2.2K_0402_5% 2 1 RH607
GPP_K23/IMGCLKOUT1 L48 STRAP3_PCH <30>
1

GPP_K22/IMGCLKOUT0 STRAP5_PCH <30> CPU_DDC2DATA RH606

T45 2.2K_0402_5% 2 1
RH9 GPP_K21 T46
100K_0402_5% 5 OF 13 GPP_K20 AJ47
GPP_H23/TIME_SYNC0
CNP-H_BGA874 Rev1.0 DDP[B..F]CTRLDATA
2

@
This signal has a weak internal Pull-down.
DEL IR CAM DET 0 = Port B~D is not detected.
1 = Port B,C,D is detected. (Default)
Notes:
1. The internal Pull-down is disabled after
PCH_PWROK de-asserts.
2. This signal is in the primary well.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P014-PCH (1/7) SATA,DDC,PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 14 of 109

5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1

CNP-H
UH1G RH70
BE33 10M_0402_5%
GPP_A16/CLKOUT_48 PCH_RTCX2

Net : XCLK_BIASREF
Vinafix.com <9>
<9>
CPU_24MHZ_P
CPU_24MHZ_N
D7
C6 CLKOUT_CPUNSSC_P
CLKOUT_CPUNSSC#
CLKOUT_ITPXDP#
CLKOUT_ITPXDP_P
Y3
Y4
PCH_XDP_CLK_N
PCH_XDP_CLK_P
T49
T50
PAD~D
PAD~D
TP@
TP@
1

YH1
2

D Trace Width/Space: 15mil /15 mil <9>

<9>
PCH_CPU_BCLK_P
PCH_CPU_BCLK_N
B8
C8 CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK#
CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P
B6
A6
PCH_CPU_PCIBCLK_N
PCH_CPU_PCIBCLK_P
<9>
<9>
32.768KHZ_X1A000141000300
D

Max Trace Length: 1000 mil XTAL24_OUT U9

XTAL_OUT CLKOUT_PCIE_N0
AJ6
CLK_PEG_N0 <27>
1 2

+1V_PCH XTAL24_IN U10 AJ7

XTAL_IN CLKOUT_PCIE_P0 CLK_PEG_P0 <27> GPU 1 1
RH71 1 @ 2 2.7K_0402_1% XCLK_BIASREF T3 AH9 CH45 CH46
XCLK_BIASREF CLKOUT_PCIE_N1 AH10 CLK_PCIE_N1 <68> 8.2P_0402_50V8B 8.2P_0402_50V8B
1 2 XCLK_BIASREF PCH_RTCX1 BA49 CLKOUT_PCIE_P1 CLK_PCIE_P1 <68> SSD1
RH590 60.4_0402_1% PCH_RTCX2 BA48 RTCX1 AE14 2 2
RTCX2 CLKOUT_PCIE_N2 AE15
+3VS BF31 CLKOUT_PCIE_P2
<27> CLKREQ_PEG#0 BE31 GPP_B5/SRCCLKREQ0# AE6
RP3
CLKREQ_PEG#0 <68> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_N3 <42>
PEG(dGPU) TBT
4 5 TP@ PAD~D T195 AR32 AE7
3 6 CLKREQ_PCIE#1 BB30 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3 CLK_PCIE_P3 <42>
<42> CLKREQ_PCIE#3 GPP_B8/SRCCLKREQ3#
SSD2
2 7 BA30 AC2
CLKREQ_PCIE#4 <73> CLKREQ_PCIE#4 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 CLK_PCIE_N4 <73>
1 8 AN29 AC3
<73> CLKREQ_PCIE#5 AE47 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_P4 <73> LAN
+3VS
10K_0804_8P4R_5%
NA <58,74>
<68>
CLKREQ_PEG#6
CLKREQ_PCIE#7
AC48
AE41
GPP_H0/SRCCLKREQ6#
GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5
AB2
AB3 CLK_PCIE_N5 <73>
WLAN
Thunderbolt GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 CLK_PCIE_P5 <73>
RP5 AF48
4 5 CLKREQ_PEG#6 AC41 GPP_H3/SRCCLKREQ9# W4
LAN
3 6 CLKREQ_PCIE#5 AC39 GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 W3 CLK_PEG_N6 <74>
2 7 AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 CLK_PEG_P6 <74> Caldera EMI@
RH91
WLAN
1 8 AB48 GPP_H6/SRCCLKREQ12# W7 33_0201_5%
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 CLK_PCIE_N7 <68>
AC44 W6
SSD2
Caldera
GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7 CLK_PCIE_P7 <68> XTAL24_IN_R XTAL24_IN
10K_0804_8P4R_5% AC43 1 2
GPP_H9/SRCCLKREQ15# AC14

SSD1 V2 CLKOUT_PCIE_N8 AC15

V3 CLKOUT_PCIE_N15 CLKOUT_PCIE_P8 RH72
CLKOUT_PCIE_P15 U2 1M_0402_5%~D
T2 CLKOUT_PCIE_N9 U3 1 2 XTAL24_OUT_R 1 2 XTAL24_OUT
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9
CLKOUT_PCIE_P14 AC9 EMI@
AA1 CLKOUT_PCIE_N10 AC11 YH2 RH92
Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10 24MHZ 12PF +-10PPM 7M24090001 33_0201_5%
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11 1 3
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11 RH1021 2 4
C C
CLKOUT_PCIE_P12 7 OF 13 R6 10mil 2 1 1 1
CLKIN_XTAL CH47 CH48
CNP-H_BGA874 Rev1.0 10K_0402_5% 12P_0402_50V8J 12P_0402_50V8J
@ 2 2

+3V_PCH +3VS

RH99 2 1 100K_0402_5% GPP_H15 CNP-H

UH1A
PCH_PLTRST#
#571182_CNL_PCH_H_EDS_V1_Rev0.7 BE36
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST#
AV29
PCH_PLTRST# <27,74> 1
CH201
External pull-up is required. Recommend 100K if pulled 0.1U_0201_6.3V6K
up to 3.3V or 75K if pulled up to 1.8V. R15
RSVD2 GPP_K16/GSXCLK
Y47
TBT_FORCE_PWR <42> 2
571007_CFL_MOW_Archive_WW22_2017 R13
RSVD1 GPP_K12/GSXDOUT
Y46
Y48
STUFF R on GPP_H15 GPP_K13/GSXSLOAD W46 UH3
GPP_K14/GSXDIN

5
RH1 close to UH4
AL37 AA45 TC7SH08FU_SSOP5
AN35 VSS GPP_K15/GSXSRESET# PCH_PLTRST# 1

P
TP B 4
1 2 RH1 PCH_SPI_0_SI AU41 AL47 2 Y PCIRST# <42,58,68,73>
1.5K_0402_1%
<7> XDP_SPI_SI PCH_SPI_0_SO SPI0_MOSI GPP_E3/CPU_GP0 A

1
G
BA45 AM45
PCH_SPI_0_CS# AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 RH199
SPI0_CS0# GPP_B3/CPU_GP2

3
PCH_SPI_0_CLK AW47 BC33 100K_0402_5%
AW48 SPI0_CLK GPP_B4/CPU_GP3
+3V_PCH SPI0_CS1# AE44 TBT CHANGE 9/27 +RTC_CELL
GPP_H18/SML4ALERT#

2
PCH_SPI_0_WP#
Internal pull high 20K , if used qual mode need 1K pull high <7> PCH_SPI_0_WP# PCH_SPI_0_HOLD#
AY48
BA46 SPI0_IO2 GPP_H17/SML4DATA
AJ46
AE43
SPI0_IO3 GPP_H16/SML4CLK GPP_H15 RTD3_CIO_PWR_EN <42>
AT40 AC47
B SPI0_CS2# GPP_H15/SML3ALERT# B

2
AD48
RH75 1 2 1K_0402_5% PCH_SPI_0_WP# BE19 GPP_H14/SML3DATA AF47 RH531
BF19 GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK AB47 GPP_H12
GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# 1M_0402_5%
BF18 AD47
RH78 1 2 1K_0402_5% PCH_SPI_0_HOLD# BE18 GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA AE48
GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK

1
BC17
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 INTRUDER#
GPP_D21/SPI1_IO2 INTRUDER#
CNP-H_BGA874 Rev1.0

@
+3V_PCH
+3V_PCH

RH100 1 @ 2 4.7K_0402_5% GPP_H12

1
This signal has a weak internal pull-down. CH49
0 = Master Attached Flash Sharing (MAFS) enabled (Default) 0.1U_0402_16V7K
1 = Slave Attached Flash Sharing (SAFS) enabled. 2
Notes: PCH_SPI_0_CS#
UH4
1 8
1. This signal is in the primary well. PCH_SPI_0_SO_R 2 /CS VCC 7 PCH_SPI_0_HOLD#_R
Warning: This strap must be configured to 0 if t he
‘

RPH5 PCH_SPI_0_WP#_R 3 DO(IO1) /HOLD(IO3) 6 PCH_SPI_0_CLK_R

eSPI or LPC strap is configured to 0 PCH_SPI_0_HOLD# PCH_SPI_0_HOLD#_R /WP(IO2) CLK PCH_SPI_0_SI_R
‘

4 5 4 5
PCH_SPI_0_SO 3 6 PCH_SPI_0_SO_R GND DI(IO0)
PCH_SPI_0_SI 2 7 PCH_SPI_0_SI_R S IC FL 128M W25Q128JVSIQ SOIC8P SPI ROM
PCH_SPI_0_WP# PCH_SPI_0_WP#_R PCH_SPI_0_SI_R <9>
1 8 128@
15_0804_8P4R_5%
PCH_SPI_0_CLK 1 2 PCH_SPI_0_CLK_R
RH104 EMI@ 15_0402_1%

1
CH244
A 10P_0402_50V8J @EMI@ A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P015-PCH (2/7) CLK,SPI,PLTRST
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 15 of 109

5 4 3 2 1
 5 4 3 2 1

+3V_PCH

0918 EMI CHANGE Vinafix.com

EC interface
WAKE#
PCH_BATLOW#
RH453 1

RH515 1
2 10K_0402_5%

2 8.2K_0402_5%

D
1
RP2
8 HDA_SDOUT Low(default) LPC AC_PRESENT RH533 1 2 8.2K_0402_5%
D
10/2 bios update
<73>
<73>
HDA_SDOUT_R
HDA_SYNC_R
2
3
7
6
HDA_SYNC
HDA_RST#
+3V_PCH
High eSPI WAKE_PCH# RH545 1 2 10K_0402_5%
<73> HDA_RST#_R 4 5
RH1035 1 2 4.7K_0402_5% SML0ALERT#
33_0804_8P4R_5% +3V_PCH

1 2 HDA_BIT_CLK
<73> HDA_BIT_CLK_R ME_SUS_PWR_ACK 1 2 1M_0402_5%
RH1031 RH506 @
33_0201_5% CNP-H
UH1D SYS_RESET# RH571 1 2 8.2K_0402_5%
EMI@ HDA_BIT_CLK
1 BD11 BF36
EMI CHANGE 12/1 CH245 BE11 HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF# AV32 CLKRUN#
10P_0402_50V8J <73> HDA_SDIN 1 2 1K_0402_1% HDA_SDOUT BF12 HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
RH16 +3VS
<58> ME_EN HDA_SYNC HDA_SDO/I2S0_TXD
@EMI@ BG13 BF41
2 HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
HDA_RST# BE10 BD42 CLKRUN# RH85 1 @ 2 8.2K_0402_5%
BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN#
BE12 HDA_SDI1/I2S1_RXD BB46
I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <23>
BD12 BE32
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
RH39 1 2 30_0402_5% CPU_DISPA_SDO_R AM2 GPP_B0/GSPI0_CS1# R47
<6> CPU_DISPA_SDO AN3 HDACPU_SDO GPP_K17/ADR_COMPLETE AP29
<6> CPU_DISPA_SDI CPU_DISPA_BCLK_R HDACPU_SDI GPP_B11/I2S_MCLK
RH38 1 2 30_0402_5% AM3 AU3
<6> CPU_DISPA_BCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <58>
AV18 BB47 WAKE# RH4 2 @ 1 0_0402_5%
GPP_D8/I2S2_SCLK WAKE# PCIE_WAKE# <58,73>
AW18 BE40
BA17 GPP_D7/I2S2_RXD GPD6/SLP_A# BF40
+3V_PCH BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28
BF15 GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# BF42
BD16 GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# BE42 PM_SLP_S3# <58,62,78,83>
GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# PM_SLP_S4# <58,78>
RH95 1 @ 2 4.7K_0402_5% SMBALERT# AV16 BC42
AW15 GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# PM_SLP_S5# <58,62>
GPP_D17/DMIC_CLK1/SNDW3_CLK BE45
GPD8/SUSCLK PCH_BATLOW# SUSCLK <68,73>
This signal has a weak internal Pull-down. GPD0/BATLOW#
BF44
BE35 SUSACK# RH1016 2
PCH_BATLOW#
1 0_0402_5% <42>
C 0 = Disable Intel ME Crypto Transport Layer Security PCH_RTCRST# BE47 GPP_A15/SUSACK# BC37 ME_SUS_PWR_ACK @
PCH_PWR_EN <58,78,87,96>
C
(TLS) cipher suite (no confidentiality). (Default) <59>
<59>
PCH_RTCRST#
PCH_SRTCRST#
PCH_SRTCRST# BD46 RTCRST#
SRTCRST#
GPP_A13/SUSWARN#/SUSPWRDNACK
1 = Enable Intel ME Crypto Transport Layer Security WAKE_PCH#
AY42 BG44
(TLS) cipher suite (with confidentiality). Must be <58> PCH_PWROK EC_RSMRST# BA47 PCH_PWROK GPD2/LAN_WAKE# BG42 AC_PRESENT 2 1 DH1
pulled up to support Intel AMT with TLS. <58> EC_RSMRST# RSMRST# GPD1/ACPRESENT BD39 RB751V-40_SOD323-2
VCIN1_AC_IN <58,83>
Notes: SLP_SUS#
GPD3/PWRBTN#
BE46 PBTN_OUT#
PBTN_OUT# <58>
@
PCH_DPWROK SYS_RESET#
1. The internal Pull-down is disabled after RSMRST# RH1017 2 1 0_0402_5% AW41
DSW_PWROK SYS_RESET#
AU2
HDA_SPKR
BE25 AW29
de-asserts. SMBALERT#
PCH_SMBCLK BE26 GPP_C2/SMBALERT# GPP_B14/SPKR AE3 HDA_SPKR <73> 12/18 Update @
2. This signal is in the primary well. PCH_SMBDATA BF26 GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <9>
SML0ALERT# BF24 GPP_C1/SMBDATA AL3
GPP_C5/SML0ALERT# ITP_PMODE XDP_ITP_PMODE <7>
SML0CLK BF25 AH4
<74> SML0CLK GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TCK <7,9>
SML0DATA BE24 AJ4
<74> SML0DATA PCH_SML1ALERT# BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 XDP_TMS <7,9>
GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO XDP_TDO <9>
1 1 SML1CLK BF27 AH2 +3VS
XDP_TDI <7,9>
10P_0402_50V8J

+RTC_CELL CH248 SML1DATA BE27 GPP_C6/SML1CLK 4 OF 13 PCH_JTAG_TDI AJ3

CH249

10P_0402_50V8J GPP_C7/SML1DATA PCH_JTAG_TCK XDP_TCK <7>

RH83 1 2 20K_0402_5%~D PCH_SRTCRST# @RF@ @RF@ CNP-H_BGA874 Rev1.0
1 1

10P_0402_50V8J
2 2 CH250 HDA_SPKR RH600 1 2 1K_0402_5%

CH251
@
1 10P_0402_50V8J
@RF@ @RF@ @
2 2
CH52
1U_0603_10V6K~D
Top Swap Override
0 = Disable Top S wap mode. ( Def ault)

““

””
2 10/2 FR update Reserve +3V_PCH
1 = Enable Top S wap mode.
The internal Pull-down is disabled after PCH_PWROK is high.
10/2 FR update Reserve RH63 1 @ 2 150K_0402_1% PCH_SML1ALERT#

+RTC_CELL
This signal has an internal pull-down.
RH84 1 2 20K_0402_5%~D PCH_RTCRST# 0 = Disable IntelR DCI-OOB (Default)
1 = Enable IntelR DCI-OOB
1 1. The internal pull-down is disabled after RSMRST# de-asserts.
1

CH53
1U_0603_10V6K~D
CLRP1
SHORT PADS
CLRP1 in DIMM door 2. When used as PCHHOT# and strap low, a 150K
pull-up is needed to ensure it does not override the
internal pull-down strap sampling.
2

B 2 +3VS B
+3VALW

1
1
@
RH2 RH5
10K_0402_5% 1K_0402_5%
+3VS

2
2
PBTN_OUT# SYS_RESET#

+3V_PCH

0.1U_0402_10V
2

1
CH174

CH175
0.1U_0402_10V @
RH460 1 2 1K_0402_5% SML1CLK SML1CLK 6 1
EC_SMB_CK2 <30,58,64,74,77>

2
RH461 1 2 1K_0402_5% SML1DATA QH5A
5

DMN66D0LDW-7
+3VS
SML1DATA 3 4
EC_SMB_DA2 <30,58,64,74,77>
RH501 1 2 499_0402_1% SML0CLK QH5B
DMN66D0LDW-7
RH502 1 2 499_0402_1% SML0DATA

RH463 1 2 1K_0402_5% PCH_SMBCLK

RH462 1 2 1K_0402_5% PCH_SMBDATA

1 1
10P_0402_50V8J

RH88 1 2 10K_0402_5% EC_RSMRST# CH252

CH253

10P_0402_50V8J
RH90 1 2 100K_0402_5% PCH_DPWROK @RF@ @RF@
A 2 2 A

10/2 FR update Reserve

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P016-PCH (3/7) PM,HDA,SMB,JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 16 of 109

5 4 3 2 1
 5 4 3 2 1

CNP-H

<6> DMI_CTX_PRX_N0
<6> DMI_CTX_PRX_P0
Vinafix.com K34
J35
UH1B
DMI0_RXN
DMI0_RXP
USB2N_1
USB2P_1
J3
J2
USB20_N1
USB20_P1
<73>
<73> JUSB3 left side (Power Share,Debug Port)
JIO right side (IO/B) USB1_2.0
C33 N13
<6> DMI_CRX_PTX_N0 DMI0_TXN USB2N_2 USB20_N2 <73>
B33 N15
D <6> DMI_CRX_PTX_P0 DMI0_TXP USB2P_2 USB20_P2 <73> D
G33 K4
<6> DMI_CTX_PRX_N1
<6> DMI_CTX_PRX_P1
F34
C32
DMI1_RXN
DMI1_RXP
USB2N_3
USB2P_3
K3
M10
USB20_N3
USB20_P3
<74>
<74> Caldera
AlienFX/ELC
<6> DMI_CRX_PTX_N1 B32 DMI1_TXN USB2N_4 L9 USB20_N4 <62>
<6> DMI_CRX_PTX_P1 DMI1_TXP USB2P_4 USB20_P4 <62>
K32 M1
<6> DMI_CTX_PRX_N2 DMI2_RXN USB2N_5
J32 L2
<6> DMI_CTX_PRX_P2 C31 DMI2_RXP USB2P_5 K7
<6> DMI_CRX_PTX_N2 DMI2_TXN USB2N_6
B31 K6
<6> DMI_CRX_PTX_P2 DMI2_TXP USB2P_6
Digital camera
G30 L4
<6> DMI_CTX_PRX_N3 DMI3_RXN USB2N_7 USB20_N7 <38>
F30 L3
<6> DMI_CTX_PRX_P3 DMI3_RXP USB2P_7 USB20_P7 <38>
C29 G4
<6> DMI_CRX_PTX_N3
<6> DMI_CRX_PTX_P3
B29
A25
DMI3_TXN
DMI3_TXP
USB2N_8
USB2P_8
G5
M6
USB20_N8
USB20_P8
<73>
<73> JIO right side (IO/B) USB2_2.0
B25
P24
DMI7_TXP
DMI7_TXN
USB2N_9
USB2P_9
N8
H3
USB20_N9
USB20_P9
<65>
<65> Tobii (17" only)
Per key
DMI7_RXP USB2N_10 USB20_N10 <64>
R24 H2
C26 DMI7_RXN USB2P_10 R10 USB20_P10 <64>

Thunderbolt PD
DMI6_TXP USB2N_11 USB20_N11 <50>
B26 P9
F26 DMI6_TXN USB2P_11 G1 USB20_P11 <50> +3V_PCH
G26 DMI6_RXP USB2N_12 G2
DMI6_RXN USB2P_12 RH1019
B27 N3 10K_0402_5%
C27 DMI5_TXP USB2N_13 N2 USB_OC0# 1 2
DMI5_TXN USB2P_13 USB_OC1#
BT
L26 E5 1 2
M26 DMI5_RXP USB2N_14 F6 USB20_N14 <73>
RH1020 10K_0402_5%
DMI5_RXN USB2P_14 USB20_P14 <73>
D29
E28 DMI4_TXP AH36 USB_OC0#
K29 DMI4_TXN GPP_E9/USB2_OC0# AL40 USB_OC1# USB_OC0# <73>
DMI4_RXP GPP_E10/USB2_OC1# USB_OC1# <73>
M29 AJ44
DMI4_RXN GPP_E11/USB2_OC2# AL41
G17 GPP_E12/USB2_OC3# AV47
<73> USB3_PRX_DTX_N7 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4#
F16 AR35
<73> USB3_PRX_DTX_P7 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5#
JIO left JUSB3
A17 AR37
<73> USB3_PTX_DRX_N7 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6#
B17 AV43
<73> USB3_PTX_DRX_P7 R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7#
<74> USB3_PRX_DTX_N8 PCIE2_RXN/USB31_8_RXN USB2_COMP
P21 F4 RH109 1 2 113_0402_1% +3V_PCH
<74> USB3_PRX_DTX_P8 PCIE2_RXP/USB31_8_RXP USB2_COMP
Caldera
B18 F3 RH580 1 2 1K_0402_5%
<74> USB3_PTX_DRX_N8 C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13
<74> USB3_PTX_DRX_P8 PCIE2_TXP/USB31_8_TXP RSVD1
C K18 G3 RH581 1 2 1K_0402_5% C
PCIE3_RXN/USB31_9_RXN USB2_ID

1
J18
B19 PCIE3_RXP/USB31_9_RXP BE41 GPD_7 RH594
C19 PCIE3_TXN/USB31_9_TXN GPD7
PCIE3_TXP/USB31_9_TXP 100K_0402_5%
N18 G45 PCIE_PTX_DRX_P24 CH217 1 2 0.22U_0201_6.3V
PCIE4_RXN/USB31_10_RXN PCIE24_TXP PCIE_PTX_DRX_N24 PCIE_PTX_C_DRX_P24 <68>
R18 G46 CH216 1 2 0.22U_0201_6.3V
PCIE4_RXP/USB31_10_RXP PCIE24_TXN PCIE_PTX_C_DRX_N24 <68>

2
D20 Y41 GPD_7
PCIE4_TXN/USB31_10_TXN PCIE24_RXP PCIE_PRX_DTX_P24 <68>
C20 Y40
PCIE4_TXP/USB31_10_TXP PCIE24_RXN PCIE_PTX_DRX_P23 PCIE_PRX_DTX_N24 <68>
F20 G48 CH215 1 2 0.22U_0201_6.3V
PCIE5_RXN PCIE23_TXP PCIE_PTX_DRX_N23 PCIE_PTX_C_DRX_P23 <68>

1
M.2 SSD Slot#1
G20 G49 CH214 1 2 0.22U_0201_6.3V
PCIE5_RXP PCIE23_TXN PCIE_PTX_C_DRX_N23 <68>
B21 W44 RH11
A22 PCIE5_TXN PCIE23_RXP W43 PCIE_PRX_DTX_P23 <68>
10K_0402_5%
PCIE5_TXP PCIE23_RXN PCIE_PTX_DRX_P22 PCIE_PRX_DTX_N23 <68>
K21 H48 0.22U_0201_6.3V 2 1 CH213 @
PCIE6_RXN PCIE22_TXP PCIE_PTX_DRX_N22 PCIE_PTX_C_DRX_P22 <68>
J21 H47 0.22U_0201_6.3V 2 1 CH212
PCIE6_RXP PCIE22_TXN PCIE_PTX_C_DRX_N22 <68>

2
D21 U41
PCIE6_TXN PCIE22_RXP PCIE_PRX_DTX_P22 <68>
C21 U40
B23 PCIE6_TXP PCIE22_RXN F46 PCIE_PTX_DRX_P21 2 1 CH211 PCIE_PRX_DTX_N22 <68>
0.22U_0201_6.3V
PCIE7_TXP PCIE21_TXP PCIE_PTX_DRX_N21 PCIE_PTX_C_DRX_P21 <68>
C23 G47 0.22U_0201_6.3V 2 1 CH210
PCIE7_TXN PCIE21_TXN PCIE_PTX_C_DRX_N21 <68>
J24 R44
PCIE7_RXP PCIE21_RXP PCIE_PRX_DTX_P21 <68>
X'tal Input:
L24 T43
PCIE7_RXN PCIE21_RXN PCIE_PRX_DTX_N21 <68>
F24
PCIE8_RXN
High: Differential
G24
B24 PCIE8_RXP
C24 PCIE8_TXN 2 OF 13
PCIE8_TXP
CNP-H_BGA874 Rev1.0
Low: Single ended
@

CNP-H
UH1F
F9 BB39
USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO0 <58>
F7 AW37 EC Change 0923
B USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 ESPI_IO1 <58> +1.8VALW B
D11 AV37
C11 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 BA38 ESPI_IO2 <58>
USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3 <58> ESPI_SERIRQ RH111 1 2 10K_0402_5%~D
C3
D4 USB31_2_TXN BE38 ESPI_KB_RST# RH518 1 2 10K_0402_5%~D
USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# ESPI_SERIRQ ESPI_FRAME# <58>
B9 AW35
USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# ESPI_SERIRQ <58>
C9
USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0#
BA36
BE39 ESPI_KB_RST# EC
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RST# ESPI_KB_RST# <58>
<73> USB3_PTX_DRX_P6 USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST# <58>
JUSB2
C16
<73> USB3_PTX_DRX_N6 USB31_6_TXP
G14 BB36 RH89 2 1 22_0402_5%
<73> USB3_PRX_DTX_P6 F14 USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK BB34 CLK_PCI_ESPI <58>
EMI@
<73> USB3_PRX_DTX_N6 USB31_6_RXP GPP_A10/CLKOUT_LPC1
C15
<73> USB3_PTX_DRX_N5 USB31_5_TXN
JUSB1
B15 T48
<73> USB3_PTX_DRX_P5 USB31_5_TXP GPP_K19/SMI#
J13 T47 0_0201_5% 2 RTD3@ 1 RT694 1
<73> USB3_PRX_DTX_N5 USB31_5_RXN GPP_K18/NMI# TBT_PCIE_WAKE_N <42>
K13 CH246
<73> USB3_PRX_DTX_P5 USB31_5_RXP TBT CHANGE 9/11 10P_0402_50V8J @EMI@
G12 AH40
F11 USB31_3_TXP GPP_E6/SATA_DEVSLP2 AH35 2
USB31_3_TXN GPP_E5/SATA_DEVSLP1 DEVSLP1 <68>
C10 AL48
B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47
USB31_3_RXN GPP_F9/SATA_DEVSLP7 AN37
C14 GPP_F8/SATA_DEVSLP6 AN46 FOR SSD
B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
USB31_4_TXN GPP_F6/SATA_DEVSLP4 DEVSLP4 <68>
J15 AP48
USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3 PCH_LCD_TEST <38>
K16
USB31_4_RXN
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P017-PCH (4/7) DMI,PCIE,USB,LPC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 17 of 109

5 4 3 2 1
 5 4 3 2 1

Hynix_8G Hynix_16G Samsung_8G Samsung_16G Micron_8G Micron_16G

DDRID_0 L H L H L H Samsung_8G Micron_8G nVidia GPU_ID N18_ID1 N18_ID0
DDRID_1 L L H H L L N18EG3 H H
RH1024 RH1026 RH1027 RH1029 RH1032 RH1024 RH1025 RH1028 RH1029 RH1032
DDRID_2 L L L L H H N18EG2 H L
DDRID_3 L L L L L L N18EG1 L H
DDRID_4 L L L L L L N18EG0 L L
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
Samsung_8G@ Samsung_8G@ Samsung_8G@ Samsung_8G@ Samsung_8G@ Micron_8G@ Micron_8G@ Micron_8G@ Micron_8G@ Micron_8G@

Vinafix.com Samsung_16G Micron_16G

D
Hynix_8G +3V_PCH
D

RH1024 RH1025 RH1027 RH1029 RH1032 RH1023 RH1026 RH1027 RH1029 RH1032 RH1023 RH1025 RH1028 RH1029 RH1032 N17_ID1 RH25 1 @ 2 10K_0201_5%
RH26 1 @ 2 10K_0201_5%

N17_ID0 RH27 1 @ 2 10K_0201_5%

RH28 1 @ 2 10K_0201_5%
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
Hynix_8G@ Hynix_8G@ Hynix_8G@ Hynix_8G@ Hynix_8G@ Samsung_16G@ Samsung_16G@ Samsung_16G@ Samsung_16G@ Samsung_16G@ Micron_16G@ Micron_16G@ Micron_16G@ Micron_16G@ Micron_16G@
GSYNC_ID RH29 1@ 2 10K_0201_5%
RH30 1 2 10K_0201_5%

Hynix_16G
RH28 N18EG0@ RH26 N18EG0@ RH27 N18EG1@ RH26 N18EG1@ RH28 N18EG2@ RH25 N18EG2@ RH27 N18EG3@ RH25 N18EG3@
RH1023 RH1025 RH1027 RH1029 RH1032
+3V_PCH

BOARD_ID 1 NV@ 2 10K_0201_5%

10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% RH21
10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%
Hynix_16G@ Hynix_16G@ Hynix_16G@ Hynix_16G@ Hynix_16G@ 10/26 Update
RH1601 1 @ 2 10K_0201_5%
+3VS
CNP-H
UH1K 1203 add BOARD ID TO GND

RH517 1 @ 2 8.2K_0402_5% BT_OFF# BBS_BIT0 BA26 BA20 BOARD_ID +3VS

BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20 DGPU_HOLD_RST#
WL_OFF# <62> ELC_RESET EC_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK PEX_RST# DGPU_HOLD_RST# <30>
RH520 1 @ 2 8.2K_0402_5% AU26 BB16
<58> EC_SCI# AW26 GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO AN18 DGPU_PWR_EN PEX_RST# <27> 8/29 add RPC7
EC_SCI# GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI DGPU_PWR_EN <32,37,58> I2C_0_SDA
RH521 1 2 10K_0402_5% 1 8
NRB_BIT BE30 BF14 N17_ID1 I2C_0_SCL 2 7
RC62 2 1 49.9K_0402_1% UART_2_PRXD_DTXD BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 N17_ID0 3 6
<62> ELC_BOOT_MODE GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN
BF29 BF17 4 5
2 1 49.9K_0402_1% UART_2_PTXD_DRXD <30> GC6_FB_EN BB26 GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL BE17 GSYNC_ID
RC63
<30> GC6_EVENT# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA
C 10K_0804_8P4R_5% C
BB24
BE23 GPP_C9/UART0A_TXD
1 2 10K_0402_5% DGPU_PWROK WL_OFF# AP24 GPP_C8/UART0A_RXD
RH516 @
<73> WL_OFF# BT_OFF# BA24 GPP_C11/UART0A_CTS# To G+Gyro sensor +3VS
VROM_SEL <73> BT_OFF# GPP_C10/UART0A_RTS#
RH588 1 @ 2 10K_0402_5% AG45
BD21 GPP_H20/ISH_I2C0_SCL AH46 ISH_I2C0_SCL <65>
<40> HDMI_HPD_PCH GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA ISH_I2C0_SDA <65>
AW24
<39> DP_HPD_PCH GPP_C14/UART1_RTS#/ISH_UART1_RTS#
AP21 AH47
AU24 GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL AH48 DGPU_PWR_EN RH537 1 2 10K_0201_5%
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA
RH589 1 @ 2 10K_0402_5% VROM_SEL AV21
<42> TBT_CIO_PLUG_EVENT# GPP_C23/UART2_CTS#
AW21
UART_2_PTXD_DRXD BE20 GPP_C22/UART2_RTS# AV34 PCH_ACC1_INT1
<58> UART_2_PTXD_DRXD UART_2_PRXD_DTXD BD20 GPP_C21/UART2_TXD GPP_A23/ISH_GP5 AW32 PCH_GYRO_INT2 PCH_ACC1_INT1 <65> +3V_PCH
GPP_C20/UART2_RXD GPP_A22/ISH_GP4 PCH_GYRO_INT2 <65>
BA33
+5VALW RTC_DET BE21 GPP_A21/ISH_GP3 BE34 XMP2 <85>
GPP_C19/I2C1_SCL GPP_A20/ISH_GP2 ISH_GP1 XMP1 <85>
BF21 BD34
<42> RTD3_USB_PWR_EN I2C_0_SCL GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 ISH_GP1 <58>
BC22 BF35 CLKDET#
<63> I2C_0_SCL I2C_0_SDA BF23 GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 BD38 DGPU_PRSNT#
JWDB
<63> I2C_0_SDA GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
1 CLKDET# RH558 1 @ 2 10K_0201_5%
UART_2_PTXD_DRXD 2 1 BE15
UART_2_PRXD_DTXD 2 TBT RTD3 <58,63> TP_INT# DGPU_PWROK GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4

2
3 5 BE14 11 OF 13
4 3 G1 6 GPP_D23/ISH_I2C2_SCL/I2C3_SCL @
4 G2 CNP-H_BGA874 Rev1.0 RH135
ACES_88266-04001 @ 10K_0402_5%
CONN@

1
+3V_PCH
+1.8V_PRIM RH130
1 2 1K_0402_5% BBS_BIT0
@

2 1 10K_0402_5% CNV_RGI_PTX_DRX
RH595 Boot BIOS Strap Bit (internal PD)
2 @ 1 10K_0402_5%
RH168
CNP-H
HIGH LPC
+3V_PCH UH1M LOW(DEFAULT) SPI
B <82> JRTC1 B
11/28 ADD RTC DET DDRID_0 AW13 BD4
DDRID_1 BE9 GPP_G0/SD_CMD CNV_WR_CLKN BE3
DDRID_2 GPP_G1/SD_DATA0 CNV_WR_CLKP +3V_PCH
M.2 CNV Mode Select DDRID_3
BF8
GPP_G2/SD_DATA1
2

BF9 BB3 RH524

An external pull-up or pull-down is required. RH1600 DDRID_4 BG8 GPP_G3/SD_DATA2 CNV_WR_D0N BB4 1 2 1K_0402_5% NRB_BIT
0 = Integrated CNVi enable. 10K_0402_5% BE8 GPP_G4/SD_DATA3
GPP_G5/SD_CD#
CNV_WR_D0P
CNV_WR_D1N
BA3 @
1 = Integrated CNVi disable.
2

BD8 BA2
GPP_G6/SD_CLK CNV_WR_D1P
2

AV13
Pulled down by CRF CNVi RGI_DT pin
G

RH1599
GPP_G7/SD_WP
1

10M_0402_5% 0_0201_5% BC5 NO REBOOT mode (internal PD)

3 1 RE724 1 2 RTC_DET AP3 CNV_WT_CLKN BB6
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP
HIGH Enable
S

GPP_I12/M2_SKT2_CFG1
1

AN4 BE6
+1.8VALW 2N7002W-T/R7_SOT323-3 AM7 GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N BD7 LOW(DEFAULT) Disable
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P BG6
QH98 CNV_WT_D1N
AV6 BF6
AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P BA1 CNV_WT_RCOMP RH213 1 2 150_0402_1%
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP 0918 BIOS CHANGE +3VS
RH603 1 2 4.7K_0402_5% CNV_BRI_PTX_DRX AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH193 1 2 100_0402_1%
AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
GPP_J_2 PCIE_RCOMPP SD_RCOMP_1P8
This signal has a weak internal pull-down 20K.
CNV_BRI_PTX_DRX
CNV_BRI_PRX_DTX
AT10
AV4
AY2
GPP_J_3
GPP_J4/CNV_BRI_DT/UART0B_RTS#
SD_1P8_RCOMP
SD_3P3_RCOMP
BE5
BE4
BD1
SD_RCOMP_3P3
RH214 1
RH215 1
2 200_0402_1%
2 200_0402_1% DDRID STRAP
0 = 38.4/19.2MHz XTAL frequency selected. CNV_RGI_PTX_DRX BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1
1 = 24MHz XTAL frequency selected. CNV_RGI_PRX_DTX AV3 GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 BE2 GPPJ_RCOMP_1P8 RH216 1 2 200_0402_1%
GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83 DDRID_0
Notes: GPP_J9
AW2
GPP_J8/CNV_MFUART2_RXD
10K_0201_5% 2 @1 RH1023
AU9 Y35 2 1 RH1024
1. The internal pull-down is disabled after RSMRST# GPP_J9/CNV_MFUART2_TXD RSVD2 Y36
10K_0201_5%
@
de-asserts. RSVD3
2. This signal is in the primary well. RSVD1
BC1 DDRID_1 10K_0201_5% 2 @1 RH1026
13 OF 13 AL35 T135 PAD~D @ 10K_0201_5% 2 1 RH1025
TP @
+1.8VALW
#571483_CFL_H_RVP_CRB_TDK_Rev0p7
CNP-H_BGA874 Rev1.0

@ DDRID_2
+1.8V_PRIM
Recommend external test point
10K_0201_5% 2 @1 RH1028
RH181 1 2 20K_0402_1% CNV_BRI_PRX_DTX 10K_0201_5% 2 1 RH1027
@
A RH182 1 2 20K_0402_1% CNV_RGI_PRX_DTX A
DDRID_3 10K_0201_5% 2 @1 RH1030
10K_0201_5% 2 1 RH1029
RH218 2 @ 1 10K_0402_5% GPP_J9 @
DDRID_4 10K_0201_5% 2 @1 RH1033
The signal has a weak internal pull-down 571391_CFL_H_PDG_Rev0p71 10K_0201_5% 2
@
1 RH1032
0 = VCCPSPI is connected to 3.3V rail To avoid floating input at the I/O pin BRI_RSP and RGI_RSP it is recommended to add
1 = VCCPSPI is connected to 1.8V rail a weak pull up resistor to the SoC pin with a recommended value of 20K ohm.
Note: If VCCPSPI is connected to 1.8V rail, this pin Security Classification Compal Secret Data Compal Electronics, Inc.
strap must be a 1 for the proper functionality
2017/05/15 2018/02/05 Title
of the SPI (Flash) I/Os Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P018-PCH (5/7) I2C,GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 18 of 109

5 4 3 2 1
 5 4 3 2 1

+1VALW +3V_PCH
CNP-H
UH1H
AA22 AW9
VCCPRIM_1P051 VCCPRIM_3P32

+1VALW @ +1V_PCH
Vinafix.com AA23
AB20
AB22
AB23
VCCPRIM_1P052
VCCPRIM_1P053
VCCPRIM_1P054
DCPRTC1
DCPRTC2
BF47
BG47
+VCCRTCEXT

AB27 VCCPRIM_1P055 V23

D JP1 VCCPRIM_1P056 VCCPRIM_3P35 D
AB28
1 2 AB30 VCCPRIM_1P057 AN44
AD20 VCCPRIM_1P058 VCCSPI
PAD-OPEN 43x39 AD23 VCCPRIM_1P059 BC49 20mil
+1V_MPHY VCCPRIM_1P0510 VCCRTC1 +RTC_CELL
AD27 BD49 1 2
AD28 VCCPRIM_1P0511 VCCRTC2 20mil CH226 0.1U_0402_10V7K
AD30 VCCPRIM_1P0512 AN21
RH12 1 2 0_0805_5% AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8
AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7
AF30 VCCPRIM_1P0517 VCCPRIM_3P34
VCCPRIM_1P0518 AC35
U26 VCCPGPPHK1 AC36
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
V27 VCCPRIM_1P0525 VCCPGPPEF2
V28 VCCPRIM_1P0526 AN24 +3VALW
V30 VCCPRIM_1P0527 VCCPGPPD AN26
+1V_PCH V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26
VCCPRIM_1P0529 VCCPGPPBC2 +1.8V_PRIM +3V_PCH
AD31 AN32
VCCPRIM_1P0514 VCCPGPPA
AE17 AT44 10/4 update
+1V_VCCDSW VCCPRIM_1P0515 VCCPRIM_3P31 BE48 15mil RH6 1 @ 2 0_0402_5%
20mil W22 VCCDSW_3P31 BE49 RH7 1 2 0_0402_5%
20mil W23 VCCDUSB_1P051 VCCDSW_3P32 15mil
+1V_MPHY VCCDUSB_1P052 BB14
BG45 VCCHDA AG19

10P_0402_50V8J
20mil
13.2A 20mil BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20
VCCDSW_1P052 VCCPRIM_1P84 1
W31 AN15

CH231
@RF@
+1.8V_PRIM +1.8VALW
VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
D1 VCCPRIM_1P86 BB11 1 2
E1 VCCPRIM_1P0521 VCCPRIM_1P87 2
C49 VCCPRIM_1P0522 AF19 20mil RH599
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20 20mil RH598 1 @ 2 0_0402_5% 0_0402_5%
VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1.8V_PRIM
E49
VCCAMPHYPLL_1P053 AG31 20mil
VCCPRIM_1P0520 +1VALW
P2 AF31 20mil
P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22 10mil T145 PAD~D @
C C
W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23 10mil
W20 VCCA_SRC_1P051 VCCPRIM_1P242 40mil
VCCA_SRC_1P052 AJ22 10mil
C1 VCCDPHY_1P241 AJ23 10mil
C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5 T146 PAD~D @
V19 VCCAPLL_1P055 VCCDPHY_1P243
VCCA_BCLK_1P05 K47 15mil
B1 VCCMPHY_SENSE K46

4.7U_0402_6.3V6M
VCCAPLL_1P051 VSSMPHY_SENSE 1
B2
B3 VCCAPLL_1P052 8 OF 13

CH36
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0 2
@

+1V_MPHY +1VALW +1V_MPHY +1VALW +1.8V_PRIM +3V_PCH +3V_PCH

1U_0402_6.3V6K~D

22U_0805_6.3V6M~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

1U_0402_6.3V6K~D

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1 1 1 1 1 1 1
CH82

CH181

CH180

CH187

CH188

CH176

CH190

CH192
2 2 2 2 2 2 2 2

B B

Close to B1,B2,B3,C1,C2 Close to U26,U29V25,V27,V28,V30,V31 Close to C49,D49,E49 Close to AF31,AG31,AD31,AA22,AA23 Close to AG19,AG20 Close to AE35,AE36 Close to AC35,AC36
,AB20,AB22,AB23,AB27,AB28,AB30 ,AR15,AN15,BB11
,AD20,AD23,AD27,AD28,AD30,AF23
,AF27,AF30,AE17

+3V_PCH +3V_PCH +RTC_CELL +1.8V_PRIM

1U_0603_10V6K

1U_0402_6.3V6K~D

0.1U_0402_10V7K

4.7U_0603_6.3V6M
0.1U_0402_10V7K

1 1 1 1 1
CH182

CH80

CH173

CH233

@
CH186

2 2 2 2 2

A A

Close to AY8,BB7 Close to BE48,BE49 Close to BC49,BD49 Close to AG19,AG20

,AR15,AN15,BB11

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P019-PCH (6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 19 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

CNP-H
UH1L
CNP-H
UH1I BG3 M24
A2 AL12 BG33 VSS VSS M32
A28 VSS VSS AL17 BG37 VSS VSS M34
A3 VSS VSS AL21 BG4 VSS VSS M49 CNP-H
A33 VSS VSS AL24 BG48 VSS VSS M5 UH1J
A37 VSS VSS AL26 C12 VSS VSS N12 Y14
A4 VSS VSS AL29 C25 VSS VSS N16 RSVD7 Y15
A45 VSS VSS AL33 C30 VSS VSS N34 RSVD8 U37
A46 VSS VSS AL38 C4 VSS VSS N35 RSVD6 U35
A47 VSS VSS AM1 C48 VSS VSS N37 RSVD5
A48 VSS VSS AM18 C5 VSS VSS N38 N32
A5 VSS VSS AM32 D12 VSS VSS P26 RSVD3 R32
A8 VSS VSS AM49 D16 VSS VSS P29 RSVD4
AA19 VSS VSS AN12 D17 VSS VSS P4 AH15
AA20 VSS VSS AN16 D30 VSS VSS P46 RSVD2 AH14
AA25 VSS VSS AN34 D33 VSS VSS R12 RSVD1
AA27 VSS VSS AN38 D8 VSS VSS R16
AA28 VSS VSS AP4 E10 VSS VSS R26
AA30 VSS VSS AP46 E13 VSS VSS R29 AL2
AA31 VSS VSS AR12 E15 VSS VSS R3 PREQ# AM5 XDP_PREQ# <7,9>
AA49 VSS VSS AR16 E17 VSS VSS R34 PRDY# AM4 XDP_PRDY# <7,9>
AA5 VSS VSS AR34 E19 VSS VSS R38 CPU_TRST# AK3 CPU_XDP_TRST# <7,9>
AB19 VSS VSS AR38 E22 VSS VSS R4 TRIGGER_OUT AK2 PCH_TRIGGER <10>
AB25 VSS VSS AT1 E24 VSS VSS T17 TRIGGER_IN CPU_TRIGGER <10>
AB31 VSS VSS AT16 E26 VSS VSS T18 10 OF 13
AC12 VSS VSS AT18 E31 VSS VSS T32 CNP-H_BGA874 Rev1.0
C AC17 VSS VSS AT21 E33 VSS VSS T4 C
VSS VSS VSS VSS @
AC33 AT24 E35 T49
AC38 VSS VSS AT26 E40 VSS VSS T5
AC4 VSS VSS AT29 E42 VSS VSS T7
AC46 VSS VSS AT32 E8 VSS VSS U12
AD1 VSS VSS AT34 F41 VSS VSS U15
AD19 VSS VSS AT45 F43 VSS VSS U17
AD2 VSS VSS AV11 F47 VSS VSS U21
AD22 VSS VSS AV39 G44 VSS VSS U24
AD25 VSS VSS AW10 G6 VSS VSS U33
AD49 VSS VSS AW4 H8 VSS VSS U38
AE12 VSS VSS AW40 J10 VSS VSS V20
AE33 VSS VSS AW46 J26 VSS VSS V22
AE38 VSS VSS B47 J29 VSS VSS V4
AE4 VSS VSS B48 J4 VSS VSS V46
AE46 VSS VSS B49 J40 VSS VSS W25
AF22 VSS VSS BA12 J46 VSS VSS W27
AF25 VSS VSS BA14 J47 VSS VSS W28
AF28 VSS VSS BA44 J48 VSS VSS W30
AG1 VSS VSS BA5 J9 VSS VSS Y10
AG22 VSS VSS BA6 K11 VSS VSS Y12
AG23 VSS VSS BB41 K39 VSS VSS Y17
AG25 VSS VSS BB43 M16 VSS VSS Y33
AG27 VSS VSS BB9 M18 VSS VSS Y38
AG28 VSS VSS BC10 M21 VSS 12 OF 13 VSS Y9
AG30 VSS VSS BC13 VSS VSS
AG49 VSS VSS BC15 CNP-H_BGA874 Rev1.0
AH12 VSS VSS BC19
VSS VSS @
AH17 BC24
AH33 VSS VSS BC26
AH38 VSS VSS BC31
AJ19 VSS VSS BC35
B AJ20 VSS VSS BC40 B
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
AK4 VSS VSS BG25
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
CNP-H_BGA874 Rev1.0

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P020-PCH (7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 20 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

Title
P021-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 21 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

Title
P022-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 22 of 109

5 4 3 2 1
 5 4 3 2 1

DDR4 Memory Down_CHA <8,24>

<8,24>
DDR_A_MA[0..16]

DDR_A_DQS[0..7]

Non-Interleave Memory <8,24>

<8,24>
DDR_A_DQS#[0..7]

DDR_A_D[0..63]

DDR4 Memory Down_CHA

D
Vinafix.com D

+1.2V_DDR Closed to UD1

Closed to UD2
VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1)
SOC side Memory side +1.2V_DDR +2.5V_MEM +0.6VS VDDQ DECAPS (1UF x2 / 10UF x1)

1
+1.2V_DDR +2.5V_MEM +0.6VS
RD160
1.8K_0402_1%

@RF@ CD378

@RF@ CD379

@RF@ CD380
100P_0201_50V8J

CD265

CD266

CD267

CD268

CD269

10U_0402_6.3V6M

10U_0402_6.3V6M

CD279

CD280

10U_0402_6.3V6M

100P_0201_50V8J

CD285

CD286

10U_0402_6.3V6M

100P_0201_50V8J

@RF@ CD381

@RF@ CD382

@RF@ CD383
2
RD161

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

100P_0201_50V8J

CD270

CD271

CD272

CD274

CD302

10U_0402_6.3V6M

10U_0402_6.3V6M

CD282

CD283

10U_0402_6.3V6M

100P_0201_50V8J

CD288

CD289

10U_0402_6.3V6M

100P_0201_50V8J
1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+0.6V_VREFCA +0.6V_DDR_VREFCA

CD276

CD277

CD281

CD287

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD273

CD278

CD284

CD290
1 2.7_0402_1%
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
CD291 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1
0.022U_0402_16V7K~D
2
RD162
1.8K_0402_1%
1

RD159
24.9_0402_1%
2

All VREF traces should

have 10 mil trace width
VREF traces should be at least 20 mils wide
with 20 mils spacing to other signals/planes. +0.6V_DDR_VREFCA
+0.6V_DDR_VREFCA
UD1
UD2
M1 G2 DDR_A_D16
VREFCA DQL0 F7 DDR_A_D22 M1 G2 DDR_A_D54
1 DQL1 H3 DDR_A_D17 VREFCA DQL0 F7 DDR_A_D52

0.047U_0402_10V7K

CD292
DDR_A_MA0 P3 DQL2 H7 DDR_A_D19 1 DQL1 H3 DDR_A_D50

0.047U_0402_10V7K

CD264
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D20 DDR_A_MA0 P3 DQL2 H7 DDR_A_D51
DDR_A_MA2 R3 A1 DQL4 H8 DDR_A_D23 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D49
2 DDR_A_MA3 A2 DQL5 DDR_A_D21 DDR_A_MA2 A1 DQL4 DDR_A_D53
C N7 J3 2 R3 H8 C
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D18 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D48
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D55
DDR_A_MA6 P2 A5 DDR_A_MA5 P8 A4 DQL7
DDR_A_MA7 R8 A6 A3 DDR_A_D26 DDR_A_MA6 P2 A5
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D27 DDR_A_MA7 R8 A6 A3 DDR_A_D62
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D30 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D61
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D31 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D59
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D24 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D63
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D29 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D57
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D25 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D56
DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D28 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D60
A14/WE DQU7 DDR_A_MA14 L2 A13 DQU6 D7 DDR_A_D58
DDR_A_BA0 +1.2V_DDR A14/WE DQU7
<8,24> DDR_A_BA0 N2 +1.2V_DDR
DDR_A_BA1 N8 BA0 B3 DDR_A_BA0 N2
+1.2V_DDR <8,24> DDR_A_BA1 BA1 VDD DDR_A_BA1 BA0
B9 +1.2V_DDR N8 B3
40mil E2 VDD D1 BA1 VDD B9
E7 DMU/DBIU VDD G7 40mil E2 VDD D1
DML/DBIL VDD J1 E7 DMU/DBIU VDD G7
VDD J9 DML/DBIL VDD J1
VDD L1 VDD J9
DDR_A_CLK0 K7 VDD L9 VDD L1
<8,24> DDR_A_CLK0 DDR_A_CLK#0 CK_t VDD DDR_A_CLK0 VDD
<8,24> DDR_A_CLK#0 K8 R1 RD230 K7 L9
DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CLK#0 K8 CK_t VDD R1
<8,24> DDR_A_CKE0 CKE VDD DDR_A_CKE0 CK_c VDD
K2 T9
CKE VDD RD231
A1
VDDQ A9 A1
VDDQ C1 VDDQ A9
VDDQ 0_0402_5% VDDQ
D9 SD028000080 C1
VDDQ F2 SDP8G@ VDDQ D9
VDDQ F8 VDDQ F2
DDR_A_ODT0 VDDQ VDDQ 0_0402_5%
<8,24> DDR_A_ODT0 K3 G1 F8 SD028000080
DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_ODT0 K3 VDDQ G1
<8,24> DDR_A_CS#0 SDP8G@
DDR_A_MA16 L8 CS VDDQ J2 RD230 BOM control for DDP@ to 240R /SDP@ to 0R DDR_A_CS#0 L7 ODT VDDQ G9
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA16 L8 CS VDDQ J2 RD231 BOM control for DDP@ to 240R /SDP@ to 0R
CAS VDDQ DDR_A_MA15 M8 RAS VDDQ J8
RD230 CAS VDDQ
B2
VSS E1 240_0402_1% B2 RD231
VSS E9 15mil 2 DDP16G@1 VSS E1 15mil 240_0402_1%
VSS VSS DDP16G@
G8 E9 2 1
DDR_A_DQS#3 A7 VSS K1 VSS G8
DDR_A_DQS3 B7 DQSU_c VSS K9 DDR_A_DQS#7 A7 VSS K1
DDP16G@
DDR_A_DQS#2 F3 DQSU_t VSS M9 2 0_0201_5% DDR_A_BG1 DDR_A_DQS7 DQSU_c VSS
RD238 1 DDR_A_BG1 <8,24> B7 K9 DDP16G@
DDR_A_DQS2 G3 DQSL_c VSS N1 DDR_A_DQS#6 F3 DQSU_t VSS M9 2 0_0201_5% DDR_A_BG1
RD240 1
DQSL_t VSS T1 DDR_A_DQS6 G3 DQSL_c VSS N1
SDP8G@
DDR_DRAMRST#_R P1 VSS DQSL_t VSS
RD239 1 2 0_0201_5% T1 SDP8G@
RESET DDR_DRAMRST#_R P1 VSS RD241 1 2 0_0201_5%
RD157 2 1 240_0402_1% F9 RESET
15mil ZQ RD158 2 1 240_0402_1% F9
B 15mil ZQ B
DDR_A_ACT# L3 A2
<8,24> DDR_A_ACT# DDR_A_BG0 ACT VSSQ DDR_A_ACT#
<8,24> DDR_A_BG0 M2 A8 L3 A2
N9 BG0 VSSQ C9 DDR_A_BG0 M2 ACT VSSQ A8
DDR_A_ALERT# P9 TEN VSSQ D2 N9 BG0 VSSQ C9
<8,24> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_ALERT# TEN VSSQ
<8,24> DDR_A_PARITY T3 D8 P9 D2
PAR VSSQ E3 DDR_A_PARITY T3 ALERT VSSQ D8
T7 VSSQ E8 PAR VSSQ E3
40mil B1 NC VSSQ F1 T7 VSSQ E8
+2.5V_MEM R9 VPP VSSQ H1 40mil B1 NC VSSQ F1
VPP VSSQ H9
+2.5V_MEM R9 VPP VSSQ H1
96-BALL VSSQ VPP VSSQ H9
SDRAM DDR4 96-BALL VSSQ
UD1 K4A8G165W B-BCPB_FBGA96 SDRAM DDR4
UD1 UD1 @ K4A8G165W B-BCPB_FBGA96
@

S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P

S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E SA0000B6F1L
SA0000BMN1L SA0000ARD1L SAM8G@
HYX8G@ MCN8G@

UD2
UD2 UD2

S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P +1.2V_DDR

S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E SA0000B6F1L
SA0000BMN1L SA0000ARD1L SAM8G@
DDR_DRAMRST#_R
HYX8G@ MCN8G@

2
1

12/12 Update SAMSUNG 8G、 HYNIX 8G RD35

CD111
0.1U_0402_10V6K
470_0402_1% @ESD@
1
2

UD1 UD1 UD1

DDR_DRAMRST#_R 1 2
PLACE NEAR TO UD1,UD2
<24,25,26> DDR_DRAMRST#_R H_DRAMRST# <16>
0.1U_0402_16V7K~D

RD31
1

1 0_0402_5%
CD69
@ESD@

DT16
A A
PESD5V0H1BSF_SOD962-2-2
16G/2666 H5ANAG6NCMR-VKC FBGA96P 16G/2666 MT40A1G16KNR-075:E FBGA 16G/2666 K4AAG165WB-MCTD FBGA96P
SA0000BZJ1L SA0000BC71L SA0000B9K1L 2
HYX16G@ MCN16G@ SAM16G@
2

UD2 UD2 UD2

SC40000AT00 2/11 ADD

ESD@

16G/2666 H5ANAG6NCMR-VKC FBGA96P 16G/2666 MT40A1G16KNR-075:E FBGA 16G/2666 K4AAG165WB-MCTD FBGA96P

SA0000BZJ1L SA0000BC71L SA0000B9K1L
HYX16G@ MCN16G@ SAM16G@

11/23 Update SAMSUNG16G、MICRON 16G 、HYNI X 16G

Security Classification
2017/04/07
Compal Secret Data
2018/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P023-DDR4_CHA_Memory Down I
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-H351P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 30, 2019 Sheet 23 of 109
5 4 3 2 1
 5 4 3 2 1

DDR4 Memory Down_CHA <8,23>

<8,23>
DDR_A_MA[0..16]

DDR_A_DQS[0..7]

Non-Interleave Memory <8,23>

<8,23>
DDR_A_DQS#[0..7]

DDR_A_D[0..63]

D
Vinafix.com D

Closed to UD3 Closed to UD4

VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)
+1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +2.5V_MEM +0.6VS
@RF@ CD384

@RF@ CD385

@RF@ CD386

@RF@ CD387

@RF@ CD388

@RF@ CD389
100P_0201_50V8J

CD307

CD309

CD317

CD299

CD308

10U_0402_6.3V6M

10U_0402_6.3V6M

CD305

CD314

10U_0402_6.3V6M

100P_0201_50V8J

CD300

CD303

10U_0402_6.3V6M

100P_0201_50V8J

100P_0201_50V8J

CD304

CD306

CD315

CD311

CD313

10U_0402_6.3V6M

10U_0402_6.3V6M

CD293

CD319

10U_0402_6.3V6M

100P_0201_50V8J

CD296

CD312

10U_0402_6.3V6M

100P_0201_50V8J
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD310

CD295

CD301

CD297

CD275

CD298

CD256

CD318
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+0.6V_DDR_VREFCA +0.6V_DDR_VREFCA

UD3 UD4
All VREF traces should DDR_A_D2 DDR_A_D39
C
have 10 mil trace width M1
VREFCA DQL0
G2
DDR_A_D3
M1
VREFCA DQL0
G2
DDR_A_D37 +0.6VS
C
F7 F7
1 DQL1 H3 DDR_A_D6 1 DQL1 H3 DDR_A_D38
0.047U_0201_10V6K
CD263

0.047U_0201_10V6K
CD316
DDR_A_MA0 P3 DQL2 H7 DDR_A_D5 DDR_A_MA0 P3 DQL2 H7 DDR_A_D32
DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D7 DDR_A_MA1 P7 A0 DQL3 H2 DDR_A_D35
DDR_A_MA0 1 2 36_0201_1%
DDR_A_MA2 A1 DQL4 DDR_A_D1 DDR_A_MA2 A1 DQL4 DDR_A_D33 RD166
2 R3 H8 2 R3 H8
DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D4 DDR_A_MA3 N7 A2 DQL5 J3 DDR_A_D34 DDR_A_MA1 1 2 36_0201_1%
RD167
DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D0 DDR_A_MA4 N3 A3 DQL6 J7 DDR_A_D36
DDR_A_MA2 1 2 36_0201_1%
DDR_A_MA5 P8 A4 DQL7 DDR_A_MA5 P8 A4 DQL7 RD168
DDR_A_MA6 P2 A5 DDR_A_MA6 P2 A5 DDR_A_MA3 1 2 36_0201_1%
RD169
DDR_A_MA7 R8 A6 A3 DDR_A_D13 DDR_A_MA7 R8 A6 A3 DDR_A_D47
DDR_A_MA4 1 2 36_0201_1%
DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D8 DDR_A_MA8 R2 A7 DQU0 B8 DDR_A_D45 RD170
DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D14 DDR_A_MA9 R7 A8 DQU1 C3 DDR_A_D46 DDR_A_MA5 1 2 36_0201_1%
RD171
DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D11 DDR_A_MA10 M3 A9 DQU2 C7 DDR_A_D41
DDR_A_MA6 1 2 36_0201_1%
DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D12 DDR_A_MA11 T2 A10/AP DQU3 C2 DDR_A_D43 RD172
DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D9 DDR_A_MA12 M7 A11 DQU4 C8 DDR_A_D44 DDR_A_MA7 1 2 36_0201_1%
RD173
DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D15 DDR_A_MA13 T8 A12/BC DQU5 D3 DDR_A_D42
DDR_A_MA8 1 2 36_0201_1%
DDR_A_MA14 A13 DQU6 DDR_A_D10 DDR_A_MA14 A13 DQU6 DDR_A_D40 RD174
L2 D7 L2 D7
A14/WE DQU7 A14/WE DQU7 DDR_A_MA9 1 2 36_0201_1%
+1.2V_DDR +1.2V_DDR RD175
DDR_A_BA0 N2 DDR_A_BA0 N2
<8,23> DDR_A_BA0 DDR_A_MA10 1 2 36_0201_1%
DDR_A_BA1 BA0 DDR_A_BA1 BA0 RD176
+1.2V_DDR <8,23> DDR_A_BA1 N8 B3 +1.2V_DDR N8 B3
BA1 VDD B9 BA1 VDD B9 DDR_A_MA11 1 2 36_0201_1%
RD177
40mil E2 VDD D1 40mil E2 VDD D1 DDR_A_MA12 1 2 36_0201_1%
E7 DMU/DBIU VDD G7 E7 DMU/DBIU VDD G7 RD178
DML/DBIL VDD J1 DML/DBIL VDD J1 DDR_A_MA13 1 2 36_0201_1%
RD179
VDD J9 VDD J9
VDD L1 VDD L1
DDR_A_CLK0 K7 VDD L9 DDR_A_CLK0 K7 VDD L9 DDR_A_MA14 1 2 36_0201_1%
<8,23> DDR_A_CLK0 RD180
DDR_A_CLK#0 K8 CK_t VDD R1 DDR_A_CLK#0 K8 CK_t VDD R1
<8,23> DDR_A_CLK#0 RD233 DDR_A_MA15 1 2 36_0201_1%
DDR_A_CKE0 K2 CK_c VDD T9 DDR_A_CKE0 K2 CK_c VDD T9 RD181
<8,23> DDR_A_CKE0 CKE VDD CKE VDD DDR_A_MA16
RD182 1 2 36_0201_1% +1.2V_DDR
A1 A1
VDDQ A9 VDDQ A9
VDDQ C1 VDDQ C1 DDR_A_BA0 1 2 36_0201_1%
VDDQ
RD232
VDDQ
0_0402_5% RD183

1
D9 D9 SD028000080 DDR_A_BA1 C2527
VDDQ VDDQ RD184 1 2 36_0201_1%
F2 F2 SDP8G@ 0.01U_0402_16V
VDDQ F8 VDDQ F8
DDR_A_ODT0 VDDQ DDR_A_ODT0 VDDQ

2
<8,23> DDR_A_ODT0 K3 G1 K3 G1
DDR_A_CS#0 L7 ODT VDDQ G9 DDR_A_CS#0 L7 ODT VDDQ G9
<8,23> DDR_A_CS#0 DDR_A_MA16 CS VDDQ DDR_A_MA16 CS VDDQ DDR_A_CLK0
L8 J2 RD232 BOM control for DDP@ to 240R /SDP@ to 0R 0_0402_5% L8 J2 RD233 BOM control for DDP@ to 240R /SDP@ to 0R RD185 1 2 36_0201_1%
DDR_A_MA15 M8 RAS VDDQ J8 DDR_A_MA15 M8 RAS VDDQ J8
SD028000080
CAS VDDQ SDP8G@ CAS VDDQ
DDR_A_CLK#0 1 2 36_0201_1%
B2 RD232 B2 RD233 RD186
VSS E1 240_0402_1% VSS E1 15mil 240_0402_1%
VSS DDP16G@ VSS DDP16G@
E9 15mil 2 1 E9 2 1
VSS G8 VSS G8 DDR_A_CKE0
DDR_A_DQS#1 VSS DDR_A_DQS#5 VSS RD187 1 2 36_0201_1%
A7 K1 A7 K1
DDR_A_DQS1 B7 DQSU_c VSS K9 DDR_A_DQS5 B7 DQSU_c VSS K9
DDP16G@ DDP16G@
DDR_A_DQS#0 F3 DQSU_t VSS M9 2 0_0201_5% DDR_A_BG1 DDR_A_DQS#4 DQSU_t VSS DDR_A_BG1 DDR_A_CS#0
RD242 1 DDR_A_BG1 <8,23> F3 M9 RD244 1 2 0_0201_5% RD188 1 2 36_0201_1%
B DDR_A_DQS0 G3 DQSL_c VSS N1 DDR_A_DQS4 G3 DQSL_c VSS N1 B
DQSL_t VSS T1 DQSL_t VSS T1 DDR_A_ODT0 1 2 36_0201_1%
SDP8G@ SDP8G@ RD189
DDR_DRAMRST#_R P1 VSS DDR_DRAMRST#_R VSS
<23,25,26> DDR_DRAMRST#_R RD243 1 2 0_0201_5% P1 RD245 1 2 0_0201_5%
RESET RESET DDR_A_ACT#
RD190 1 2 36_0201_1%
2 1 RD164 15mil F9 2 1 RD163 15mil F9
240_0402_1% ZQ 240_0402_1% ZQ DDR_A_BG0
RD191 1 2 36_0201_1%
DDR_A_ACT# L3 A2 DDR_A_ACT# L3 A2
<8,23> DDR_A_ACT# DDR_A_PARITY 1 2 36_0201_1%
DDR_A_BG0 M2 ACT VSSQ A8 DDR_A_BG0 M2 ACT VSSQ A8 RD192
<8,23> DDR_A_BG0 BG0 VSSQ BG0 VSSQ
N9 C9 N9 C9
DDR_A_ALERT# P9 TEN VSSQ D2 DDR_A_ALERT# P9 TEN VSSQ D2
<8,23> DDR_A_ALERT# DDR_A_PARITY ALERT VSSQ DDR_A_PARITY ALERT VSSQ
<8,23> DDR_A_PARITY T3 D8 T3 D8
PAR VSSQ E3 PAR VSSQ E3 +1.2V_DDR
T7 VSSQ E8 T7 VSSQ E8
40mil B1 NC VSSQ F1 40mil B1 NC VSSQ F1 DDR_A_ALERT#
+2.5V_MEM R9 VPP VSSQ H1
+2.5V_MEM R9 VPP VSSQ H1
RD193 2 1 49.9_0201_1%
VPP VSSQ H9 VPP VSSQ H9
96-BALL VSSQ 96-BALL VSSQ
SDRAM DDR4 SDRAM DDR4
K4A8G165W B-BCPB_FBGA96 K4A8G165W B-BCPB_FBGA96
@ @

UD3
UD3 UD3 UD3 UD3 UD3

DDR_DRAMRST#_R S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P

S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E SA0000B6F1L 16G/2666 H5ANAG6NCMR-VKC FBGA96P S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P
SA0000BMN1L SA0000ARD1L SAM8G@ SA0000BZJ1L SA0000BC71L SA0000B9K1L
HYX8G@ MCN8G@ HYX16G@ MCN16G@ SAM16G@
2
CD113
0.1U_0402_10V6K
@ESD@
1
UD4 UD4 UD4 UD4 UD4 UD4

PLACE NEAR TO UD3,UD4

A S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P 16G/2666 H5ANAG6NCMR-VKC FBGA96P S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P A
SA0000BMN1L SA0000ARD1L SA0000B6F1L SA0000BZJ1L SA0000BC71L SA0000B9K1L
HYX8G@ MCN8G@ SAM8G@ HYX16G@ MCN16G@ SAM16G@

Security Classification
2017/04/07
Compal Secret Data
2018/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P024-DDR4_CHA_Memory Down II
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-H351P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 30, 2019 Sheet 24 of 109
5 4 3 2 1
 5 4 3 2 1

DDR4 Memory Down_CHB <8,26>

<8,26>
DDR_B_MA[0..16]

DDR_B_DQS[0..7]

Non-Interleave Memory <8,26>

<8,26>
DDR_B_DQS#[0..7]

DDR_B_D[0..63]

D
DDR4 Memory Down_CHB Vinafix.com D

+1.2V_DDR

Closed to UD5 Closed to UD6

VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
SOC side Memory side
VDD DECAPS (1UF x3 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)

1
RD226 +1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +2.5V_MEM +0.6VS
1.8K_0402_1%

2
RD228

@RF@ CD390

@RF@ CD391

@RF@ CD392

@RF@ CD393

@RF@ CD394

@RF@ CD395
1 2
+0.6V_B_VREFDQ +0.6V_DDR_B_VREFDQ

100P_0201_50V8J

CD376

CD375

1U_0402_6.3V6K

CD368

1U_0402_6.3V6K

CD352

CD372

10U_0402_6.3V6M

10U_0402_6.3V6M

CD359

CD344

10U_0402_6.3V6M

100P_0201_50V8J

CD328

CD373

10U_0402_6.3V6M

100P_0201_50V8J

100P_0201_50V8J

CD350

CD338

1U_0402_6.3V6K

CD371

1U_0402_6.3V6K

CD374

CD332

10U_0402_6.3V6M

10U_0402_6.3V6M

CD331

CD333

10U_0402_6.3V6M

100P_0201_50V8J

CD341

CD349

10U_0402_6.3V6M

100P_0201_50V8J
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
2.7_0402_1% 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1

CD329

CD354

CD366

CD351

CD353

CD357

CD365

CD348
CD324
1

0.022U_0402_16V7K~D 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2
RD227
X10_12 1.8K_0402_1%
1

RD229
24.9_0402_1%
2

VREF traces should be at least 20 mils wide

with 20 mils spacing to other signals/planes.

+0.6V_DDR_B_VREFDQ
C C

+0.6V_DDR_B_VREFDQ
UD5

M1 G2 DDR_B_D29
All VREF traces should VREFCA DQL0 F7 DDR_B_D30
DDR_B_D25
UD6
DQL1
have 10 mil trace width 1 H3

0.047U_0402_10V7K

CD321
DDR_B_MA0 P3 DQL2 H7 DDR_B_D31 M1 G2 DDR_B_D61
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D28 1 VREFCA DQL0 F7 DDR_B_D58

0.047U_0402_10V7K

CD320
DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D26 DQL1 H3 DDR_B_D59
2 DDR_B_MA3 A2 DQL5 DDR_B_D24 DDR_B_MA0 DQL2 DDR_B_D63
N7 J3 P3 H7
DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D27 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D57
DDR_B_MA5 A4 DQL7 2 DDR_B_MA2 A1 DQL4 DDR_B_D56
P8 R3 H8
DDR_DRAMRST#_R DDR_B_MA6 P2 A5 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D62
DDR_B_MA7 R8 A6 A3 DDR_B_D22 DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D60
DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D20 DDR_B_MA5 P8 A4 DQL7
DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D23 DDR_B_MA6 P2 A5
2 DDR_B_MA10 A9 DQU2 DDR_B_D21 DDR_B_MA7 A6 DDR_B_D48
CD112 M3 C7 R8 A3
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D18 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D55
0.1U_0402_10V6K
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D17 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D51
@ESD@
1 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D19 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D50
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D16 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D52
A14/WE DQU7 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D49
DDR_B_BA0 +1.2V_DDR DDR_B_MA13 A12/BC DQU5 DDR_B_D54
N2 T8 D3
PLACE NEAR TO UD5,UD6 <8,26> DDR_B_BA0 DDR_B_BA1 N8 BA0 B3 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D53
+1.2V_DDR <8,26> DDR_B_BA1 BA1 VDD A14/WE DQU7 +1.2V_DDR
B9
40mil E2 VDD D1 DDR_B_BA0 N2
DMU/DBIU VDD +1.2V_DDR DDR_B_BA1 BA0
E7 G7 N8 B3
DML/DBIL VDD J1 40mil BA1 VDD B9
VDD J9 E2 VDD D1
VDD L1 E7 DMU/DBIU VDD G7
DDR_B_CLK0 K7 VDD L9 DML/DBIL VDD J1
<8,26> DDR_B_CLK0 DDR_B_CLK#0 CK_t VDD VDD
<8,26> DDR_B_CLK#0 K8 R1 J9
DDR_B_CKE0 K2 CK_c VDD T9 VDD L1
<8,26> DDR_B_CKE0 CKE VDD DDR_B_CLK0 VDD
RD234 K7 L9
DDR_B_CLK#0 K8 CK_t VDD R1
A1 DDR_B_CKE0 K2 CK_c VDD T9 RD235
VDDQ A9 CKE VDD
VDDQ C1
VDDQ D9 A1
VDDQ F2 VDDQ A9
VDDQ
0_0402_5% VDDQ
F8 SD028000080 C1
DDR_B_ODT0 K3 VDDQ G1 VDDQ D9
<8,26> DDR_B_ODT0 DDR_B_CS#0 ODT VDDQ
SDP8G@
VDDQ
0_0402_5%
<8,26> DDR_B_CS#0 L7 G9 F2 SD028000080
DDR_B_MA16 L8 CS VDDQ J2 VDDQ F8
RD234 BOM control for DDP@ to 240R /SDP@ to 0R SDP8G@
+1.2V_DDR DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_ODT0 K3 VDDQ G1
11/10 UPDATE ADD CAS VDDQ DDR_B_CS#0 L7 ODT VDDQ G9 RD235 BOM control for DDP@ to 240R /SDP@ to 0R
RD234 DDR_B_MA16 CS VDDQ
1 B2 L8 J2
VSS E1 240_0402_1% DDR_B_MA15 M8 RAS VDDQ J8
+ VSS E9 2 DDP16G@
1 CAS VDDQ RD235
CD330 15mil
VSS 240_0402_1%
B
330U_D3_2.5VY_R6M G8 B2 B
DDR_B_DQS#2 A7 VSS K1 VSS E1 15mil 2 DDP16G@
1
2 DDR_B_DQS2 B7 DQSU_c VSS K9 VSS E9
<BOM Structure> DDP16G@
DDR_B_DQS#3 F3 DQSU_t VSS M9 2 0_0201_5% DDR_B_BG1 VSS
RD2461 DDR_B_BG1 <8,26> G8
DDR_B_DQS3 G3 DQSL_c VSS N1 DDR_B_DQS#6 A7 VSS K1 DDP16G@
DQSL_t VSS T1 DDR_B_DQS6 B7 DQSU_c VSS K9 DDR_B_BG1
SDP8G@ RD2481 2 0_0201_5%
DDR_DRAMRST#_R P1 VSS DDR_B_DQS#7 DQSU_t VSS
<23,24,26> DDR_DRAMRST#_R RD2471 2 0_0201_5% F3 M9
RESET DDR_B_DQS7 G3 DQSL_c VSS N1 SDP8G@
2 1 RD195 15mil F9 DQSL_t VSS T1 RD2491 2 0_0201_5%
ZQ DDR_DRAMRST#_R P1 VSS
240_0402_1%
2 1 RD194 15mil RESET
DDR_B_ACT# L3 A2 F9
<8,26> DDR_B_ACT# 240_0402_1%
DDR_B_BG0 M2 ACT VSSQ A8 ZQ
<8,26> DDR_B_BG0 BG0 VSSQ
N9 C9
DDR_B_ALERT# P9 TEN VSSQ D2 DDR_B_ACT# L3 A2
<8,26> DDR_B_ALERT# DDR_B_PARITY ALERT VSSQ DDR_B_BG0 ACT VSSQ
<8,26> DDR_B_PARITY T3 D8 M2 A8
PAR VSSQ E3 N9 BG0 VSSQ C9
T7 VSSQ E8 DDR_B_ALERT# P9 TEN VSSQ D2
40mil B1 NC VSSQ F1 DDR_B_PARITY T3 ALERT VSSQ D8
+2.5V_MEM R9 VPP VSSQ H1 PAR VSSQ E3
VPP VSSQ H9 40mil T7 VSSQ E8
96-BALL VSSQ +2.5V_MEM B1 NC VSSQ F1
SDRAM DDR4 R9 VPP VSSQ H1
K4A8G165W B-BCPB_FBGA96 VPP VSSQ H9
96-BALL VSSQ
@
SDRAM DDR4
K4A8G165W B-BCPB_FBGA96
@

UD5 UD5
UD5 UD5 UD5 UD5

S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P

SA0000BMN1L 8G(DDR4-2666)_MT40A512M16LY-075:E SA0000B6F1L 16G/2666 H5ANAG6NCMR-VKC FBGA96P S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P
HYX8G@ SA0000ARD1L SAM8G@ SA0000BZJ1L SA0000BC71L SA0000B9K1L
MCN8G@ HYX16G@ MCN16G@ SAM16G@

UD6 UD6 UD6 UD6

UD6 UD6

A A

8G(DDR4-2666)_MT40A512M16LY-075:E 16G/2666 H5ANAG6NCMR-VKC FBGA96P S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P
S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA SA0000ARD1L S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P SA0000BZJ1L SA0000BC71L SA0000B9K1L
SA0000BMN1L MCN8G@ SA0000B6F1L HYX16G@ MCN16G@ SAM16G@
HYX8G@ SAM8G@

Security Classification
2017/04/07
Compal Secret Data
2018/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P025-DDR4_CHB_Memory Down I
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-H351P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 30, 2019 Sheet 25 of 109
5 4 3 2 1
 5 4 3 2 1

DDR4 Memory Down_CHB <8,25>

<8,25>
DDR_B_MA[0..16]

DDR_B_DQS[0..7]

Non-Interleave Memory <8,25>

<8,25>
DDR_B_DQS#[0..7]

DDR_B_D[0..63]

D
Vinafix.com D

Closed to UD7 Closed to UD8

VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1) VDD DECAPS (1UF x3 / 10UF x1) VPP DECAPS (1UF x2 / 10UF x1) VTT DECAPS (1UF x2 / 10UF x1)
VDDQ DECAPS (1UF x2 / 10UF x1) VDDQ DECAPS (1UF x2 / 10UF x1)
+1.2V_DDR +2.5V_MEM +0.6VS +1.2V_DDR +2.5V_MEM +0.6VS

@RF@ CD396

@RF@ CD397

@RF@ CD398

@RF@ CD399

@RF@ CD400

@RF@ CD401
100P_0201_50V8J

CD355

CD356

CD335

CD334

CD367

10U_0402_6.3V6M

10U_0402_6.3V6M

CD377

CD370

10U_0402_6.3V6M

100P_0201_50V8J

CD364

CD336

10U_0402_6.3V6M

100P_0201_50V8J

100P_0201_50V8J

CD343

CD362

CD360

CD346

CD325

10U_0402_6.3V6M

10U_0402_6.3V6M

CD327

CD345

10U_0402_6.3V6M

100P_0201_50V8J

CD337

CD361

10U_0402_6.3V6M

100P_0201_50V8J
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

CD340

CD339

CD347

CD363

CD358

CD369

CD326

CD342
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+0.6V_DDR_B_VREFDQ
C C
+0.6V_DDR_B_VREFDQ
UD7
All VREF traces should DDR_B_D11
UD8
have 10 mil trace width M1
VREFCA DQL0
G2
DDR_B_D8 DDR_B_D47
F7 200mil M1 G2
1 DQL1 H3 DDR_B_D10 VREFCA DQL0 F7 DDR_B_D45
0.047U_0201_10V6K
CD323

DDR_B_MA0 P3 DQL2 H7 DDR_B_D9 1 DQL1 H3 DDR_B_D43

0.047U_0201_10V6K
CD322
DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D14 DDR_B_MA0 P3 DQL2 H7 DDR_B_D41 +0.6VS
DDR_B_MA2 R3 A1 DQL4 H8 DDR_B_D13 DDR_B_MA1 P7 A0 DQL3 H2 DDR_B_D42
2 DDR_B_MA3 A2 DQL5 DDR_B_D15 DDR_B_MA2 A1 DQL4 DDR_B_D44
N7 J3 2 R3 H8
DDR_B_MA4 N3 A3 DQL6 J7 DDR_B_D12 DDR_B_MA3 N7 A2 DQL5 J3 DDR_B_D46
DDR_B_MA0 1 2 36_0201_1%
DDR_B_MA5 A4 DQL7 DDR_B_MA4 A3 DQL6 DDR_B_D40 RD206
P8 N3 J7
DDR_B_MA6 P2 A5 DDR_B_MA5 P8 A4 DQL7 DDR_B_MA1 1 2 36_0201_1%
RD198
DDR_B_MA7 R8 A6 A3 DDR_B_D2 DDR_B_MA6 P2 A5
DDR_B_MA2 1 2 36_0201_1%
DDR_B_MA8 A7 DQU0 DDR_B_D0 DDR_B_MA7 A6 DDR_B_D35 RD217
R2 B8 R8 A3
DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D6 DDR_B_MA8 R2 A7 DQU0 B8 DDR_B_D32 DDR_B_MA3 1 2 36_0201_1%
RD213
DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D1 DDR_B_MA9 R7 A8 DQU1 C3 DDR_B_D37
DDR_B_MA4 1 2 36_0201_1%
DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D3 DDR_B_MA10 M3 A9 DQU2 C7 DDR_B_D38 RD205
DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D5 DDR_B_MA11 T2 A10/AP DQU3 C2 DDR_B_D33 DDR_B_MA5 1 2 36_0201_1%
RD204
DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D7 DDR_B_MA12 M7 A11 DQU4 C8 DDR_B_D34
DDR_B_MA6 1 2 36_0201_1%
DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D4 DDR_B_MA13 T8 A12/BC DQU5 D3 DDR_B_D39 RD211
A14/WE DQU7 DDR_B_MA14 L2 A13 DQU6 D7 DDR_B_D36 DDR_B_MA7 1 2 36_0201_1%
+1.2V_DDR RD216
DDR_B_BA0 N2 A14/WE DQU7
<8,25> DDR_B_BA0 +1.2V_DDR DDR_B_MA8 1 2 36_0201_1%
DDR_B_BA1 N8 BA0 B3 DDR_B_BA0 N2 RD214
+1.2V_DDR <8,25> DDR_B_BA1 BA1 VDD DDR_B_BA1 BA0 DDR_B_MA9
B9 +1.2V_DDR N8 B3 RD224 1 2 36_0201_1%
40mil E2 VDD D1 BA1 VDD B9 DDR_B_MA10
DMU/DBIU VDD VDD RD209 1 2 36_0201_1%
E7 G7 40mil E2 D1
DML/DBIL VDD J1 E7 DMU/DBIU VDD G7 DDR_B_MA11 1 2 36_0201_1%
RD215
VDD J9 DML/DBIL VDD J1 DDR_B_MA12 1 2 36_0201_1%
VDD VDD RD219
L1 J9
DDR_B_CLK0 K7 VDD L9 VDD L1 DDR_B_MA13 1 2 36_0201_1%
<8,25> DDR_B_CLK0 RD236 RD221
DDR_B_CLK#0 K8 CK_t VDD R1 DDR_B_CLK0 K7 VDD L9 11/7 UPDATE RD237
<8,25> DDR_B_CLK#0 DDR_B_CKE0 CK_c VDD DDR_B_CLK#0 CK_t VDD
<8,25> DDR_B_CKE0 K2 T9 K8 R1 RD237
CKE VDD DDR_B_CKE0 K2 CK_c VDD T9 DDR_B_MA14 1 2 36_0201_1%
RD203
CKE VDD DDR_B_MA15
RD223 1 2 36_0201_1%
A1
VDDQ A9 A1 DDR_B_MA16 1 2 36_0201_1%
VDDQ
0_0402_5% VDDQ
RD222
C1 SD028000080 A9
VDDQ D9 VDDQ C1 +1.2V_DDR
VDDQ
SDP8G@
VDDQ
0_0402_5%
F2 D9 SD028000080
VDDQ F8 VDDQ F2 DDR_B_BA0 1 2 36_0201_1%
SDP8G@ RD218
DDR_B_ODT0 K3 VDDQ G1 VDDQ F8
<8,25> DDR_B_ODT0 DDR_B_BA1 1 2 36_0201_1%
DDR_B_CS#0 L7 ODT VDDQ G9 DDR_B_ODT0 K3 VDDQ G1 RD212
<8,25> DDR_B_CS#0 DDR_B_MA16 CS VDDQ DDR_B_CS#0 ODT VDDQ
L8 J2 RD236 BOM control for DDP@ to 240R /SDP@ to 0R L7 G9
DDR_B_MA15 M8 RAS VDDQ J8 DDR_B_MA16 L8 CS VDDQ J2 RD237 BOM control for DDP@ to 240R /SDP@ to 0R
CAS VDDQ DDR_B_MA15 RAS VDDQ

1
M8 J8 C2528
RD236 CAS VDDQ DDR_B_CLK0
B2 RD201 1 2 36_0201_1% 0.01U_0402_16V
VSS E1 240_0402_1% B2 RD237
VSS DDP16G@ VSS 240_0402_1%

2
E9 15mil 2 1 E1 DDR_B_CLK#0
VSS VSS DDP16G@ RD225 1 2 36_0201_1%
B G8 E9 15mil 2 1 B
DDR_B_DQS#0 A7 VSS K1 VSS G8
DDR_B_DQS0 B7 DQSU_c VSS K9 DDR_B_DQS#4 A7 VSS K1
DDP16G@
DDR_B_DQS#1 F3 DQSU_t VSS M9 2 0_0201_5% DDR_B_BG1 DDR_B_DQS4 DQSU_c VSS
RD2501 DDR_B_BG1 <8,25> B7 K9 RD252 DDP16G@ DDR_B_CKE0 1 2 36_0201_1%
DDR_B_DQS1 G3 DQSL_c VSS N1 DDR_B_DQS#5 F3 DQSU_t VSS M9 1 2 0_0201_5% DDR_B_BG1 RD220
DQSL_t VSS T1 DDR_B_DQS5 G3 DQSL_c VSS N1
SDP8G@
DDR_DRAMRST#_R P1 VSS DQSL_t VSS DDR_B_CS#0
<23,24,25> DDR_DRAMRST#_R RD2511 2 0_0201_5% T1 SDP8G@ RD207 1 2 36_0201_1%
RESET DDR_DRAMRST#_R P1 VSS RD2531 2 0_0201_5%
2 1 RD196 15milF9 RESET DDR_B_ODT0 1 2 36_0201_1%
RD199
240_0402_1% ZQ 2 1 RD197 15mil F9
240_0402_1% ZQ DDR_B_ACT#
DDR_B_ACT# RD200 1 2 36_0201_1%
<8,25> DDR_B_ACT# L3 A2
DDR_B_BG0 M2 ACT VSSQ A8 DDR_B_ACT# L3 A2
<8,25> DDR_B_BG0 DDR_B_BG0 1 2 36_0201_1%
N9 BG0 VSSQ C9 DDR_B_BG0 M2 ACT VSSQ A8 RD210
DDR_B_ALERT# P9 TEN VSSQ D2 N9 BG0 VSSQ C9
<8,25> DDR_B_ALERT# DDR_B_PARITY 1 2 36_0201_1%
DDR_B_PARITY ALERT VSSQ DDR_B_ALERT# TEN VSSQ RD208
<8,25> DDR_B_PARITY T3 D8 P9 D2
PAR VSSQ E3 DDR_B_PARITY T3 ALERT VSSQ D8
VSSQ PAR VSSQ DDR_B_BG1 RD255
T7 E8 E3 1 2 36_0201_1%
40mil B1 NC VSSQ F1 T7 VSSQ E8
+2.5V_MEM R9 VPP VSSQ H1 40mil B1 NC VSSQ F1 +1.2V_DDR
VPP VSSQ H9
+2.5V_MEM R9 VPP VSSQ H1
96-BALL VSSQ VPP VSSQ H9 DDR_B_ALERT#
VSSQ RD202 2 1 49.9_0201_1%
SDRAM DDR4 96-BALL
K4A8G165W B-BCPB_FBGA96 SDRAM DDR4
@ K4A8G165W B-BCPB_FBGA96
@

DDR_DRAMRST#_R
0.1U_0201_10V6K

1
CD114

UD7 UD7 UD7

UD7 UD7 UD7
2
@ESD@

A
PLACE NEAR TO UD7,UD8 S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P
16G/2666 H5ANAG6NCMR-VKC FBGA96P
SA0000BZJ1L
S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA
SA0000BC71L
S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P
SA0000B9K1L A
SA0000BMN1L SA0000ARD1L SA0000B6F1L HYX16G@ MCN16G@ SAM16G@
HYX8G@ MCN8G@ SAM8G@
UD8
UD8 UD8
UD8 UD8 UD8

S IC D4 16G/2666 K4AAG165WB-MCTD FBGA96P

S IC D4 512M16/2666 H5AN8G6NCJR-VKC FBGA 8G(DDR4-2666)_MT40A512M16LY-075:E SA0000B9K1L
SA0000BMN1L SA0000ARD1L S IC D4 512M16 K4A8G165WC-BCTD FBGA 96P 16G/2666 H5ANAG6NCMR-VKC FBGA96P S IC D4 16G/2666 MT40A1G16KNR-075:E FBGA SAM16G@
HYX8G@ MCN8G@ SA0000B6F1L SA0000BZJ1L SA0000BC71L
SAM8G@ HYX16G@ MCN16G@

Security Classification
2017/04/07
Compal Secret Data
2018/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P026-DDR4_CHB_Memory Down II
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

LA-H351P
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS D 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, May 30, 2019 Sheet 26 of 109
5 4 3 2 1
 A B C D E

UG1

S IC N18E-G1-KD-A1 FCBGA 2228 GPU

SA0000CFC2L
N18EG1@

UG1

+1V8_AON

GC OFF 1.0 GPU Power ON/OFF

1
PEX_RST#
@

RG1522
10K_0201_5%
1 2
Vinafix.com S IC N18E-G2-A1 FCBGA 2228
SA0000CCX2L
N18EG2@
1

+1V8_AON

UG1
1 2 1
CG6824
RG3 0.1U_0201_6.3V6K
10K_0201_5%
2

5
S IC N18E-G3-A1 FCBGA 2228

GND VCC
PEX_RST# 1 SA0000CD52L
<18> PEX_RST# IN B 4 1 2 N18EG3@
2 OUT Y RG537 0_0201_5%
<15,74> PCH_PLTRST# IN A

1
UG10 RG562
NL17SZ08DFT2G_SC70-5 100K_0402_5% UG1

3
@

2
S IC N18E-G0-A1 QS BGA 2228 GPU
SA0000CK43L
N18EG0@
<30,39,40> DGPU_PEX_RST#

+PEX_VDD
PEX_DVDD 11/21 Update UG1 料 號 Fo r PV T R3

PEX_CVDD

4.7U_0402_4V_M

4.7U_0402_4V_M

4.7U_0402_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M
+1V8_AON 1 1 1 1 1 1 1 1 1 1 1

047@

047@

047@

047@

047@
CG29

CG28

CG27

CG19

CG20

CG21

CG22

CG23

CG24

CG25

CG26
2 2 2 2 2 2 2 2 2 2 2
1
CG483
0.1U_0201_6.3V6K
2
5

+1V8_AON
GND VCC

Under GPU
UG1A
<37,97> +1.35VS_VGA_PGOOD IN B 4 2 1
NVVDD_PGOOD OUT Y

2
2 RG1 0_0201_5% PEX_WAKE# doesn’ t appl y i n not ebook MBD. 1/22 PCI_EXPRESS
<30,32,39,95,99> NVVDD_PGOOD IN A +PEX_VDD +PEX_VDD
RG2
10K_0201_5% PEX_W AKE# BK44
UG29 @ T14 PAD~D PEX_WAKE
BB35

Near GPU
NL17SZ08DFT2G_SC70-5 PEX_DVDD
DGPU_PEX_RST# DGPU_PEX_RST#_R BK26
3

2
1 2 BB36

G
PEX_RST PEX_DVDD

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
1
2 RG4 0_0201_5% PEX_DVDD BC35 1 1 1 1 1 1 1 1 2 2 2 1 1
2
1 3 CLKREQ_PEG#0_R BL26 BC36
<15> CLKREQ_PEG#0 PEX_CLKREQ PEX_DVDD
BD33

CG5

CG6

CG7

CG1

CG2
CG11

CG12

CG13

CG14

CG15

CG16

CG17

CG18
PEX_DVDD

S
QG510 BM26 PEX_REFCLK PEX_DVDD BD36
<15> CLK_PEG_P0 BM27 2 2 2 2 2 2 2 2 1 1 1 2 2
MESS138W -G_SOT323-3 PEX_REFCLK
<15> CLK_PEG_N0
PEX_CVDD BB33
PEG_CRX_GTX_P0 2 1 PEG_CRX_C_GTX_P0 BG26 BC33
<6> PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 PEG_CRX_C_GTX_N0 PEX_TX0 PEX_CVDD
0.22U_0201_6.3V 2 1 CC50 BH26 PEX_TX0
<6> PEG_CRX_GTX_N0 0.22U_0201_6.3V CC51
BL27 PEX_RX0
<6> PEG_CTX_C_GRX_P0
BK27 PEX_RX0
<6> PEG_CTX_C_GRX_N0 +1V8_MAIN +1V8_MAIN
PEG_CRX_GTX_P1 2 1 PEG_CRX_C_GTX_P1 BF26
<6> PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 PEG_CRX_C_GTX_N1 PEX_TX1
0.22U_0201_6.3V 2 1 CC48 BE26 BB26

Near GPU
<6> PEG_CRX_GTX_N1 PEX_TX1 PEX_HVDD

0.47U_0201_4VAM

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M
0.22U_0201_6.3V CC43 PEX_HVDD BB27 1 1 1 1

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
BK29 PEX_RX1 PEX_HVDD BB29 1 1 1 1 1 2 2 2 1 1
<6> PEG_CTX_C_GRX_P1 BL29 BB32

047@

047@

047@

047@
CG36

CG37

CG38

CG39
<6> PEG_CTX_C_GRX_N1 PEX_RX1 PEX_HVDD
BC26

CG8

CG9

CG3

CG4
CG31

CG32

CG33

CG34

CG35

CG10
PEG_CRX_GTX_P2 PEG_CRX_C_GTX_P2 PEX_HVDD
2 1 BF27 BC27 2 2 2 2
<6> PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_C_GTX_N2 PEX_TX2 PEX_HVDD
0.22U_0201_6.3V 2 1 CC45 BG27 BC29 2 2 2 2 2 1 1 1 2 2
<6> PEG_CRX_GTX_N2 PEX_TX2 PEX_HVDD
0.22U_0201_6.3V CC44 PEX_HVDD BC30
BM29 PEX_RX2 PEX_HVDD BC32
<6> PEG_CTX_C_GRX_P2
BM30 PEX_RX2 PEX_HVDD BD27
<6> PEG_CTX_C_GRX_N2 BD30

Under GPU
PEG_CRX_GTX_P3 PEG_CRX_C_GTX_P3 PEX_HVDD
2 1 BG29 PEX_TX3
<6> PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 0.22U_0201_6.3V PEG_CRX_C_GTX_N3
2 1 CC49 BH29 PEX_TX3
<6> PEG_CRX_GTX_N3 0.22U_0201_6.3V CC41
BL30 PEX_RX3
<6> PEG_CTX_C_GRX_P3 BK30
<6> PEG_CTX_C_GRX_N3 PEX_RX3
+1V8_MAIN
PEG_CRX_GTX_P4 2 1 PEG_CRX_C_GTX_P4 BF29
<6> PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 PEG_CRX_C_GTX_N4 PEX_TX4
0.22U_0201_6.3V 2 1 CC47 BE29

Under GPU
<6> PEG_CRX_GTX_N4 PEX_TX4
0.22U_0201_6.3V CC53

4.7U_0402_4V_M

4.7U_0402_4V_M

4.7U_0402_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M
BK32 PEX_RX4 1 1 1 1 1
<6> PEG_CTX_C_GRX_P4 BL32
<6> PEG_CTX_C_GRX_N4 PEX_RX4

047@

047@
CG45

CG43

CG42

CG41

CG40
PEG_CRX_GTX_P5 2 1 PEG_CRX_C_GTX_P5 BF30
<6> PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 PEG_CRX_C_GTX_N5 PEX_TX5
0.22U_0201_6.3V 2 1 CC52 BG30 2 2 2 2 2
<6> PEG_CRX_GTX_N5 PEX_TX5 +PEX_PLL_HVDD
0.22U_0201_6.3V CC40 PEX_PLL_HVDD BB30 1 2
+1V8_MAIN
BM32 PEX_RX5
<6> PEG_CTX_C_GRX_P5
BM33 PEX_RX5 1 LG1
<6> PEG_CTX_C_GRX_N5
CG30 PBY160808T-301Y-N
PEG_CRX_GTX_P6 2 1 PEG_CRX_C_GTX_P6 BG32 PEX_TX6 1U_0201_4V6M
<6> PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 0.22U_0201_6.3V 2 1 CC42 PEG_CRX_C_GTX_N6 BH32
<6> PEG_CRX_GTX_N6 PEX_TX6
0.22U_0201_6.3V CC55 2

<6>
<6>
PEG_CTX_C_GRX_P6
PEG_CTX_C_GRX_N6
BL33
BK33
PEX_RX6
PEX_RX6
PEX_HVDD
<6>
<6>
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
PEG_CRX_GTX_P7
PEG_CRX_GTX_N7
0.22U_0201_6.3V
0.22U_0201_6.3V
2
2
1 CC54
1 CC46
PEG_CRX_C_GTX_P7
PEG_CRX_C_GTX_N7
BF32
BE32
PEX_TX7
PEX_TX7
Under GPU PEX_PLL_HVDD
3 3
BK35 PEX_RX7
<6> PEG_CTX_C_GRX_P7
BL35 PEX_RX7
<6> PEG_CTX_C_GRX_N7
BF33 PEX_TX8
BG33 PEX_TX8

BM35 PEX_RX8
BM36 PEX_RX8

BG35 PEX_TX9
BH35 PEX_TX9

BL36 PEX_RX9
22uF 10uF 4.7uF 1uF 0.1uF
BK36 PEX_RX9

BF35
BE35
PEX_TX10
PEX_TX10 PEX_DVDD 2 3 3 8
BK38 PEX_RX10
BL38 PEX_RX10
PEX_HVDD 2 3 3 5
BF36 PEX_TX11
BG36 PEX_TX11

BM38 PEX_RX11
BM39 PEX_RX11

BG38 PEX_TX12
BH38 PEX_TX12

BL39 PEX_RX12
BK39 PEX_RX12

BF38 PEX_TX13
BE38 PEX_TX13

BK41 PEX_RX13
BL41 PEX_RX13

BF39 PEX_TX14
BG39 PEX_TX14

BM41 PEX_RX14
BM42 PEX_RX14

BH41 PEX_TX15
BG41 PEX_TX15

BL42 BL44 PEX_TERMP 2 1

PEX_RX15 PEX_TERMP
4 BK42 PEX_RX15 4
RG23
2.49K_0402_1%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P027-NV(1/7) PCI EXPRESS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 27 of 109
A B C D E
 A B C D E

UG1N

7/22 IFPAB
Place Near GPU
DL-DVI DVI/HDMI DP

SDA SDA IFPA_AUX BH11

+1V8_MAIN
Under GPU UG1V
13/22 XTAL/PLL

RG1502
Vinafix.com
SCL SCL IFPA_AUX BG11
1 2 BD12 SP_PLLVDD

1U_0201_4V6M

1U_0201_4V6M
22U_0603_4V_M

4.7U_0402_4V_M
1K_0402_1% IFPA_L3 BF21 LG8 1 1 1 1 BC12 VID_PLLVDD
2 1 IFPAB_RSET BD23 TX C TX C
BG21 PBY160808T-300Y-N_2P

CG911

CG896

CG907
CG6501
1
IFPAB_RSET TX C TX C IFPA_L3 1

100MHz 2 2 2 2
IFPA_L2 BG23
TXD0 TXD0
IFPA_L2 BH23 30ohm, Bead
TXD0 TXD0
+1V8_MAIN BD21 IFPAB_PLLVDD

IFPA_L1 BF23

1U_0201_4V6M
TXD1 TXD1
1 TXD1 TXD1 IFPA_L1 BE23
CG312 U42 GPCPLL_AVDD0

TXD2 TXD2 IFPA_L0 BF24 AF11 GPCPLL_AVDD1

2 BG24
IFPA_L0

1U_0201_4V6M

1U_0201_4V6M

1U_0201_4V6M
TXD2 TXD2
1 1 1 BB24 XSN_PLLVDD

CG908

CG909

CG910
2 2 2

Under GPU
XTALOUTBUFF : 100K ohm pull down only.
IFPB_AUX BG12
SDA +1V8_AON
SCL IFPB_AUX BH12 @
RG1497
BL18 BJ6 BK6 XTALOUTBUFF_R 1 2
IFPB_L3 EXT_REFCLK_FL XTALOUTBUFF
TX C
BB18 IFP_IOVDD IFPB_L3 BK18
+PEX_VDD TX C
BB17 IFP_IOVDD BL6 XTALIN XTALOUT BM6
100K_0402_5%

1
1U_0201_4V6M
4.7U_0402_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

1 1 1 1 1 BB20 IFP_IOVDD TXD3 TXD0 IFPB_L2 BK20 RG1498 RG1496 RG98

BB21 BL20 10K_0402_5% 10K_0402_5% @ 100K_0402_5%
CG7136

CG7137

CG7138

CG7139

CG7140

IFP_IOVDD TXD3 TXD0 IFPB_L2

RG99

2
2 2 2 2 2 BM20 10M_0402_5%
TXD4 TXD1 IFPB_L1
@ TXD4 TXD1 IFPB_L1 BM21 1 2
1
CG6825 YG1
TXD5 TXD2 IFPB_L0 BL21 18P_0402_50V8J
BK21 XTALIN 1 3 XTALOUT
Near GPU
TXD5 TXD2 IFPB_L0
2 1 3
2 2
IFPAB GND GND

Under GPU
2 CG75 CG76 2
22P_0402_50V8J 22P_0402_50V8J
2 4
@ 1 1

27MHZ 16PF +-30PPM 7M27070004F50Q5

2
RG1499
1K_0402_1%
1
HDMI 2.0
UG1O
8/22 IFPC

IFPCD_RSET BD20 IFPCD_RSET

+1V8_MAIN +IFPCD_PLLVDD

1 2
Under GPU BD18
DVI/HDMI DP

BL9
IFPCD_PLLVDD SDA IFPC_AUX GPU_HDMI_CTRL_DAT <40>
IFPC_AUX BK9
SCL GPU_HDMI_CTRL_CLK <40>
LG10
1U_0201_4V6M
22U_0603_4V_M

4.7U_0402_4V_M

PBY160808T-300Y-N_2P 1 1
1

BF17
eDP
CG7110

CG7109

CG7108

TXC IFPC_L3 GPU_HDMI_CLKN <40>

IFPC_L3 BE17
TXC GPU_HDMI_CLKP <40>
2

2 2 BF18
TXD0 IFPC_L2 GPU_HDMI_TX_N0 <40>
IFPC_L2 BG18 UG1P
TXD0 GPU_HDMI_TX_P0 <40>

Near GPU
9/22 IFPD
IFPC IFPC_L1 BG20
TXD1 GPU_HDMI_TX_N1 <40>
TXD1 IFPC_L1 BH20
GPU_HDMI_TX_P1 <40>
DVI/HDMI DP
IFPC_L0 BF20
TXD2 GPU_HDMI_TX_N2 <40>
TXD2 IFPC_L0 BE20 GPU_HDMI_TX_P2 <40>
IFPD_AUX BF11
SDA
IFPD_AUX BE11
SCL
+PEX_VDD BB23 IFP_IOVDD
BC17 IFP_IOVDD
TXC IFPD_L3 BM14
1U_0201_4V6M
4.7U_0402_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

3 3
1 1 1 1 TXC IFPD_L3 BM15
@
CG7125

CG7126

CG7127

CG6502

TXD0 IFPD_L2 BL15

TXD0 IFPD_L2 BK15
2 2 2 2
IFPD IFPD_L1 BK17
TXD1
TXD1 IFPD_L1 BL17

TXD2 IFPD_L0 BM17

BM18
Near GPU Under GPU
TXD2 IFPD_L0

BC18 IFP_IOVDD
BC20
mini DP
IFP_IOVDD

UG1Q @
10/22 IFPE
DVI/HDMI DP
RG1500
1K_0402_1%
2 1 IFPEF_RSET BD17 BL8
IFPE_RSET SDA IFPE_AUX GPU_DP_AUXN <39>
SCL IFPE_AUX BK8
+1V8_MAIN +IFPE_PLLVDD GPU_DP_AUXP <39>

1 2
Under GPU BD15
TXC IFPE_L3 BG14
BH14
GPU_DP_N3 <39>
IFPE_PLLVDD TXC IFPE_L3 GPU_DP_P3 <39>
LG9 IFPE_L2 BF14
GPU_DP_N2 <39>
1U_0201_4V6M
22U_0603_4V_M

TXD0
4.7U_0402_4V_M

PBY160808T-300Y-N_2P 1 1 TXD0 IFPE_L2 BE14 GPU_DP_P2 <39>

1

CG6507

CG6804

CG6509

TXD1 IFPE_L1 BF15

GPU_DP_N1 <39>
TXD1 IFPE_L1 BG15 GPU_DP_P1 <39>
2

2 2 IFPE
TXD2 IFPE_L0 BG17 GPU_DP_N0 <39>
BH17
Near GPU
TXD2 IFPE_L0 GPU_DP_P0 <39>
4 4

+PEX_VDD BC21 IFP_IOVDD

BC23 IFP_IOVDD
1U_0201_4V6M

1U_0201_4V6M
4.7U_0402_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

1 1 1 1 1
CG6506

CG7133

CG7134

CG7135

CG6508

@
2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

P028-NV(2/7) IFP_ABCDEF_DAC_XTAL
Near GPU Under GPU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size Document Number

LA-H351P
Rev
0.1

Date: Thursday, May 30, 2019 Sheet 28 of 109

A B C D E
 5 4 3 2 1

UG1K +1V8_AON
20/22 NC/1V8

1V8_AON BA10
UG1F UG1G
1V8_AON BB14
UG1H
15/22 GND_1/3 16/22 GND_2/3 1V8_AON BC14
21/22 GND_3/3
A2 GND GND AH6 AR20 GND GND B52 +1V8_AON
A26 GND GND AH8 AR21 GND GND B7 BL40 GND GND N51 +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD +NVVDD
A29 GND GND AJ14 AR22 GND GND BA48 BL43 GND GND N6 UG9
UG1I UG1J UG1M FP_FUSE_GPU
A3 AJ15 AR23 BA9 BL5 N8 6 1 BD14 BD24

2.2U_0402_6.3V6M
GND GND GND GND GND GND FP_FUSE_SRC NC
A32 GND GND AJ16 AR24 GND GND BB49 BL7 GND GND P14 17/22 VDD_1/3 18/22 VDD_2/3 22/22 VDD_3/3 5 VIN1 VOUT1 2 NC BM44

Vinafix.com
VIN2 VOUT2

2
A50 AJ17 AR25 BC13 BM2 P15 BM45

2.2U_0402_6.3V6M
D GND GND GND GND GND GND NC D

2
A51 AJ18 AR26 BC16 BM3 P16 AA13 AE28 AH39 AP23 4 3 RG1559

CG7117
GND GND GND GND GND GND VDD VDD VDD VDD
VSS EN

2
AA49 GND GND AJ19 AR27 GND GND BC19 C1 GND GND P17 AA14 VDD VDD AE29 AH40 VDD VDD AP24 BG45 VDD VDD R23 2.21K_0402_1%
AA8 AJ2 AR28 BC2 C29 P18 AA15 AE30 AJ13 AP25 BG46 R24 GS7616SC-R_SOT363-6

CG270
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD

1
AB10 GND GND AJ20 AR29 GND GND BC22 C33 GND GND P19 AA16 VDD VDD AE31 AJ40 VDD VDD AP26 BG47 VDD VDD R25

1
AB14 GND GND AJ21 AR30 GND GND BC25 C5 GND GND P20 AA17 VDD VDD AE32 AK13 VDD VDD AP27 BG48 VDD VDD R26
AB15 GND GND AJ22 AR31 GND GND BC28 C51 GND GND P21 AA18 VDD VDD AE33 AK14 VDD VDD AP28 BG49 VDD VDD R27
AB16 GND GND AJ23 AR32 GND GND BC31 C52 GND GND P22 AA19 VDD VDD AE34 AK15 VDD VDD AP29 BG50 VDD VDD R28 @
AB17 GND GND AJ24 AR33 GND GND BC34 D10 GND GND P23 AA20 VDD VDD AE35 AK16 VDD VDD AP30 BG51 VDD VDD R29
AB18 AJ25 AR34 BC37 D12 P24 AA21 AE36 AK17 AP31 BG52 R30 <30> FP_FUSE
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD
AB19 GND GND AJ26 AR35 GND GND BC4 D13 GND GND P25 AA22 VDD VDD AE37 AK18 VDD VDD AP32 BH44 VDD VDD R31

2
AB2 GND GND AJ27 AR36 GND GND BC51 D16 GND GND P26 AA23 VDD VDD AE38 AK19 VDD VDD AP33 BH45 VDD VDD R32
AB20 GND GND AJ28 AR37 GND GND BC6 D19 GND GND P27 AA24 VDD VDD AE39 AK20 VDD VDD AP34 BH47 VDD VDD R33 RG1558
AB21 GND GND AJ29 AR38 GND GND BC8 D22 GND GND P28 AA25 VDD VDD AE40 AK21 VDD VDD AP35 BH48 VDD VDD R34 10K_0402_1%
AB22 GND GND AJ30 AR39 GND GND BD26 D24 GND GND P29 AA26 VDD VDD AF13 AK22 VDD VDD AP36 BH49 VDD VDD R35
AB23 GND GND AJ31 AR4 GND GND BD29 D25 GND GND P30 AA27 VDD VDD AF14 AK23 VDD VDD AP37 BH50 VDD VDD R36 +1V8_AON

1
AB24 GND GND AJ32 AR52 GND GND BD32 D28 GND GND P31 AA28 VDD VDD AF15 AK24 VDD VDD AP38 BH51 VDD VDD R37
AB25 GND GND AJ33 AR9 GND GND BD35 D30 GND GND P32 AA29 VDD VDD AF16 AK25 VDD VDD AP39 BH52 VDD VDD R38
AB26 GND GND AJ34 AT4 GND GND BD38 D31 GND GND P33 AA30 VDD VDD AF17 AK26 VDD VDD AP40 BJ44 VDD VDD R39
AB27 GND GND AJ35 AT5 GND GND BD52 D34 GND GND P34 AA31 VDD VDD AF18 AK27 VDD VDD AR13 BJ45 VDD VDD R40 1 1 1
AB28 GND GND AJ36 AT51 GND GND BE10 D37 GND GND P35 AA32 VDD VDD AF24 AK28 VDD VDD AR40 BJ46 VDD VDD T13
AB29 GND GND AJ37 AT52 GND GND BE13 D4 GND GND P36 AA33 VDD VDD AF25 AK29 VDD VDD AT13 BJ47 VDD VDD T40 CG6815 CG6817 CG6816
AB30 GND GND AJ38 AT8 GND GND BE15 D40 GND GND P37 AA34 VDD VDD AF26 AK30 VDD VDD AT14 BJ48 VDD VDD U13 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
AB31 AJ39 AU10 BE16 D43 P38 AA35 AF30 AK31 AT15 BJ49 U14 2 2 2
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD
AB32 GND GND AJ9 AU14 GND GND BE18 D46 GND GND P39 AA36 VDD VDD AF31 AK32 VDD VDD AT16 BJ50 VDD VDD U15 +1.35VS_VGA +1.35VS_VGA
AB33 AK1 AU15 BE19 D49 P51 AA37 AF32 AK33 AT17 BJ51 U16 UG1L
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD
AB34 AK44 AU16 BE21 D7 R49 AA38 AF33 AK34 AT18 BJ52 U17
Under GPU
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD 19/22 FBVDDQ
AB35 GND GND AK47 AU17 GND GND BE22 E2 GND GND R52 AA39 VDD VDD AF34 AK35 VDD VDD AT19 BK47 VDD VDD U18
AB36 GND GND AL10 AU18 GND GND BE24 E4 GND GND T10 AA40 VDD VDD AF40 AK36 VDD VDD AT20 BK48 VDD VDD U19 AA10 FBVDDQ FBVDDQ AT43
AB37 GND GND AL14 AU19 GND GND BE25 E48 GND GND T14 AB13 VDD VDD AG13 AK37 VDD VDD AT21 BK49 VDD VDD U20 AA11 FBVDDQ FBVDDQ K12
AB38 GND GND AL15 AU2 GND GND BE27 E5 GND GND T15 AB40 VDD VDD AG19 AK38 VDD VDD AT22 BK50 VDD VDD U21 AA42 FBVDDQ FBVDDQ K14
AB39 GND GND AL16 AU20 GND GND BE28 E51 GND GND T16 AC13 VDD VDD AG20 AK39 VDD VDD AT23 BK51 VDD VDD U22 AA43 FBVDDQ FBVDDQ K15 +1V8_AON
AB4 GND GND AL17 AU21 GND GND BE30 E8 GND GND T17 AC14 VDD VDD AG21 AK40 VDD VDD AT24 BK52 VDD VDD U23 AC10 FBVDDQ FBVDDQ K17
AB43 GND GND AL18 AU22 GND GND BE31 F10 GND GND T18 AC15 VDD VDD AG22 AL13 VDD VDD AT25 BL46 VDD VDD U24 AC11 FBVDDQ FBVDDQ K18
AB45 GND GND AL19 AU23 GND GND BE33 F13 GND GND T19 AC16 VDD VDD AG23 AL40 VDD VDD AT26 BL47 VDD VDD U25 AC42 FBVDDQ FBVDDQ K20
AB47 GND GND AL2 AU24 GND GND BE34 F16 GND GND T2 AC17 VDD VDD AG27 AM13 VDD VDD AT27 BL48 VDD VDD U26 AC43 FBVDDQ FBVDDQ K21 1 1 1 1 1 1
AB49 GND GND AL20 AU25 GND GND BE36 F17 GND GND T20 AC18 VDD VDD AG28 AM14 VDD VDD AT28 BL49 VDD VDD U27 AD10 FBVDDQ FBVDDQ K23
AB51 GND GND AL21 AU26 GND GND BE37 F19 GND GND T21 AC19 VDD VDD AG29 AM15 VDD VDD AT29 BL50 VDD VDD U28 AD11 FBVDDQ FBVDDQ K24 CG6818 CG6822 CG6823 CG6819 CG6821 CG6820
C AB6 GND GND AL22 AU27 GND GND BE39 F21 GND GND T22 AC20 VDD VDD AG35 AM16 VDD VDD AY26 BL51 VDD VDD U29 AD42 FBVDDQ FBVDDQ K26 4.7U_0402_4V_M 4.7U_0402_4V_M 4.7U_0402_4V_M 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K C
AB8 AL23 AU28 BE40 F22 T23 AC21 AG36 AM17 AY27 BL52 U30 AD43 K27 2 2 2 2 2 2
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ
AD14 GND GND AL24 AU29 GND GND BF2 F25 GND GND T24 AC22 VDD VDD AG37 AM18 VDD VDD AY28 BM47 VDD VDD U31 AF10 FBVDDQ FBVDDQ K29
AD15 GND GND AL25 AU30 GND GND BF4 F28 GND GND T25 AC23 VDD VDD AG38 AM19 VDD VDD AY29 BM48 VDD VDD U32 AF43 FBVDDQ FBVDDQ K30
AD16 GND GND AL26 AU31 GND GND BF41 F31 GND GND T26 AC24 VDD VDD AG39 AM20 VDD VDD AY30 BM49 VDD VDD U33 AG10 FBVDDQ FBVDDQ K32
AD17 AL27 AU32 BF6 F34 T27 AC25 AG40 AM21 AY31 BM50 U34 AG11 K33
Near GPU
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ
AD18 GND GND AL28 AU33 GND GND BG10 F35 GND GND T28 AC26 VDD VDD AH13 AM22 VDD VDD AY32 BM51 VDD VDD U35 AG42 FBVDDQ FBVDDQ K35
AD19 GND GND AL29 AU34 GND GND BG13 F37 GND GND T29 AC27 VDD VDD AH14 AM23 VDD VDD AY33 N13 VDD VDD U36 AG43 FBVDDQ FBVDDQ K36
AD20 GND GND AL30 AU35 GND GND BG16 F40 GND GND T30 AC28 VDD VDD AH15 AM24 VDD VDD AY34 N14 VDD VDD U37 AJ10 FBVDDQ FBVDDQ K38
AD21 GND GND AL31 AU36 GND GND BG19 F43 GND GND T31 AC29 VDD VDD AH16 AM25 VDD VDD AY35 N15 VDD VDD U38 AJ11 FBVDDQ FBVDDQ K39
AD22 GND GND AL32 AU37 GND GND BG22 F44 GND GND T32 AC30 VDD VDD AH17 AM26 VDD VDD AY36 N16 VDD VDD U39 AJ42 FBVDDQ FBVDDQ K41
AD23 GND GND AL33 AU38 GND GND BG25 F46 GND GND T33 AC31 VDD VDD AH18 AM27 VDD VDD AY37 N17 VDD VDD U40 AJ43 FBVDDQ FBVDDQ L14
AD24 GND GND AL34 AU39 GND GND BG28 F52 GND GND T34 AC32 VDD VDD AH19 AM28 VDD VDD AY38 N18 VDD VDD V13 AK10 FBVDDQ FBVDDQ L15
AD25 GND GND AL35 AU4 GND GND BG31 F7 GND GND T35 AC33 VDD VDD AH20 AM29 VDD VDD AY39 N19 VDD VDD V40 AK11 FBVDDQ FBVDDQ L18
AD26 AL36 AU45 BG34 G2 T36 AC34 AH21 AM30 AY40 N20 W13 AK42 L20 FB_GND_SENSE_R 1 2
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ FB_GND_SENSE <97>
AD27 GND GND AL37 AU47 GND GND BG37 G38 GND GND T37 AC35 VDD VDD AH22 AM31 VDD VDD AY43 N21 VDD VDD W14 AK43 FBVDDQ FBVDDQ L21 RG7 2_0402_1%
AD28 GND GND AL38 AU49 GND GND BG40 G4 GND GND T38 AC36 VDD VDD AH23 AM32 VDD VDD AY45 N22 VDD VDD W15 AM42 FBVDDQ FBVDDQ L23
AD29 GND GND AL39 AU51 GND GND BG42 G47 GND GND T39 AC37 VDD VDD AH24 AM33 VDD VDD BA43 N23 VDD VDD W16 AM43 FBVDDQ FBVDDQ L24
AD30 GND GND AL4 AU6 GND GND BG7 G49 GND GND T4 AC38 VDD VDD AH25 AM34 VDD VDD BA44 N24 VDD VDD W17 AN43 FBVDDQ FBVDDQ L26
AD31 GND GND AL43 AU8 GND GND BH15 G51 GND GND T43 AC39 VDD VDD AH26 AM35 VDD VDD BA45 N25 VDD VDD W18 AR42 FBVDDQ FBVDDQ L27
AD32 AL45 AV4 BH18 G6 T45 AC40 AH27 AM36 BA46 N26 W19 AR43 L30
RG7 near GPU
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ FBVDDQ
AD33 GND GND AL47 AV45 GND GND BH2 H1 GND GND T47 AD13 VDD VDD AH28 AM37 VDD VDD BA47 N27 VDD VDD W20 R42 FBVDDQ FBVDDQ L32
AD34 GND GND AL49 AV9 GND GND BH21 H10 GND GND T49 AD40 VDD VDD AH29 AM38 VDD VDD BB38 N28 VDD VDD W21 R43 FBVDDQ FBVDDQ L33
AD35 GND GND AL51 AW14 GND GND BH24 H13 GND GND T51 AE13 VDD VDD AH30 AM39 VDD VDD BB39 N29 VDD VDD W22 U10 FBVDDQ FBVDDQ L35
AD36 GND GND AL6 AW15 GND GND BH27 H16 GND GND T6 AE14 VDD VDD AH31 AM40 VDD VDD BB45 N30 VDD VDD W23 U11 FBVDDQ FBVDDQ L36
AD37 GND GND AL8 AW16 GND GND BH30 H19 GND GND T8 AE15 VDD VDD AH32 AN13 VDD VDD BB46 N31 VDD VDD W24 U43 FBVDDQ FBVDDQ L39
AD38 GND GND AM4 AW17 GND GND BH33 H22 GND GND U7 AE16 VDD VDD AH33 AN40 VDD VDD BB47 N32 VDD VDD W25 V10 FBVDDQ FBVDDQ M10
AD39 GND GND AM9 AW18 GND GND BH36 H25 GND GND U9 AE17 VDD VDD AH34 AP13 VDD VDD BB48 N33 VDD VDD W26 V42 FBVDDQ FBVDDQ M43
AD44 GND GND AN14 AW19 GND GND BH39 H28 GND GND V14 AE18 VDD VDD AH35 AP14 VDD VDD BC38 N34 VDD VDD W27 V43 FBVDDQ FBVDDQ P10
AE10 GND GND AN15 AW20 GND GND BH42 H31 GND GND V15 AE19 VDD VDD AH36 AP15 VDD VDD BC39 N35 VDD VDD W28 Y10 FBVDDQ FBVDDQ P11
AE2 GND GND AN16 AW21 GND GND BH5 H34 GND GND V16 AE20 VDD VDD AH37 AP16 VDD VDD BC40 N36 VDD VDD W29 Y11 FBVDDQ FBVDDQ P42
AE4 GND GND AN17 AW22 GND GND BJ10 H37 GND GND V17 AE21 VDD VDD AH38 AP17 VDD VDD BC41 N37 VDD VDD W30 Y42 FBVDDQ FBVDDQ P43
AE43 GND GND AN18 AW23 GND GND BJ12 H40 GND GND V18 AE22 VDD VDD AV28 AP18 VDD VDD BC45 N38 VDD VDD W31 Y43 FBVDDQ FBVDDQ R10
AE45 GND GND AN19 AW24 GND GND BJ13 H43 GND GND V19 AE23 VDD VDD AV29 AP19 VDD VDD BC47 N39 VDD VDD W32 FBVDDQ R11
AE47 GND GND AN20 AW25 GND GND BJ14 J1 GND GND V20 AE24 VDD VDD AV30 AP20 VDD VDD BC49 N40 VDD VDD W33
AE49 GND GND AN21 AW26 GND GND BJ15 J12 GND GND V21 AE25 VDD VDD AV31 AP21 VDD VDD BD39 P13 VDD VDD W34
AE51 GND GND AN22 AW27 GND GND BJ16 J17 GND GND V22 AE26 VDD VDD AV32 AP22 VDD VDD BE48 P40 VDD VDD W35
AE6 GND GND AN23 AW28 GND GND BJ17 J20 GND GND V23 AE27 VDD VDD AV33 BD41 VDD VDD BE49 R13 VDD VDD W36
B
AE8 AN24 AW29 BJ18 J38 V24 AT30 AV34 BD46 BE50 R14 W37 FB_VDDQ_SENSE_R
E52
1 2 B
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FBVDDQ_SENSE FB_VDDQ_SENSE <97>
AF1 GND GND AN25 AW30 GND GND BJ19 J49 GND GND V25 AT31 VDD VDD AV35 BD47 VDD VDD BE51 R15 VDD VDD W38 RG35 2_0402_1%
AF19 GND GND AN26 AW31 GND GND BJ20 J52 GND GND V26 AT32 VDD VDD AV36 BD48 VDD VDD BE52 R16 VDD VDD W39
AF20 GND GND AN27 AW32 GND GND BJ21 K13 GND GND V27 AT33 VDD VDD AV37 BD49 VDD VDD BF42 R17 VDD VDD W40
AF21 AN28 AW33 BJ22 K16 V28 AT34 AV38 BD50 BF44 R18 Y13 P45 FB_VREF
GND GND GND GND GND GND VDD VDD VDD VDD VDD VDD FB_VREF
AF22 GND GND AN29 AW34 GND GND BJ23 K19 GND GND V29 AT35 VDD VDD AV39 BD51 VDD VDD BF45 R19 VDD VDD Y40
AF23 GND GND AN30 AW35 GND GND BJ24 K2 GND GND V30 AT36 VDD VDD AV40 BE41 VDD VDD BF47 R20 VDD
+1.35VS_VGA
AF27 GND GND AN31 AW36 GND GND BJ25 K22 GND GND V31 AT37 VDD VDD AV42 BE42 VDD VDD BF49 R21 VDD
AF28 GND GND AN32 AW37 GND GND BJ26 K25 GND GND V32 AT38 VDD VDD AV43 BE43 VDD VDD BF51 R22 VDD
AF29 GND GND AN33 AW38 GND GND BJ27 K28 GND GND V33 AT39 VDD VDD AV44 BE46 VDD VDD BG43
AF35 GND GND AN34 AW39 GND GND BJ28 K31 GND GND V34 AT40 VDD VDD AW13 BE47 VDD VDD BG44 FB_CAL_PD_VDDQ R44 FBCAL_VDDQRG67 1 2 40.2_0402_1%
AF36 GND GND AN35 AW4 GND GND BJ29 K34 GND GND V35 AT42 VDD VDD AW40 Refer to the GPU-specific Partner Guidelines document for
AF37 AN36 AW46 BJ30 K37 V36 AU13 AW42 P44 FBCAL_GND RG68 1 2 40.2_0402_1%
AF38
GND
GND
GND
GND AN37 AW5
GND
GND
GND
GND BJ31 K4
GND
GND
GND
GND V37 AU40
VDD
VDD
VDD
VDD AW43 NVVDD_SENSE BK45
FB_CAL_PU_GND
the final Driver Calibration values. Only 1% resistors should
AF39 AN38 AW52 BJ32 K40 V38 AU43 AW44 BL45 NVVDD_VCC_SENSE <99> R45 FBCAL_TERMRG69 1 2 40.2_0402_1% be used for driver calibration.
GND GND GND GND GND GND VDD VDD GND_SENSE NVVDD_VSS_SENSE <99> FB_CALTERM_GND
AF45 GND GND AN39 AW8 GND GND BJ33 K45 GND GND V39 AV13 VDD VDD AW45
AF5 GND GND AN4 AY10 GND GND BJ34 K47 GND GND V49 AV14 VDD VDD AY13
AG14 GND GND AN5 AY2 GND GND BJ35 K49 GND GND V52 AV15 VDD VDD AY14
AG15 GND GND AN8 AY4 GND GND BJ36 K51 GND GND W10 AV16 VDD VDD AY15 @ @
AG16 GND GND AP10 AY47 GND GND BJ37 K6 GND GND W2 AV17 VDD VDD AY16 @
AG17 GND GND AP2 AY49 GND GND BJ38 K8 GND GND W4 AV18 VDD VDD AY17
AG18 GND GND AP4 AY51 GND GND BJ39 M52 GND GND W43 AV19 VDD VDD AY18
AG24 GND GND AP43 AY6 GND GND BJ40 M6 GND GND Y9 AV20 VDD VDD AY19
AG25 AP45 AY8 BJ41 N10 AV21 AY20 FB_VREF
GND GND GND GND GND VDD VDD
AG26 GND GND AP47 B1 GND GND BJ42 N2 GND AV22 VDD VDD AY21
AG3 GND GND AP49 B10 GND GND BJ43 N4 GND AV23 VDD VDD AY22

1
AG30 GND GND AP51 B13 GND GND BJ7 N43 GND AV24 VDD VDD AY23 1
AG31 GND GND AP6 B16 GND GND BK1 N45 GND AV25 VDD VDD AY24 RG59 CG6826
AG32 GND GND AP8 B19 GND GND BL1 N47 GND AV26 VDD VDD AY25 49.9_0402_1% 3.9P_0402_50V+-0.25PF
AG33 GND GND AR14 B2 GND GND BL10 N49 GND AV27 VDD
AG34 AR15 B22 BL13 BL37 2
GND GND GND GND GND

2
AG44 GND GND AR16 B25 GND GND BL16
AH10 GND GND AR17 B28 GND GND BL19
AH2 GND GND AR18 B31 GND GND BL2 @ @
AH4 GND GND AR19 B34 GND GND BL22
AH43 GND GND BL34 B37 GND GND BL25
AH45 GND GND BC24 B40 GND GND BL28
A AH47 GND B43 GND GND BL31 A
AH49 GND B46 GND GND B5
AH51 GND B48 GND GND B51

@ @

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P029-NV(3/7) Power_GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 29 of 109

5 4 3 2 1
 A B C D E

+1V8_AON

GPIO +3VS

@
DGPU_PEX_RST# RG1555

1
+1V8_AON GPU_OVERT# <58> 0_0402_5%
<27,39,40> DGPU_PEX_RST# NVVDD_ENP
RG534 1 2
NVVDD_ENP <32>

2
10K_0201_1% DGPU_PEX_RST#
RB751S40T1G_SOD523-2 RG29 RG28

1
@ DG7 1.8K_0402_5% 1.8K_0402_5%

2
RG533 GPU_OVERT# 1V8_MAIN_EN QG7B

5
RG568 100K_0201_5% 1 2 2 1 DMN53D0LDW-7 2N SOT363-6
NVVDD_EN <34,95,99>

1
+1V8_AON
GC6_FB_EN: +3VS 100K_0201_5% I2CC_SCL
4 3
requires a 10kohm pulled-down SCL_GPU <99>

6
D DG3

2
UG1T 2 UG23A RB751S40T1G_SOD523-2 QG7A 08/29 Confirm to Power IC
12/22 MISC 1 GPU_EVENT# RG561 G BSS138DW_SC88-6 1 2 I2CC_SDA DMN53D0LDW-7 2N SOT363-6
100K_0201_5% RG549 1 6
reqires a 10 kohm pulled-up to 1V8_AON. SDA_GPU <99>

3
D

G
VGA_SMB_CK2 S
PCH/EC pin connected to GPU_EVENT# must be 100K_0402_5%

1
OVERT# BG5 OVERT I2CS_SCL
BJ8 VGA_SMB_DA2 GPU_GC6_FB_EN OVERT# 5 UG23B CG481

2
I2CS_SDA
BH8 open-drain for output function to prevent back drive if 3 1
GC6_FB_EN <18>
G BSS138DW_SC88-6 2/10 CHANGE to 100K 2200P_0402_25V7K
diode is not used.

2
BF12 TS_VREF I2CC_SCL S

4
I2CC_SCL
BG9 I2CC_SDA +1V8_AON QG511 +1V8_AON

Vinafix.com
I2CC_SDA BH9 1V8_MAIN_EN: MESS138W-G_SOT323-3
+1V8_AON
is an open-drain GPIO.
I2CB_SCL BG8 RG19 1 2 2.2K_0402_1% It requires a 10 kohm pull-up to the 1V8_AON power domain.

1
I2CB_SDA BF8 RG20 1 2 2.2K_0402_1% 1
GPU_GC6_FB_EN <32>
FRAME_LOCK#: RG516 CG246
10K_0201_5%
BJ1 is an assert-low signal and is required to pull- 0.1U_0201_6.3V6K
+3VS
THERMDN
up to 1V8_AON with a 10K? resistor. 1V8_AON is required to be

3
2

2
1 BJ2 THERMDP powered up while the GPU is resident in GC6, and must be DGPU_PEX_RST# QG521B 1

VCC
1
powered on at all times while the panel is powered. IN B
DMN53D0LDW-7_SOT363-6

1
4 1 2 5
08/29 Confirm to Power IC DG2 2 OUT Y RG554 0_0201_5% RG506

GND
BD6 RB751S40T1G_SOD523-2 IN A 10K_0201_5%
GPIO0 GPU_GC6_FB_EN NVVDD_PWM_VID <99>

4
External current sense for power monitoring GPIO1 BB5 GC6_EVENT#_D UG22

6
GPIO2 BD1 2 1 NL17SZ08DFT2G_SC70-5 DG4
GC6_EVENT# <18>

2
BJ9 ADC_IN GPIO3 BE4 1V8_MAIN_EN PAD~D T18 @ QG502A RB751S40T1G_SOD523-2
<34> ADC_IN_P BJ11 BE1
ADC_IN GPIO4 GPU_GC6_FB_EN RG553 DMN53D0LDW-7_SOT363-6 NVVDD_PGOOD
<34> ADC_IN_N BG2 1V8_MAIN_EN <32,34,37> 1 2 2 2 1
GPIO5 GPU_NVVDD_PSI# NVVDD_PGOOD <27,32,39,95,99>
GPIO6 BD2 LCD_BL_PWM
GPIO7 BD7 0_0201_5%

1
GPIO8 BH4 THERM_ALERT#
BJ3 MEM_VDD_CTL <97>
GPIO9 MEM_VREF_CTL
JTAG_TCLK GPIO10 BD3
BK24 BH3 MEM_VREF_CTL <35,36>
@ T10 PAD~D JTAG_TMS JTAG_TCK GPIO11 EC_AC_BAT#
@ T11 PAD~D JTAG_TDI BL23 JTAG_TMS GPIO12 BE6
BM23 BB1 EC_AC_BAT# <58>
@ T12 PAD~D JTAG_TDO JTAG_TDI GPIO13 HPD_IFPA# PAD~D T25 @
@ T13 PAD~D JTAG_TRST# BM24 JTAG_TDO GPIO14 BG4 HPD_IFPB#
@ T16 BL24 BG1 +1V8_AON
JTAG_TRST GPIO15
PAD~D GPIO16 BE2 PAD~D T21 @
GPIO17 BH1
GPIO18 BE3
BK23 BD4 GPU_DP_HPD# <39>
@ T15 NVJTAG_SEL GPIO19 NB_FGC6 PAD~D T22 @ 1
PAD~D GPIO20 BE5 LCD_BLEN CG476
BA5 NB_FGC6 <32>
GPIO21 SWAPRDY_IN 0.1U_0201_6.3V6K
1

GPIO22 BB6 RASTER_SYNC1

RG518 RG26 BG3 2
GPIO23 DP_CBL_DET#
10K_0201_5% 10K_0201_5% GPIO24 BD5 GPU_FBVDD_PSI

5
GPIO25 BB2 FP_FUSE
GPIO26 BE7 1 VCC
FP_FUSE <29>
2

BA4 B 4
GPIO27 OC_WARN# GPU_HDMI_HPD# <40> Y FBVDD/Q_EN <32,34,97>
GPIO28 BB4 IDLE_IN_SW 2 A
BA3 OC_WARN# <34> <95> +1.0VS_VGA_PGOOD G
GPIO29

1
GPIO30 BB3 PAD~D T24 @

3
UG27 RG557
74LVC1G32GW_TSSOP5 10K_0402_1%
1

Pin Name Default Functio n RG1504

2
@ 10K_0402_5%
JTAG_ T RS T L JTAG module will drive signal.
GPU side need to pull low as default
2

NVJTAG _ S E L L Test Mode --> Disable

H Test Mode --> Enable

+1V8_AON

10/15 NV change
DGPU_PEX_RST# RG1595
0_0402_5%

2
2 1
+1V8_AON QG6B RG15

5
DMN53D0LDW-7 2N SOT363-6 10K_0201_5%
GC6_EVENT#_D VGA_SMB_CK2 @ @
RG8 1 2 10K_0201_5% 4 3 RG1579 1 2 +1V8_AON
EC_SMB_CK2 <16,58,64,74,77> NVVDD_PSI# <99>

1
GPU_NVVDD_PSI# 10K_0402_1% C

2
OVERT# RG9 1 2 10K_0201_5% QG6A 1 2 2 QX4 300K_0402_1% 08/29 Confirm to Power IC

1
DMN53D0LDW-7 2N SOT363-6 B RG1580
MMBT3904WH_SOT323-3
DGPU_HOLD_RST# VGA_SMB_DA2
RG13 1 @ 2 10K_0201_5% 1 6 E RG504
<18> DGPU_HOLD_RST# EC_SMB_DA2 <16,58,64,74,77>

3
10K_0201_5%
@

2
EC_AC_BAT# 1

2
RG16 1 2 10K_0201_5% RG1578 @ THERM_ALERT#
VGA_SMB_CK2 10K_0201_5% CG7141
RG17 1 2 1.8K_0402_5% 0.1U_0402_10V7K
2
VGA_SMB_DA2

1
RG18 1 2 1.8K_0402_5%
1V8_MAIN_EN
RG27 1 2 10K_0201_5%

+1V8_AON
DP_CBL_DET#
RG501 1 2 10K_0201_5% 10/15 NV change
+1V8_AON

1
OC_WARN# RG1596
2 RG522 1 2 10K_0201_5% 0_0402_5% RG530 2

HPD_IFPA# 2 1 10K_0201_5%
RG523 1 2 10K_0201_5% @

2
HPD_IFPB#

2
RG524 1 2 10K_0201_5% RG1581 @ DP_CBL_DET#
SWAPRDY_IN 10K_0201_5% RG1584 1 @ 2
RG526 1 2 2.2K_0201_5% @ 300K_0402_1% RG540 0_0201_5%
RG1583 1 2
PSI_FBVDDQ <97>

6
GPU_FBVDD_PSI 10K_0402_1% C
1 2 2 2
D

RASTER_SYNC1 QX5 QG500B G

1 2 DP_CBL_DET <39>
RG527 100K_0201_5% B MMBT3904WH_SOT323-3 08/29 Confirm to Power IC DMN66D0LDW-7_SOT363-6 S

LCD_BLEN E

1
RG525 1 2 100K_0201_5%
@
NB_FGC6

2
RG21 1 2 10K_0201_5% 1
GPU_GC6_FB_EN RG1582 @
RG22 1 2 10K_0201_5% 20K_0201_5% CG7142
MEM_VREF_CTL 0.1U_0402_10V7K
RG24 1 2 10K_0201_5% 2

1
DGPU_PEX_RST#
RG25 1 2 1M_0201_1%
LCD_BL_PWM
RG150 1 2 100K_0201_5%

11/06 CHANGE PN , ADD SD043200280

FP_FUSE
RG528 1 2 10K_0201_5%

BIOS_STRAP

ROM, Straps
H=High :Tied to 1.8V
M=Middle:Tied to 0.9V
L=Low :Tied to 0V
RAMCFG[4:0] DENSITY W IDTH VENDOR
STRAP 2 STRAP 1 STRAP 0 RAMCFG[4:0]
00000 8Gb 256-bit Samsung

L L L 00000 RAMCFG TBD 00001 8Gb 256-bit Micron

3
GDDR6 VRAM Strap0 Strap1 Strap2 Strap3 RAMCFG 00010 8Gb 256-bit Hynix 3
L L H 00001 RAMCFG TBD DEFAULT
Samsung , K4Z80325BC-HC14 L L L H 0X0
Micron , MT61K256M32JE-14:A H L L H 0X1 L 00010 RAMCFG TBD
H L

+1V8_AON L H 00011 RAMCFG TBD

H
00110 16Gb 256-bit Hynix
N18E-G3 N18E-G2 N18E-G1 H L 00110 RAMCFG TBD
H 00111 16Gb 256-bit Samsung
Samsung , K4Z80325BC-HC14 X7680231L01 X7680231L03
Micron , MT61K256M32JE-14:A H H 00111 RAMCFG TBD
X7680231L02 X7680231L04 H 01000 16Gb 256-bit Micron
+1V8_AON

RG78
11/5 UPDATE Config
2

UG1U
RG78 RG79 RG80 RG81 RG82 RG83 14/22 MISC 2 RG84 RG85 RG86
@ 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% ROM_CS# 100K_0402_1% 100K_0402_1% 100K_0402_1%
@ @ @ GSYNC@ BJ4 @ @ @ ROM_SO ROM_S I ROM_SCLK DUMMY[2:0],FS_OVERT 1:ENABLE 0:DISABLE
ROM_CS
S RES 1/16W 100K +-1% 0402 ROM_SI
1

Vram Micron@ ROM_SI BK2 ROM_SO

BK4 ROM_SCLK L L L XXX1 FS_OVERT ENABLE
SD034100380 ROM_SO DGPU_ROM_SCLK DEFAULT
STRAP0 BL3 STRAP0 ROM_SCLK BK3 1 2
STRAP1 BL4 STRAP1 RG100 33_0402_5%
RG90 STRAP2 BM4 L L M XXX0 FS_OVERT DISABLE
STRAP2 EMI@
STRAP3 BM5 STRAP3
1

STRAP4 BK5 STRAP4

STRAP5 BJ5 STRAP5 @EMI@ RG87 RG88 RG89
CG895 100K_0402_1% 10K_0402_1% 100K_0402_1%
2

20P_0402_50V8
2

S RES 1/16W 100K +-1% 0402 GPU_BUFRST# @

1

Vram Samsung@ RG90 RG91 RG92 RG93 RG94 RG95 BUFRST BF9 T6
SD034100380 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% 100K_0402_1% PAD~D
@ @
1

STRAP 5 STRAP 4 STRAP 3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE

1:SMB_ALT_ADDR ENABLE
M H H 1 1 1 1
@ 0:SMB_ALT_ADDR DISABLE

M H L 1 1 1 0 1:DEVID_SEL REBRAND
Discrete/MSHybrid
Strap to PCH STRAP3_PCH STRAP5_PCH GPU DID
GSYNC VBIOS ROM M L H 1 1 0 1 0:DEVID_SEL ORIGNAL
L Without display head L NON-GSYNC
M 1:PCIE_CFG LOW POWER
With display head L L 1 1 0 0
H H GSYNC +1V8_AON
+1V8_AON
0:PCIE_CFG HIGH POWER
1 2 STRAP3 1 2 STRAP5 L H M 1 0 1 1
<14> STRAP3_PCH <14> STRAP5_PCH
1:VGA_DEVICE ENABLE
L M H 1 0 1 0
1

DG8 DG9 0:VGA_DEVICE DISABLE

RB751S40T1G_SOD523-2 RB751S40T1G_SOD523-2 RG74 1
@ @ 10K_0402_5% CG66
0.1U_0402_16V4Z L M L 1 0 0 1
2

2
L L M 1 0 0 0
GPU have display out then set to PCI class code = 0x300h; STRAP5
ROM_CS# RG75
1
33_0402_5%
ROM_CS#_R
2 DGPU_ROM_SO_R 1
UG34
8
Discrete/MSHybrid with display head. ROM_SO
1 2 2 CS# VCC 7 DGPU_ROM_SCLK
GPU didn’ t have any di s pl ay out t hen set PCI cl ass code = RG76 0_0402_5% 3 DO(IO1) HOLD#(IO3) 6 DGPU_ROM_SI ROM_SI
H H H 0 1 1 1
WP#(IO2) CLK
0x302h. Pure Optimus W/O display head. 4
GND DI(IO0)
5 1 2
RG77 33_0402_5%
W25Q80EWSSIG_SO8 H H L 0 1 1 0
1 2
H L H 0 1 0 1 DEFAULT
RG1495
2.2K_0201_1%
H L L 0 1 0 0
1

D
@
QG516 2
GPU_STRAP5_EC <58>
2N7002W-T/R7_SOT323-3 G
S L H H 0 0 1 1
3

4 4
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L H L 0 0 1 0

L L H 0 0 0 1

L L L 0 0 0 0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P030-NV(4/7) GPIO_BIOS_STRAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Si ze Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Dat e: Thursday, May 30, 2019 Sheet 30 of 109

A B C D E
 A B C D E

UG1B
Vinafix.com UG1C
UG1D
4/22 FBC
UG1E
5/22 FBD
1 2/22 FBA 3/22 FBB 1
C6 FBC_D0 FBC_CMD0
C11 FB_C_CMD1 AK8 FBD_D0 FBD_CMD0
AD2 FB_D_CMD1
U51 Y51 FB_A_CMD1 H32 B35FB_B_CMD1 <36> FB_C_D0 D6 B11 FB_C_CMD0 <36> <36> FB_D_D0 AK4 AD1 FB_D_CMD0 <36>
<35> FB_A_D0 FBA_D0 FBA_CMD0 FB_A_CMD0 <35> <35> FB_B_D0 FBB_D0 FBB_CMD0 FB_B_CMD0 <35> <36> FB_C_D1 FBC_D1 FBC_CMD1 FB_C_CMD1 <36> <36> FB_D_D1 FBD_D1 FBD_CMD1 FB_D_CMD1 <36>
U48 FBA_D1 FBA_CMD1 Y52 D32 FBB_D1 FBB_CMD1 A35 A6 FBC_D2 FBC_CMD2 A11 AK2 FBD_D2 FBD_CMD2 AD4
<35> FB_A_D1 U50 Y49 FB_A_CMD1 <35> <35> FB_B_D1 A33 D35 FB_B_CMD1 <35> <36> FB_C_D2 B6 D11 FB_C_CMD2 <36> <36> FB_D_D2 AK3 AC1 FB_D_CMD2 <36>
<35> FB_A_D2 FBA_D2 FBA_CMD2 FB_A_CMD2 <35> <35> FB_B_D2 FBB_D2 FBB_CMD2 FB_B_CMD2 <35> <36> FB_C_D3 FBC_D3 FBC_CMD3 FB_C_CMD3 <36> <36> FB_D_D3 FBD_D3 FBD_CMD3 FB_D_CMD3 <36>
U49 FBA_D3 FBA_CMD3 AA52 B32 FBB_D3 FBB_CMD3 A36 B4 FBC_D4 FBC_CMD4 A12 AK5 FBD_D4 FBD_CMD4 AC2
<35> FB_A_D3 R51 AA51 FB_A_CMD3 <35> <35> FB_B_D3 E32 B36 FB_B_CMD3 <35> <36> FB_C_D4 A4 B12 FB_C_CMD4 <36> <36> FB_D_D4 AK6 AC3 FB_D_CMD4 <36>
<35> FB_A_D4 FBA_D4 FBA_CMD4 FB_A_CMD4 <35> <35> FB_B_D4 FBB_D4 FBB_CMD4 FB_B_CMD4 <35> <36> FB_C_D5 FBC_D5 FBC_CMD5 FB_C_CMD5 <36> <36> FB_D_D5 FBD_D5 FBD_CMD5 FB_D_CMD5 <36>
R50 FBA_D5 FBA_CMD5 AA50 G32 FBB_D5 FBB_CMD5 C36 B3 FBC_D6 FBC_CMD6 C12 AK9 FBD_D6 FBD_CMD6 AA3
<35> FB_A_D5 R47 AC50 FB_A_CMD5 <35> <35> FB_B_D5 J30 C38 FB_B_CMD5 <35> <36> FB_C_D6 C4 C14 FB_C_CMD6 <36> <36> FB_D_D6 AK7 AA2 FB_D_CMD6 <36>
<35> FB_A_D6 FBA_D6 FBA_CMD6 FB_A_CMD6 <35> <35> FB_B_D6 FBB_D6 FBB_CMD6 FB_B_CMD6 <35> <36> FB_C_D7 FBC_D7 FBC_CMD7 FB_C_CMD7 <36> <36> FB_D_D7 FBD_D7 FBD_CMD7 FB_D_CMD7 <36>
U46 FBA_D7 FBA_CMD7 AC51 F32 FBB_D7 FBB_CMD7 B38 D9 FBC_D8 FBC_CMD8 B14 AG4 FBD_D8 FBD_CMD8 AA1
<35> FB_A_D7 V46 AC52 FB_A_CMD7 <35> <35> FB_B_D7 H36 A38 FB_B_CMD7 <35> <36> FB_C_D8 C9 A14 FB_C_CMD8 <36> <36> FB_D_D8 AF9 AA4 FB_D_CMD8 <36>
<35> FB_A_D8 FBA_D8 FBA_CMD8 FB_A_CMD8 <35> <35> FB_B_D8 FBB_D8 FBB_CMD8 FB_B_CMD8 <35> <36> FB_C_D9 FBC_D9 FBC_CMD9 FB_C_CMD9 <36> <36> FB_D_D9 FBD_D9 FBD_CMD9 FB_D_CMD9 <36>
Y45 FBA_D9 FBA_CMD9 AC49 G36 FBB_D9 FBB_CMD9 D38 E9 FBC_D10 FBC_CMD10 D14 AG6 FBD_D10 FBD_CMD10 Y1
<35> FB_A_D9 Y47 AD52 FB_A_CMD9 <35> <35> FB_B_D9 J36 A39 FB_B_CMD9 <35> <36> FB_C_D10 B9 A15 FB_C_CMD10 <36> <36> FB_D_D10 AG7 Y2 FB_D_CMD10 <36>
<35> FB_A_D10 FBA_D10 FBA_CMD10 FB_A_CMD10 <35> <35> FB_B_D10 FBB_D10 FBB_CMD10 FB_B_CMD10 <35> <36> FB_C_D11 FBC_D11 FBC_CMD11 FB_C_CMD11 <36> <36> FB_D_D11 FBD_D11 FBD_CMD11 FB_D_CMD11 <36>
Y46 FBA_D11 FBA_CMD11 AD51 F36 FBB_D11 FBB_CMD11 B39 B8 FBC_D12 FBC_CMD12 B15 FB_C_CMD13 AJ4 FBD_D12 FBD_CMD12 Y3 FB_D_CMD13
<35> FB_A_D11 V50 AD50 FB_A_CMD13 FB_A_CMD11 <35> <35> FB_B_D11 F33 C39FB_B_CMD13 FB_B_CMD11 <35> <36> FB_C_D12 A8 C15 FB_C_CMD12 <36> <36> FB_D_D12 AJ5 V3 FB_D_CMD12 <36>
<35> FB_A_D12 FBA_D12 FBA_CMD12 FB_A_CMD12 <35> <35> FB_B_D12 FBB_D12 FBB_CMD12 FB_B_CMD12 <35> <36> FB_C_D13 FBC_D13 FBC_CMD13 FB_C_CMD13 <36> <36> FB_D_D13 FBD_D13 FBD_CMD13 FB_D_CMD13 <36>
V47 FBA_D13 FBA_CMD13 AF50 D33 FBB_D13 FBB_CMD13 C41 F6 FBC_D14 FBC_CMD14 C17 AJ6 FBD_D14 FBD_CMD14 V2
<35> FB_A_D13 U52 AF51 FB_A_CMD13 <35> <35> FB_B_D13 J32 B41 FB_B_CMD13 <35> <36> FB_C_D14 E6 B17 FB_C_CMD14 <36> <36> FB_D_D14 AG5 V1 FB_D_CMD14 <36>
<35> FB_A_D14 FBA_D14 FBA_CMD14 FB_A_CMD14 <35> <35> FB_B_D14 FBB_D14 FBB_CMD14 FB_B_CMD14 <35> <36> FB_C_D15 FBC_D15 FBC_CMD15 FB_C_CMD15 <36> <36> FB_D_D15 FBD_D15 FBD_CMD15 FB_D_CMD15 <36>
V51 FBA_D15 FBA_CMD15 AF52 G33 FBB_D15 FBB_CMD15 A41 F18 FBC_D16 FBC_CMD16 B24FB_C_CMD17 Y6 FBD_D16 FBD_CMD16 L3 FB_D_CMD17
<35> FB_A_D15 AJ44 AN50 FB_A_CMD17 FB_A_CMD15 <35> <35> FB_B_D15 E45 B49FB_B_CMD17 FB_B_CMD15 <35> <36> FB_C_D16 G18 A24 FB_C_CMD16 <36> <36> FB_D_D16 Y5 L2 FB_D_CMD16 <36>
<35> FB_A_D16 FBA_D16 FBA_CMD16 FB_A_CMD16 <35> <35> FB_B_D16 FBB_D16 FBB_CMD16 FB_B_CMD16 <35> <36> FB_C_D17 FBC_D17 FBC_CMD17 FB_C_CMD17 <36> <36> FB_D_D17 FBD_D17 FBD_CMD17 FB_D_CMD17 <36>
AG48 FBA_D17 FBA_CMD17 AN51 D45 FBB_D17 FBB_CMD17 A49 E18 FBC_D18 FBC_CMD18 D23 V5 FBD_D18 FBD_CMD18 L1
<35> FB_A_D17 AJ45 AN52 FB_A_CMD17 <35> <35> FB_B_D17 F45 A48 FB_B_CMD17 <35> <36> FB_C_D18 H18 A23 FB_C_CMD18 <36> <36> FB_D_D18 Y4 M4 FB_D_CMD18 <36>
<35> FB_A_D18 FBA_D18 FBA_CMD18 FB_A_CMD18 <35> <35> FB_B_D18 FBB_D18 FBB_CMD18 FB_B_CMD18 <35> <36> FB_C_D19 FBC_D19 FBC_CMD19 FB_C_CMD19 <36> <36> FB_D_D19 FBD_D19 FBD_CMD19 FB_D_CMD19 <36>
AG49 FBA_D19 FBA_CMD19 AM49 G45 FBB_D19 FBB_CMD19 D47 D15 FBC_D20 FBC_CMD20 B23 AA6 FBD_D20 FBD_CMD20 M1
<35> FB_A_D19 AF46 AM52 FB_A_CMD19 <35> <35> FB_B_D19 D42 A47 FB_B_CMD19 <35> <36> FB_C_D20 E15 C23 FB_C_CMD20 <36> <36> FB_D_D20 AA5 M2 FB_D_CMD20 <36>
<35> FB_A_D20 FBA_D20 FBA_CMD20 FB_A_CMD20 <35> <35> FB_B_D20 FBB_D20 FBB_CMD20 FB_B_CMD20 <35> <36> FB_C_D21 FBC_D21 FBC_CMD21 FB_C_CMD21 <36> <36> FB_D_D21 FBD_D21 FBD_CMD21 FB_D_CMD21 <36>
AF47 FBA_D21 FBA_CMD21 AM51 E42 FBB_D21 FBB_CMD21 B47 G17 FBC_D22 FBC_CMD22 C21 AC5 FBD_D22 FBD_CMD22 M3
<35> FB_A_D21 AF48 AM50 FB_A_CMD21 <35> <35> FB_B_D21 F42 C47 FB_B_CMD21 <35> <36> FB_C_D22 H17 B21 FB_C_CMD22 <36> <36> FB_D_D22 AC4 P3 FB_D_CMD22 <36>
<35> FB_A_D22 FBA_D22 FBA_CMD22 FB_A_CMD22 <35> <35> FB_B_D22 FBB_D22 FBB_CMD22 FB_B_CMD22 <35> <36> FB_C_D23 FBC_D23 FBC_CMD23 FB_C_CMD23 <36> <36> FB_D_D23 FBD_D23 FBD_CMD23 FB_D_CMD23 <36>
AD47 FBA_D23 FBA_CMD23 AK50 H41 FBB_D23 FBB_CMD23 C45 J15 FBC_D24 FBC_CMD24 A21 AD7 FBD_D24 FBD_CMD24 P2
<35> FB_A_D23 AD49 AK51 FB_A_CMD23 <35> <35> FB_B_D23 E41 B45 FB_B_CMD23 <35> <36> FB_C_D24 H15 D20 FB_C_CMD24 <36> <36> FB_D_D24 AC6 P1 FB_D_CMD24 <36>
<35> FB_A_D24 FBA_D24 FBA_CMD24 FB_A_CMD24 <35> <35> FB_B_D24 FBB_D24 FBB_CMD24 FB_B_CMD24 <35> <36> FB_C_D25 FBC_D25 FBC_CMD25 FB_C_CMD25 <36> <36> FB_D_D25 FBD_D25 FBD_CMD25 FB_D_CMD25 <36>
AD48 FBA_D25 FBA_CMD25 AK52 F39 FBB_D25 FBB_CMD25 A45 E14 FBC_D26 FBC_CMD26 A20 AF6 FBD_D26 FBD_CMD26 R4
<35> FB_A_D25 AC46 AJ49 FB_A_CMD25 <35> <35> FB_B_D25 E39 D44 FB_B_CMD25 <35> <36> FB_C_D26 F14 B20 FB_C_CMD26 <36> <36> FB_D_D26 AD6 R1 FB_D_CMD26 <36>
<35> FB_A_D26 FBA_D26 FBA_CMD26 FB_A_CMD26 <35> <35> FB_B_D26 FBB_D26 FBB_CMD26 FB_B_CMD26 <35> <36> FB_C_D27 FBC_D27 FBC_CMD27 FB_C_CMD27 <36> <36> FB_D_D27 FBD_D27 FBD_CMD27 FB_D_CMD27 <36>
AC47 FBA_D27 FBA_CMD27 AJ52 D39 FBB_D27 FBB_CMD27 A44 H11 FBC_D28 FBC_CMD28 C20 FB_C_CMD29 AF7 FBD_D28 FBD_CMD28 R2 FB_D_CMD29
<35> FB_A_D27 AA47 AJ51 FB_A_CMD29 FB_A_CMD27 <35> <35> FB_B_D27 F38 B44FB_B_CMD29 FB_B_CMD27 <35> <36> FB_C_D28 G11 C18 FB_C_CMD28 <36> <36> FB_D_D28 AF8 R3 FB_D_CMD28 <36>
<35> FB_A_D28 FBA_D28 FBA_CMD28 FB_A_CMD28 <35> <35> FB_B_D28 FBB_D28 FBB_CMD28 FB_B_CMD28 <35> <36> FB_C_D29 FBC_D29 FBC_CMD29 FB_C_CMD29 <36> <36> FB_D_D29 FBD_D29 FBD_CMD29 FB_D_CMD29 <36>
AA46 FBA_D29 FBA_CMD29 AJ50 E38 FBB_D29 FBB_CMD29 C44 F11 FBC_D30 FBC_CMD30 B18 AF2 FBD_D30 FBD_CMD30 U3
<35> FB_A_D29 AA45 AG50 FB_A_CMD29 <35> <35> FB_B_D29 D36 C42 FB_B_CMD29 <35> <36> FB_C_D30 E11 A18 FB_C_CMD30 <36> <36> FB_D_D30 AF3 U2 FB_D_CMD30 <36>
<35> FB_A_D30 FBA_D30 FBA_CMD30 FB_A_CMD30 <35> <35> FB_B_D30 FBB_D30 FBB_CMD30 FB_B_CMD30 <35> <36> FB_C_D31 FBC_D31 FBC_CMD31 FB_C_CMD31 <36> <36> FB_D_D31 FBD_D31 FBD_CMD31 FB_D_CMD31 <36>
Y44 FBA_D31 FBA_CMD31 AG51 E36 FBB_D31 FBB_CMD31 B42 J29 FBC_D32 FBC_CMD32 A17 +1.35VS_VGA F4 FBD_D32 FBD_CMD32 V4 +1.35VS_VGA
<35> FB_A_D31 AW51 AF49 FB_A_CMD31 <35> +1.35VS_VGA <35> FB_B_D31 M50 D41 FB_B_CMD31 <35> +1.35VS_VGA <36> FB_C_D32 F30 D17 FB_C_DEBUG0 FB_C_CMD32 <36> <36> FB_D_D32 E1 U1 FB_D_DEBUG0 FB_D_CMD32 <36>
FBA_D32 FBA_CMD32 FBB_D32 FBB_CMD32 FBC_D33 FBC_CMD33 @ FBD_D33 FBD_CMD33 @
<35> FB_A_D32 BA52 AG52 FB_A_DEBUG0 FB_A_CMD32 <35> <35> FB_B_D32 P48 A42 FB_B_DEBUG0 FB_B_CMD32 <35> <36> FB_C_D33 H29 A9 FB_C_DEBUG1 FB_C_CMD33 <36>
1 <36> FB_D_D33 FB_D_CMD33 <36>
FBA_D33 FBA_CMD33 @ FBB_D33 FBB_CMD33 @ FBC_D34 FBC_CMD34 RG1410 2 60.4_0402_1% F3 FBD_D34 FBD_CMD34 AD3 FB_D_DEBUG1 1 RG1412 2 60.4_0402_1%
<35> FB_A_D33 AW50 Y50 FB_A_DEBUG1 FB_A_CMD33 <35>
1 <35> FB_B_D33 FB_B_CMD33 <35> <36> FB_C_D34 <36> FB_D_D34
FBA_D34 FBA_CMD34 RG1478 2 60.4_0402_1% M51 FBB_D34 FBB_CMD34 C35 FB_B_DEBUG1 1 RG1446 2 60.4_0402_1% G30 FBC_D35 FBC_CMD35 C24 1 RG1411 2 60.4_0402_1% F5 FBD_D35 FBD_CMD35 J3 1 RG1413 2 60.4_0402_1%
<35> FB_A_D34 BA51 AR50 1 RG1476 2 60.4_0402_1% <35> FB_B_D34 M49 B50 1 RG1451 2 60.4_0402_1% <36> FB_C_D35 B30 <36> FB_D_D35 D2
FBA_D35 FBA_CMD35 FBB_D35 FBB_CMD35 FBC_D36 @ FBD_D36 @
<35> FB_A_D35 BA50 <35> FB_B_D35 P47 <36> FB_C_D36 A30 <36> FB_D_D36 D1
FBA_D36 @ FBB_D36 @ FBC_D37 FBD_D37
<35> FB_A_D36 BB50 <35> FB_B_D36 P52 <36> FB_C_D37 H30 <36> FB_D_D37 C3
<35> FB_A_D37 FBA_D37 <35> FB_B_D37 FBB_D37 <36> FB_C_D38 FBC_D38 <36> FB_D_D38 FBD_D38
BA49 FBA_D38 R46 FBB_D38 C30 FBC_D39 FBC_DBG_RFU1 J14 C2 FBD_D39 FBD_DBG_RFU1 AC9
<35> FB_A_D38 AW49 AA44 <35> FB_B_D38 P46 J35 <36> FB_C_D39 D27 J23 <36> FB_D_D39 J5 P9
<35> FB_A_D39 FBA_D39 FBA_DBG_RFU1 <35> FB_B_D39 FBB_D39 FBB_DBG_RFU1 <36> FB_C_D40 FBC_D40 FBC_DBG_RFU2 <36> FB_D_D40 FBD_D40 FBD_DBG_RFU2
AV48 FBA_D40 FBA_DBG_RFU2 AN44 L50 FBB_D40 FBB_DBG_RFU2 J41 J26 FBC_D41 J4 FBD_D41
<35> FB_A_D40 AT49 <35> FB_B_D40 L51 <36> FB_C_D41 F27 <36> FB_D_D41 L8
<35> FB_A_D41 FBA_D41 <35> FB_B_D41 FBB_D41 <36> FB_C_D42 FBC_D42 <36> FB_D_D42 FBD_D42
AT47 FBA_D42 L52 FBB_D42 G27 FBC_D43 J2 FBD_D43
<35> FB_A_D42 AT48 <35> FB_B_D42 L49 <36> FB_C_D43 C27 G15 <36> FB_D_D43 F1 Y8
<35> FB_A_D43 FBA_D43 <35> FB_B_D43 FBB_D43 <36> FB_C_D44 FBC_D44 FBC_CLK0 FB_C_CLK0 <36> <36> FB_D_D44 FBD_D44 FBD_CLK0 FB_D_CLK0 <36>
AT46 FBA_D44 FBA_CLK0 AG45 M46 FBB_D44 FBB_CLK0 H42 B27 FBC_D45 FBC_CLK0 F15 F2 FBD_D45 FBD_CLK0 Y7
<35> FB_A_D44 AV51 AG46 FB_A_CLK0 <35> <35> FB_B_D44 L47 G42 FB_B_CLK0 <35> <36> FB_C_D45 A27 H21 FB_C_CLK#0 <36> <36> FB_D_D45 H4 R8 FB_D_CLK#0 <36>
<35> FB_A_D45 FBA_D45 FBA_CLK0 FB_A_CLK#0 <35> <35> FB_B_D45 FBB_D45 FBB_CLK0 FB_B_CLK#0 <35> <36> FB_C_D46 FBC_D46 FBC_CLK1 FB_C_CLK1 <36> <36> FB_D_D46 FBD_D46 FBD_CLK1 FB_D_CLK1 <36>
AV52 FBA_D46 FBA_CLK1 AK46 M48 FBB_D46 FBB_CLK1 F47 G29 FBC_D47 FBC_CLK1 J21 H5 FBD_D47 FBD_CLK1 R7
<35> FB_A_D46 AV49 AK45 FB_A_CLK1 <35> <35> FB_B_D46 M47 E47 FB_B_CLK1 <35> <36> FB_C_D47 H20 FB_C_CLK#1 <36> <36> FB_D_D47 V7 FB_D_CLK#1 <36>
<35> FB_A_D47 FBA_D47 FBA_CLK1 FB_A_CLK#1 <35> <35> FB_B_D47 FBB_D47 FBB_CLK1 FB_B_CLK#1 <35> <36> FB_C_D48 FBC_D48 <36> FB_D_D48 FBD_D48
AJ48 FBA_D48 D48 FBB_D48 D18 FBC_D49 V8 FBD_D49
<35> FB_A_D48 AJ46 <35> FB_B_D48 C50 <36> FB_C_D49 G20 <36> FB_D_D49 V6
<35> FB_A_D49 FBA_D49 <35> FB_B_D49 FBB_D49 <36> FB_C_D50 FBC_D50 <36> FB_D_D50 FBD_D50
AJ47 FBA_D50 C48 FBB_D50 E20 FBC_D51 V9 FBD_D51
<35> FB_A_D50 AK49 <35> FB_B_D50 C49 <36> FB_C_D51 F23 <36> FB_D_D51 U4
<35> FB_A_D51 FBA_D51 <35> FB_B_D51 FBB_D51 <36> FB_C_D52 FBC_D52 <36> FB_D_D52 FBD_D52
AM47 FBA_D52 E49 FBB_D52 E21 FBC_D53 R5 FBD_D53
<35> FB_A_D52 AM46 <35> FB_B_D52 E50 <36> FB_C_D53 D21 <36> FB_D_D53 R6
<35> FB_A_D53 FBA_D53 <35> FB_B_D53 FBB_D53 <36> FB_C_D54 FBC_D54 <36> FB_D_D54 FBD_D54
AN48 FBA_D54 F49 FBB_D54 E23 FBC_D55 U8 FBD_D55
<35> FB_A_D54 AN49 <35> FB_B_D54 F48 <36> FB_C_D55 G24 F8 <36> FB_D_D55 P6 AJ8
<35> FB_A_D55 FBA_D55 <35> FB_B_D55 FBB_D55 <36> FB_C_D56 FBC_D56 FBC_WCK01 FB_C_WCK01 <36> <36> FB_D_D56 FBD_D56 FBD_WCK01 FB_D_WCK01 <36>
AM44 FBA_D56 FBA_WCK01 U45 F50 FBB_D56 FBB_WCK01 J33 H26 FBC_D57 FBC_WCK01 G8 R9 FBD_D57 FBD_WCK01 AJ7
<35> FB_A_D56 AM45 U44 FB_A_WCK01 <35> <35> FB_B_D56 D52 H33 FB_B_WCK01 <35> <36> FB_C_D57 F24 G9 FB_C_WCK#01 <36> <36> FB_D_D57 P4 AG8 FB_D_WCK#01 <36>
<35> FB_A_D57 FBA_D57 FBA_WCK01 FB_A_WCK#01 <35> <35> FB_B_D57 FBB_D57 FBB_WCK01 FB_B_WCK#01 <35> <36> FB_C_D58 FBC_D58 FBC_WCKB01 FB_C_WCKB01 <36> <36> FB_D_D58 FBD_D58 FBD_WCKB01 FB_D_WCKB01 <36>
AN45 FBA_D58 FBA_WCKB01 V45 J50 FBB_D58 FBB_WCKB01 G35 G26 FBC_D59 FBC_WCKB01 F9 P5 FBD_D59 FBD_WCKB01 AG9
<35> FB_A_D58 AN46 V44 FB_A_WCKB01 <35> <35> FB_B_D58 H48 H35 FB_B_WCKB01 <35> <36> FB_C_D59 F26 H12 FB_C_WCKB#01 <36> <36> FB_D_D59 L7 AD8 FB_D_WCKB#01 <36>
<35> FB_A_D59 FBA_D59 FBA_WCKB01 FB_A_WCKB#01 <35> <35> FB_B_D59 FBB_D59 FBB_WCKB01 FB_B_WCKB#01 <35> <36> FB_C_D60 FBC_D60 FBC_WCK23 FB_C_WCK23 <36> <36> FB_D_D60 FBD_D60 FBD_WCK23 FB_D_WCK23 <36>
AR48 FBA_D60 FBA_WCK23 AC45 H51 FBB_D60 FBB_WCK23 J39 D26 FBC_D61 FBC_WCK23 G12 L6 FBD_D61 FBD_WCK23 AD9
<35> FB_A_D60 AN47 AC44 FB_A_WCK23 <35> <35> FB_B_D60 J51 H39 FB_B_WCK23 <35> <36> FB_C_D61 B26 G14 FB_C_WCK#23 <36> <36> FB_D_D61 L4 AC7 FB_D_WCK#23 <36>
<35> FB_A_D61 FBA_D61 FBA_WCK23 FB_A_WCK#23 <35> <35> FB_B_D61 FBB_D61 FBB_WCK23 FB_B_WCK#23 <35> <36> FB_C_D62 FBC_D62 FBC_WCKB23 FB_C_WCKB23 <36> <36> FB_D_D62 FBD_D62 FBD_WCKB23 FB_D_WCKB23 <36>
AR47 FBA_D62 FBA_WCKB23 AD46 H49 FBB_D62 FBB_WCKB23 F41 C26 FBC_D63 FBC_WCKB23 H14 L5 FBD_D63 FBD_WCKB23 AC8
<35> FB_A_D62 AR46 AD45 FB_A_WCKB23 <35> <35> FB_B_D62 H52 G41 FB_B_WCKB23 <35> <36> FB_C_D63 J27 FB_C_WCKB#23 <36> <36> FB_D_D63 J6 FB_D_WCKB#23 <36>
<35> FB_A_D63 FBA_D63 FBA_WCKB23 FB_A_WCKB#23 <35> <35> FB_B_D63 FBB_D63 FBB_WCKB23 FB_B_WCKB#23 <35> FBC_WCK45 FB_C_WCK45 <36> FBD_WCK45 FB_D_WCK45 <36>
FBA_WCK45 AV47 FBB_WCK45 L46 FBC_WCK45 H27 FBD_WCK45 J7
AV46 FB_A_WCK45 <35> L45 FB_B_WCK45 <35> A5 E29 FB_C_WCK#45 <36> AJ1 H7 FB_D_WCK#45 <36>
FBA_WCK45 FB_A_WCK#45 <35> FBB_WCK45 FB_B_WCK#45 <35> <36> FB_C_DBI0 FBC_DQM0 FBC_WCKB45 FB_C_WCKB45 <36> <36> FB_D_DBI0 FBD_DQM0 FBD_WCKB45 FB_D_WCKB45 <36>
U47 FBA_DQM0 FBA_WCKB45 AW48 C32 FBB_DQM0 FBB_WCKB45 M44 C8 FBC_DQM1 FBC_WCKB45 F29 AG1 FBD_DQM1 FBD_WCKB45 H6
<35> FB_A_DBI0 Y48 AW47 FB_A_WCKB45 <35> <35> FB_B_DBI0 E33 M45 FB_B_WCKB45 <35> <36> FB_C_DBI1 J18 G23 FB_C_WCKB#45 <36> <36> FB_D_DBI1 AA7 P8 FB_D_WCKB#45 <36>
<35> FB_A_DBI1 FBA_DQM1 FBA_WCKB45 FB_A_WCKB#45 <35> <35> FB_B_DBI1 FBB_DQM1 FBB_WCKB45 FB_B_WCKB#45 <35> <36> FB_C_DBI2 FBC_DQM2 FBC_WCK67 FB_C_WCK67 <36> <36> FB_D_DBI2 FBD_DQM2 FBD_WCK67 FB_D_WCK67 <36>
AG47 FBA_DQM2 FBA_WCK67 AR45 E44 FBB_DQM2 FBB_WCK67 H47 F12 FBC_DQM3 FBC_WCK67 H23 AD5 FBD_DQM3 FBD_WCK67 P7
<35> FB_A_DBI2 AC48 AR44 FB_A_WCK67 <35> <35> FB_B_DBI2 G39 H46 FB_B_WCK67 <35> <36> FB_C_DBI3 D29 H24 FB_C_WCK#67 <36> <36> FB_D_DBI3 D3 M7 FB_D_WCK#67 <36>
<35> FB_A_DBI3 FBA_DQM3 FBA_WCK67 FB_A_WCK#67 <35> <35> FB_B_DBI3 FBB_DQM3 FBB_WCK67 FB_B_WCK#67 <35> <36> FB_C_DBI4 FBC_DQM4 FBC_WCKB67 FB_C_WCKB67 <36> <36> FB_D_DBI4 FBD_DQM4 FBD_WCKB67 FB_D_WCKB67 <36>
BB51 FBA_DQM4 FBA_WCKB67 AT45 P49 FBB_DQM4 FBB_WCKB67 J47 E27 FBC_DQM5 FBC_WCKB67 J24 H3 FBD_DQM5 FBD_WCKB67 M8
<35> FB_A_DBI4 AV50 AT44 FB_A_WCKB67 <35> <35> FB_B_DBI4 L48 J46 FB_B_WCKB67 <35> <36> FB_C_DBI5 F20 FB_C_WCKB#67 <36> <36> FB_D_DBI5 U5 FB_D_WCKB#67 <36>
<35> FB_A_DBI5 FBA_DQM5 FBA_WCKB67 FB_A_WCKB#67 <35> <35> FB_B_DBI5 FBB_DQM5 FBB_WCKB67 FB_B_WCKB#67 <35> <36> FB_C_DBI6 FBC_DQM6 <36> FB_D_DBI6 FBD_DQM6
AM48 FBA_DQM6 D50 FBB_DQM6 E26 FBC_DQM7 M9 FBD_DQM7
<35> FB_A_DBI6 AR49 <35> FB_B_DBI6 H50 <36> FB_C_DBI7 <36> FB_D_DBI7
<35> FB_A_DBI7 FBA_DQM7 <35> FB_B_DBI7 FBB_DQM7

D5 FBC_DQS_WP0 AJ3 FBD_DQS_WP0

R48 B33 <36> FB_C_EDC0 D8 <36> FB_D_EDC0 AG2
<35> FB_A_EDC0 FBA_DQS_WP0 <35> FB_B_EDC0 FBB_DQS_WP0 <36> FB_C_EDC1 FBC_DQS_WP1 <36> FB_D_EDC1 FBD_DQS_WP1
V48 FBA_DQS_WP1 E35 FBB_DQS_WP1 E17 FBC_DQS_WP2
+FBX_PLLAVDD AA9 FBD_DQS_WP2
+FBX_PLLAVDD
2 <35> FB_A_EDC1 AF44 +FBX_PLLAVDD +1V8_MAIN <35> FB_B_EDC1 G44 +FBX_PLLAVDD <36> FB_C_EDC2 E12 <36> FB_D_EDC2 AF4 2
<35> FB_A_EDC2 FBA_DQS_WP2 <35> FB_B_EDC2 FBB_DQS_WP2 <36> FB_C_EDC3 FBC_DQS_WP3 <36> FB_D_EDC3 FBD_DQS_WP3
AA48 FBA_DQS_WP3 H38 FBB_DQS_WP3 E30 FBC_DQS_WP4 E3 FBD_DQS_WP4
<35> FB_A_EDC3 BB52 <35> FB_B_EDC3 P50 <36> FB_C_EDC4 B29 <36> FB_D_EDC4 H2
<35> FB_A_EDC4 FBA_DQS_WP4 100MHz <35> FB_B_EDC4 FBB_DQS_WP4 <36> FB_C_EDC5 FBC_DQS_WP5 <36> FB_D_EDC5 FBD_DQS_WP5
AT50 J48 G21 U6
<35> FB_A_EDC5 AK48
FBA_DQS_WP5 30ohm, Bead <35> FB_B_EDC5 D51
FBB_DQS_WP5 <36> FB_C_EDC6 E24
FBC_DQS_WP6
L17 <36> FB_D_EDC6 M5
FBD_DQS_WP6
V11
<35> FB_A_EDC6 FBA_DQS_WP6 <35> FB_B_EDC6 FBB_DQS_WP6 <36> FB_C_EDC7 FBC_DQS_WP7 FBC_PLL_AVDD <36> FB_D_EDC7 FBD_DQS_WP7 FBD_PLL_AVDD
AR51 FBA_DQS_WP7 FBA_PLL_AVDD AN42 1 2 F51 FBB_DQS_WP7 FBB_PLL_AVDD L38
<35> FB_A_EDC7 <35> FB_B_EDC7

1U_0201_4V6M

1U_0201_4V6M
22U_0603_4V_M
4.7U_0402_4V_M

4.7U_0402_4V_M
1U_0201_4V6M

1U_0201_4V6M
LG6 Y24 GND 1 Y32 GND 1
W45 Y16 Y25 Y33

CG65

CG570
GND 1 1 1 PBY160808T-300Y-N_2P GND 1 GND GND
1

W47 Y17 Y26 Y34

CG61

CG64

CG63

CG62

CG569
GND GND GND GND
W49 GND Y18 GND Y27 GND Y35 GND
W51 Y19 Y28 2 Y36 2
GND GND GND GND
2

W6 2 2 2 Y20 2 Y29 Y37

GND GND GND GND
W8 GND Y21 GND Y30 GND Y38 GND
Y14 GND Y22 GND Y31 GND Y39 GND
+FBX_PLLAVDD Y15 Y23
GND GND

Under GPU Under GPU

N18E-G3

Under GPU Near GPU Under GPU

N18E-G2 N18E-G1
AF42 FB_REFPLL_AVDD0
1U_0201_4V6M

1U_0201_4V6M

L29 FB_REFPLL_AVDD1
1 1 FBD N/A
CG59

CG60

@ @
@ @
2 2

Under GPU

+1.35VS_VGA +1.35VS_VGA
+1.35VS_VGA +1.35VS_VGA
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
1

1
RG1479

RG1480

RG1483

RG1484

For CKE_A

RG1487

RG1488

RG1491

RG1492
For CKE_A
2

FB_A_CMD10 FB_B_CMD10

2
FB_C_CMD10 FB_D_CMD10
FB_A_CMD26 FB_B_CMD26
FB_C_CMD26 FB_D_CMD26
FB_A_CMD2 FB_B_CMD2
FB_C_CMD2 FB_D_CMD2
FB_A_CMD18 FB_B_CMD18
FB_C_CMD18 FB_D_CMD18
2

2
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
RG1481

RG1482

RG1486

RG1485

2
10K_0402_1%

10K_0402_1%

10K_0402_1%

10K_0402_1%
For Reset

RG1490

RG1489

RG1494

RG1493
For Reset
1

1
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P031-NV(5/7) MEMORY_FB_ABCD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Si ze Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Dat e: Thursday, May 30, 2019 Sheet 31 of 109

A B C D E
 A B C D E

UG1S
NVLink Interface
11/22 NVHS

NVHS_RX0 AM1 @
AN1 2 1 RG1585 +NVHS_DVDD1
NVHS_RX0 +PEX_VDD 0_0201_5%
2 1 RG1586 +NVHS_DVDD2
0_0201_5% @
AN2 2 1 RG1587 +NVHS_DVDD3

USB-C Display Interface

NVHS_RX1 0_0201_5% @
AN3 2 1 RG1588 +NVHS_DVDD4
NVHS_RX1 0_0201_5% @
2 1 RG1594 +NVHS_PLL_HVDD
0412 Change

Vinafix.com
UG1R 0_0201_5% @
6/22 IFPF/USB-C NVHS_RX2 AR3
AR2

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M
NVHS_RX2
USB-C DP 1 1 1 1 1
1 AR1 1

CG7148

CG7147

CG7146

CG7145

CG7157
NVHS_RX3
NVHS_RX3 AT1
USB_DVDD1 BB15
10K_0201_5% 2 1 RG1505 USB_DVDD SBU2 IFPF_AUX BM9
USB_DVDD2 BC15 +NVHS_DVDD1 2 2 2 2 2
10K_0201_5% 2 1 RG1506 USB_DVDD SBU1 IFPF_AUX BM8 10K_0201_5% 2 1 RG1523 AT10 NVHS_DVDD NVHS_RX4 AT2
2 1 RG1524 +NVHS_DVDD2 AT9 AT3
10K_0201_5% NVHS_DVDD NVHS_RX4 @ @ @ @ @
2 1 RG1525 +NVHS_DVDD3 AV10
10K_0201_5% NVHS_DVDD
BK11 2 1 RG1526 +NVHS_DVDD4 AV11 AV3
RX1 IFPF_L3 10K_0201_5% NVHS_DVDD NVHS_RX5
RX1 IFPF_L3 BL11 NVHS_RX5 AV2
2 1 RG1527 +NVHS_CVDD1 AR10
+PEX_VDD 0_0201_5% NVHS_CVDD
BM11 2 1 RG1528 +NVHS_CVDD2 AT11 AV1
TX1 IFPF_L2 0_0201_5% NVHS_CVDD NVHS_RX6
BM12 AW1

0.47U_0201_4V_M

0.47U_0201_4V_M
TX1 IFPF_L2 NVHS_RX6 +NVHS_HVDD1
1 1 0_0201_5% 2 @ 1 RG1589
+PEX_VDD +NVHS_HVDD2
BL12 AW2 2 1

CG7144

CG7143
TX2 IFPF_L1 NVHS_RX7 0_0201_5% @ RG1590
BK12 AW3 2 1 +NVHS_HVDD3
TX2 IFPF_L1 NVHS_RX7 0_0201_5% @ RG1591
USB_HVDD1 AW10 +NVHS_HVDD4
10K_0201_5% 2 1 RG1507 USB_HVDD 0_0201_5% 2 @ 1 RG1592
USB_HVDD2 AW11 2 2 +NVHS_HVDD5
10K_0201_5% 2 1 RG1508 USB_HVDD RX2 IFPF_L0 BK14 NVHS_TX0 AM7 0_0201_5% 2 @ 1 RG1593
RX2 IFPF_L0 BL14 @ @ NVHS_TX0 AM8
AW9

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M

0.47U_0201_4V_M
+1V8_AON USB_PLL_HVDD
1 1 NVHS_TX1 AN7 1 1 1 1 1

1
AN6

CG7153

CG7152

CG7151

CG7150

CG7149
NVHS_TX1
CG7084 CG7083 CG7082 USB_L0 BA1
BA2 2 1 RG1529 +NVHS_HVDD1 AM10 AR6
22U_0603_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M USB_L0 10K_0201_5% NVHS_HVDD NVHS_TX2
+NVHS_HVDD2

2
2 2 10K_0201_5% 2 1 RG1530 AM11 AR5 2 2 2 2 2
+NVHS_HVDD3 NVHS_HVDD NVHS_TX2
USB_L1 BA7 10K_0201_5% 2 1 RG1531 AN10 NVHS_HVDD @ @ @ @ @
BA8 2 1 RG1532 +NVHS_HVDD4 AN11 AR7
Near GPU Under GPU USB_L1 10K_0201_5%
2 1 RG1533 +NVHS_HVDD5 AR11
NVHS_HVDD NVHS_TX3
AR8
10K_0201_5% NVHS_HVDD NVHS_TX3
USB_VDDP
10K_0201_5% 2 1 RG1509 BE12 USB_VDDP
2 1 RG1534 +NVHS_PLL_HVDD AN9 AT7
10K_0201_5% NVHS_PLL_HVDD NVHS_TX4
AT6
NVHS_TX4

NVHS_TX5
AV6
AV5
If it’ s no US Bt ype C desi gni n and no I FPF used, t hen NVHS_TX5
USB_VDDP,USB_DVDD and USB_HVDD pull to GND with a AV7
NVHS_TX6
10K resistor. But USB_PLL_HVDD must connect to 1.8V_AON NVHS_TX6
AV8
power rails even no USB/IFPF used.
USB_SCL BB8 NVHS_TX7 AW7
USB_SDA BB7 NVHS_TX7 AW6

BG6 USB_TERMP0

BH6 USB_TERMP1 AM3 NVHS_TERMP NVHS_REFCLK AM6

NVHS_REFCLK AM5
BA6 USB_RBIAS
IFPF/USB-C
EXT_REFCLK_SLI
AM2

@ N18E-G2
N18E-G3 N18E-G1
2 2
NVHS RX/TX N/A

@
N18E GPU does not support NVLink. Pull down NVHS_DVDD,
NVHS_CVDD, NVHS_HVDD, NVHS_PLL_HVDD rails to GND
with 10K Resistor. Do not use any decoupling or filtering capacitor for NVHS_DVDD, NVHS_CVDD,
NVHS_HVDD,NVHS_PLL_HVDD rails. Leave NVHS_TERMP, EXT_REFCLK_SLI, NVHS_REFCLK, NVHS_TX and NVHS_RX
signals floating (NC)."

FGC6 Reserved Reference board power seq. will handle by PMU

Therefore demo circuit will have other power path to control the
FGC6 or other GPU power seq.
ODM must associate FGC6 power circuit includes power on/off
into its owned circuit.

Note: GC6 3.0 is mandatory for N18x GeForce GPU. GC6 2.1
BOM option is recom-mended for N18x GeForce GPU.
+1V8_AON
3
+1V8_AON
To 1V8_MAIN 3
+1V8_AON +1V8_MAIN +1V8_AON
1

@
RG1518 1 @

1
10K_0402_5% CG7085 1 @ @
0.1U_0201_6.3V6K CG7088 RG1519 1 @
0.1U_0201_6.3V6K 10K_0402_5% CG7091
2

2
5

@ 0.1U_0201_6.3V6K
RG1510 2
GND VCC

2
2
5

5
1 0_0402_5%
IN B 4 1 2 1V8_MAIN_AON_EN 1 VCC
To NVVDD

GND VCC
1V8_MAIN_EN 2 OUT Y B 4 1V8_MAIN_ENP 1
<30> 1V8_MAIN_EN IN A Y 1V8_MAIN_ENP <37> IN B NVVDD_ENP
2 A 4
1V8_MAIN_EN OUT Y NVVDD_ENP <30>
1

UG40 CG7089 G UG39 2

NL17SZ08DFT2G_SC70-5 2200P_0402_25V7K 74LVC1G32GW_TSSOP5 IN A
3

1204 change @ @ @ UG42

2

NL17SZ08DFT2G_SC70-5

3
@

NVVDD_PGOOD 1 2

+1V8_AON RG1602
0_0402_5%
2/10 change to NVVDD_PGOOD SQE +1V8_AON +1V8_AON

1 @ RB751S40T1G_SOD523-2
CG7087 1 DG10
0.1U_0201_6.3V6K @ CG7092 @ 1
0.1U_0201_6.3V6K 2 1 1203 CHANGE CG7106
2
5

@ 0.1U_0201_6.3V6K
RG1511 2
GND VCC

GPU_GC6_FB_EN 2
5

5
1 0_0402_5% RG1512
<30> GPU_GC6_FB_EN IN B 4 1 2 GPU_GC6_FB_FGC6_EN 1 VCC 0_0402_5%
To PEX_VDD

GND VCC
NB_FGC6 2 OUT Y B 4 1 2 PEX_VDD_RC_ENP 1 RG1521
<30> NB_FGC6 IN A NVVDD_PGOOD 2
Y IN B 4 1 2 PEX_VDD_ENP
<27,30,95,99> NVVDD_PGOOD A OUT Y PEX_VDD_ENP <34,95>
1

UG41 CG7090 G UG43 2 0_0402_5%

IN A 1

1
NL17SZ08DFT2G_SC70-5 2200P_0402_25V7K 74LVC1G32GW_TSSOP5 CG7094
3

@ @ @ 2200P_0402_25V7K UG47 CG7107

2

NL17SZ08DFT2G_SC70-5 0.22U_0402_10V6K

3
2
12/18 Update @

RG1520
DGPU_PW R_EN 1 2 12/03 ADD UG47 , RG1521
<18,58> DGPU_PW R_EN
0_0402_5%

1
+1V8_AON CG7159
2/10 ADD 0ohm 2200P_0402_25V7K
4 4

2
1 @
@
CG7093
0.1U_0201_6.3V6K
2
5

NVVDD_PGOOD 1
B
VCC
RG1513
0_0402_5% To FBVDD
FBVDD/Q_EN
4 1 2
GPU_GC6_FB_EN 2
Y FBVDD/Q_EN <30,34,97>
A
G UG44 @
1

74LVC1G32GW_TSSOP5 CG7095
3

@ 2200P_0402_25V7K
@
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P032-NV(6/7) USB-C_NVLink_GC6
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 32 of 109
A B C D E
 5 4 3 2 1

GPU Decoupling - NV Spec Recommendation Total : 1UF_0201 X 95 pcs

0.47UF_0201 X 90 pcs

FBVDDQ_GPU NVVDD_GPU
+1.35VS_VGA +NVVDD
1UF_0201 X 24 pcs Total : 1UF_0201 X 95 pcs
(@:0.47UF_0201 X 24 pcs)
Place under GPU (@: 0.47UF_0201 X 90 pcs) Place under GPU
10UF_0603 X 5 pcs 1. 1UF_0201 X 19 pcs
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

D
2
CG6838
1U_0201_4V6M
2
CG6829
1U_0201_4V6M
2
CG6828
1U_0201_4V6M
2
CG6831
1U_0201_4V6M
2
CG6833
1U_0201_4V6M
2
CG6834
1U_0201_4V6M
Vinafix.com 2
CG6910
1U_0201_4V6M
2
CG6911
1U_0201_4V6M
2
CG6897
1U_0201_4V6M
2
CG6898
1U_0201_4V6M
2
CG6899
1U_0201_4V6M
CG6900
1U_0201_4V6M
2
CG6901
1U_0201_4V6M
2
CG6902
1U_0201_4V6M
2
CG6903
1U_0201_4V6M
2
CG6904
1U_0201_4V6M
2
CG6905
1U_0201_4V6M
2
CG6906
1U_0201_4V6M
2
CG6907
1U_0201_4V6M
2
CG6908
1U_0201_4V6M
2
CG6909
1U_0201_4V6M
2
CG6912
1U_0201_4V6M
2
CG6913
1U_0201_4V6M
2
CG6914
1U_0201_4V6M
2
CG7001
1U_0201_4V6M
2
D

1 1 1 1 1 1 2. 1UF_0201 X 19 pcs
CG6839 CG6830 CG6832 CG6835 CG6836 CG6837 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2 2 2 2 2 2 CG6929 CG6928 CG6916 CG6915 CG6917 CG6918 CG6919 CG6920 CG6921 CG6922 CG6923 CG6924 CG6925 CG6926 CG6927 CG6930 CG6931 CG6932 CG7000
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1 1 1 1 1 1
CG6849 CG6841 CG6840 CG6843 CG6845 CG6846
3. 1UF_0201 X 19 pcs
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2
CG6947 CG6946 CG6934 CG6933 CG6935 CG6936 CG6937 CG6938 CG6939 CG6940 CG6941 CG6942 CG6943 CG6944 CG6945 CG6948 CG6949 CG6950 CG6988
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
CG6851 CG6842 CG6844 CG6847 CG6848 CG6850
1U_0201_4V6M
2
1U_0201_4V6M
2
1U_0201_4V6M
2
1U_0201_4V6M
2
1U_0201_4V6M
2
1U_0201_4V6M
2 4. 1UF_0201 X 19 pcs
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG6965 CG6964 CG6952 CG6951 CG6953 CG6954 CG6955 CG6956 CG6957 CG6958 CG6959 CG6960 CG6961 CG6962 CG6963 CG6966 CG6967 CG6968 CG6987
1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 1 1 1 1 1
047u@ 047u@ 047u@ 047u@ 047u@ 047u@
CG6861 CG6854 CG6852 CG6856 CG6858 CG6857
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2
5. 1UF_0201 X 19 pcs
C 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C

1 1 1 1 1 1 CG6983 CG6982 CG6970 CG6969 CG6971 CG6972 CG6973 CG6974 CG6975 CG6976 CG6977 CG6978 CG6979 CG6980 CG6981 CG6984 CG6985 CG6986 CG6989
047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M 1U_0201_4V6M
CG6863 CG6853 CG6855 CG6859 CG6860 CG6862 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2

6. 0.47UF_0201 X 18 pcs
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@
CG6873 CG6866 CG6864 CG6868 CG6870 CG6869 CG7081 CG7080 CG7078 CG7077 CG7079 CG6990 CG6991 CG6992 CG6993 CG6994 CG6995 CG6996 CG6997 CG6998 CG6999 CG7002 CG7003 CG7004
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

1
047u@
1
047u@
1
047u@
1
047u@
1
047u@
1
047u@
7. 0.47UF_0201 X 18 pcs
CG6875 CG6865 CG6867 CG6871 CG6872 CG6874 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@
2 2 2 2 2 2 CG7019 CG7018 CG7006 CG7005 CG7007 CG7008 CG7009 CG7010 CG7011 CG7012 CG7013 CG7014 CG7015 CG7016 CG7017 CG7020 CG7021 CG7022
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1

CG6879
10U_0603_4V_M
CG6876
10U_0603_4V_M
CG6877
10U_0603_4V_M
CG6878
10U_0603_4V_M
CG6880
10U_0603_4V_M
8. 0.47UF_0201 X 18 pcs
2

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@
CG7037 CG7036 CG7024 CG7023 CG7025 CG7026 CG7027 CG7028 CG7029 CG7030 CG7031 CG7032 CG7033 CG7034 CG7035 CG7038 CG7039 CG7040
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

B B

9. 0.47UF_0201 X 18 pcs
1

CG6885 CG6881 CG6882 CG6883 CG6884 CG6886 CG6887 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

10U_0603_4V_M 10U_0603_4V_M 10U_0603_4V_M 10U_0603_4V_M 10U_0603_4V_M 10U_0603_4V_M 10U_0603_4V_M 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@
2

CG7055 CG7054 CG7042 CG7041 CG7043 CG7044 CG7045 CG7046 CG7047 CG7048 CG7049 CG7050 CG7051 CG7052 CG7053 CG7056 CG7057 CG7058
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

10. 0.47UF_0201 X 18 pcs

1

1
CG6888

CG6889

CG6890

CG6891

CG6892

CG6893

CG6894

CG6895

CG6896

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ CG7064 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@ 047u@
2

CG7073 CG7072 CG7060 CG7059 CG7061 CG7062 CG7063 047u@ CG7065 CG7066 CG7067 CG7068 CG7069 CG7070 CG7071 CG7074 CG7075 CG7076
0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M 0.47U_0201_4V_M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Place near GPU

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P033-NV(7/7) GPU DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 33 of 109

5 4 3 2 1
 A B C D E

+3VLP +3VALW +3V3_SYS RG1575

0_0402_5%
1 2

2
RG1576 10/15 NV change
RG1611 RG1609 @ RG1608 0_0402_5%
0_0402_5% 0_0402_5% 0_0402_5% 1 2 RG1542 CG7115 10/15 NV change
649_0402_1% 1000P_0402_50V
1203 change 2 1 1 2

1
Vinafix.com
RG1501
@ +3V_OC_PWR

1U_0402_25V6K
100_0402_1% 20mil RG1543 CG7116

CG6802
CSSP_B+

1
2 1 649_0402_1% 1000P_0402_50V
<101> CSSP_B+
2 1 1 2
1 1

2
UG37 RG1540
75K_0402_1%
27 3 2 1 CSSP_B+
RG62 VCC BS_IN1 6 2 1 CSSP_NVVDD
0_0402_5% VIN1P 2 BS_IN2 11 75K_0402_1%
CSSN_B+ 1 2 VIN1N 1 SH_IN_P1 BS_IN3 14 RG1541
<101> CSSN_B+ CSSP_NVVDD SH_IN_N1 BS_IN4
2 1 VIN2P 5
<101> CSSP_NVVDD 4 SH_IN_P2
RG64 VIN2N @ 10/15 NV change
100_0402_1% SH_IN_P3 12 SH_IN_N2 9 1 2 CG7120
SH_IN_N3 13 SH_IN_P3 GND_FET 0.015U_0402_25V
SH_IN_P4 15 SH_IN_N3 0_0402_5% 1 2
SH_IN_N4 16 SH_IN_P4 32 SH_O1 RG1539
RG66 SH_IN_N4 SH_O1 7 SH_O2 SH_O1 RG1563 2 1 287_0402_1%
0_0402_5% ADC_IN_P 20 SH_O2 10
CSSN_NVVDD 1 2 ADC_IN_N 19 DIFF_OUT_P SH_O3 17 SH_O2 RG1564 2 1 287_0402_1%
<101> CSSN_NVVDD DIFF_OUT_N SH_O4
CG7118 RG1560
47P_0402_50V_5% 0_0402_5% BS_OK 30 RG1537 1 2
1 2 ADC_IN_P_RC 1 2 BS_OK 0_0402_5%
8 29 ADC_MUX_SEL 1 2 0.015U_0402_25V
NC MUX_SEL OC_WARN# <30> CG7121
18 RG1610
<30> ADC_IN_P 21 NC RG1601 2 @ 110K_0402_5%
+3VALW 0_0402_5%
<30> ADC_IN_N NC
31 28 1 @ 2 1/11 221Ω change 287Ω
1 2 ADC_IN_N_RC 1 2 NC ENABLE RG1613 OC_EN# <58>
BG_REF_OUT 23 2 1
47P_0402_50V_5% 0_0402_5% BS_REF BG_REF_OUT +3VLP
24 25 SKIP
CG7119 RG1561 CM_REF_IN 22 BS_REF SKIP @
1203 change CM_REF_IN 120K_0402_1%
MODE_SEL 2
33 26
GND MODE_SEL CG7160
2/10 change @ CG7122
1000P_0402_50V
1U_0402_6.3V6K 1 2
1

2
+3V_OC_PWR NCP45491XMNTWG_QFN32_4X4
@
RG1562 RG1566 RG1567
10K_0402_5% 10K_0402_5% 243K_0402_1% 10K_0402_5%
2 1 BS_OK RG1538 2 1 2 1

2N7002W-T/R7_SOT323-3
2/11 CG7160 to 1U & RG1613 to 120K change

1
RG135 CG7123
D

1
2 1K_0402_1% 1000P_0402_50V 2
2 1 SKIP 2 1 2

QG525
+3VS
G
RG1570 S RG1568 RG1569
BS_REF

3
2
2K_0402_1% 365K_0402_1% 681K_0402_1%
1 2 SH_IN_P3 RG1600 2 1 2 1
100K_0402_1%
RG1571 BG_REF_OUT CG7124
2K_0402_1% @ 1000P_0402_50V
SH_IN_N3 CM_REF_IN

1
1 2 1 2
@
RG1572
2K_0402_1%
1 2 SH_IN_P4

RG1573
2K_0402_1%
1 2 SH_IN_N4

RG1565
10K_0402_5%
2 1 MODE_SEL
@

+NVVDD +1V8_AON 11/12 DEL RG510 +1V8_MAIN +3V3_SYS

10mil
10mil 10mil

1
10mil
1

1
RG510
+5VALW RG544 +5VALW 10_0402_1% +5VALW RG512 +5VALW RG514
10K_0402_5% 51_0402_5% 10_0402_1% cgange 10R
@

2
2

2
1

1
RG543 RG509 RG511 RG513
3 3
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
3

3
2

2
QG508B

QG503B

QG520B

QG505B
5 5 5 5
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
4

4
6

6
QG508A

QG503A

QG520A

QG505A
2 1V8_AON_EN 2 1V8_MAIN_EN 2 3V3_SYS_EN 2
<30,95,99> NVVDD_EN <37> 1V8_AON_EN <30> 1V8_MAIN_EN <37> 3V3_SYS_EN
1

1
+PEX_VDD
+1.35VS_VGA
10mil 10mil
1

+5VALW RG1605 1203add +5VALW RG1607

10_0402_1% 3_0402_5%

2/12 Update
2

2
1

RG1604 RG1606
10K_0402_5% 10K_0402_5%
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
3

3
2

2
QG522B

QG523B

4 5 5 4
DMN53D0LDW-7 2N SOT363-6

DMN53D0LDW-7 2N SOT363-6
4

4
6

6
QG523A

QG524A

2 2
<30,32,97> FBVDD/Q_EN <32,95> PEX_VDD_ENP
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P034-NV OC_Discharging
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 34 of 109

A B C D E
 A B C D E

UG11 UG12 UG13 UG14 UG15 UG16 UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18

S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS S IC D6 256M32 161-0325-900 FBGA G3-QS
MCNGD6@ MCNGD6@ MCNGD6@ MCNGD6@ MCNGD6@ MCNGD6@ MCNGD8@ MCNGD8@ MCNGD8@ MCNGD8@ MCNGD8@ MCNGD8@ MCNGD8@ MCNGD8@
SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L SA0000BND1L

UG11 UG12 UG13 UG14 UG15 UG16

UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18

S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS
SAMGD6@ SAMGD6@ SAMGD6@ SAMGD6@ SAMGD6@ SAMGD6@ S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS S IC D6 256M32 161-0327-600 FBGA G3-QS
SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L SAMGD8@ SAMGD8@ SAMGD8@ SAMGD8@ SAMGD8@ SAMGD8@ SAMGD8@ SAMGD8@
SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L SA0000C621L

@
UG11

Vinafix.com
@
UG12
C2 B4 @ @
<31> FB_A_EDC0 C13 EDC0_A DQ0_A A3 FB_A_D4 <31>
UG13 UG14
<31> FB_A_EDC1 T2 EDC1_A DQ1_A B3 FB_A_D7 <31> C2 B4
<31> FB_A_EDC3 T13 EDC0_B DQ2_A B2 FB_A_D5 <31> <31> FB_A_EDC4 C13 EDC0_A DQ0_A A3 FB_A_D32 <31>
<31> FB_A_EDC2 EDC1_B DQ3_A E3 FB_A_D6 <31> <31> FB_A_EDC5 T2 EDC1_A DQ1_A B3 FB_A_D35 <31> C2 B4 C2 B4
DQ4_A E2 FB_A_D3 <31> <31> FB_A_EDC7 T13 EDC0_B DQ2_A B2 FB_A_D34 <31> <31> FB_B_EDC0 C13 EDC0_A DQ0_A A3 FB_B_D1 <31> <31> FB_B_EDC4 C13 EDC0_A DQ0_A A3 FB_B_D35 <31>
D2 DQ5_A F2 FB_A_D1 <31> <31> FB_A_EDC6 EDC1_B DQ3_A E3 FB_A_D33 <31> <31> FB_B_EDC1 T2 EDC1_A DQ1_A B3 FB_B_D6 <31> <31> FB_B_EDC5 T2 EDC1_A DQ1_A B3 FB_B_D34 <31>
1 <31> FB_A_DBI0 D13 DBI0#_A DQ6_A G2 FB_A_D2 <31> DQ4_A E2 FB_A_D36 <31> <31> FB_B_EDC3 T13 EDC0_B DQ2_A B2 FB_B_D2 <31> <31> FB_B_EDC7 T13 EDC0_B DQ2_A B2 FB_B_D32 <31> 1
<31> FB_A_DBI1 R2 DBI1#_A DQ7_A B11 FB_A_D0 <31> D2 DQ5_A F2 FB_A_D37 <31> <31> FB_B_EDC2 EDC1_B DQ3_A E3 FB_B_D3 <31> <31> FB_B_EDC6 EDC1_B DQ3_A E3 FB_B_D37 <31>
<31> FB_A_DBI3 R13 DBI0#_B DQ8_A A12 FB_A_D14 <31> <31> FB_A_DBI4 D13 DBI0#_A DQ6_A G2 FB_A_D38 <31> DQ4_A E2 FB_B_D0 <31> DQ4_A E2 FB_B_D33 <31>
<31> FB_A_DBI2 DBI1#_B DQ9_A B12 FB_A_D15 <31> <31> FB_A_DBI5 R2 DBI1#_A DQ7_A B11 FB_A_D39 <31> D2 DQ5_A F2 FB_B_D5 <31> D2 DQ5_A F2 FB_B_D36 <31>
DQ10_A B13 FB_A_D12 <31> <31> FB_A_DBI7 R13 DBI0#_B DQ8_A A12 FB_A_D46 <31> <31> FB_B_DBI0 D13 DBI0#_A DQ6_A G2 FB_B_D4 <31> <31> FB_B_DBI4 D13 DBI0#_A DQ6_A G2 FB_B_D39 <31>
J10 DQ11_A E12 FB_A_D8 <31> <31> FB_A_DBI6 DBI1#_B DQ9_A B12 FB_A_D47 <31> <31> FB_B_DBI1 R2 DBI1#_A DQ7_A B11 FB_B_D7 <31> <31> FB_B_DBI5 R2 DBI1#_A DQ7_A B11 FB_B_D38 <31>
<31> FB_A_CLK0 K10 CK_T DQ12_A E13 FB_A_D13 <31> DQ10_A B13 FB_A_D45 <31> <31> FB_B_DBI3 R13 DBI0#_B DQ8_A A12 FB_B_D13 <31> <31> FB_B_DBI7 R13 DBI0#_B DQ8_A A12 FB_B_D42 <31>
<31> FB_A_CLK#0 G10 CK_C DQ13_A F13 FB_A_D9 <31> J10 DQ11_A E12 FB_A_D41 <31> <31> FB_B_DBI2 DBI1#_B DQ9_A B12 FB_B_D14 <31> <31> FB_B_DBI6 DBI1#_B DQ9_A B12 FB_B_D43 <31>
<31> FB_A_CMD10 M10 CKE#_A DQ14_A G13 FB_A_D11 <31> <31> FB_A_CLK1 K10 CK_T DQ12_A E13 FB_A_D40 <31> DQ10_A B13 FB_B_D12 <31> DQ10_A B13 FB_B_D40 <31>
CKE#_B DQ15_A FB_A_D10 <31> <31> FB_A_CLK#1 G10 CK_C DQ13_A F13 FB_A_D43 <31> J10 DQ11_A E12 FB_B_D15 <31> J10 DQ11_A E12 FB_B_D45 <31>
U4 <31> FB_A_CMD26 M10 CKE#_A DQ14_A G13 FB_A_D42 <31> <31> FB_B_CLK0 K10 CK_T DQ12_A E13 FB_B_D11 <31> <31> FB_B_CLK1 K10 CK_T DQ12_A E13 FB_B_D41 <31>
DQ0_B V3 FB_A_D28 <31> CKE#_B DQ15_A FB_A_D44 <31> <31> FB_B_CLK#0 G10 CK_C DQ13_A F13 FB_B_D8 <31> <31> FB_B_CLK#1 G10 CK_C DQ13_A F13 FB_B_D46 <31>
DQ1_B U3 FB_A_D30 <31> U4 <31> FB_B_CMD10 M10 CKE#_A DQ14_A G13 FB_B_D9 <31> <31> FB_B_CMD26 M10 CKE#_A DQ14_A G13 FB_B_D47 <31>
J5 DQ2_B U2 FB_A_D29 <31> DQ0_B V3 FB_A_D62 <31> CKE#_B DQ15_A FB_B_D10 <31> CKE#_B DQ15_A FB_B_D44 <31>
<31> FB_A_CMD6 K5 CABI#_A DQ3_B P3 FB_A_D31 <31> DQ1_B U3 FB_A_D59 <31> U4 U4
CABI#_B DQ4_B P2 FB_A_D27 <31> J5 DQ2_B U2 FB_A_D61 <31> DQ0_B V3 FB_B_D28 <31> DQ0_B V3 FB_B_D59 <31>
DQ5_B N2 FB_A_D26 <31> <31> FB_A_CMD22 K5 CABI#_A DQ3_B P3 FB_A_D60 <31> DQ1_B U3 FB_B_D31 <31> DQ1_B U3 FB_B_D57 <31>
DQ6_B M2 FB_A_D25 <31> CABI#_B DQ4_B P2 FB_A_D63 <31> J5 DQ2_B U2 FB_B_D29 <31> J5 DQ2_B U2 FB_B_D62 <31>
DQ7_B U11 FB_A_D24 <31> DQ5_B N2 FB_A_D58 <31> <31> FB_B_CMD6 K5 CABI#_A DQ3_B P3 FB_B_D30 <31> <31> FB_B_CMD22 K5 CABI#_A DQ3_B P3 FB_B_D56 <31>
DQ8_B V12 FB_A_D20 <31> DQ6_B M2 FB_A_D56 <31> CABI#_B DQ4_B P2 FB_B_D26 <31> CABI#_B DQ4_B P2 FB_B_D63 <31>
RG101 2 1 121_0402_1% J14 DQ9_B U12 FB_A_D23 <31> DQ7_B U11 FB_A_D57 <31> DQ5_B N2 FB_B_D27 <31> DQ5_B N2 FB_B_D60 <31>
RG102 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_A_D21 <31> DQ8_B V12 FB_A_D49 <31> DQ6_B M2 FB_B_D25 <31> DQ6_B M2 FB_B_D61 <31>
ZQ_B DQ11_B P12 FB_A_D22 <31>
RG573 2 1 121_0402_1% J14 DQ9_B U12 FB_A_D50 <31> DQ7_B U11 FB_B_D24 <31> DQ7_B U11 FB_B_D58 <31>
DQ12_B P13 FB_A_D19 <31>
RG574 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_A_D51 <31> DQ8_B V12 FB_B_D21 <31> DQ8_B V12 FB_B_D55 <31>
DQ13_B N13 FB_A_D17 <31> ZQ_B DQ11_B P12 FB_A_D48 <31>
RG103 2 1 121_0402_1% J14 DQ9_B U12 FB_B_D16 <31>
RG575 2 1 121_0402_1% J14 DQ9_B U12 FB_B_D52 <31>
DQ14_B M13 FB_A_D16 <31> DQ12_B P13 FB_A_D53 <31>
RG104 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_B_D20 <31>
RG576 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_B_D48 <31>
DQ15_B FB_A_D18 <31> DQ13_B N13 FB_A_D52 <31> ZQ_B DQ11_B P12 FB_B_D17 <31> ZQ_B DQ11_B P12 FB_B_D50 <31>
DQ14_B M13 FB_A_D55 <31> DQ12_B P13 FB_B_D18 <31> DQ12_B P13 FB_B_D53 <31>
N5 H3 DQ15_B FB_A_D54 <31> DQ13_B N13 FB_B_D22 <31> DQ13_B N13 FB_B_D51 <31>
F10 TCK CA0_A G11 FB_A_CMD0 <31> DQ14_B M13 FB_B_D23 <31> DQ14_B M13 FB_B_D49 <31>
N10 TDI CA1_A G4 FB_A_CMD9 <31> N5 H3 DQ15_B FB_B_D19 <31> DQ15_B FB_B_D54 <31>
F5 TDO CA2_A H12 FB_A_CMD8 <31> F10 TCK CA0_A G11 FB_A_CMD20 <31>
TMS CA3_A FB_A_CMD7 FB_A_CMD32 <31> TDI CA1_A FB_A_CMD28 <31>
H5 FB_A_CMD11 N10 G4 N5 H3 N5 H3
CA4_A H10 FB_A_CMD7 <31> F5 TDO CA2_A H12 FB_A_CMD21 <31> F10 TCK CA0_A G11 FB_B_CMD0 <31> F10 TCK CA0_A G11 FB_B_CMD20 <31>
CA5_A FB_A_CMD15 FB_A_CMD11 <31> TMS CA3_A FB_A_CMD23 FB_A_CMD29 <31> TDI CA1_A FB_B_CMD9 <31> TDI CA1_A FB_B_CMD28 <31>
J12 FB_A_CMD14 H5 FB_A_CMD27 N10 G4 N10 G4
D4 CA6_A J11 FB_A_CMD15 <31> CA4_A H10 FB_A_CMD23 <31> F5 TDO CA2_A H12 FB_B_CMD7 FB_B_CMD8 <31> F5 TDO CA2_A H12 FB_B_CMD23 FB_B_CMD21 <31>
<31> FB_A_WCK01 WCK0_T_A CA7_A FB_A_CMD3 FB_A_CMD14 <31> CA5_A FB_A_CMD30 FB_A_CMD27 <31> TMS CA3_A FB_B_CMD32 <31> TMS CA3_A FB_B_CMD29 <31>
D5 J4 FB_A_CMD1 J12 FB_A_CMD31 H5 FB_B_CMD11 H5 FB_B_CMD27
<31> FB_A_WCK#01 D11 WCK0_C_A CA8_A J3 FB_A_CMD3 <31> D4 CA6_A J11 FB_A_CMD30 <31> CA4_A H10 FB_B_CMD15 FB_B_CMD7 <31> CA4_A H10 FB_B_CMD30 FB_B_CMD23 <31>
<31> FB_A_WCKB01 WCK1_T_A CA9_A FB_A_CMD1 <31> <31> FB_A_WCK45 WCK0_T_A CA7_A FB_A_CMD19 FB_A_CMD31 <31> CA5_A FB_B_CMD11 <31> CA5_A FB_B_CMD27 <31>
D10 D5 J4 FB_A_CMD17 J12 FB_B_CMD14 J12 FB_B_CMD31
<31> FB_A_WCKB#01 WCK1_C_A L3 <31> FB_A_WCK#45 D11 WCK0_C_A CA8_A J3 FB_A_CMD19 <31> D4 CA6_A J11 FB_B_CMD3 FB_B_CMD15 <31> D4 CA6_A J11 FB_B_CMD19 FB_B_CMD30 <31>
CA0_B M11 FB_A_CMD4 <31> <31> FB_A_WCKB45 D10 WCK1_T_A CA9_A FB_A_CMD17 <31> <31> FB_B_WCK01 D5 WCK0_T_A CA7_A J4 FB_B_CMD14 <31> <31> FB_B_WCK45 D5 WCK0_T_A CA7_A J4 FB_B_CMD31 <31>
CA1_B FB_A_CMD12 <31> <31> FB_A_WCKB#45 WCK1_C_A <31> FB_B_WCK#01 WCK0_C_A CA8_A FB_B_CMD1 FB_B_CMD3 <31> <31> FB_B_WCK#45 WCK0_C_A CA8_A FB_B_CMD17 FB_B_CMD19 <31>
R4 M4 L3 D11 J3 D11 J3
<31> FB_A_WCKB23 R5 WCK0_T_B CA2_B L12 FB_A_CMD5 <31> CA0_B M11 FB_A_CMD16 <31> <31> FB_B_WCKB01 D10 WCK1_T_A CA9_A FB_B_CMD1 <31> <31> FB_B_WCKB45 D10 WCK1_T_A CA9_A FB_B_CMD17 <31>
<31> FB_A_WCKB#23 WCK0_C_B CA3_B FB_A_CMD7 FB_A_CMD13 <31> CA1_B FB_A_CMD25 <31> <31> FB_B_WCKB#01 WCK1_C_A <31> FB_B_WCKB#45 WCK1_C_A
R11 L5 FB_A_CMD11 R4 M4 L3 L3
<31> FB_A_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_A_WCKB67 R5 WCK0_T_B CA2_B L12 FB_A_CMD24 <31> CA0_B M11 FB_B_CMD4 <31> CA0_B M11 FB_B_CMD16 <31>
<31> FB_A_WCK#23 WCK1_C_B CA5_B FB_A_CMD15 <31> FB_A_WCKB#67 WCK0_C_B CA3_B FB_A_CMD23 FB_A_CMD33 <31> CA1_B FB_B_CMD12 <31> CA1_B FB_B_CMD25 <31>
K12 FB_A_CMD14 R11 L5 FB_A_CMD27 R4 M4 R4 M4
CA6_B K11 <31> FB_A_WCK67 R10 WCK1_T_B CA4_B L10 <31> FB_B_WCKB23 R5 WCK0_T_B CA2_B L12 FB_B_CMD7 FB_B_CMD5 <31> <31> FB_B_WCKB67 R5 WCK0_T_B CA2_B L12 FB_B_CMD23 FB_B_CMD24 <31>
CA7_B FB_A_CMD3 <31> FB_A_WCK#67 WCK1_C_B CA5_B FB_A_CMD30 <31> FB_B_WCKB#23 WCK0_C_B CA3_B FB_B_CMD13 <31> <31> FB_B_WCKB#67 WCK0_C_B CA3_B FB_B_CMD33 <31>
K4 FB_A_CMD1 K12 FB_A_CMD31 R11 L5 FB_B_CMD11 R11 L5 FB_B_CMD27
CA8_B K3 CA6_B K11 <31> FB_B_WCK23 R10 WCK1_T_B CA4_B L10 FB_B_CMD15 <31> FB_B_WCK67 R10 WCK1_T_B CA4_B L10 FB_B_CMD30
+FBA_VREFC CA9_B CA7_B FB_A_CMD19 <31> FB_B_WCK#23 WCK1_C_B CA5_B <31> FB_B_WCK#67 WCK1_C_B CA5_B
K1 +1.35VS_VGA K4 FB_A_CMD17 K12 FB_B_CMD14 K12 FB_B_CMD31
VREFC CA8_B K3 CA6_B K11 FB_B_CMD3 CA6_B K11 FB_B_CMD19
+FBA_VREFC CA9_B CA7_B CA7_B
C1 K1 +1.35VS_VGA K4 FB_B_CMD1 K4 FB_B_CMD17
J1 VDDQ1 E1 VREFC CA8_B K3 CA8_B K3
<31> FB_A_CMD2 RESET# VDDQ2 +FBB_VREFC CA9_B +FBB_VREFC CA9_B
H1 C1 K1 +1.35VS_VGA K1 +1.35VS_VGA
VDDQ3 L1 J1 VDDQ1 E1 VREFC VREFC
B1 VDDQ4 P1 <31> FB_A_CMD18 RESET# VDDQ2 H1 C1 C1
D1 VSS1 VDDQ5 T1 VDDQ3 L1 J1 VDDQ1 E1 J1 VDDQ1 E1
F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1 <31> FB_B_CMD2 RESET# VDDQ2 H1 <31> FB_B_CMD18 RESET# VDDQ2 H1
G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 VDDQ3 L1 VDDQ3 L1
M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 B1 VDDQ4 P1 B1 VDDQ4 P1
N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 T3 VSS17 VDDQ21 K13 T3 VSS17 VDDQ21 K13
P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
C5 VSS24 VDDQ28 +1.35VS_VGA P4 VSS22 VDDQ26 P14 H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
2 T5 VSS25 V4 VSS23 VDDQ27 T14 L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14 2
C10 VSS26 A1 C5 VSS24 VDDQ28 +1.35VS_VGA P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
T10 VSS27 VDD1 V1 T5 VSS25 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
A11 VSS28 VDD2 H2 C10 VSS26 A1 C5 VSS24 VDDQ28 +1.35VS_VGA C5 VSS24 VDDQ28 +1.35VS_VGA
E11 VSS29 VDD3 L2 T10 VSS27 VDD1 V1 T5 VSS25 T5 VSS25
H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 C10 VSS26 A1 C10 VSS26 A1
L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2 T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 A11 VSS28 VDD2 H2 A11 VSS28 VDD2 H2
V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 H11 VSS30 VDD4 E5 H11 VSS30 VDD4 E5
D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
M12 VSS38 VDD12 +1V8_AON F12 VSS36 VDD10 A14 C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13
N12 VSS39 G12 VSS37 VDD11 V14 D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
R12 VSS40 A5 M12 VSS38 VDD12 +1V8_AON F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
T12 VSS41 VPP1 V5 N12 VSS39 G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
A13 VSS42 VPP2 A10 R12 VSS40 A5 M12 VSS38 VDD12 +1V8_AON M12 VSS38 VDD12 +1V8_AON
V13 VSS43 VPP3 V10 T12 VSS41 VPP1 V5 N12 VSS39 N12 VSS39
B14 VSS44 VPP4 A13 VSS42 VPP2 A10 R12 VSS40 A5 R12 VSS40 A5
D14 VSS45 V13 VSS43 VPP3 V10 T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
F14 VSS46 G5 B14 VSS44 VPP4 A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
G14 VSS47 NC1 M5 D14 VSS45 V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
M14 VSS48 NC2 F14 VSS46 G5 B14 VSS44 VPP4 B14 VSS44 VPP4
N14 VSS49 G14 VSS47 NC1 M5 D14 VSS45 D14 VSS45
R14 VSS50 M14 VSS48 NC2 F14 VSS46 G5 F14 VSS46 G5
U14 VSS51 N14 VSS49 G14 VSS47 NC1 M5 G14 VSS47 NC1 M5
180-B A LL
VSS52 SGRAM GDDR6 R14 VSS50 M14 VSS48 NC2 M14 VSS48 NC2
U14 VSS51 N14 VSS49 N14 VSS49
180-B A LL
VSS52 SGRAM GDDR6 R14 VSS50 R14 VSS50
MT61K256M32JE-13-A_FBGA180~D U14 VSS51 U14 VSS51
180-B A LL 180-B A LL
+1V8_AON VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
MT61K256M32JE-13-A_FBGA180~D

MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D

UG11 UG12 UG13 UG14 UG15 UG16

GDDR6 CMD Mapping x16 Mode

Lower 0..31 Upper 32..63 S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P
DRAM1 DRAM2 MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ MCNGD6A@ GDDR6 CMD Mapping x16 Mode
CHA-Byte 0,1 CHA-Byte 4,5 SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L Lower 0..31 Upper 32..63
DRAM1 DRAM2
CA0_A CMD 0 CMD20 UG11 UG12 UG13 UG14 UG15 UG16 CHA-Byte 0,1 CHA-Byte 4,5
CA1_A CMD 9 CMD28
CA2_A CMD 8 CMD21 CA0_A CMD 0 CMD20
CA3_A CMD32 CMD29 CA1_A CMD 9 CMD28
CA4_A CMD 7 CMD23 CA2_A CMD 8 CMD21
CA5_A CMD 11 CMD27 CA3_A CMD32 CMD29
CA6_A CMD15 CMD30 S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P CA4_A CMD 7 CMD23
CA7_A CMD14 CMD31 SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ SAMGD6A@ CA5_A CMD 11 CMD27
CA8_A CMD 3 CMD19 SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L CA6_A CMD15 CMD30
CA9_A CMD 1 CMD17 CA7_A CMD14 CMD31
CABI _A CMD 6 CMD22 CA8_A CMD 3 CMD19
CKE_A CMD10 CMD26 CA9_A CMD 1 CMD17
CABI _A CMD 6 CMD22
CHB-Byte 2,3 CHB-Byte 6,7 CKE_A CMD10 CMD26
CA0_B CMD 4 CMD16
CA1_B CMD12 CMD25 CHB-Byte 2,3 CHB-Byte 6,7
CA2_B CMD 5 CMD24 UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18 CA0_B CMD 4 CMD16
CA3_B CMD13 CMD33 CA1_B CMD12 CMD25
CA4_B CMD 7 CMD23 CA2_B CMD 5 CMD24
CA5_B CMD 11 CMD27 CA3_B CMD13 CMD33
CA6_B CMD15 CMD30 CA4_B CMD 7 CMD23
CA7_B CMD14 CMD31 CA5_B CMD 11 CMD27
CA8_B CMD 3 CMD19 S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P S IC D6 256M32 MT61K256M32JE-14:A 180P CA6_B CMD15 CMD30
CA9_B CMD 1 CMD17 MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ MCNGD8A@ CA7_B CMD14 CMD31
CABI _B CMD 6 CMD22 SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L SA0000BND0L CA8_B CMD 3 CMD19
CKE_B CMD10 CMD26 CA9_B CMD 1 CMD17
UG11 UG12 UG13 UG14 UG15 UG16 UG17 UG18 CABI _B CMD 6 CMD22
RESET * CMD 2 CMD18 CKE_B CMD10 CMD26
+1.35VS_VGA
3 RESET * CMD 2 CMD18
3
1

RG110 S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
S IC D6 256M32 K4Z80325BC-HC14 FBGA 180P
549_0402_1% SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@ SAMGD8A@
@ SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L SA0000C620L

W=16mils
2

+FBA_VREFC
1 2
12/18 Update
820P_0402_25V7
1K_0402_1%
1

RG112

CG78

RG111 1
931_0402_1%
@ @
1

D
2 QG2 2 +1.35VS_VGA
<30> MEM_VREF_CTL
2

G MESS138W-G_SOT323-3
S @
3

1
RG121
549_0402_1%
@

2
1 2
+FBB_VREFC
W=16mils

820P_0402_25V7
1K_0402_1%
1

RG123

CG571
RG122 1
931_0402_1%
@ @ 10UF_0603 X 4 pcs

1
D +1.35VS_VGA
10UF_0603 X 4 pcs 10UF_0603 X 4 pcs
Close to GDDR6 UG14
MEM_VREF_CTL
+1.35VS_VGA +1.35VS_VGA 2 2

Close to GDDR6 UG11 Close to GDDR6 UG13

QG3

2
10UF_0603 X 4 pcs G MESS138W-G_SOT323-3

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
+1.35VS_VGA

Close to GDDR6 UG12

S @
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

3
2 2 2 2

CG642

CG638

CG639

CG640
2 2 2 2 2 2 2 2
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
CG103

CG104

CG105

CG106

CG577

CG573

CG574

CG575
2 2 2 2
1 1 1 1
CG550

CG546

CG547

CG551

1 1 1 1 1 1 1 1

1 1 1 1

4.7UF_0402 X 1 pcs 10UF_0603 X 2 pcs 4.7UF_0402 X 1 pcs

10UF_0603 X 2 pcs 4.7UF_0402 X 1 pcs 10UF_0603 X 2 pcs 0.47UF_0201 X 4 pcs +1V8_AON 22UF_0603 X 6 pcs 0.47UF_0201 X 4 pcs +1V8_AON

Close to +1V8_AON Around GDDR6 UG14 Close to +1V8_AON

+1.35VS_VGA
22UF_0603 X 6 pcs 0.47UF_0201 X 4 pcs 22UF_0603 X 6 pcs
Around GDDR6 UG11 Close to +1V8_AON
10UF_0603 X 2 pcs 4.7UF_0402 X 1 pcs
Around GDDR6 UG13
+1.35VS_VGA +1.35VS_VGA
22UF_0603 X 6 pcs 0.47UF_0201 X 4 pcs +1V8_AON

Around GDDR6 UG12 Close to +1V8_AON

+1.35VS_VGA

10U_0603_4V_M

10U_0603_4V_M

0.47U_0201_4V_M CG6803
4.7U_0402_4V_M CG625

0.47U_0201_4V_M CG621

0.47U_0201_4V_M CG622

0.47U_0201_4V_M CG623

0.47U_0201_4V_M CG624

CG648

CG644

CG645

CG649

CG646

CG647

4.7U_0402_4V_M CG678

0.47U_0201_4V_M CG674

0.47U_0201_4V_M CG676

0.47U_0201_4V_M CG677
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
CG107

CG108

CG109

CG110

CG111

CG112

4.7U_0402_4V_M CG511

0.47U_0201_4V_M CG512

0.47U_0201_4V_M CG513

0.47U_0201_4V_M CG514

0.47U_0201_4V_M CG515

CG583

CG579

CG580

CG584

CG581

CG582
1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1

CG643

CG641
2 2 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1
10U_0603_4V_M

10U_0603_4V_M
CG101

CG102

CG521

CG517

CG518

CG516

CG519

CG520

4.7U_0402_4V_M CG552

0.47U_0201_4V_M CG553

0.47U_0201_4V_M CG554

0.47U_0201_4V_M CG555

0.47U_0201_4V_M CG556

CG578

CG576

2 2 1 1 1 1 1 1 1 1 1 1 1

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
2 2 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2
CG548

CG549
22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2
22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

1 1 2 2 2 2 2 2 2 2 2 2 2

0.47UF_0201 X 36 pcs
0.47UF_0201 X 36 pcs 0.47UF_0201 X 36 pcs
Close to GDDR6 UG14
+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA

Close to GDDR6 UG11 Close to GDDR6 UG13

+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA
0.47UF_0201 X 36 pcs
Close to GDDR6 UG12
+1.35VS_VGA +1.35VS_VGA

0.47U_0201_4V_M CG6629

0.47U_0201_4V_M CG6619

0.47U_0201_4V_M CG6621

0.47U_0201_4V_M CG6620

0.47U_0201_4V_M CG6623

0.47U_0201_4V_M CG6622

0.47U_0201_4V_M CG6625

0.47U_0201_4V_M CG6624

0.47U_0201_4V_M CG6627

0.47U_0201_4V_M CG6626

0.47U_0201_4V_M CG6628

0.47U_0201_4V_M CG6618

0.47U_0201_4V_M CG6653

0.47U_0201_4V_M CG6630

0.47U_0201_4V_M CG6631

0.47U_0201_4V_M CG6634

0.47U_0201_4V_M CG6633

0.47U_0201_4V_M CG6636

0.47U_0201_4V_M CG6635

0.47U_0201_4V_M CG6638

0.47U_0201_4V_M CG6648

0.47U_0201_4V_M CG6650

0.47U_0201_4V_M CG6652

0.47U_0201_4V_M CG6632

0.47U_0201_4V_M CG6665

0.47U_0201_4V_M CG6656

0.47U_0201_4V_M CG6658

0.47U_0201_4V_M CG6655

0.47U_0201_4V_M CG6659

0.47U_0201_4V_M CG6657

0.47U_0201_4V_M CG6661

0.47U_0201_4V_M CG6660

0.47U_0201_4V_M CG6663

0.47U_0201_4V_M CG6662

0.47U_0201_4V_M CG6664

0.47U_0201_4V_M CG6654
0.47U_0201_4V_M CG6522

0.47U_0201_4V_M CG6523

0.47U_0201_4V_M CG6524

0.47U_0201_4V_M CG6525

0.47U_0201_4V_M CG6526

0.47U_0201_4V_M CG6527

0.47U_0201_4V_M CG6528

0.47U_0201_4V_M CG6529

0.47U_0201_4V_M CG6530

0.47U_0201_4V_M CG6531

0.47U_0201_4V_M CG6532

0.47U_0201_4V_M CG6533

0.47U_0201_4V_M CG6557

0.47U_0201_4V_M CG6547

0.47U_0201_4V_M CG6549

0.47U_0201_4V_M CG6548

0.47U_0201_4V_M CG6551

0.47U_0201_4V_M CG6550

0.47U_0201_4V_M CG6553

0.47U_0201_4V_M CG6552

0.47U_0201_4V_M CG6555

0.47U_0201_4V_M CG6554

0.47U_0201_4V_M CG6556

0.47U_0201_4V_M CG6546

0.47U_0201_4V_M CG6617

0.47U_0201_4V_M CG6594

0.47U_0201_4V_M CG6596

0.47U_0201_4V_M CG6597

0.47U_0201_4V_M CG6598

0.47U_0201_4V_M CG6599

0.47U_0201_4V_M CG6600

0.47U_0201_4V_M CG6601

0.47U_0201_4V_M CG6612

0.47U_0201_4V_M CG6615

0.47U_0201_4V_M CG6616

0.47U_0201_4V_M CG6595

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47U_0201_4V_M CG6581

0.47U_0201_4V_M CG6558

0.47U_0201_4V_M CG6560

0.47U_0201_4V_M CG6561

0.47U_0201_4V_M CG6562

0.47U_0201_4V_M CG6563

0.47U_0201_4V_M CG6564

0.47U_0201_4V_M CG6565

0.47U_0201_4V_M CG6576

0.47U_0201_4V_M CG6579

0.47U_0201_4V_M CG6580

0.47U_0201_4V_M CG6559

0.47U_0201_4V_M CG6593

0.47U_0201_4V_M CG6584

0.47U_0201_4V_M CG6586

0.47U_0201_4V_M CG6583

0.47U_0201_4V_M CG6588

0.47U_0201_4V_M CG6585

0.47U_0201_4V_M CG6590

0.47U_0201_4V_M CG6587

0.47U_0201_4V_M CG6591

0.47U_0201_4V_M CG6589

0.47U_0201_4V_M CG6592

0.47U_0201_4V_M CG6582

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

4 4

+1.35VS_VGA
+1.35VS_VGA +1.35VS_VGA

+1.35VS_VGA

0.47U_0201_4V_M CG6651

0.47U_0201_4V_M CG6639

0.47U_0201_4V_M CG6641

0.47U_0201_4V_M CG6640

0.47U_0201_4V_M CG6643

0.47U_0201_4V_M CG6642

0.47U_0201_4V_M CG6645

0.47U_0201_4V_M CG6644

0.47U_0201_4V_M CG6647

0.47U_0201_4V_M CG6646

0.47U_0201_4V_M CG6649

0.47U_0201_4V_M CG6637
0.47U_0201_4V_M CG6545

0.47U_0201_4V_M CG6534

0.47U_0201_4V_M CG6536

0.47U_0201_4V_M CG6537

0.47U_0201_4V_M CG6538

0.47U_0201_4V_M CG6539

0.47U_0201_4V_M CG6540

0.47U_0201_4V_M CG6541

0.47U_0201_4V_M CG6542

0.47U_0201_4V_M CG6543

0.47U_0201_4V_M CG6544

0.47U_0201_4V_M CG6535

0.47U_0201_4V_M CG6614

0.47U_0201_4V_M CG6603

0.47U_0201_4V_M CG6605

0.47U_0201_4V_M CG6604

0.47U_0201_4V_M CG6607

0.47U_0201_4V_M CG6606

0.47U_0201_4V_M CG6609

0.47U_0201_4V_M CG6608

0.47U_0201_4V_M CG6611

0.47U_0201_4V_M CG6610

0.47U_0201_4V_M CG6613

0.47U_0201_4V_M CG6602

1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47U_0201_4V_M CG6578

0.47U_0201_4V_M CG6567

0.47U_0201_4V_M CG6569

0.47U_0201_4V_M CG6568

0.47U_0201_4V_M CG6571

0.47U_0201_4V_M CG6570

0.47U_0201_4V_M CG6573

0.47U_0201_4V_M CG6572

0.47U_0201_4V_M CG6575

0.47U_0201_4V_M CG6574

0.47U_0201_4V_M CG6577

0.47U_0201_4V_M CG6566

1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P035-VRAM_GDDR6_AB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Si ze Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Dat e: Thursday, May 30, 2019 Sheet 35 of 109

A B C D E
 A B C D E

@
UG15 @

Vinafix.com
UG16 @
UG17 @
C2 B4 UG18
<31> FB_C_EDC0 C13 EDC0_A DQ0_A A3 FB_C_D1 <31> C2 B4
<31> FB_C_EDC1 T2 EDC1_A DQ1_A B3 FB_C_D7 <31> <31> FB_C_EDC4 C13 EDC0_A DQ0_A A3 FB_C_D32 <31> C2 B4
<31> FB_C_EDC3 T13 EDC0_B DQ2_A B2 FB_C_D5 <31> <31> FB_C_EDC5 T2 EDC1_A DQ1_A B3 FB_C_D34 <31> <31> FB_D_EDC0 C13 EDC0_A DQ0_A A3 FB_D_D0 <31> C2 B4
<31> FB_C_EDC2 EDC1_B DQ3_A E3 FB_C_D4 <31> <31> FB_C_EDC7 T13 EDC0_B DQ2_A B2 FB_C_D36 <31> <31> FB_D_EDC1 T2 EDC1_A DQ1_A B3 FB_D_D7 <31> <31> FB_D_EDC4 C13 EDC0_A DQ0_A A3 FB_D_D35 <31>
DQ4_A E2 FB_C_D6 <31> <31> FB_C_EDC6 EDC1_B DQ3_A E3 FB_C_D38 <31> <31> FB_D_EDC3 T13 EDC0_B DQ2_A B2 FB_D_D1 <31> <31> FB_D_EDC5 T2 EDC1_A DQ1_A B3 FB_D_D33 <31>
D2 DQ5_A F2 FB_C_D3 <31> DQ4_A E2 FB_C_D35 <31> <31> FB_D_EDC2 EDC1_B DQ3_A E3 FB_D_D3 <31> <31> FB_D_EDC7 T13 EDC0_B DQ2_A B2 FB_D_D32 <31>
1 <31> FB_C_DBI0 D13 DBI0#_A DQ6_A G2 FB_C_D0 <31> D2 DQ5_A F2 FB_C_D37 <31> DQ4_A E2 FB_D_D6 <31> <31> FB_D_EDC6 EDC1_B DQ3_A E3 FB_D_D37 <31> 1
<31> FB_C_DBI1 R2 DBI1#_A DQ7_A B11 FB_C_D2 <31> <31> FB_C_DBI4 D13 DBI0#_A DQ6_A G2 FB_C_D39 <31> D2 DQ5_A F2 FB_D_D5 <31> DQ4_A E2 FB_D_D34 <31>
<31> FB_C_DBI3 R13 DBI0#_B DQ8_A A12 FB_C_D14 <31> <31> FB_C_DBI5 R2 DBI1#_A DQ7_A B11 FB_C_D33 <31> <31> FB_D_DBI0 D13 DBI0#_A DQ6_A G2 FB_D_D2 <31> D2 DQ5_A F2 FB_D_D39 <31>
<31> FB_C_DBI2 DBI1#_B DQ9_A B12 FB_C_D15 <31> <31> FB_C_DBI7 R13 DBI0#_B DQ8_A A12 FB_C_D46 <31> <31> FB_D_DBI1 R2 DBI1#_A DQ7_A B11 FB_D_D4 <31> <31> FB_D_DBI4 D13 DBI0#_A DQ6_A G2 FB_D_D36 <31>
DQ10_A B13 FB_C_D8 <31> <31> FB_C_DBI6 DBI1#_B DQ9_A B12 FB_C_D44 <31> <31> FB_D_DBI3 R13 DBI0#_B DQ8_A A12 FB_D_D13 <31> <31> FB_D_DBI5 R2 DBI1#_A DQ7_A B11 FB_D_D38 <31>
J10 DQ11_A E12 FB_C_D12 <31> DQ10_A B13 FB_C_D45 <31> <31> FB_D_DBI2 DBI1#_B DQ9_A B12 FB_D_D14 <31> <31> FB_D_DBI7 R13 DBI0#_B DQ8_A A12 FB_D_D43 <31>
<31> FB_C_CLK0 K10 CK_T DQ12_A E13 FB_C_D13 <31> J10 DQ11_A E12 FB_C_D40 <31> DQ10_A B13 FB_D_D8 <31> <31> FB_D_DBI6 DBI1#_B DQ9_A B12 FB_D_D40 <31>
<31> FB_C_CLK#0 G10 CK_C DQ13_A F13 FB_C_D9 <31> <31> FB_C_CLK1 K10 CK_T DQ12_A E13 FB_C_D43 <31> J10 DQ11_A E12 FB_D_D12 <31> DQ10_A B13 FB_D_D41 <31>
<31> FB_C_CMD10 M10 CKE#_A DQ14_A G13 FB_C_D11 <31> <31> FB_C_CLK#1 G10 CK_C DQ13_A F13 FB_C_D42 <31> <31> FB_D_CLK0 K10 CK_T DQ12_A E13 FB_D_D10 <31> J10 DQ11_A E12 FB_D_D42 <31>
CKE#_B DQ15_A FB_C_D10 <31> <31> FB_C_CMD26 M10 CKE#_A DQ14_A G13 FB_C_D47 <31> <31> FB_D_CLK#0 G10 CK_C DQ13_A F13 FB_D_D15 <31> <31> FB_D_CLK1 K10 CK_T DQ12_A E13 FB_D_D45 <31>
U4 CKE#_B DQ15_A FB_C_D41 <31> <31> FB_D_CMD10 M10 CKE#_A DQ14_A G13 FB_D_D9 <31> <31> FB_D_CLK#1 G10 CK_C DQ13_A F13 FB_D_D46 <31>
DQ0_B V3 FB_C_D31 <31> U4 CKE#_B DQ15_A FB_D_D11 <31> <31> FB_D_CMD26 M10 CKE#_A DQ14_A G13 FB_D_D44 <31>
DQ1_B U3 FB_C_D29 <31> DQ0_B V3 FB_C_D56 <31> U4 CKE#_B DQ15_A FB_D_D47 <31>
J5 DQ2_B U2 FB_C_D30 <31> DQ1_B U3 FB_C_D57 <31> DQ0_B V3 FB_D_D30 <31> U4
<31> FB_C_CMD6 K5 CABI#_A DQ3_B P3 FB_C_D28 <31> J5 DQ2_B U2 FB_C_D58 <31> DQ1_B U3 FB_D_D26 <31> DQ0_B V3 FB_D_D56 <31>
CABI#_B DQ4_B P2 FB_C_D25 <31> <31> FB_C_CMD22 K5 CABI#_A DQ3_B P3 FB_C_D59 <31> J5 DQ2_B U2 FB_D_D31 <31> DQ1_B U3 FB_D_D59 <31>
DQ5_B N2 FB_C_D24 <31> CABI#_B DQ4_B P2 FB_C_D60 <31> <31> FB_D_CMD6 K5 CABI#_A DQ3_B P3 FB_D_D28 <31> J5 DQ2_B U2 FB_D_D58 <31>
DQ6_B M2 FB_C_D27 <31> DQ5_B N2 FB_C_D61 <31> CABI#_B DQ4_B P2 FB_D_D27 <31> <31> FB_D_CMD22 K5 CABI#_A DQ3_B P3 FB_D_D60 <31>
DQ7_B U11 FB_C_D26 <31> DQ6_B M2 FB_C_D62 <31> DQ5_B N2 FB_D_D25 <31> CABI#_B DQ4_B P2 FB_D_D57 <31>
DQ8_B V12 FB_C_D23 <31> DQ7_B U11 FB_C_D63 <31> DQ6_B M2 FB_D_D24 <31> DQ5_B N2 FB_D_D62 <31>
RG105 2 1 121_0402_1% J14 DQ9_B U12 FB_C_D21 <31> DQ8_B V12 FB_C_D51 <31> DQ7_B U11 FB_D_D29 <31> DQ6_B M2 FB_D_D61 <31>
RG106 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_C_D22 <31>
RG577 2 1 121_0402_1% J14 DQ9_B U12 FB_C_D48 <31> DQ8_B V12 FB_D_D22 <31> DQ7_B U11 FB_D_D63 <31>
ZQ_B DQ11_B P12 FB_C_D20 <31>
RG578 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_C_D49 <31>
RG107 2 1 121_0402_1% J14 DQ9_B U12 FB_D_D20 <31> DQ8_B V12 FB_D_D51 <31>
DQ12_B P13 FB_C_D17 <31> ZQ_B DQ11_B P12 FB_C_D50 <31>
RG108 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_D_D23 <31>
RG579 2 1 121_0402_1% J14 DQ9_B U12 FB_D_D49 <31>
DQ13_B N13 FB_C_D18 <31> DQ12_B P13 FB_C_D53 <31> ZQ_B DQ11_B P12 FB_D_D21 <31>
RG580 2 1 121_0402_1% K14 ZQ_A DQ10_B U13 FB_D_D48 <31>
DQ14_B M13 FB_C_D16 <31> DQ13_B N13 FB_C_D54 <31> DQ12_B P13 FB_D_D17 <31> ZQ_B DQ11_B P12 FB_D_D50 <31>
DQ15_B FB_C_D19 <31> DQ14_B M13 FB_C_D55 <31> DQ13_B N13 FB_D_D19 <31> DQ12_B P13 FB_D_D52 <31>
DQ15_B FB_C_D52 <31> DQ14_B M13 FB_D_D16 <31> DQ13_B N13 FB_D_D55 <31>
N5 H3 DQ15_B FB_D_D18 <31> DQ14_B M13 FB_D_D53 <31>
F10 TCK CA0_A G11 FB_C_CMD0 <31> N5 H3 DQ15_B FB_D_D54 <31>
N10 TDI CA1_A G4 FB_C_CMD9 <31> F10 TCK CA0_A G11 FB_C_CMD20 <31> N5 H3
F5 TDO CA2_A H12 FB_C_CMD8 <31> N10 TDI CA1_A G4 FB_C_CMD28 <31> F10 TCK CA0_A G11 FB_D_CMD0 <31> N5 H3
TMS CA3_A FB_C_CMD7 FB_C_CMD32 <31> TDO CA2_A FB_C_CMD21 <31> TDI CA1_A FB_D_CMD9 <31> TCK CA0_A FB_D_CMD20 <31>
H5 FB_C_CMD11 F5 H12 FB_C_CMD23 N10 G4 F10 G11
CA4_A H10 FB_C_CMD7 <31> TMS CA3_A H5 FB_C_CMD27 FB_C_CMD29 <31> F5 TDO CA2_A H12 FB_D_CMD8 <31> N10 TDI CA1_A G4 FB_D_CMD28 <31>
CA5_A FB_C_CMD15 FB_C_CMD11 <31> CA4_A FB_C_CMD23 <31> TMS CA3_A FB_D_CMD7 FB_D_CMD32 <31> TDO CA2_A FB_D_CMD21 <31>
J12 FB_C_CMD14 H10 FB_C_CMD30 H5 FB_D_CMD11 F5 H12 FB_D_CMD23
D4 CA6_A J11 FB_C_CMD15 <31> CA5_A J12 FB_C_CMD31 FB_C_CMD27 <31> CA4_A H10 FB_D_CMD7 <31> TMS CA3_A H5 FB_D_CMD27 FB_D_CMD29 <31>
<31> FB_C_WCK01 WCK0_T_A CA7_A FB_C_CMD3 FB_C_CMD14 <31> CA6_A FB_C_CMD30 <31> CA5_A FB_D_CMD15 FB_D_CMD11 <31> CA4_A FB_D_CMD23 <31>
D5 J4 FB_C_CMD1 D4 J11 FB_C_CMD19 J12 FB_D_CMD14 H10 FB_D_CMD30
<31> FB_C_WCK#01 D11 WCK0_C_A CA8_A J3 FB_C_CMD3 <31> <31> FB_C_WCK45 D5 WCK0_T_A CA7_A J4 FB_C_CMD31 <31> D4 CA6_A J11 FB_D_CMD15 <31> CA5_A J12 FB_D_CMD31 FB_D_CMD27 <31>
<31> FB_C_WCKB01 WCK1_T_A CA9_A FB_C_CMD1 <31> <31> FB_C_WCK#45 WCK0_C_A CA8_A FB_C_CMD17 FB_C_CMD19 <31> <31> FB_D_WCK01 WCK0_T_A CA7_A FB_D_CMD3 FB_D_CMD14 <31> CA6_A FB_D_CMD30 <31>
D10 D11 J3 D5 J4 FB_D_CMD1 D4 J11 FB_D_CMD19
<31> FB_C_WCKB#01 WCK1_C_A L3 <31> FB_C_WCKB45 D10 WCK1_T_A CA9_A FB_C_CMD17 <31> <31> FB_D_WCK#01 D11 WCK0_C_A CA8_A J3 FB_D_CMD3 <31> <31> FB_D_WCK45 D5 WCK0_T_A CA7_A J4 FB_D_CMD31 <31>
CA0_B FB_C_CMD4 <31> <31> FB_C_WCKB#45 WCK1_C_A <31> FB_D_WCKB01 WCK1_T_A CA9_A FB_D_CMD1 <31> <31> FB_D_WCK#45 WCK0_C_A CA8_A FB_D_CMD17 FB_D_CMD19 <31>
M11 L3 D10 D11 J3
R4 CA1_B M4 FB_C_CMD12 <31> CA0_B M11 FB_C_CMD16 <31> <31> FB_D_WCKB#01 WCK1_C_A L3 <31> FB_D_WCKB45 D10 WCK1_T_A CA9_A FB_D_CMD17 <31>
<31> FB_C_WCKB23 R5 WCK0_T_B CA2_B L12 FB_C_CMD5 <31> R4 CA1_B M4 FB_C_CMD25 <31> CA0_B M11 FB_D_CMD4 <31> <31> FB_D_WCKB#45 WCK1_C_A L3
<31> FB_C_WCKB#23 WCK0_C_B CA3_B FB_C_CMD7 FB_C_CMD13 <31> <31> FB_C_WCKB67 WCK0_T_B CA2_B FB_C_CMD24 <31> CA1_B FB_D_CMD12 <31> CA0_B FB_D_CMD16 <31>
R11 L5 FB_C_CMD11 R5 L12 FB_C_CMD23 R4 M4 M11
<31> FB_C_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_C_WCKB#67 R11 WCK0_C_B CA3_B L5 FB_C_CMD33 <31> <31> FB_D_WCKB23 R5 WCK0_T_B CA2_B L12 FB_D_CMD5 <31> R4 CA1_B M4 FB_D_CMD25 <31>
<31> FB_C_WCK#23 WCK1_C_B CA5_B FB_C_CMD15 <31> FB_C_WCK67 WCK1_T_B CA4_B FB_C_CMD27 <31> FB_D_WCKB#23 WCK0_C_B CA3_B FB_D_CMD7 FB_D_CMD13 <31> <31> FB_D_WCKB67 WCK0_T_B CA2_B FB_D_CMD24 <31>
K12 FB_C_CMD14 R10 L10 FB_C_CMD30 R11 L5 FB_D_CMD11 R5 L12 FB_D_CMD23
CA6_B K11 <31> FB_C_WCK#67 WCK1_C_B CA5_B K12 FB_C_CMD31 <31> FB_D_WCK23 R10 WCK1_T_B CA4_B L10 <31> FB_D_WCKB#67 R11 WCK0_C_B CA3_B L5 FB_D_CMD33 <31>
CA7_B FB_C_CMD3 CA6_B <31> FB_D_WCK#23 WCK1_C_B CA5_B FB_D_CMD15 <31> FB_D_WCK67 WCK1_T_B CA4_B FB_D_CMD27
K4 FB_C_CMD1 K11 FB_C_CMD19 K12 FB_D_CMD14 R10 L10 FB_D_CMD30
CA8_B K3 CA7_B K4 FB_C_CMD17 CA6_B K11 <31> FB_D_WCK#67 WCK1_C_B CA5_B K12 FB_D_CMD31
+FBC_VREFC CA9_B CA8_B CA7_B FB_D_CMD3 CA6_B
K1 +1.35VS_VGA
+FBC_VREFC K3 K4 FB_D_CMD1 K11 FB_D_CMD19
VREFC K1 CA9_B +1.35VS_VGA CA8_B K3 CA7_B K4 FB_D_CMD17
VREFC +FBD_VREFC CA9_B CA8_B
C1 K1 +1.35VS_VGA
+FBD_VREFC K3
J1 VDDQ1 E1 C1 VREFC K1 CA9_B +1.35VS_VGA
<31> FB_C_CMD2 RESET# VDDQ2 H1 J1 VDDQ1 E1 C1 VREFC
VDDQ3 L1 <31> FB_C_CMD18 RESET# VDDQ2 H1 J1 VDDQ1 E1 C1
B1 VDDQ4 P1 VDDQ3 L1 <31> FB_D_CMD2 RESET# VDDQ2 H1 J1 VDDQ1 E1
D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 VDDQ3 L1 <31> FB_D_CMD18 RESET# VDDQ2 H1
F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1 VDDQ3 L1
G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1 B1 VDDQ4 P1
M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2 D1 VSS1 VDDQ5 T1
N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2 F1 VSS2 VDDQ6 J2
R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4 G1 VSS3 VDDQ7 K2
U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4 M1 VSS4 VDDQ8 C4
A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4 N1 VSS5 VDDQ9 F4
V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4 R1 VSS6 VDDQ10 N4
C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5 U1 VSS7 VDDQ11 T4
D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5 A2 VSS8 VDDQ12 B5
F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10 V2 VSS9 VDDQ13 U5
G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10 C3 VSS10 VDDQ14 B10
M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11 D3 VSS11 VDDQ15 U10
N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11 F3 VSS12 VDDQ16 C11
R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11 G3 VSS13 VDDQ17 F11
T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11 M3 VSS14 VDDQ18 N11
A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13 N3 VSS15 VDDQ19 T11
E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13 R3 VSS16 VDDQ20 J13
H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14 T3 VSS17 VDDQ21 K13
L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14 A4 VSS18 VDDQ22 C14
P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14 E4 VSS19 VDDQ23 E14
V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14 H4 VSS20 VDDQ24 H14
C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 L4 VSS21 VDDQ25 L14
2 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14 P4 VSS22 VDDQ26 P14 2
C10 VSS26 A1 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA V4 VSS23 VDDQ27 T14
T10 VSS27 VDD1 V1 C10 VSS26 A1 T5 VSS25 C5 VSS24 VDDQ28 +1.35VS_VGA
A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1 C10 VSS26 A1 T5 VSS25
E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1 C10 VSS26 A1
H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2 T10 VSS27 VDD1 V1
L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2 A11 VSS28 VDD2 H2
P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5 E11 VSS29 VDD3 L2
V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5 H11 VSS30 VDD4 E5
C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10 L11 VSS31 VDD5 P5
D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10 P11 VSS32 VDD6 E10
F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13 V11 VSS33 VDD7 P10
G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13 C12 VSS34 VDD8 H13
M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14 D12 VSS35 VDD9 L13
N12 VSS39 M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14 F12 VSS36 VDD10 A14
R12 VSS40 A5 N12 VSS39 M12 VSS38 VDD12 +1V8_AON G12 VSS37 VDD11 V14
T12 VSS41 VPP1 V5 R12 VSS40 A5 N12 VSS39 M12 VSS38 VDD12 +1V8_AON
A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5 R12 VSS40 A5 N12 VSS39
V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5 R12 VSS40 A5
B14 VSS44 VPP4 V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10 T12 VSS41 VPP1 V5
D14 VSS45 B14 VSS44 VPP4 V13 VSS43 VPP3 V10 A13 VSS42 VPP2 A10
F14 VSS46 G5 D14 VSS45 B14 VSS44 VPP4 V13 VSS43 VPP3 V10
G14 VSS47 NC1 M5 F14 VSS46 G5 D14 VSS45 B14 VSS44 VPP4
M14 VSS48 NC2 G14 VSS47 NC1 M5 F14 VSS46 G5 D14 VSS45
N14 VSS49 M14 VSS48 NC2 G14 VSS47 NC1 M5 F14 VSS46 G5
R14 VSS50 N14 VSS49 M14 VSS48 NC2 G14 VSS47 NC1 M5
U14 VSS51 R14 VSS50 N14 VSS49 M14 VSS48 NC2
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51 R14 VSS50 N14 VSS49
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51 R14 VSS50
180-B A LL
VSS52 SGRAM GDDR6 U14 VSS51
180-B A LL
MT61K256M32JE-13-A_FBGA180~D VSS52 SGRAM GDDR6
+1V8_AON MT61K256M32JE-13-A_FBGA180~D
MT61K256M32JE-13-A_FBGA180~D
MT61K256M32JE-13-A_FBGA180~D

GDDR6 CMD Mapping x16 Mode

Lower 0..31 Upper 32..63
DRAM1 DRAM2
CHA-Byte 0,1 CHA-Byte 4,5

CA0_A CMD 0 CMD20 GDDR6 CMD Mapping x16 Mode

CA1_A CMD 9 CMD28 Lower 0..31 Upper 32..63
CA2_A CMD 8 CMD21 DRAM1 DRAM2
CA3_A CMD32 CMD29 CHA-Byte 0,1 CHA-Byte 4,5
CA4_A CMD 7 CMD23
CA5_A CMD 11 CMD27 CA0_A CMD 0 CMD20
CA6_A CMD15 CMD30 CA1_A CMD 9 CMD28
CA7_A CMD14 CMD31 CA2_A CMD 8 CMD21
CA8_A CMD 3 CMD19 CA3_A CMD32 CMD29
CA9_A CMD 1 CMD17 CA4_A CMD 7 CMD23
CABI _A CMD 6 CMD22 CA5_A CMD 11 CMD27
CKE_A CMD10 CMD26 CA6_A CMD15 CMD30
CA7_A CMD14 CMD31
CHB-Byte 2,3 CHB-Byte 6,7 +1.35VS_VGA CA8_A CMD 3 CMD19
CA0_B CMD 4 CMD16 CA9_A CMD 1 CMD17
CA1_B CMD12 CMD25 CABI _A CMD 6 CMD22
1

CA2_B CMD 5 CMD24 +1.35VS_VGA CKE_A CMD10 CMD26

CA3_B CMD13 CMD33 RG132
CA4_B CMD 7 CMD23 549_0402_1% CHB-Byte 2,3 CHB-Byte 6,7

1
CA5_B CMD 11 CMD27 @ CA0_B CMD 4 CMD16
CA6_B CMD15 CMD30 RG155 CA1_B CMD12 CMD25
2

3
CA7_B
CA8_B
CMD14
CMD 3
CMD31
CMD19 1 2
+FBC_VREFC
W=16mils 549_0402_1%
@
CA2_B
CA3_B
CMD 5
CMD13
CMD24
CMD33
3
CA9_B CMD 1 CMD17 CA4_B CMD 7 CMD23
820P_0402_25V7
1K_0402_1%
1

2
RG134

CG148

CABI _B
CKE_B
CMD 6
CMD10
CMD22
CMD26
RG133
931_0402_1%
1
1 2
+FBD_VREFC
W=16mils CA5_B
CA6_B
CMD 11
CMD15
CMD27
CMD30

@ @ CA7_B CMD14 CMD31

820P_0402_25V7
1K_0402_1%
1

1
D

RG154

CG256
RESET * CMD 2 CMD18 RG156 1 CA8_B CMD 3 CMD19
2 QG4 2 931_0402_1% CA9_B CMD 1 CMD17
<30> MEM_VREF_CTL
2

G MESS138W-G_SOT323-3 @ @ CABI _B CMD 6 CMD22

1
@ D
S MEM_VREF_CTL CKE_B CMD10 CMD26
3

2 QG8 2

2
G MESS138W-G_SOT323-3 RESET * CMD 2 CMD18

S @

3
10UF_0603 X 4 pcs +1.35VS_VGA
10UF_0603 X 4 pcs 10UF_0603 X 4 pcs
10UF_0603 X 4 pcs +1.35VS_VGA
Close to GDDR6 UG16
+1.35VS_VGA

Close to GDDR6 UG17

+1.35VS_VGA
Close to GDDR6 UG18
Close to GDDR6 UG15

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
2 2 2 2
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

CG844

CG845

CG840

CG848
2 2 2 2 2 2 2 2 Chage:0.47uF
CG739

CG736

CG735

CG743

CG794

CG785

CG789

CG795
2 2 2 2 1. 0401 --> 0201
CG684

CG681

CG686

CG685

1 1 1 1 2. X5R --> X7R or X6S

1 1 1 1 1 1 1 1
1 1 1 1

10UF_0603 X 2 pcs
10UF_0603 X 2 pcs 4.7UF_0402 X 1 pcs 10UF_0603 X 2 pcs 22UF_0603 X 6 pcs
10UF_0603 X 2 pcs
Around GDDR6 UG18
+1.35VS_VGA
22UF_0603 X 6 pcs 0.47UF_0201 X 4 pcs +1V8_AON 22UF_0603 X 6 pcs
Around GDDR6 UG16 Close to +1V8_AON Around GDDR6 UG17
+1.35VS_VGA +1.35VS_VGA
22UF_0603 X 6 pcs
Around GDDR6 UG15
+1.35VS_VGA

10U_0603_4V_M

10U_0603_4V_M

CG849

CG839

CG838

CG842

CG847

CG841
10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M

10U_0603_4V_M
CG741

CG737

CG733

CG738

CG734

CG740

4.7U_0402_4V_M CG770

0.47U_0201_4V_M CG778

0.47U_0201_4V_M CG781

0.47U_0201_4V_M CG769

0.47U_0201_4V_M CG775

CG790

CG787

CG788

CG796

CG792

CG791
2 2 1 1 1 1 1 1
10U_0603_4V_M

10U_0603_4V_M

CG679

CG680

CG682

CG690

CG683

CG687

CG846

CG843
2 2 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1
CG732

CG742

CG786

CG793
2 2 1 1 1 1 1 1
CG688

CG689

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
1 1 2 2 2 2 2 2
22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M
1 1 2 2 2 2 2 2 2 2 2 2 2 1 1 2 2 2 2 2 2
22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

22U_0603_4V_M

1 1 2 2 2 2 2 2

4.7UF_0402 X 1 pcs
4.7UF_0402 X 1 pcs 0.47UF_0201 X 36 pcs 0.47UF_0201 X 4 pcs +1V8_AON
4.7UF_0402 X 1 pcs 0.47UF_0201 X 36 pcs 0.47UF_0201 X 36 pcs
Close to GDDR6 UG18 Close to +1V8_AON
+1.35VS_VGA
0.47UF_0201 X 4 pcs +1V8_AON
0.47UF_0201 X 36 pcs
Close to GDDR6 UG16 Close to GDDR6 UG17 Close to +1V8_AON
+1.35VS_VGA +1.35VS_VGA +1.35VS_VGA
0.47UF_0201 X 4 pcs
Close to GDDR6 UG15 Close to +1V8_AON
+1.35VS_VGA

0.47U_0201_4V_M CG6785

0.47U_0201_4V_M CG6762

0.47U_0201_4V_M CG6764

0.47U_0201_4V_M CG6765

0.47U_0201_4V_M CG6766

0.47U_0201_4V_M CG6767

0.47U_0201_4V_M CG6768

0.47U_0201_4V_M CG6769

0.47U_0201_4V_M CG6780

0.47U_0201_4V_M CG6782

0.47U_0201_4V_M CG6784

0.47U_0201_4V_M CG6763

4.7U_0402_4V_M CG888

0.47U_0201_4V_M CG878

0.47U_0201_4V_M CG887

0.47U_0201_4V_M CG882

0.47U_0201_4V_M CG889
0.47U_0201_4V_M CG6725

0.47U_0201_4V_M CG6702

0.47U_0201_4V_M CG6703

0.47U_0201_4V_M CG6706

0.47U_0201_4V_M CG6705

0.47U_0201_4V_M CG6708

0.47U_0201_4V_M CG6707

0.47U_0201_4V_M CG6710

0.47U_0201_4V_M CG6720

0.47U_0201_4V_M CG6721

0.47U_0201_4V_M CG6724

0.47U_0201_4V_M CG6704

0.47U_0201_4V_M CG6749

0.47U_0201_4V_M CG6726

0.47U_0201_4V_M CG6727

0.47U_0201_4V_M CG6730

0.47U_0201_4V_M CG6729

0.47U_0201_4V_M CG6732

0.47U_0201_4V_M CG6731

0.47U_0201_4V_M CG6734

0.47U_0201_4V_M CG6744

0.47U_0201_4V_M CG6745

0.47U_0201_4V_M CG6748

0.47U_0201_4V_M CG6728
0.47U_0201_4V_M CG783

0.47U_0201_4V_M CG768

0.47U_0201_4V_M CG779

0.47U_0201_4V_M CG782

0.47U_0201_4V_M CG780

0.47U_0201_4V_M CG771

0.47U_0201_4V_M CG772

0.47U_0201_4V_M CG777

0.47U_0201_4V_M CG784

0.47U_0201_4V_M CG776

0.47U_0201_4V_M CG773

0.47U_0201_4V_M CG774

4.7U_0402_4V_M CG827

0.47U_0201_4V_M CG823

0.47U_0201_4V_M CG835

0.47U_0201_4V_M CG826

0.47U_0201_4V_M CG837
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47U_0201_4V_M CG6689

0.47U_0201_4V_M CG6666

0.47U_0201_4V_M CG6667

0.47U_0201_4V_M CG6670

0.47U_0201_4V_M CG6669

0.47U_0201_4V_M CG6672

0.47U_0201_4V_M CG6671

0.47U_0201_4V_M CG6674

0.47U_0201_4V_M CG6684

0.47U_0201_4V_M CG6686

0.47U_0201_4V_M CG6688

0.47U_0201_4V_M CG6668

4.7U_0402_4V_M CG727

0.47U_0201_4V_M CG718

0.47U_0201_4V_M CG723

0.47U_0201_4V_M CG722

0.47U_0201_4V_M CG726

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

+1.35VS_VGA +1.35VS_VGA
4 +1.35VS_VGA +1.35VS_VGA +1.35VS_VGA 4
+1.35VS_VGA +1.35VS_VGA

0.47U_0201_4V_M CG6783

0.47U_0201_4V_M CG6771

0.47U_0201_4V_M CG6773

0.47U_0201_4V_M CG6772

0.47U_0201_4V_M CG6775

0.47U_0201_4V_M CG6774

0.47U_0201_4V_M CG6777

0.47U_0201_4V_M CG6776

0.47U_0201_4V_M CG6779

0.47U_0201_4V_M CG6778

0.47U_0201_4V_M CG6781

0.47U_0201_4V_M CG6770

0.47U_0201_4V_M CG6797

0.47U_0201_4V_M CG6787

0.47U_0201_4V_M CG6789

0.47U_0201_4V_M CG6788

0.47U_0201_4V_M CG6791

0.47U_0201_4V_M CG6790

0.47U_0201_4V_M CG6793

0.47U_0201_4V_M CG6792

0.47U_0201_4V_M CG6795

0.47U_0201_4V_M CG6794

0.47U_0201_4V_M CG6796

0.47U_0201_4V_M CG6786
0.47U_0201_4V_M CG6723

0.47U_0201_4V_M CG6711

0.47U_0201_4V_M CG6713

0.47U_0201_4V_M CG6712

0.47U_0201_4V_M CG6715

0.47U_0201_4V_M CG6714

0.47U_0201_4V_M CG6717

0.47U_0201_4V_M CG6716

0.47U_0201_4V_M CG6719

0.47U_0201_4V_M CG6718

0.47U_0201_4V_M CG6722

0.47U_0201_4V_M CG6709

0.47U_0201_4V_M CG6747

0.47U_0201_4V_M CG6735

0.47U_0201_4V_M CG6737

0.47U_0201_4V_M CG6736

0.47U_0201_4V_M CG6739

0.47U_0201_4V_M CG6738

0.47U_0201_4V_M CG6741

0.47U_0201_4V_M CG6740

0.47U_0201_4V_M CG6743

0.47U_0201_4V_M CG6742

0.47U_0201_4V_M CG6746

0.47U_0201_4V_M CG6733

0.47U_0201_4V_M CG6761

0.47U_0201_4V_M CG6751

0.47U_0201_4V_M CG6753

0.47U_0201_4V_M CG6752

0.47U_0201_4V_M CG6755

0.47U_0201_4V_M CG6754

0.47U_0201_4V_M CG6757

0.47U_0201_4V_M CG6756

0.47U_0201_4V_M CG6759

0.47U_0201_4V_M CG6758

0.47U_0201_4V_M CG6760

0.47U_0201_4V_M CG6750
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.47U_0201_4V_M CG6687

0.47U_0201_4V_M CG6675

0.47U_0201_4V_M CG6677

0.47U_0201_4V_M CG6676

0.47U_0201_4V_M CG6679

0.47U_0201_4V_M CG6678

0.47U_0201_4V_M CG6681

0.47U_0201_4V_M CG6680

0.47U_0201_4V_M CG6683

0.47U_0201_4V_M CG6682

0.47U_0201_4V_M CG6685

0.47U_0201_4V_M CG6673

0.47U_0201_4V_M CG6701

0.47U_0201_4V_M CG6691

0.47U_0201_4V_M CG6693

0.47U_0201_4V_M CG6692

0.47U_0201_4V_M CG6695

0.47U_0201_4V_M CG6694

0.47U_0201_4V_M CG6697

0.47U_0201_4V_M CG6696

0.47U_0201_4V_M CG6699

0.47U_0201_4V_M CG6698

0.47U_0201_4V_M CG6700

0.47U_0201_4V_M CG6690

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P036-VRAM_GDDR6_CD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Si ze Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Dat e: Thursday, May 30, 2019 Sheet 36 of 109

A B C D E
 5 4 3 2 1

Vinafix.com
D D

+1V8_AON

+1V8_AON / +1V8_MAIN

1
+3VS
RG1516
100K_0402_5%

1
1
CG7105 RG1514

2
0.1U_0201_6.3V6K 10K_0402_5%
+1V8_AON
2 +1.8VALW UG45

2
1 14
VIN1 VOUT1

5
2 13
1 VIN1 VOUT1

10U_0603_6.3V6M
VCC CG7099
<27,97> +1.35VS_VGA_PGOOD B 1V8_AON_EN
Y
4 3 12 1 2 220P_0402_50V8J 1
DGPU_PWR_EN 2 ON1 CT1

CG7100
<18,58> DGPU_PWR_EN A
G UG46 +5VS 4 11
74LVC1G32GW_TSSOP5 VBIAS GND CG7097

3
1V8_MAIN_ENR 5 10 1 2 220P_0402_50V8J 2
ON2 CT2 Near UG12.13
+1V8_AON 6 9
VIN2 VOUT2 +1V8_MAIN
1 7 8
VIN2 VOUT2

10U_0603_6.3V6M
CG7103

22U_0603_4V_M

10U_0402_6.3V6M

0.1U_0402_10V7K
0.1U_0402_16V7K 15 1
GPAD

CG7098
@ 1 1
2

CG7104

CG7101

CG7096
AOZ1331_SON14_2X3
<34> 1V8_AON_EN 2
Near UG12.8

2
2 2
Near UG12.1
@
1V8_MAIN_ENP 1 2
<32> 1V8_MAIN_ENP
0_0402_5%
RG1556
Near UG12.6 Near UG12.4
C 1 2 C
<30> 1V8_MAIN_EN
0_0402_5%
RG1557

+1V8_MAIN +1V8_AON +1V8_MAIN +3VS

NV_3V3 +3V3_SYS

UG36
1 1
VIN1
1

1
@ CG478 1 2
RG1517 RG515 CG322 VIN2
0.1U_0201_6.3V6K
10K_0402_5% 10K_0402_5% 1U_0402_6.3V6K 7 6
2 VIN thermal VOUT
5

@
RG545 2 3
+5VALW 1 1
VCC

VBIAS
2

2
DGPU_PWR_EN 1 2.2K_0201_1% CG323 CG385
IN B 4 1 2 3V3_SYS_EN 4 5 0.1U_0402_16V7K 10U_0402_6.3V6M
1V8_MAIN_EN 1 2 2 OUT Y ON GND
GND

IN A 2 2
1 1
RG1544 UG26 CG240 CG384
NL17SZ08DFT2G_SC70-5 0.1U_0402_16V7K 0.1U_0402_10V7K AOZ1334DI-01_DFN8-7_3X3
1
3
0.047U_0201_10V6K
CD402

10K_0402_5% @
2 2

2 2/12
B B

<34> 3V3_SYS_EN
2/12

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/08/07 Deciphered Date 2019/08/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P037-DGPU_DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 37 of 109

5 4 3 2 1
 A B C D E

UPDATE 0914 Vout=3.3V

Imax=1.33A
LCD power control OCP(min):1.8A
Vinafix.com(typ):2A
(max):2.2A
+LCDVDD
1 +3VALW
eDP connector 1

UV4
W=60 mils 6
IN OUT
1 W=60 mils

@EMI@ CV1081
5 2
10P_0402_50V8J

10U_0603_6.3V6M

10U_0603_6.3V6M

47U_0603_6.3V6M

10U_0603_6.3V6M

10P_0402_50V8J

RF@ CV1080

2200P_0402_25V7K
SET GND

@ CV1078
1 1 1 RV683 1 1 JEDP
2 ENVDD_PCH EDP_TXP0_C

1
4 3 1 2 1 CV1 1
CV1075
RF@

CV1076

CV1077

CV1079
0.1U_0201_6.3V6K
DSG FLAG/EN ENVDD_PCH <14> <6> EDP_TXP0_PCH 2 1 CV2 EDP_TXN0_C 2 1
100K_0402_1% 0.1U_0201_6.3V6K
<6> EDP_TXN0_PCH 2
1

2
3
RV684 G517AH1TP1U_TSOT23-6 3

2
2 2 2 RV685 2 2 0.1U_0201_6.3V6K 2 1 CV3 EDP_TXP1_C 4
<6> EDP_TXP1_PCH 2 1 CV4 EDP_TXN1_C 5 4
10.5K_0402_1% 100_0402_5% 0.1U_0201_6.3V6K
<6> EDP_TXN1_PCH 6 5
0.1U_0201_6.3V6K 2 1 CV8 EDP_TXP2_C 7 6
<6> EDP_TXP2_PCH 7
2

0.1U_0201_6.3V6K 2 1 CV6 EDP_TXN2_C 8

<6> EDP_TXN2_PCH 9 8
0.1U_0201_6.3V6K 2 1 CV7 EDP_TXP3_C 10 9
<6> EDP_TXP3_PCH 2 1 CV11 EDP_TXN3_C 11 10
0.1U_0201_6.3V6K
<6> EDP_TXN3_PCH 12 11
0.1U_0201_6.3V6K 2 1 CV12 EDP_AUXP_C 13 12
<6> EDP_AUXP_PCH 2 1 CV13 EDP_AUXN_C 14 13
0.1U_0201_6.3V6K
<6> EDP_AUXN_PCH 15 14
16 15
USB20_N7_R 17 16
USB20_P7_R 18 17
19 18
20 19
2 1 <14> EDP_HPD_CPU DISP_OFF# 21 20
<58> BKOFF EDP_PWM 21

1
22
EDP_LCD_TEST 22
LCD backlight power control
DV1 RV1 23
RB751V-40_SOD323-2 10K_0201_5% 24 23
25 24
2 <73> MIC_DATA 26 25 2
<73> MIC_CLK 26

2
27
+19VB ALIEN_LED_R_DRV# 28 27
+INV_PWR_SRC <63> ALIEN_LED_R_DRV# ALIEN_LED_G_DRV# 29 28
<63> ALIEN_LED_G_DRV# ALIEN_LED_B_DRV# 30 29
<63> ALIEN_LED_B_DRV# 31 30
31

1
+LCDVDD 100mA 32
6 W=60 mils RV679
+5VS
+3VS_CAMERA
0.5A 33 32
33
5 34

10U_0603_6.3V6M
W=60 mils
0_0402_5%
2 35 34

0.1U_0402_10V7K
W=60 mils
@EMI@ +LCDVDD
4 1 36 35
S

1 1 36

2
37

CV17

CV18
1 37
38
0.47U_0402_50V7K
CV15

100K_0402_5%
RV9

W=60 mils
CV14
38
1

0.1U_0603_25V7K FV4 39
G

1 2 2 +INV_PWR_LCD 39

1
QV1 CV1071 1 2 40
+INV_PWR_SRC 40
3

SI3457CDV-T1-GE3_TSOP6 2 10P_0402_50V8J

1
@RF@ 1.5A_24V_SMD1812P150TF-24CV375 41
GND

2
2 10P_0402_50V8J 42
GND
2

1.5A @RF@ 43
GND

2
0928 EE Change 44

1/23 ADD 0.47U for Inrush current

PWR_SRC_ON Place close to JEDP GND
ACES_50473-0400M-P01
1

CONN@
RV12
100K_0402_5%

0412 Change
2

D
1

2 QV2
3 <58> EN_INVPWR 3
G 2N7002W-T/R7_SOT323-3
S
3

RV681
0_0402_5%
1 2 EDP_PWM
CAMERA POWER UPDATE 0914
<14> BIA_PWM_PCH
+3VS_CAMERA
RV682
LV2
EMI@ 0_0402_5%
4 3 USB20_P7_R 1 2 EDP_LCD_TEST
<17> USB20_P7 4 3 <17> PCH_LCD_TEST
@
UV1
1 2 USB20_N7_R
<17> USB20_N7 1 2 3
LCDTESTEC@ 1
RD2541 2 0_0201_5% OUT
DLM0NSN900HY2D_4P <58> EC_LCD_TEST 1@
1 CV7160 CV7161
+3VS IN
3

0.1U_0402_16V4Z 4.7U_0402_6.3V6M
DV4 2 2
3

GND 2
AZC199-02SPR7G_SOT23-3
@ESD@
1

SA000080300
4 4
1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P038-eDP/Camera/AW head LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 38 of 109

A B C D E
 A B C D E

Vinafix.com
+5VS +3VS

9/27 change
1 1
JDP
1
CV23 1

2.2K_0201_5%

2.2K_0201_5%
GPU_DP_HPD_R GND

1
0.1U_0201_6.3V6K 2
CV26 1 2 0.1U_0201_6.3V6K GPU_DP_P0_C 3 HPD

RV671

RV672
RV16
2 <28> GPU_DP_P0 DP_CBL_DET 4 LANE0_P
100K_0201_5% <30> DP_CBL_DET CONFIG1
CV27 1 2 0.1U_0201_6.3V6K GPU_DP_N0_C 5
<28> GPU_DP_N0 1 2 5.1M_0402_5% DISP_CEC 6 LANE0_N
UV3 RV18
CONFIG2

2
16 7
Vcc 4 DISP_CLK_AUXP_CONN 8 GND
GPU_DP_AUXP_R 0.1U_0201_6.3V6K 2 1 CV24 GPU_DP_AUXP_C 2 1A 7 DISP_DAT_AUXN_CONN CV28 1 2 0.1U_0201_6.3V6K GPU_DP_P1_C 9 GND
GPU_DP_AUXP 3 1B1 2A 9 <28> GPU_DP_P1 1 2 GPU_DP_P3_C 10 LANE1_P
CV29 0.1U_0201_6.3V6K
GPU_DP_AUXN_R 0.1U_0201_6.3V6K 2 1 CV25 GPU_DP_AUXN_C 5 1B2 3A 12 <28> GPU_DP_P3 1 2 GPU_DP_N1_C 11 LANE3_P
CV30 0.1U_0201_6.3V6K
GPU_DP_AUXN 2B1 4A <28> GPU_DP_N1 GPU_DP_N3_C LANE1_N

2
6 CV31 1 2 0.1U_0201_6.3V6K 12
11 2B2 15 <28> GPU_DP_N3 13 LANE3_N
RV15
10 3B1 OE# 1 DP_CBL_DET 14 GND
3B2 S 100K_0201_5% GND
14 CV32 1 2 0.1U_0201_6.3V6K GPU_DP_P2_C 15
4B1 <28> GPU_DP_P2 DISP_CLK_AUXP_CONN LANE2_P

1
13 8 16
4B2 GND AUX_CH_P

1
RV17 CV33 1 2 0.1U_0201_6.3V6K GPU_DP_N2_C 17 21
<28> GPU_DP_N2 DISP_DAT_AUXN_CONN 18 LANE2_N GND1 22
SN74CBT3257CPWR_TSSOP16 1M_0201_1%
19 AUX_CH_N GND2 23
20 GND GND3 24
DP_PWR GND4

2
+3VS +3VS_DP
ACON_MAR2A-2061801

+5VS 1 2

10U_0402_6.3V6M

0.1U_0201_6.3V6K
FV2

1
1.1A_6V_SPR-P110 1 1

CV34

CV35
RX39 @
10K_0402_5%
2 2
2 2

2
D

1
QV3 2
NVVDD_PGOOD <27,30,95,99>
2N7002W-T/R7_SOT323-3 G
S

3
UX3
5 1
IN OUT
2
GND
1 2 4 3 1 2
+1V8_MAIN EN OC +3VS_DP
GPU_DP_AUXP RX3 SY6288C20AAC_SOT23-5 RX9
10K_0201_5% 10K_0201_5% 0412 Change
GPU_DP_AUXN @
+3VS

QX2
S TR MMST3904-7-F NPN SOT323-3

1
C
+1V8_AON 2 1 2 GPU_DP_HPD_R
B
E RX2

3
150K_0402_5% 1
<18> DP_HPD_PCH

1
RX5 CX1

1
10K_0402_5% +1.8VALW 0.1U_0402_16V7K
3 CV20 2 3
1 2 RX4

2
10K_0402_5%
<30> GPU_DP_HPD#
0.1U_0402_16V7K

2
GPU_DP_AUXP_R

5
1 2
<28> GPU_DP_AUXP
RV619 0_0402_5% QV97B

VCC
DMN53D0LDW-7 2N SOT363-6 1
5 4 IN B
OUT Y 2

GND
1 2 GPU_DP_AUXN_R IN A DGPU_PEX_RST# <27,30,40>
<28> GPU_DP_AUXN

4
RV618 0_0402_5%
UX1

3
NL17SZ08DFT2G_SC70-5
1

RV664 RV665
100K_0402_5% 100K_0402_5%
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P039-Mini DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 39 of 109

A B C D E
 5 4 3 2 1

1 EMI@ 2 HDMI_L_CLKN 1 2 HDMI_CLKN

RV641 5.6_0402_1%
LV3 @EMI@ 6.04 +-1% 0402
HDMI_C_CLKN

2
CV1057 2 1 0.1U_0201_6.3V6K 1 2 RV673

Vinafix.com
<28> GPU_HDMI_CLKN
RV500
150_0402_1%
CV1058 2 1 0.1U_0201_6.3V6K HDMI_C_CLKP 4 3 +5VS +HDMI_5V_OUT
<28> GPU_HDMI_CLKP @EMI@
6.04 +-1% 0402

1
D HCM1012GH900BP_4P RV674 FV3 D
1 EMI@ 2 HDMI_L_CLKP 1 2 HDMI_CLKP 1 2 +3V3_SYS
RV640 5.6_0402_1%

10U_0603_6.3V6M~D

0.1U_0201_6.3V6K
1.1A_6V_SPR-P110
HDMI_L_TX_N0 HDMI_TX_N0 1 1

1
1 EMI@ 2 1 2

CV1068

CV1069
@
RV643 5.6_0402_1% RV655
LV4 @EMI@ 6.04 +-1% 0402 10K_0402_5%
HDMI_C_TX_N0 2 2

2
CV1060 2 1 0.1U_0201_6.3V6K 1 2 RV27
<28> GPU_HDMI_TX_N0
RV501

2
150_0402_1%
CV1059 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P0 4 3
<28> GPU_HDMI_TX_P0 @EMI@
6.04 +-1% 0402

1
HCM1012GH900BP_4P RV28
1 EMI@ 2 HDMI_L_TX_P0 1 2 HDMI_TX_P0
RV646 5.6_0402_1%
JHDMI
1 EMI@ 2 HDMI_L_TX_N1 1 2 HDMI_TX_N1
RV642 5.6_0402_1% HDMI_TX_P2 1
LV5 @EMI@ 6.04 +-1% 0402 2 D2+
HDMI_C_TX_N1 HDMI_TX_N2 D2_Shield

2
CV1062 2 1 0.1U_0201_6.3V6K 1 2 RV29 3
<28> GPU_HDMI_TX_N1 HDMI_TX_P1 4 D2-
RV502
5 D1+
150_0402_1% D1_Shield
CV1061 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P1 4 3 HDMI_TX_N1 6
<28> GPU_HDMI_TX_P1 @EMI@ HDMI_TX_P0 D1-
6.04 +-1% 0402 7
D0+

1
HCM1012GH900BP_4P RV30 8
1 EMI@ 2 HDMI_L_TX_P1 1 2 HDMI_TX_P1 HDMI_TX_N0 9 D0_Shield
RV639 5.6_0402_1% HDMI_CLKP 10 D0-
11 CK+
HDMI_CLKN 12 CK_Shield
13 CK- 20
1 EMI@ 2 HDMI_L_TX_N2 1 2 HDMI_TX_N2 14 CEC GND 21
RV645 5.6_0402_1% HDMI_CTRL_CLK 15 Reserved GND 22
HDMI_CTRL_DAT SCL GND
HDMI_C_TX_N2
LV6 @EMI@ 6.04 +-1% 0402
11/21 change 16
SDA GND
23

2
CV1064 2 1 0.1U_0201_6.3V6K 1 2 RV33 17
<28> GPU_HDMI_TX_N2 18 DDC/CEC GND
RV503
HDMI_HPD 19 +5V
C 150_0402_1% HPD C
CV1063 2 1 0.1U_0201_6.3V6K HDMI_C_TX_P2 4 3
<28> GPU_HDMI_TX_P2 @EMI@
6.04 +-1% 0402

1
HCM1012GH900BP_4P RV34
1 EMI@ 2 HDMI_L_TX_P2 1 2 HDMI_TX_P2 ACON_HMRF5-AK1L0C
RV638 5.6_0402_1%

HDMI_C_TX_N0 RX31 1 2 499_0201_1% LX1 1 2 PBY100505T-601Y-N_2P

HDMI_C_TX_P0 RX32 1 2 499_0201_1% LX2 1 2 PBY100505T-601Y-N_2P
HDMI_C_CLKN RX33 1 2 499_0201_1% LX3 1 2 PBY100505T-601Y-N_2P
HDMI_C_CLKP RX34 1 2 499_0201_1% LX4 1 2 PBY100505T-601Y-N_2P
QX1 QX1@

HDMI_C_TX_N1 RX35 1 2 499_0201_1% LX5 1 2 PBY100505T-601Y-N_2P

HDMI_C_TX_P1 RX36 1 2 499_0201_1% LX6 1 2 PBY100505T-601Y-N_2P
HDMI_C_TX_N2 RX37 1 2 499_0201_1% LX7 1 2 PBY100505T-601Y-N_2P
HDMI_C_TX_P2 1 2 1 2
RX38 499_0201_1% LX8 PBY100505T-601Y-N_2P BSS138 1N SOT23-3 PANJIT
SB00000PF00

10/26 EVT SB00000QO00 Change SB00000PF00

+3V3_SYS HDMI_Down

1
2 QX1
G LBSS138LT1G_SOT-23-3

1
S

3
RX1
@
100K_0402_5%

B B

2
+HDMI_5V_OUT

DGPU_PEX_RST#
0412 Change
SDM10U45-7_SOD523-2

SDM10U45-7_SOD523-2
2

+1V8_AON
DV12

DV13

+3VS
1

QX3
S TR MMST3904-7-F NPN SOT323-3

1
C
10K_0402_5%

10K_0402_5%

HDMI_HPD
1

+1V8_AON 2 1 2
RV652

B
RV648

3.3K_0402_1%

3.3K_0402_1%

E RX6
RV649

RV653

3
150K_0402_5% 1
<18> HDMI_HPD_PCH

1
2

RX7 CX2
1

1
10K_0402_5% +1.8VALW 0.1U_0402_16V7K
2
5

CV1056
1 2 RX8

2
4 3 HDMI_CTRL_CLK_R 2 1 HDMI_CTRL_CLK 10K_0402_5%
<28> GPU_HDMI_CTRL_CLK <30> GPU_HDMI_HPD#
0.1U_0402_16V7K

2
6

5
QV96B RV651
2

DMN53D0LDW-7 2N SOT363-6 33_0402_1% QV97A

VCC
DMN53D0LDW-7 2N SOT363-6 1
1 6 HDMI_CTRL_DAT_R 2 1 HDMI_CTRL_DAT 2 4 IN B
<28> GPU_HDMI_CTRL_DAT OUT Y 2 DGPU_PEX_RST#

GND
IN A DGPU_PEX_RST# <27,30,39>
QV96A RV650

1
DMN53D0LDW-7 2N SOT363-6 33_0402_1%
UX2

3
NL17SZ08DFT2G_SC70-5

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/05/15 Deciphered Date 2018/02/05 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P040-HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 40 of 109

5 4 3 2 1
 5 4 3 2 1

Vinafix.com
D D

C C

B B

A A

Title
P041-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 41 of 109

5 4 3 2 1
 5 4 3 2 1

@NRTD3@
TBT_RST#_R RT1 1 2 0_0201_5% PCIRST# PCIRST# <15,58,68,73>
CONN@
CLIP1 TBT_PCIE_WAKE_N RT10 1 2 0_0201_5%
TBT_PCIE_WAKE# <58>
CLIP_10P2X7P2_SHIELDING_CASE1
EC26M000600
UT1A
Y23 V23 PCIE_PRX_C_DTX_P17 0.22U_0201_6.3V 2 1 CT14
<14> PCIE_PTX_C_DRX_P17 Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_PRX_C_DTX_N17 2 1 CT16 PCIE_PRX_DTX_P17 <14>
0.22U_0201_6.3V
<14> PCIE_PTX_C_DRX_N17 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_DTX_N17 <14>
T23 P23 PCIE_PRX_C_DTX_P18 0.22U_0201_6.3V 2 1 CT12

PCIe GEN3
<14> PCIE_PTX_C_DRX_P18 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_DTX_N18 PCIE_PRX_DTX_P18 <14>

Vinafix.com
T22 0.22U_0201_6.3V 2 1 CT2
<14> PCIE_PTX_C_DRX_N18 PCIE_RX1_N PCIE_TX1_N PCIE_PRX_DTX_N18 <14>

PCIE TX <14> PCIE_PTX_C_DRX_P19

M23
M22 PCIE_RX2_P PCIE_TX2_P
K23 PCIE_PRX_C_DTX_P19
K22 PCIE_PRX_C_DTX_N19
0.22U_0201_6.3V
0.22U_0201_6.3V
2
2
1 CT109
1 CT108 PCIE_PRX_DTX_P19 <14>
<14> PCIE_PTX_C_DRX_N19 PCIE_RX2_N PCIE_TX2_N PCIE_PRX_DTX_N19 <14>
D PCIE_PRX_C_DTX_P20 D
H23 F23 0.22U_0201_6.3V 2 1 CT111
<14> PCIE_PTX_C_DRX_P20 H22 PCIE_RX3_P PCIE_TX3_P F22 PCIE_PRX_C_DTX_N20 2 1 CT110 PCIE_PRX_DTX_P20 <14>
0.22U_0201_6.3V
<14> PCIE_PTX_C_DRX_N20 PCIE_RX3_N PCIE_TX3_N PCIE_PRX_DTX_N20 <14>
CLK_PCIE_P3 V19 L4 TBT_RST#_R +3VALW
<15> CLK_PCIE_P3 CLK_PCIE_N3 PCIE_REFCLK_100_IN_P PERST_N
PCIE CLK
T19
<15> CLK_PCIE_N3 2 1 CLKREQ_PCIE#3_R AC5 PCIE_REFCLK_100_IN_N N16 PCIE_RBIAS 1 2 3.01K_0201_1%
RT3
<15> CLKREQ_PCIE#3 PCIE_CLKREQ_N PCIE_RBIAS
RT2 0_0201_5%
CT6 1 2 0.1U_0201_6.3V6K CPU_DP1_P0_C AB7 R2
<6> CPU_DP1_P0 CPU_DP1_N0_C DPSNK0_ML0_P DPSRC_ML0_P 1 RTD3@
<6> CPU_DP1_N0 CT7 1 2 0.1U_0201_6.3V6K AC7 R1 CT5361
DPSNK0_ML0_N DPSRC_ML0_N 0.1U_0402_10V6K
CT8 1 2 0.1U_0201_6.3V6K CPU_DP1_P1_C AB9 N2
<6> CPU_DP1_P1 CPU_DP1_N1_C DPSNK0_ML1_P DPSRC_ML1_P 2
CT9 1 2 0.1U_0201_6.3V6K AC9 N1

SOURCE PORT 0
<6> CPU_DP1_N1 DPSNK0_ML1_N DPSRC_ML1_N

SINK PORT 0
CPU_DP1_P2_C

5
<6> CPU_DP1_P2 CT10 1 2 0.1U_0201_6.3V6K AB11 L2
CT23 1 2 0.1U_0201_6.3V6K CPU_DP1_N2_C AC11 DPSNK0_ML2_P DPSRC_ML2_P L1
<6> CPU_DP1_N2

VCC
DPSNK0_ML2_N DPSRC_ML2_N
CPU DDI1
1 PCIRST#
CT11 1 2 0.1U_0201_6.3V6K CPU_DP1_P3_C AB13 J2 TBT_RST#_R 4 IN B
<6> CPU_DP1_P3 CPU_DP1_N3_C DPSNK0_ML3_P DPSRC_ML3_P OUT Y
CT24 1 2 0.1U_0201_6.3V6K AC13 J1 2TBT_RTD3_RST#
<6> CPU_DP1_N3 TBT_RTD3_RST# <14>

GND
DPSNK0_ML3_N DPSRC_ML3_N IN A
CPU_DP1_AUXP_C

1
CT25 1 2 0.1U_0201_6.3V6K Y11 W19 @RTD3@
+3VALW_TBT <6> CPU_DP1_AUXP CPU_DP1_AUXN_C DPSNK0_AUX_P DPSRC_AUX_P
CT26 1 2 0.1U_0201_6.3V6K W11 Y19 RT693
<6> CPU_DP1_AUXN DPSNK0_AUX_N DPSRC_AUX_N

3
100K_0402_5% UT3 RTD3@
CPU_DP1_HPD AA2 G1 TBT_SRC_HPD RT4 1 2 1M_0201_1% NL17SZ08DFT2G_SC70-5
CPU_DP1_AUXN_C <14> CPU_DP1_HPD DPSNK0_HPD DPSRC_HPD
RT76 1 @ 2 100K_0201_5%

2
CPU_DP2_AUXN_C RT77 1 @ 2 100K_0201_5% CPU_DDC1CLK_T Y5 N6 DPSRC_RBIAS RT5 1 2 14K_0402_1%
CPU_DP1_AUXP_C RT78 1 @ 2 100K_0201_5% CPU_DDC1DATA_T R4 DPSNK0_DDC_CLK DPSRC_RBIAS
CPU_DP2_AUXP_C RT79 1 @ 2 100K_0201_5% DPSNK0_DDC_DATA U1
CPU_DP2_P0_C GPIO_0 TBT_I2C_SDA <50>
<6> CPU_DP2_P0 CT27 1 2 0.1U_0201_6.3V6K AB15 U2
TBT_I2C_SCL <50>
CT28 1 2 0.1U_0201_6.3V6K CPU_DP2_N0_C AC15 DPSNK1_ML0_P GPIO_1 V1 TBT_EE_WP_N

LC GPIO
<6> CPU_DP2_N0 DPSNK1_ML0_N GPIO_2 TBT_TMU_CLK_OUT
V2 @ T2
CT29 1 2 0.1U_0201_6.3V6K CPU_DP2_P1_C AB17 GPIO_3 W1 TBT_PCIE_WAKE_N
+3.3V_LC <6> CPU_DP2_P1 CPU_DP2_N1_C DPSNK1_ML1_P GPIO_4 TBT_CIO_PLUG_EVENT# TBT_PCIE_WAKE_N <17>
<6> CPU_DP2_N1 CT30 1 2 0.1U_0201_6.3V6K AC17 W2 TBT_CIO_PLUG_EVENT# <18>
DPSNK1_ML1_N GPIO_5 Y1 RT724 2 1 100K_0201_5%
CT31 1 2 0.1U_0201_6.3V6K CPU_DP2_P2_C AB19 GPIO_6 Y2 RT725 2 1 100K_0201_5% 0918 intel CHANGE

SINK PORT 1
<6> CPU_DP2_P2 CPU_DP2_N2_C DPSNK1_ML2_P GPIO_7 TBT_SRC_CFG1
<6> CPU_DP2_N2 CT32 1 2 0.1U_0201_6.3V6K AC19 AA1 RT11 1 2 1M_0201_1%
C DPSNK1_ML2_N GPIO_8 TBTA_I2C_INT C

CPU DDI2
J4 TBTA_I2C_INT <50>
CT33 1 2 0.1U_0201_6.3V6K CPU_DP2_P3_C AB21 POC_GPIO_0 E2 TBTB_I2C_INT
<6> CPU_DP2_P3

POC GPIO
CPU_DP2_N3_C DPSNK1_ML3_P POC_GPIO_1 RTD3_USB_PWR_EN_R
1

CT34 1 2 0.1U_0201_6.3V6K AC21 D4 1 2

10K_0201_5%

10K_0201_5%

10K_0201_5%

10K_0201_5%

RT6 RT7 RT8 RT9 <6> CPU_DP2_N3 RT12 0_0201_5% RTD3_USB_PWR_EN <18>
DPSNK1_ML3_N POC_GPIO_2 H4 TBT_FORCE_PWR_R RT13 1 2 0_0201_5%
CPU_DP2_AUXP_C POC_GPIO_3 TBT_FORCE_PWR <15>
CT35 1 2 0.1U_0201_6.3V6K Y12 F2 BATLOW# RT14 1 @ 2 0_0201_5% PCH_BATLOW# <16>
<6> CPU_DP2_AUXP CPU_DP2_AUXN_C DPSNK1_AUX_P POC_GPIO_4 SUSP#_R
CT36 1 2 0.1U_0201_6.3V6K W12 D2 RT15 1 2 0_0201_5% SUSP# <58,68,73,78,85,88>
<6> CPU_DP2_AUXN DPSNK1_AUX_N POC_GPIO_5 RTD3_CIO_PWR_EN_R
F1 RT16 1 2 0_0201_5% RTD3_CIO_PWR_EN <15>
CPU_DP2_HPD POC_GPIO_6
2

Y6
TBT_TDI <14> CPU_DP2_HPD DPSNK1_HPD TBT_TEST_EN
E1 RT17 1 2 100_0201_5%
TBT_TMS CPU_DDC2CLK_T Y8 TEST_EN

Misc
TBT_TCK CPU_DDC2DATA_T N4 DPSNK1_DDC_CLK AB5 TBT_TEST_PWG RT18 1 2 100_0201_5%
TBT_TDO DPSNK1_DDC_DATA TEST_PWR_GOOD YT2
2 1 DPSNK_RBIAS Y18 F4 TBT_RESET_N 25MHZ_20PF_XRCGB25M000F2P18R0
DPSNK_RBIAS RESET_N TBT_RESET_N <50>
RT19 14K_0402_1% RT23 1 2 0_0201_5%
TBT_TDI TBT_RESET_N_EC <59>
Y4 D22 TBT_XTAL_25_IN RT116 1 2 0_0402_5% EMI@ 1 3
TBT_TMS V4 TDI XTAL_25_IN D23 TBT_XTAL_25_OUT RT117 1 2 0_0402_5% EMI@ 1 3
TBT_TCK TMS XTAL_25_OUT 1 NC NC 1
0918 intel CHANGE +3VALW_TBT T4 CT37 CT38
TBT_TDO W4 TCK AB3 TBT_EE_DI
TBT_RST#_R TDO MISC EE_DI TBT_EE_DO
27P_0201_25V
2 4
27P_0201_25V
RT723 2 1 10K_0201_5%
RTD3@ AC4
TBTA_LSTX RT21 2 @ 1 10K_0201_5% 2 1 TBT_RBIAS H6 EE_DO AC3 TBT_EE_CS_N 2 2
CLKREQ_PCIE#3_R RT20 2 1 10K_0201_5% RT25 4.75K_0402_0.5% TBT_RSENSE J6 RBIAS EE_CS_N AB4 TBT_EE_CLK_R 1 2 TBT_EE_CLK
RSENSE EE_CLK
TBT_RTD3_RST# RT695 2@RTD3@ 1 10K_0201_5% A15 B7 RT52 EMI@
<50> TBT_A_TRX_DTX_P1 PA_RX1_P PB_RX1_P 1
B15 A7 15_0402_5% CH247
<50> TBT_A_TRX_DTX_N1 PA_RX1_N PB_RX1_N 10P_0402_50V8J @EMI@
CT39 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P1 A17 A9
CPU_DDC1CLK_T RT127 1 <50> TBT_A_TTX_C_DRX_P1 TBT_A_TTX_DRX_N1 PA_TX1_P PB_TX1_P 2
2 100K_0201_5% CT40 1 2 0.22U_0201_6.3V B17 B9
CPU_DDC1DATA_TRT126 1 <50> TBT_A_TTX_C_DRX_N1 PA_TX1_N PB_TX1_N
2 100K_0201_5%
CPU_DDC2CLK_T RT129 1 2 100K_0201_5% CT41 1 2 0.22U_0201_6.3V TBT_A_TTX_DRX_P0 A19 A11
CPU_DDC2DATA_TRT128 1 <50> TBT_A_TTX_C_DRX_P0 TBT_A_TTX_DRX_N0 PA_TX0_P PB_TX0_P
2 100K_0201_5% CT42 1 2 0.22U_0201_6.3V B19 B11
<50> TBT_A_TTX_C_DRX_N0 PA_TX0_N PB_TX0_N

TBT PORTS
<50> TBT_A_TRX_DTX_P0 B21 A13 0918 EMI CHANGE
A21 PA_RX0_P PB_RX0_P B13

Port A

PORT B
<50> TBT_A_TRX_DTX_N0 PA_RX0_N PB_RX0_N
CPU_DP1_HPD RT38 1 2 100K_0201_5% CT43 1 2 0.1U_0201_6.3V6K TBT_A_AUX_P Y15 Y16
CPU_DP2_HPD <50> TBT_A_AUX_P_C TBT_A_AUX_N PA_DPSRC_AUX_P PB_DPSRC_AUX_P
B RT39 1 2 100K_0201_5% <50> TBT_A_AUX_N_C CT44 1 2 0.1U_0201_6.3V6K W15 W16 B
TBTA_LSTX RT40 1 2 1M_0201_1% PA_DPSRC_AUX_N PB_DPSRC_AUX_N +3.3V_TBT_SX
TBTA_HPD RT41 1 2 100K_0201_5% E20 E19
TBTA_LSRX <50> TBT_A_USB20_P PA_USB2_D_P PB_USB2_D_P TBT_I2C_SDA
RT42 1 2 1M_0201_1% D20 D19 RT26 2 1 3.3K_0201_5%
<50> TBT_A_USB20_N PA_USB2_D_N PB_USB2_D_N TBT_I2C_SCL RT27 2 1 3.3K_0201_5%
TBTA_LSTX A5 B4 NC_B4 TBT_PCIE_WAKE_N RT28 2 1 10K_0201_5%
<50> TBTA_LSTX TBTA_LSRX PA_LS_G1 PB_LS_G1 NC_B5 TBT_CIO_PLUG_EVENT#

POC
A4 B5 2 1

POC
<50> TBTA_LSRX RT29 10K_0201_5%
TBTA_HPD M4 PA_LS_G2 PB_LS_G2 G2 NC_G2 SUSP#_R RT30 2 @ 1 10K_0201_5%
<50> TBTA_HPD PA_LS_G3 PB_LS_G3 BATLOW# RT31 2 1 10K_0201_5%
2 1 PA_USB2_RBIAS H19 F19 PB_USB2_RBIAS 1 2 TBTA_I2C_INT RT32 2 1 10K_0201_5%
RT43 499_0201_1% PA_USB2_RBIAS PB_USB2_RBIAS RT44 499_0201_1% TBTB_I2C_INT RT33 2 1 10K_0201_5%
AC23 D6 RTD3_CIO_PWR_EN_R RT36 2 @ 1 10K_0201_5%
AB23 THERMDA MONDC_SVR NC_B4 RT86 2 @ 1 10K_0201_5%
THERMDA A23 TBT_FORCE_PWR_R RT94 2 @ 1 10K_0201_5%
V18 ATEST_P B23
PCIE_ATEST ATEST_N

1
AC1 DEBUG E18 RT727
TEST_EDM USB2_ATEST
100K_0201_5%
+3.3V_FLASH L15 W13
N15 FUSE_VQPS_64 MONDC_DPSNK_0 0918 intel CHANGE
FUSE_VQPS_128 Close to UT2

2
W18
C23 MONDC_DPSNK_1 TBT_EE_DI RT98 1 2 0_0201_5%
1 MONDC_CIO_0 TBT_EE_DO PD_EE_DI <50>
CT45 C22 AB2 RT99 1 2 0_0201_5%
MONDC_CIO_1 MONDC_DPSRC TBT_EE_CS_N PD_EE_DO <50>
0.1U_0201_6.3V6K RT100 1 2 0_0201_5%
TBT_EE_CLK PD_EE_CS_N <50>
ALPINE-RIDGE_BGA337 RT101 1 2 0_0201_5% PD_EE_CLK <50>
2
UT2
RT50 1 2 2.2K_0201_5% TBT_EE_CS_N 1 8
RT49 1 2 2.2K_0201_5% TBT_EE_DO 2 CS# VCC 7 TBT_HOLD_N 2 1
RT48 1 2 3.3K_0201_5% TBT_EE_WP_N 3 DO(IO1) HOLD#(IO3) 6 TBT_EE_CLK
4 WP#(IO2) CLK 5 TBT_EE_DI RT51
GND DI(IO0) 3.3K_0201_5% TBT_TMU_CLK_OUT RT34 1 2 100K_0201_5%
W25Q80DVSSIG_SO8 TBT_FORCE_PWR_R RT35 1 2 100K_0201_5%
RTD3_USB_PWR_EN_R RT37 1 2 100K_0201_5%
TBT_RESET_N RT80 1 @ 2 100K_0201_5%
A A
NC_B4 RT45 1 2 100K_0201_5%
NC_B5 RT46 1 2 100K_0201_5%
NC_G2 RT47 1 2 100K_0201_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P042-Thunderbolt(1/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 42 of 109
5 4 3 2 1
 5 4 3 2 1

+3VALW_TBT
+3VALW_TBT_S5 +3.3V_TBT_SX +3VALW_TBT_S5 +3VALW_TBT +3.3V_LC +3.3V_TBT_SX
1 2

1U_0201_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
1 2 +3VALW_TBT LT4
1 1 1

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0.1U_0201_6.3V6K

1U_0201_6.3V6M

CT153

CT154

CT155
RT97 0_0402_5% 1UH_LQM18PN1R0MFHD_20%
+3VS

@RF@ CH242
@ 1 1
1 2 CT46 CT47
2 2 2

1U_0201_6.3V6M

1U_0201_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10U_0402_6.3V6M

10P_0402_50V8J
RT95 0_0805_5%
D 2 2 1 1 1 1 1 1 1 D
1 2

CT48

CT49

CT50

CT51

CT52

CT53
RT729 0_0805_5%

R13
+0.9V_DP 2/21 change for S3 Consumption

R6

H9
F8
UT1B 2 2 2 2 2 2 2
L8 A2

VCC3P3_SX

VCC3P3A
VCC3P3_LC

VCC3P3_S0
L11 VCC0P9_DP VCC3P3_SVR A3

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
L12 VCC0P9_DP VCC3P3_SVR B3
1 1 1 1 1 1 1 VCC0P9_DP VCC3P3_SVR
CT54 CT57 CT58 CT59 CT60 CT61 CT62 M8
T11 VCC0P9_DP
T12 VCC0P9_DP L9 +0.9V_SVR
2 2 2 2 2 2 2 L6 VCC0P9_DP VCC0P9_SVR M9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M6 VCC0P9_ANA_DPSRC VCC0P9_SVR E12
VCC0P9_ANA_DPSRC VCC0P9_SVR_ANA 1 1 1 1 1 1 1
V11 E13 CT63 CT64 CT65 CT66 CT67 CT68 CT69
V12 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F11
+0.9V_PCIE V13 VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F12
VCC0P9_ANA_DPSNK VCC0P9_SVR_ANA F13 2 2 2 2 2 2 2
M13 VCC0P9_SVR_ANA F15
M15 VCC0P9_PCIE VCC0P9_SVR_ANA J9

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
M16 VCC0P9_PCIE VCC0P9_SVR_SENSE
1 1 1 1 VCC0P9_PCIE
CT55 CT70 CT71 CT72 L19 LT1
N19 VCC0P9_ANA_PCIE_1 C1 TBT_SVR_IND 1 2
L18 VCC0P9_ANA_PCIE_1 SVR_IND C2

47U_0603_6.3V6M

47U_0603_6.3V6M

47U_0603_6.3V6M
0.6UH_MND-04ABIR60M-XGL_20%
2 2 2 2 M18 VCC0P9_ANA_PCIE_2 SVR_IND D1
VCC0P9_ANA_PCIE_2 SVR_IND 1 1 1
+0.9V_USB N18 CT73 CT74 CT75

VCC
VCC0P9_ANA_PCIE_2
R15 A1
R16 VCC0P9_USB SVR_VSS B1 2 2 2
1U_0201_6.3V6M

1U_0201_6.3V6M

+0.9V_CIO VCC0P9_USB SVR_VSS B2

1 1 SVR_VSS
CT77 CT56 R8
R9 VCC0P9_CIO
R11 VCC0P9_CIO
2 2 R12 VCC0P9_CIO F18 +0.9V_LVR_OUT
1U_0201_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
VCC0P9_CIO VCC0P9_LVR H18

10U_0402_6.3V6M

10U_0402_6.3V6M

1U_0201_6.3V6M

1U_0201_6.3V6M
1 1 1 +3.3V_ANA_PCIE VCC0P9_LVR
CT78 CT79 CT80 L16 J11 1 1 1 1
+3.3V_ANA_USB2 J16 VCC3P3_ANA_PCIE VCC0P9_LVR H11 CT81 CT82 CT83 CT84
C VCC3P3_ANA_USB2 VCC0P9_LVR_SENSE C
2 2 2 A6 V5

10K_0201_5%

1U_0201_6.3V6M

1U_0201_6.3V6M
VSS_ANA VSS_ANA 2 2 2 2

2
1 1 A8 V6
RT200 CT85 CT86 A10 VSS_ANA VSS_ANA V8
A12 VSS_ANA VSS_ANA V9
A14 VSS_ANA VSS_ANA V15
2 2 A16 VSS_ANA VSS_ANA V16
1 A18 VSS_ANA VSS_ANA V20
A20 VSS_ANA VSS_ANA W5
A22 VSS_ANA VSS_ANA W6
B6 VSS_ANA VSS_ANA W8
B8 VSS_ANA VSS_ANA W9
B10 VSS_ANA VSS_ANA W20
B12 VSS_ANA VSS_ANA W22
B14 VSS_ANA VSS_ANA W23
B16 VSS_ANA VSS_ANA Y9
B18 VSS_ANA VSS_ANA Y13
B20 VSS_ANA VSS_ANA Y20
B22 VSS_ANA VSS_ANA AA22
D8 VSS_ANA VSS_ANA AA23
D9 VSS_ANA VSS_ANA AB6
D11 VSS_ANA VSS_ANA AB8
D12 VSS_ANA VSS_ANA AB10
D13 VSS_ANA VSS_ANA AB12
D15 VSS_ANA VSS_ANA AB14
D16 VSS_ANA VSS_ANA AB16

GND
D18 VSS_ANA VSS_ANA AB18
E8 VSS_ANA VSS_ANA AB20
E9 VSS_ANA VSS_ANA AB22
E11 VSS_ANA VSS_ANA AC6
E15 VSS_ANA VSS_ANA AC8
E16 VSS_ANA VSS_ANA AC10
E22 VSS_ANA VSS_ANA AC12
E23 VSS_ANA VSS_ANA AC14
F9 VSS_ANA VSS_ANA AC16
B F16 VSS_ANA VSS_ANA AC18 B
+3VALW VSS_ANA VSS_ANA
F20 AC20
G22 VSS_ANA VSS_ANA AC22
G23 VSS_ANA VSS_ANA D5
H1 VSS_ANA VSS E4
H2 VSS_ANA VSS E5
1 1 VSS_ANA VSS
CT122 CT121 +3VALW_TBT_S5 H12 E6
4.7U_0805_10V4Z 0.1U_0402_16V7K H13 VSS_ANA VSS F5
H15 VSS_ANA VSS F6
2 2 H16 VSS_ANA VSS H5
UT8 H20 VSS_ANA VSS H8
1 J5 VSS_ANA VSS J8
5 OUT J18 VSS_ANA VSS J12
22U_0603_6.3V6M
CT124

IN 1 VSS_ANA VSS
2 J19 J13
4 GND J20 VSS_ANA VSS J15
<59> TBT_S5_OFF# EN 3 1 2 J22 VSS_ANA VSS L13
OCB +3VS 2 VSS_ANA VSS
RT132 J23 M11
10K_0402_5% K1 VSS_ANA VSS M12
SY6288D20AAC_SOT23-5 K2 VSS_ANA VSS N8
1 VSS_ANA VSS
CT123 L5 N9
0.1U_0402_16V7K L20 VSS_ANA VSS N11
L22 VSS_ANA VSS N12
2 L23 VSS_ANA VSS N13
M1 VSS_ANA VSS T6
M2 VSS_ANA VSS T8
M5 VSS_ANA VSS T9
M19 VSS_ANA VSS T13
M20 VSS_ANA VSS T15
N5 VSS_ANA VSS T16
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA
VSS_ANA

N20 VSS_ANA VSS T18

N22 VSS_ANA VSS AB1
N23 VSS_ANA VSS AC2
VSS_ANA VSS
ALPINE-RIDGE_BGA337
R5

T20
T1
T2
T5
P1
P2

R18
R19
R20
R22
R23

U22
U23

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2018/03/29 Deciphered Date 2019/03/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P043-Thunderbolt(2/2)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-H351P
Date: Thursday, May 30, 2019 Sheet 43 of 109
5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P044-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 44 of 109

5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P045-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 45 of 109

5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P046-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 46 of 109

5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P047-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 47 of 109

5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P048-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 48 of 109

5 4 3 2 1
 5 4 3 2 1

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D D

C C

B B

A A

Title
P049-Reserve

Size Document Number Rev

A LA-H351P 0.1

Date: Thursday, May 30, 2019 Sheet 49 of 109

5 4 3 2 1
 5 4 3 2 1

DT2 ESD@
TBT_A_TTX_C_DRX_P0 1 2
PESD5V0H1BSF_SOD962-2-2
SC40000AT00
DT3 ESD@
+5VALW +TBTA_VBUS
+3VALW_TBT_S5 +3VALW_PD TBT_A_TTX_C_DRX_N0 1 2

60mil 3A 60mil 3A
PESD5V0H1BSF_SOD962-2-2
+3VALW SC40000AT00
1 2
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10P_0402_50V8J
DT4 ESD@

4.7U_0603_10V6K

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
RT53 0_0402_5% 1 1 1 1 1 TBT_A_TRX_DTX_P0

1
1 2 1 2

CV1074
@RF@
1 CT90 CT157 CT91 CT92 CT93

3
RT728 0_0402_5% CT88 CT106 PESD5V0H1BSF_SOD962-2-2
@ 0.1U_0402_10V6K 1U_0603_25V6K DT1 DT15 SC40000AT00

2
D 2 2 2 2 2 SDM10U45-7_SOD523-2~D PESD24VS2UT_SOT23-3 DT5 ESD@ D

2
2 ESD@
TBT_A_TRX_DTX_N0 1 2

2
PESD5V0H1BSF_SOD962-2-2
TBTA_LDO_BMC

1
SC40000AT00
+1.8VD_TBTA_LDO
Close to UT4
DT6 ESD@
+1.8VA_TBTA_LDO
TBT_A_TTX_C_DRX_P1 1 2
1 1 1
PESD5V0H1BSF_SOD962-2-2
CT98 CT99 CT100 SC40000AT00

2
2.2U_0402_16V6K 4.7U_0603_10V6K 4.7U_0603_10V6K DT7 ESD@
2 2 2 RT22
+3VALW_PD +3.3V_FLASH 0_0201_5% TBT_A_TTX_C_DRX_N1 1 2
@ PESD5V0H1BSF_SOD962-2-2
SC40000AT00

1
+3VALW_TBT_S5 DT8 ESD@
1

Master0:0 ohm
CT101
10U_0402_6.3V6M TBT_A_TRX_DTX_P1 1 2
PD_IRQ# 2 1 10K_0201_5%
Slave1:93.1K ohm
RT107 0.6A PESD5V0H1BSF_SOD962-2-2
2 SC40000AT00

H10

C11
D11
A11
B11

B10

A10
DT9 ESD@

H1

B1

K1

A2

E1

A6
A7
A8
B7

B9

A9
UT4
RT83 1 2 0_0201_5% F1 TBT_A_TRX_DTX_N1 1 2

VIN_3V3

VDDIO

LDO_1V8A

PP_CABLE

PP_5V0
PP_5V0
PP_5V0
PP_5V0

PP_HV
PP_HV
PP_HV
PP_HV

HV_GATE1

HV_GATE2
SENSEP
LDO_1V8D

LDO_BMC

SENSEN
I2C_ADDR PESD5V0H1BSF_SOD962-2-2
RT720 1 2 0_0201_5% TBT_I2C_SDA_R D1 SC40000AT00
<42> TBT_I2C_SDA TBT_I2C_SCL_R I2C_SDA1
<42> TBT_I2C_SCL RT721 1 2 0_0201_5% D2 DT11 ESD@
RT722 1 2 0_0201_5% TBTA_I2C_INT_R C1 I2C_SCL1
<42> TBTA_I2C_INT I2C_IRQ1_N +3.3V_TBT_SX_R +3.3V_TBT_SX TBT_A_CC1 1 2
PESD5V