V.

PRAKASH
Asst. Professor(Sr.), SENSE,
VIT Chennai

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 • Boolean Algebra: Basic definitions, Axiomatic definition of
Boolean Algebra, Basic Theorems and Properties of
Boolean Algebra, Boolean Functions, Canonical and
Standard Forms, Simplification of Boolean functions.
Digital • Gate-Level Minimization: The Map Method (K-map up to
Logic 4 variable), Product of Sums and Sum of Products
Simplification, NAND and NOR Implementation.

• Logic Families: Digital Logic Gates, TTL and CMOS logic

families.

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 3

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 Analog Circuits
Process continuous range of values
Electronic Circuits

During a given day, the temperature does not go from, say, 80 to 81 instantaneously; it changes
over a continuous range of values

Digital Circuits
Process discrete values

Suppose recording temperature reading every hour, sampled values representing the
temperature at discrete points in time (every hour) over a 24-hour period.

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 EXAMPLE CIRCUITS

Analog circuits are usually complex combinations

of op-amps, resistors, caps, and other
foundational electronic components.

Digital circuits make use of components like logic

gates, or more complicated digital ICs

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 DIGITAL SYSTEM - ADVANTAGES

 Easy to design
 Information storage is easy

 Less affected by noise (HIGH or LOW)

 Highly reliable due to error correction codes

 More digital circuitry can be fabricated

 Applications: communications systems, radar, navigation, military
systems, medical instrumentation, industrial process control.
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 DIGITAL SYSTEM

 For digital systems, two level or binary values are the most commonly
used values.

 Binary values are represented by two basic states:

 1 (logic “high”, or H, or “on” or “True”)
 0 (logic “low”, or L, or “off” or “False”)
V(t)
Logic 1

undefine

tities . Logic 0
t

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 Decimal Binary Octal Hex
(Base 10) (Base 2) (Base 8) (Base 16)
00 0000 00 0
01 0001 01 1
02 0010 02 2
03 0011 03 3
04 0100 04 4
05 0101 05 5
06 0110 06 6
07 0111 07 7
08 1000 10 8
09 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
10
15 1111 17 F

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  A logic gate is the basic building block of digital circuits.

 A logic gate is an electronic circuits devices which makes a logical

decision based on the different combination of inputs.

 There are seven logic gates: NOT, AND, OR, NAND, NOR, XOR, XNOR

 Universal Logic gates: NAND, NOR

 A logic gate truth table shows each possible input combination to the
gate with the resultant output
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 NOT GATE

 NOT gate produces an inverted version of the input at its output.

 Output is high when the input is low, output is low when the input is high
 It is also known as an inverter, IC 7404 is a NOT gate IC.
PIN DIAGRAM

SYMBOL TRUTH TABLE

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 AND GATE
 AND gate gives a high output (1) only if all its inputs are high
 Output is low level when any one of the inputs is low
 A dot (.) is used to show the AND operation i.e. A.B
 IC 7408 is the two Inputs AND gate IC. PIN DIAGRAM

SYMBOL TRUTH TABLE

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 OR GATE
 OR gate a high output (1) if one or more of its inputs are high
 A plus (+) is used to show the OR operation.

 IC 7432 is the two Input OR gate IC.

PIN DIAGRAM

SYMBOL TRUTH TABLE

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 NAND GATE
 NAND (NOT+AND) gate is equal to an AND followed by a NOT gate
 Outputs of all NAND gates are high if any of the inputs are low
 The output is low level when both inputs are high
 IC7400 is a two input NAND gate PIN DIAGRAM

SYMBOL TRUTH TABLE

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 NOR GATE
 NOR (NOT+OR) gate is equal to OR gate followed by a NOT gate
 Outputs of all NOR gates are low if any of the inputs are high
 The output is HIGH when all inputs are LOW
 IC 7402 is a two input NOR gate PIN DIAGRAM

SYMBOL TRUTH TABLE

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 XOR GATE
 XOR (Exclusive-OR) gate is a circuit which will give the output is HIGH
only when odd number of is HIGH
 Symbol + is used to represent XOR operation
 IC 7486 is a two input XOR gate
PIN DIAGRAM

SYMBOL TRUTH TABLE

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 XNOR GATE
 XNOR (Exclusive-NOR) ” gate is a combination of the Exclusive-OR gate
and the NOT gate and exact inverse of the output of the XOR gate
 Output is HIGH when odd numbers of inputs are at LOW level
 Symbol (ʘ) is used to represent XOR operation PIN DIAGRAM
 IC 7426 is two input XNOR gate
TRUTH TABLE
SYMBOL

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 TRUTH TABLE OF 3-INPUT LOGIC GATES

A B C AND OR NAND NOR XOR XNOR

0 0 0 0 0 1 1 0 1
0 0 1 0 1 1 0 1 0
0 1 0 0 1 1 0 1 0
0 1 1 0 1 1 0 0 1
1 0 0 0 1 1 0 1 0
1 0 1 0 1 1 0 0 1
1 1 0 0 1 1 0 0 1
1 1 1 1 1 0 0 1 0
All inputs Any one Any one All inputs Odd no. of Odd number
are HIGH input is HIGH input is LOW are LOW HIGH of LOW
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 INTRODUCTION

 It is the mathematics used to express and analyse digital circuits

 Boolean Algebra uses its own set of rules or laws which are used to
define and reduce Boolean expressions

 This will result with fewest literals and thus less gates in final
implementation

 The variables used in Boolean Algebra only have one of two possible
values, a logic “0” and a logic “1”

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 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA
 Axioms are assumption that are valid without proof. For every x ∈ B,
 Axiom 1 (Closure): (a) B is closed with respect to the operator +; (b) B is also
closed with respect to the operator ∙
 Axiom 2 (Identity): (a) B has an identity element with respect to +, designated by
0; (b) B also has an identity element with respect ∙, designated by 1
 Axiom 3 (Commutativity): (a) B is commutative with respect to +; (b) B is also
commutative with respect to ∙
 Axiom 4 (Distributivity): (a) The operator ∙ is distributive over +; (b) similarly, the
operator + is distributive over ∙
 Axiom 5 (Complement Element): For every x ∈ B, there exists an element x′ ∈ B
such that (a) x + x′ = 1 and (b) x ∙ x′ = 0 x′, is called the complement of x
 Axiom 6 (Cardinality): There are at least two elements x, y ∈ B such that x≠y
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 LAWS OF BOOLEAN ALGEBRA

 Commutative Laws: Order of literals does not matter

 Associative Laws: Grouping of literals does not matter

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 LAWS OF BOOLEAN ALGEBRA

 Distributive Law: Permits multiplying or factoring out of an expression

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 BASIC THEOREMS OF BOOLEAN ALGEBRA

 Principles of Duality: One Boolean expression can be obtained from

other by replacing their symbols with their counterparts (i.e)
 0’s by 1’s and 1’s by 0’s
 + by . and . by +
 Variables should be represented as it is

 Examples:
1. Dual of ABC’+A’BC+ABC is (A+B+C’)(A’+B+C)(A+B+C)
2. Dual of XYZ+X’YZ’+Y’Z=1 is (X+Y+Z)(X’+Y+Z’)(Y’+Z)=0

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 BASIC THEOREMS OF BOOLEAN ALGEBRA

 DeMorgan’s Theorem: Help to simplify digital circuits using NOR,NAND

 The complement of a product of variables is equal to the sum of the
complements of the variables (A.B)’ = (A’+B’)
 The complement of a sum of variables is equal to the product of the
complements of the variables (A+B)’ = (A’.B’)

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 BASIC THEOREMS OF BOOLEAN ALGEBRA

 Consensus Theorem : Very useful in simplifying Boolean expressions

 Given an expression, AB+A’C+BC then term BC is redundant and can be
eliminated to form the equivalent expression AB+A’C
 The eliminated term is referred to as the consensus term.
 Example: (a).AB+A’C+BC=AB+A’C (b).(A+B).(A'+C).(B+C)=(A+B).(A'+C)
 Proof:
AB+A’C+BC = AB+A’C+(A+A’)(BC)
= AB+A’C+ABC+A’BC
= AB(1+C)+A’C(1+B)
= AB+A’C
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 PROPERTIES OF BOOLEAN ALGEBRA

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 PROPERTIES OF BOOLEAN ALGEBRA

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 MINIMIZATION OF BOOLEAN EXPRESSION

Example:1 (x’+ y) (x+ y)

= x’.x+ x’y+ yx+ y.y
= 0+ x’y+ xy+ y [ x.x’= 0]; [ y. y= y]
= y ( x’+ x+ 1)
= y( 1 ) [ 1+ x = 1 ]
= y. Example:2 xy+ xyz+ xyz’+ x’yz
= xy ( 1+ z+ z’)+ x’yz
= xy ( 1 ) + x’yz [ 1+ x = 1 ]
= xy+ x’yz
= y ( x+ x’z ) [ x+ x’y = x+ y]
= y ( x+ z ).
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 MINIMIZATION OF BOOLEAN EXPRESSION
Example:3 x’yz+ xy’z’+ x’y’z’+ xy’z+ xyz
= yz (x’+x) + xy’z’+ x’y’z’+ xy’z
= yz (1) + y’z’ (x+ x’) + xy’z [ x+ x’= 1]
= yz+ y’z’ (1) + xy’z [ x+ x’= 1]
= yz+ y’z’+ xy’z Example:4 [(xy)’+ x’+ xy]’
= yz+ y’ (z’+ xz) = [ x’+ y’+ x’+ xy]’
= yz+ y’ (z’+ x) [ x’+ xy = x’+ y] = [ x’+ y’+ xy]’ [x’+x’= x’]
= yz+ y’z’+ xy’ = [x’+ y’+ x]’ [x’+xy=x’+y]
= [y’+ 1]’ [x+x’=1]
= [ 1 ]’ [1+x=1]
= 0.
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 MINIMIZATION OF BOOLEAN EXPRESSION - EXERCISES

1. xyz+ xy’z+ xyz’ = x(y+ z)

2. w’xyz’+ xyz’+ xy’z’+ xy’z = xz
3. w’xy’z+ w’xyz+ wxz = xz
4. AB + (AC)' + AB’C (AB + C) = 1
5. x’y’z’+ x’y’z+ x’yz’+ x’yz+ xy’z’ = x’+ y’z’
6. (x+ y) (x’z’+ z) (y’+ xz)’ = x’y

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 BOOLEAN EXPRESSION FOR A LOGIC CIRCUIT

 Algebraic expression with binary variables and Boolean operators

AND, OR and NOT.

 To derive the Boolean expression for a given logic circuit, begin at the
left-most inputs and work toward the final output, writing the expression
for each gate.

 When we evaluate Boolean expressions we must follow a specific order

of operation namely (1) Parenthesis (2) NOT (3) AND (4) OR

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 TRUTH TABLE

 Truth table shows the output for all possible values of the input variables
can be developed.

 The procedure requires that you evaluate the Boolean expression for all
possible combinations of values for the input variables.

 The first step is to list all the possible input variable combinations of 1’s
and 0’s in binary sequence.

 Next apply the inputs to the circuit and find the output, enter it in the
output column of truth table.
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 BOOLEAN EXPRESSION FOR A LOGIC CIRCUIT

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  Standard form: In a standard form we don’t have to compulsorily write
all the literals in all the terms of an expression. Ex.: f = xyz + y + x

 Canonical form: In a canonical form we have to compulsorily write all

the literals in all the terms of an expression. Ex.: f = xyz+x’yz’+xy’z’

 All Boolean expressions, regardless of their form, can be represented

into either of two forms:
 Sum-of-Products Form (SOP)
 Product-of Sums Form (POS)

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  Sum of Products(SOP): The logical sum of two or more logical product
terms is referred to as a sum of products expression.

 It is basically an OR operation on AND operated variables. For

example, Y = A + BC + AB’C or Y = AB’C’ + A’BC + AB’C

 Product of Sums(POS): Similarly, the logical product of two or more

logical sum terms is called a product of sums expression.

 It is an AND operation on OR operated variables. For example,

Y=(A) (B+C) (A+B’+C) or Y= (A+B’+C’)(A′+ B+C) (A+B’+C)
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  A binary variable may appear either in its normal form (x) or in its
complement form (x’).

 Minterm: When two binary variables x and y combined with an AND

operation, there are four possible combinations: x’y’, x’y, xy’ and xy.
Each of these four AND terms is called as ‘minterm’.

 Maxterm: In a similar fashion, when two binary variables x and y

combined with an OR operation, there are four possible combinations:
x+ y, x+ y’, x’+ y and x’+ y’. Each of these four OR terms is called as
‘maxterm’.
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 DERIVING SOP AND POS FROM TRUTH TABLE

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  Canonical Sum of Product Expression: If each term in SOP form contains
all the literals then the SOP is known as Canonical SOP form.

 Example: F (A, B, C) = AB’C+ ABC+ ABC’

 The same can be expressed in a compact form by listing the

corresponding decimal-equivalent codes of the minterms containing a
function value of 1. For example,
F (A,B,C) = Σ (3,5,6)
= m3 + m5 + m6
= A′BC + AB′C + ABC′
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  The canonical sum of products of a logic function can be
obtained by the following procedure
– For all missing variables, apply (x+x’)=1 to the AND terms of the expression
– Multiply all the products and remove the redundant term
– List all the min-terms in forms of the complete set of variables
 Obtain the canonical SOP form of the function, F(A,B,C)=A+BC

Exercise: Y(A,B,C)=AB+BC+AC Ans: ∑m(3,5,6,7)

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  Canonical Product of Sum Expression: If each term in POS form
contains all the literals then the POS is known as Canonical POS form.

 Example: F (A, B, C) = (A + B + C).(A + B′+ C).(A′+ B + C′)

 The same can be expressed by listing the corresponding decimal

equivalent codes of the maxterms containing a function value of 0.

 For example, F(A,B,C)=∏M(0,2,5)

= M0 . M2 . M5
= (A + B + C).(A + B′+ C).(A′+ B + C′)

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  The canonical products of sum of a logic function can be obtained
by the following procedure
– For all missing variables, apply (x.x’)=0 to the OR terms of the expression
– Add all the sum terms and remove the redundant term
– List all the maxterms in forms of the complete set of variables
 Obtain the canonical POS form: F(A,B,C,D)=(A+B’+C) (B’+C+D’)(A+B’+C’+D)
=(A+B’+C+0)(0+B’+C+D’)(A+B’+C’+D)
=(A+B’+C+D’D)(A’A+B’+C+D’)(A+B’+C’+D)
=(A+B’+C+D’) (A+B’+C+D)(A’+B’+C+D’)(A+B’+C+D’)(A+B’+C’+D)
=(0101)(0100) (0110)(1101)= ΠM(4,5,6,13)

Exercise: Y(A,B,C)=(A+B).(B+C).(A+C) Ans: ∏M(0,1,2,4)

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  To convert from canonical SOP to canonical POS,
~ Step-1: Evaluate each product term in the SOP expression. That is, determine the
binary numbers that represent the product terms.
~ Step-2: Determine all of the binary numbers not included in evaluation in Step-1.
~ Step-3: Write the equivalent sum term for each binary number from Step-2 and
express in POS form.

 Convert the given SOP to POS:

SOP= A’B’C’+A’BC’+A’BC+AB’C+ABC=0+2+3+5+7 =S(0,2,3,5,7)
POS=(1)(4)(6) = P(1, 4, 6) =(A+B+C’)(A’+B+C)(A’+B’+C)

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 EXERCISE

 Obtain the canonical Sum of products form of the following function

(i). Y (A, B, C, D) = AB + ACD
(ii). Y (A, B, C) = A + ABC
(iii). F(X, Y, Z) + XY’+XZ+Y

 Obtain the canonical product of sum form of the following function

(i). Y= A. (B+ C+ A)
(ii). Y= (A+B’) . (B+C) . (A+C’)
(iii). F= (X+Z’) . (Y+Z).X

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 INTRODUCTION
 Drawbacks of Boolean algebra based gate minimization,
 Lack of clear rules for each succeeding step
 Difficult to determine whether the simplest expression achieved or not

 In contrast, Karnaugh map (K-map) method provides a straightforward

systematic procedure for simplifying Boolean functions.
 The Karnaugh map is an array of cells in which each cell represents a
binary value of the input variables.
 The number of cells in a Karnaugh map is equal to the total number of
possible input variable combinations.
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 INTRODUCTION
 For “n” variables on a Karnaugh map there are 2n numbers of cells. For
three variables, number of cells is 23= 8, and for four variables, the
number of cells is 24 = 16.

 Each square or cell represents one of the minterm/maxterm.

 It can be drawn directly from either minterm (sum-of-products) or

maxterm (product-of-sums) Boolean expressions.

 K-maps of up to 4 variables are very common to use. Maps of 5 and 6

variables can be made as well, but are more cumbersome to use.
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 WHY K-MAP FOLLOWS GRAY CODE LOGIC?
 In the case of K-Map, we have difference of only 1-bit between
adjacent cells.
 Consider the case of first 2 cells: 00 and 01. In case(SOP) is 1 in both
these cells then it will produce A'B'+A'B.

 Which will give A‘ since B+B'=1. To utilize this concept of B+B'=1 easily
Gray code is used in K-Map.

 When there is a difference of 1-bit between two adjacent cells, it helps

to easily eliminate Redundant literals from the expression and minimize
our function which is the aim of K-Map!
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 GROUPING IN KARNAUGH MAP
 In K-maps, gate minimization is achieved with the help of grouping
adjacent 1’s or 0’s. Grouping is nothing but combining terms in adjacent
cells to form a single term.

 When forming groups of cells, observe the following:

 Every square containing 1 must be considered at least once.
 The number of 1’s in a group must be equal to 2n , i.e. 2,4,8.
 A group must be as large as possible.
 A square containing 1 can be included in as many groups as desired.
 If a square containing 1 cannot be placed in a group, then leave it out to include in
final expression.
 The simplified logic expression from a K-map is not always unique.
 Groupings can be made in different ways.
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 GROUPING IN KARNAUGH MAP
 PAIR: Grouping of two 1’s together and it is represented with three
variables

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 GROUPING IN KARNAUGH MAP
 QUAD: Grouping of four adjacent 1’s and it results two variables

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 GROUPING IN KARNAUGH MAP
 OCTET: If eight adjacent 1’s are combined; and represented with by
one variable.

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 RULES FOR KARNAUGH MAP MINIMIZATION

1. No zeros allowed in SOP grouping and no one’s allowed in POS.

2. No diagonals grouping.
3. Only power of 2, number of cells in each group.
4. Groups should be as large as possible.
5. Every 1’s must be in at least one group.
6. Overlapping allowed.
7. Wrap around allowed.
8. Fewest number of groups possible.
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 RULES FOR KARNAUGH MAP MINIMIZATION
1. Groups may not include any cell containing a zero in SOP

2. Groups may be horizontal or vertical, but not diagonal

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 RULES FOR KARNAUGH MAP MINIMIZATION
4. Each group should be as large as possible.

5. Each cell containing a one must be in at least one group.

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 RULES FOR KARNAUGH MAP MINIMIZATION
6. Groups may overlap.

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 RULES FOR KARNAUGH MAP MINIMIZATION
7. Groups may wrap around the table. The leftmost cell in a row may be grouped with the
rightmost cell and the top cell in a column may be grouped with the bottom cell.

8. There should be as few groups as possible, as long as this does not contradict any of the
previous rules.

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 PROCEDURE FOR K- MAP SOP MINIMIZATION

1) Plot the K-map and place 1’s in those cells corresponding to the 1’s in the sum of product
expression. Place 0’s in the other cells.

2) Check for octets and quads of adjacent 1’s even if it contains some 1’s that have already
been encircled. While doing this make sure that there are minimum number of groups.

3) Check for those 1’s which are adjacent to only one other 1 and encircle such pairs.

4) Check the K-map for adjacent 1’s and encircle those 1’s which are not adjacent to any
other 1’s. These are called isolated 1’s.

5) Form the simplified expression by summing product terms of all the groups.

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 3-VARIABLE K-MAP SIMPLIFICATION

Example-1: Simplify the Boolean expression, F(x, y, z) = ∑m (3, 4, 6, 7)

F = yz+ xz’

Example-2: Simplify the Boolean expression, F(x, y, z) = ∑m (0, 2, 4, 5, 6)

F = z’+ xy’’

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 3-VARIABLE K-MAP SIMPLIFICATION

Example-3:
F = A’C + A’B + AB’C + BC
= A’C (B+ B’) + A’B (C+ C’) + AB’C + BC (A+ A’)
= A’BC+ A’B’C + A’BC + A’BC’ + AB’C + ABC + A’BC
= A’BC+ A’B’C + A’BC’ + AB’C + ABC
= m3+ m1+ m2+ m5+ m7
= ∑ m (1, 2, 3, 5, 7)

F = C + A’B

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 4-VARIABLE K-MAP SIMPLIFICATION

Example-1: F (A, B, C, D) = ∑ m (0, 1, 4, 8, 9, 10)

F= A’C’D’+ AB’D’+ B’C’

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 4-VARIABLE K-MAP SIMPLIFICATION

Example-2: Y (A, B, C, D)= ∑ m (7, 9, 10, 11, 12, 13, 14, 15)

Y= AB+ AC+ AD+BCD.

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 4-VARIABLE K-MAP SIMPLIFICATION

Example-3: Y = A’BC’D’ + A’BC’D + ABC’D’ + ABC’D + AB’C’D + A’B’CD’

Y= A’B’CD’+ AC’D+ BC’

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 4-VARIABLE K-MAP SIMPLIFICATION

Example-4:
F = A’B’C’+ B’CD’+ A’BCD’+ AB’C’
= A’B’C’ (D+ D’) + B’CD’ (A+ A’) + A’BCD’+ AB’C’ (D+ D’)
= A’B’C’D+ A’B’C’D’+ AB’CD’+ A’B’CD’+ A’BCD’+ AB’C’D+ AB’C’D’
= m1+ m0+ m10+ m2+ m6+ m9+ m8
= ∑ m (0, 1, 2, 6, 8, 9, 10)

F= B’D’+ B’C’+ A’CD’.

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 4-VARIABLE K-MAP SIMPLIFICATION
Example-5: Design an car driver alert system based on following condition. The buzzer (B=1)
will alert the driver whenever any one of the following condition is satisfied.
(i). When engine is ON (E=1) and any one of the door is opened (D=1)
(ii). When fuel level is low (F=1)
(iii). When car exceed speed limit (S=1)
Truth table
K-Map

Logic diagram

B=F+S+ED

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 4-VARIABLE K-MAP SIMPLIFICATION WITH DON’T CARES
 A don’t care minterm is a combination of variables whose logical value is not specified.
 When choosing adjacent squares to simplify the function in a k-map, the don’t care may
be assumed either 0 or 1, depending on which combination gives the simplest expression.

Example-1: F (w, x, y, z) = ∑m (0, 1, 4, 8, 9, 10)+∑d (2, 11)

F = wx’+ x’y’+ w’y’z’

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 4-VARIABLE K-MAP SIMPLIFICATION WITH DON’T CARES

Example-2: F (w, x, y, z) = ∑m (0, 7, 8, 9, 10, 12)+∑d (2, 5, 13)

F (w, x, y, z) = w’xz+ wy’+ x’z’

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 75

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 K-MAP SIMPLIFICATION OF POS FORMS

 For a POS expression in standard form, 0 is placed on the Karnaugh map for
each sum term in the expression & the cells that do not have a 0 are the cells
for which the expression is 1.
 Steps for the POS K-mapping process.
 Step 1: Determine the binary value of each sum term in the standard POS
expression. This is the binary value that makes the term equal to 0.
 Step 2: As each sum term is evaluated, place 0 on the Karnaugh map in
the corresponding cell.
 Step3: Other procedure are similar to SOP K-map method

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 3-VARIABLE K-MAP SIMPLIFICATION

Example-1: Simplify the Boolean expression,

F(A, B, C) = (A+B+C’).(A+B’+C’).(A’+B’+C).(A’+B’+C’)

F = (A+C’).(A’+B’)

Example-2: Simplify the given Maxterm, F(A, B, C) = ∏M(0, 1, 3, 5).∏D(2, 6)

F = (A). (B+C’)

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 4-VARIABLE K-MAP SIMPLIFICATION
Example-1:
F(A,B,C,D)=(A+B+C+D).(A+B+C’+D’).(A+B+C’+D).(A+B’+C’+D’).(A’+B’+C+D’).(A’+B+C+D).(A’+B+C’+D’).(A’+B+C’+D)

F = (B+D).(B+C’).(A+C’+D’).
(A’+B’+C+D’)

Example-2: F (A, B, C, D) = ∏M (3, 4, 6, 7, 11, 12,13, 14, 15)

F = (A’+B’).(C’+D’).(B’+D)

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 4-VARIABLE K-MAP SIMPLIFICATION WITH DON’T CARE
Example-1: F (A, B, C, D) = ∏M(3,6,9,12,15) · ∏D(0,1,2)

F = (A+B).(B+C+D’).(A+C’+D).(A’+B’+C+D).(A’+B’+C’+D’)

Example-2: F (A, B, C, D) = ∏M(2,5,6,7,12,13) · ∏D(1,8,9,10,11,15)

F = (B+D’).(A’+C).(A+C’+D)

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  OR, AND and NOT gates are the three basic logic gates as they together
can be used to construct the logic circuit for any given Boolean expression.

 NAND and NOR gates are referred to as universal logic gates because we
can create any Boolean expression using ONLY NOR or ONLY NAND gates.

 Digital circuits are more frequently constructed using NAND and NOR gates
than with AND and OR gates because of
 Low cost and easy to fabricated
 Small die size and small delay
 Fast and Low power consumption
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 NAND GATE AS UNIVERSAL LOGIC GATE
By DeMorgan's Law

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 NAND IMPLEMENTATION
Example-1: Implement the logical expression using only NAND gates F= AB + CD + E
Note: AND is gate is replaced by NAND gate, OR gate is replaced by NAND gate with INVERT-OR gate

F= [(A.B)’.(C.D)’.E’]’ = AB + CD + E

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 NAND IMPLEMENTATION
Example-2: Implement the logical expression using only NAND gates F=(AB’+CD’).(A’+B)
Note: AND is gate is replaced by NAND gate, OR gate is replaced by NAND gate with INVERT-OR gate

F = [[(A.B’)’.(C.D’)’]’.(A.B’)’]’’ = [[(A.B’)’.(C.D’)’]’.(A.B’)’] = (AB’+CD’).(A’+B)

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 NAND IMPLEMENTATION
Example-3: Implement the logical expression using only NAND gates F = A(B+CD)+BD’
Note: AND is gate is replaced by NAND gate, OR gate is replaced by NAND gate with INVERT-OR gate

F = [((C.D)’.B’)’.A]’.(B.D’)’]’ = A(B+CD)+BD’

MODULE-1 ECE102L-DIGITAL SYSTEM DESIGN 85

 NOR GATE AS UNIVERSAL LOGIC GATE
By DeMorgan's Law

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 NOR IMPLEMENTATION
Example-1: Implement the logical expression using only NOR gates F= (A+B).(C+D).E
Note: OR is gate is replaced by NOR gate, AND gate is replaced by NOR gate with INVERT-AND gate

F= [(A+B)’ + (C+D)’ + E’]’= (A+B).(C+D).E

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 NOR IMPLEMENTATION
Example-2: Implement the logical expression using only NOR gates F = (AB’+CD’).(A’+B)
Note: OR is gate is replaced by NOR gate, AND gate is replaced by NOR gate with INVERT-AND gate

F = [[(A’+B)’ + (C’+D)’]’ +(A’+B)’]’ = (AB’+CD’).(A’+B)

MODULE-1 ECE102L-DIGITAL SYSTEM DESIGN 88

 NOR IMPLEMENTATION
Example-3: Implement the logical expression using only NOR gates F = (A+B(C +D))(B+D’)
Note: OR is gate is replaced by NOR gate, AND gate is replaced by NOR gate with INVERT-AND gate

F = [[((C+D)’ + B’)’ + A]’ + (B+D’)’]’ = (A+B(C +D))(B+D’)

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 EXERCISE
 Using a Karnaugh map, simplify the following functions and implement them with basic gates.
(a) F (A, B, C, D) = Σm(0, 2, 3, 6, 7, 8, 10, 11, 12, 15)
(b) F (A, B, C, D) = Σm(0, 2, 3, 5, 7, 8, 13) + Σd(1, 6, 12)
(c) F (A, B, C, D) = Σm(1, 7, 9, 10, 12, 13, 14, 15) + Σd(4, 5, 8)
(d) F (A, B, C, D) = πM (0, 8, 10, 11, 14) . πD (6)
(e) F (A, B, C, D) = πM(2, 8, 11, 15) . πD (3, 12, 14)
(f) F (W, X, Y, Z) = πM (0, 2, 6, 11, 13, 15) . πD (1, 9, 10, 14)
 Prepare a Karnaugh map for the following functions.
(a) F = ABC + A'BC + B'C'
(b) Y = AB + B'CD
 Using the Karnaugh map method, simplify the following functions, obtain their SOP form, and POS form.
Realize them with basic gates, then convert into ONLY NAND and ONLY NOR gates.
(a) F (W, X, Y, Z) = Σm (1, 3, 4, 5, 6, 7, 9, 12, 13)
(b) F (W, X, Y, Z) = Σm (1, 5, 6, 7, 11, 12, 13, 15)

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  Logic family refers to digital ICs which are constructed using basic
electronic components such as Diodes, Resistors, Transistors and MOSFET

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 TRANSISTOR-TRANSISTOR LOGIC (TTL)

 In TTL, logic gates are constructed around the BJT and resistors
 Advantages:
 TTL has a strong drive capability
 It is least susceptible to electrical damage
 Lesser immune to noise when compared to ECL
 Fastest saturation compared to DTL
 74xx or 74Nxx: Standard TTL
 Disadvantages: 

74Lxx: Low Power TTL
74Hxx: High Speed TTL
 High power dissipation compared to CMOS  74Sxx: Schottky TTL
 74LSxx: Low Power Schottky TTL
 Occupy more space  74ASxx: Advanced Schottky TTL
 74ALSxx: Advanced Low Power Schottky TTL
 Expensive compared to MOSFET  54xx : Military grade IC

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 TRANSISTOR-TRANSISTOR LOGIC (TTL) – NOT GATE

TTL NOT gate TTL NOT gate with input as “HIGH” TTL NOT gate with input as “LOW”
INPUT Q1 Q2 Q3 Q4 D1 D2 OUTPUT
LOW ON OFF ON OFF FB FB HIGH
HIGH OFF ON ON ON RB FB LOW
Reference: https://www.allaboutcircuits.com/textbook/digital/chpt-3/not-gate/
MODULE-1 ECE102L-DIGITAL SYSTEM DESIGN 94
 TRANSISTOR-TRANSISTOR LOGIC (TTL) – NAND GATE

TTL 2-INPUT NAND Gate TTL 2-INPUT NAND Gate with Q1 as Diodes

Reference: https://www.allaboutcircuits.com/textbook/digital/chpt-3/ttl-nand-and-gates/

MODULE-1 ECE102L-DIGITAL SYSTEM DESIGN 95

 TRANSISTOR-TRANSISTOR LOGIC (TTL) – NAND GATE

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 TRANSISTOR-TRANSISTOR LOGIC (TTL) – NOR GATE

TTL 2-INPUT NOR Gate TTL 2-INPUT NOR Gate with Q1 as Diodes

Reference: https://www.allaboutcircuits.com/textbook/digital/chpt-3/ttl-nor-and-or-gates/

MODULE-1 ECE102L-DIGITAL SYSTEM DESIGN 97

 TRANSISTOR-TRANSISTOR LOGIC (TTL) – AND, OR GATE

TTL 2-INPUT AND Gate TTL 2-INPUT OR Gate

Reference: https://www.technocrazed.com/3-5-ttl-nand-and-and-gates

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 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR LOGIC (CMOS)
 CMOS uses MOSFET, both NMOS and PMOS complement each other and are used
symmetrically in each configuration of the logic circuit
 IC families: 74Cxx Series: 5v CMOS, 74HCxx: High Speed CMOS, 74HCTxx: High
Speed CMOS
 Advantages:
 Low power consumption
 High immunity to noise
 Very large fan-out
 Works on wide temperature range
 Disadvantages:
 Difficult to implement
 Worst propagation delay
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 COMPLEMENTARY METAL OXIDE SEMICONDUCTOR LOGIC (CMOS)
Truth Table
2-Input NAND gate
A B P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0

2-Input NOR gate

A B P1 P2 N1 N2 Y
CMOS NOT gate 0 0 ON ON OFF OFF 1
A P1 N1 Y 0 1 ON OFF OFF ON 0
0 ON OFF 1 CMOS 2-Input NAND gate CMOS 2-Input NOR gate 1 0 OFF ON ON OFF 0
1 OFF ON 0 1 1 OFF OFF ON ON 0
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 CMOS EXAMPLES

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 CMOS EXAMPLES

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 EXERCISE

Realize following logical expressions using CMOS logic:

1. Y = (AB+C)’
2. Y = AB’+A’B
3. Y = B’C+ ABC’
4. Y = (A(BC+D))’
5. Y = (AB+A(C+D))’
6. Y = (ABC+DE+F)

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