Sequential Circuits

• The combinational circuit does not use any memory.

• Hence the previous state of input does not have any effect on the present state of the
circuit.

• But sequential circuit has memory so output can vary based on input.

• This type of circuits uses previous input, output, clock and a memory element.
• A Flip Flop is a memory element that is capable of storing one bit of information.
• It is also called as Bistable Multivibrator since it has two stable states either 0 or 1.
Two Main Types of Sequential Circuits
There are two types of sequential circuit,
(i) synchronous
(ii) asynchronous
Synchronous Sequential Logic Circuit
➢ Clocked
➢ All Flip-Flops use the same clock and change state on the same triggering edge.
Asynchronous Sequential Logic Circuit
➢ No clock
➢ Can change state at any instance in time.
➢ Faster but more complex than synchronous sequential circuits.
General Models for Sequential Circuits
• A sequential circuit can be divided conveniently into two parts -- the flip-flops which serve
as memory for the circuit and the combinational logic which realizes the input functions for
the flip-flops and the output functions.
• The combinational logic may be implemented with gates, with a ROM, or with a PLA.
Combinational vs. Sequential
⚫ Combinational Logic Circuit
➢ Output is a function only of the present inputs.
➢ Does not have state information.
➢ Does not require memory.
⚫ Sequential Logic Circuit (Finite State Machine)
➢ Output is a function of the present state.
➢ Has state information
➢ Requires memory.
➢ Uses Flip-Flops to implement memory
Latches and Flip Flops:
✓ Both Latches and flip flops are circuit elements wherein the output not
only depends on the current inputs, but also depends on the previous input
and outputs.
✓ The main difference between the latch and flip flop is that a flip flop has a
clock signal, whereas a latch does not. Basically, there are four types of
latches and flip flops: SR, D, JK and T.
✓ The major differences between these types of flip flops and latches are the
number of i/ps they have and how they change the states.
✓ There are different variations for each type of latches and flip-flops which
can enhance their operations.
 Flip Flop

• Flip flop is a sequential circuit which generally samples its inputs

and changes its outputs only at particular instants of time and not
continuously.
• Flip flop is said to be edge sensitive or edge triggered rather than
being level triggered like latches.
 S-R Flip Flop

• It is basically S-R latch using NAND gates with an

additional enable input.
• It is also called as level triggered SR-FF. For this, circuit in
output will take place if and only if the enable input (E) is made
active.
• In short this circuit will operate as an S-R latch if E = 1 but there
is no change in the output if E = 0.
S.N. Condition Operation

• If S = R = 0 then output of NAND gates 3 and 4 are forced to become 1.

S=R=0: • Hence R' and S' both will be equal to 1. Since S' and R' are the input of the
1
No change basic S-R latch using NAND gates, there will be no change in the state of
outputs.

S = 0, R = 1, • Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output of NAND-4

2
E=1 i.e. S' = 0. Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

• Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.

S = 1, R = 0,
3 • Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0. This is the
E=1
reset condition.

• As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4 both are 0 i.e.

S = 1, R = 1,
4 S' = R' = 0.
E=1
• Hence the Race condition will occur in the basic NAND latch.
 J-K Flip-flop • The JK flip-flop operates with only positive or negative clock
transitions.

Due to the undefined state in the SR • The operation of the JK flip-flop is similar to the SR flip-flop.
flip-flop, another flip-flop is required
in electronics. • When the input J and K are different then the output Q takes
The JK flip-flop is an improvement the value of J at the next clock edge.
on the SR flip-flop where S=R=1 is
not a problem. • When J and K both are low then NO change occurs at the
output.

• If both J and K are high, then at the clock edge, the output
will toggle from one state to the other.
 Truth table of JK flip-flop

J K Q State
0 0 0 No Change
0 1 0 Reset
1 0 1 Set
1 1 Toggles Toggle
• If J and K data input are different (i.e. high and low) then J K Q Q’
the output Q takes the value of J at the next clock edge. 0 0 0 0
• If J and K are both low then no change occurs. 0 1 0 0
1 0 0 1
• If J and K are both high at the clock edge then the output 1 1 0 1
will toggle from one state to the other. 0 0 1 1
0 1 1 0
• JK Flip-Flops can function as Set or Reset Flip-flops
1 0 1 1
1 1 1 0

• The conversion of flip-flops to a JK flip-flop is to cross connect the Q and Q outputs with the S and R inputs through
additional 3-input AND gates
• If the J and K inputs are both HIGH, logic “1” then the Q output will change state (Toggle) for as long as the clock
input, (CLK) is HIGH. Thus the output will be unstable creating a race-around problem with this basic JK circuit.
• This problem is avoided by ensuring that the clock input is at logic “1” only for a very short time, or to produce a
more sophisticated JK flip-flop circuit called a Master–slave flip-flop.
 The Master-Slave Flip-Flops
✓ The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse.
✓ The outputs from Q and Q from the “Slave” flip-flop are fed back to the inputs of the “Master”
with the outputs of the “Master” flip flop being connected to the two inputs of the “Slave” flip
flop.
✓ This feedback configuration from the slave’s output to the master’s input gives the characteristic
toggle of the JK flip.

• The conversion of flip-flops to a “Master-Slave”

configuration involves the addition of a second
bistable circuit.
• The master-slave configuration consists of two SR
latches connected in cascade.
• One bistable flip-flop acts as the master receiving
the external inputs while the other acts as its slave,
taking its inputs directly from the master flip-flop
✓ Master slave JK FF is a cascade of two S-R FF with feedback from
the output of second to input of first. Master is a positive level
triggered.
✓ But due to the presence of the inverter in the clock line, the slave will
respond to the negative level. Hence when the clock = 1 (positive
level) the master is active and the slave is inactive.
✓ Whereas when clock = 0 (low level) the slave is active and master is
inactive.
 Condition Operation
J = K = 0 (No • When clock = 0, the slave becomes active and master is inactive. But since the S and R inputs have not
change) changed, the slave outputs will also remain unchanged. Therefore outputs will not change if J = K =0.
• Clock = 1: Master active, slave inactive. Therefore outputs of the master become Q1 = 0 and Q1 bar = 1.
That means S = 0 and R =1.
• Clock = 0: Slave active, master inactive Therefore outputs of the slave become Q = 0 and Q bar = 1.
J = 0 and K = 1
• Again clock = 1: Master active, slave inactive. Therefore even with the changed outputs Q = 0 and Q bar
(Reset)
= 1 fed back to master, its outputs will Q1 = 0 and Q1 bar = 1. That means S = 0 and R = 1.
• Hence with clock = 0 and slave becoming active the outputs of slave will remain Q = 0 and Q bar = 1.
Thus we get a stable output from the Master slave.
• Clock = 1: Master active, slave inactive. Therefore outputs of the master become Q1 = 1 and Q1 bar = 0.
J = 1 and K = 0 That means S = 1 and R =0.
(Set) • Clock = 0: Slave active, master inactive Therefore outputs of the slave become Q = 1 and Q bar = 0.
• Again clock = 1: then it can be shown that the outputs of the slave are stabilized to Q = 1 and Q bar = 0.

• Clock = 1: Master active, slave inactive. Outputs of master will toggle. So S and R also will be inverted.
• Clock = 0: Slave active, master inactive. Outputs of slave will toggle.
J=K=1
4 • These changed output are returned back to the master inputs. But since clock = 0, the master is still
(Toggle)
inactive. So it does not respond to these changed outputs. This avoids the multiple toggling which leads
to the race around condition. The master slave flip flop will avoid the race around condition.
 D Flip-Flop
• D Flip-flop operation is same as D latch. The only difference is that D
flip-flop changes its output only when there is an edge of the clock
signal.
• In SR NAND Gate Bistable circuit, the undefined input condition of SET =
"0" and RESET = "0" is forbidden. It is the drawback of the SR flip flop. This
state:
1.Override the feedback latching action.
2.Force both outputs to be 1.
3.Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.
• We connect the inverter between the Set and Reset inputs for producing another
type of flip flop circuit called D flip flop, Delay flip flop, D-type Bistable, D-type
flip flop.

• The D flip flop is the most important flip flop from other clocked types. It ensures
that at the same time, both the inputs,

• i.e., S and R, are never equal to 1. The Delay flip-flop is designed using a
gated SR flip-flop with an inverter connected between the inputs allowing for a
single input D(Data).

• This single data input, which is labeled as "D" used in place of the "Set" input and
for the complementary "Reset" input, the inverter is used. Thus, the level-sensitive
D-type or D flip flop is constructed from a level-sensitive SR flip flop.
Toggle Flip Flop / T Flip Flop

• Toggle flip flop is basically a JK flip flop with J and K terminals

permanently connected together.
• It has only input denoted by T as shown in the Symbol Diagram.
The symbol for positive edge triggered T flip flop is shown in the
Block Diagram.
S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't

change
2 T = 1, J = K = 1 Output will toggle
corresponding to every
leading edge of clock signal.
 Shift register
• A Register is a device which is used to store such information. It is a group of flip flops
connected in series used to store multiple bits of data.
• A shift register is a type of digital circuit using a cascade of flip-flops where the output of one
flip-flop is connected to the input of the next.
• They share a single clock signal, which causes the data stored in the system to shift from one
location to the next.
• The information stored within these registers can be transferred with the help of shift registers.
Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and in/out of the
registers by applying clock pulses.
• An n-bit shift register can be formed by connecting n flip-flops where each flip flop stores a
single bit of data.
• The registers which will shift the bits to left are called “Shift left registers”.
• The registers which will shift the bits to right are called “Shift right registers”.
 Shift register
• A Shift Register can shift the bits either to the left or to the right. A Shift Register, which shifts
the bit to the left, is known as "Shift left register", and it shifts the bit to the right, known as
"Right left register".

The shift register is classified into the following types:

• Serial In Serial Out
• Serial In Parallel Out
• Parallel In Serial Out
• Parallel In Parallel Out
 Serial-In Serial-Out Shift Register (SISO)
• The shift register, which allows serial input (one bit after the other through a single data line)
and produces a serial output is known as Serial-In Serial-Out shift register.
• Since there is only one output, the data leaves the shift register one bit at a time in a serial
pattern, thus the name Serial-In Serial-Out Shift Register.
• The circuit consists of four D flip-flops which are connected in a serial manner. All these flip-
flops are synchronous with each other since the same clock signal is applied to each flip flop.

The above circuit is an example of

shift right register, taking the serial
data input from the left side of the flip
flop.
The main use of a SISO is to act as a
delay element.
Data Transfer Table and Time Period
 Serial-In Parallel-Out shift Register (SIPO)
• The shift register, which allows serial input (one bit after the other through a single data line)
and produces a parallel output is known as Serial-In Parallel-Out shift register.
• The circuit consists of four D flip-flops which are connected. The clear (CLR) signal is
connected in addition to the clock signal to all the 4 flip flops in order to RESET them.
• The output of the first flip flop is connected to the input of the next flip flop and so on.
• All these flip-flops are synchronous with each other since the same clock signal is applied to
each flip flop.
The above circuit is an example of shift right
register, taking the serial data input from the left
side of the flip flop and producing a parallel
output.
They are used in communication lines where
demultiplexing of a data line into several parallel
lines is required because the main use of the
SIPO register is to convert serial data into
parallel data.
Clock Pulse
QA QB QC QD
No
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
 Parallel-In Serial-Out Shift Register (PISO)
• The shift register, which allows parallel input (data is given separately to each flip flop and in a simultaneous
manner) and produces a serial output is known as Parallel-In Serial-Out shift register.
• The clock input is directly connected to all the flip flops but the input data is connected individually to each
flip flop through a multiplexer at the input of every flip flop.
• The output of the previous flip flop and parallel data input are connected to the input of the MUX and the
output of MUX is connected to the next flip flop.
• All these flip-flops are synchronous with each other since the same clock signal is applied to each flip flop.

A Parallel in Serial out

(PISO) shift register us
used to convert parallel
data to serial data.
 Parallel-In Parallel-Out Shift Register (PIPO)
• The shift register, which allows parallel input (data is given separately to each flip flop and in a
simultaneous manner) and also produces a parallel output is known as Parallel-In parallel-Out shift
register.
• The clear (CLR) signal and clock signals are connected to all the 4 flip flops.
• In this type of register, there are no interconnections between the individual flip-flops since no
serial shifting of the data is required.
• Data is given as input separately for each flip flop and in the same way, output also collected
individually from each flip flop.

A Parallel in Parallel out (PIPO) shift

register is used as a temporary
storage device and like SISO Shift
register it acts as a delay element.
 Bidirectional Shift Register
• Bidirectional shift registers are the registers which are capable of shifting the data either right or left
depending on the mode selected.
• If the mode selected is 1(high), the data will be shifted towards the right direction and if the mode
selected is 0(low), the data will be shifted towards the left direction.
 Shift Register Counter
• Shift Register Counters are the shift registers in which the outputs are connected back to
the inputs in order to produce particular sequences. These are basically of two types:
• Ring Counter – A ring counter is basically a shift register counter in which the output of
the first flip flop is connected to the next flip flop and so on and the output of the last flip
flop is again fed back to the input of the first flip flop, thus the name ring counter.
• The data pattern within the shift register will circulate as long as clock pulses are applied.
 Johnson Counter
• A Johnson counter is basically a shift register counter in which the output of the first flip flop is
connected to the next flip flop and so on and the inverted output of the last flip flop is again fed
back to the input of the first flip flop. They are also known as twisted ring counters.
 Applications of shift Registers:
• The shift registers are used for temporary data storage.

• The shift registers are also used for data transfer and data manipulation.
• The serial-in serial-out and parallel-in parallel-out shift registers are used to produce time
delay to digital circuits.
• The serial-in parallel-out shift register is used to convert serial data into parallel data thus
they are used in communication lines where demultiplexing of a data line into several
parallel line is required.

• A Parallel in Serial out shift register us used to convert parallel data to serial data.
Counters
 Digital Logic Counter
• In digital logic and computing, a Counter is a device which stores (and sometimes
displays) the number of times a particular event or process has occurred

• Counter is a sequential circuit. A digital circuit which is used for a counting pulses is
known counter.

• Counter is the widest application of flip-flops. It is a group of flip-flops with a clock

signal applied.
• Counters are used in digital electronics for counting purpose, they can count specific
event happening in the circuit.

• For example, in UP counter a counter increases count for every rising edge of clock.

• Not only counting, a counter can follow the certain sequence based on our design like
any random sequence 0,1,3,2… .They can also be designed with the help of flip flops.
 Counters are of two types.
Asynchronous or ripple counters
- In asynchronous counter we don’t use universal clock, only first flip flop is driven
by main clock and the clock input of rest of the following flip flop is driven by output of
previous flip flops.

Synchronous counter
• synchronous counter has one global clock which drives each flip flop so output changes in
parallel.
• advantage of synchronous counter is it can operate on higher frequency
• But asynchronous counter as it does not have cumulative delay because of same clock is
given to each flip flop
 Asynchronous Counter

Q0 is changing as soon as the rising edge of

clock pulse is encountered,

Q1 is changing when rising edge of Q0 is

encountered(because Q0 is like clock pulse
for second flip flop) and so on.

In this way ripples are generated through

Q0,Q1,Q2,Q3 hence it is also
called RIPPLE counter.
Asynchronous Up/Down counter (or) Bidirectional counter
For asynchronous up/down counter, control input is necessary for the control of the operation as up or down
counter.

When the control input is 0, in the following figure, the AND gates 1 and 3 are disabled. It enables gate 2 and 4,
which means, Q’ output of first and second flip-flop drives the clock input of JK FF2 and JK FF3 respectively. In
this case, the counter will perform the operation of the down counter.

When the control input is 1, gates 1 and 3 are enabled and gates 2 and 4 are disabled. This makes a way for the Q
output of flip-flops to drive the clock input of the next stage flip-flop. Now, the counter will perform the up
counter operation.
Synchronous Counters
Johnson Counter

• The Johnson counter is similar to the Ring counter.

• The only difference between the Johnson counter and the ring counter is that the outcome of the last
flip flop is passed to the first flip flop as an input.
• But in Johnson counter, the inverted outcome Q' of the last flip flop is passed as an input.
• The remaining work of the Johnson counter is the same as a ring counter. The Johnson counter is also
referred to as the Creeping counter.
Advantages

•The number of flip flops in the Johnson counter is equal to the number of flip
flops in the ring counter, and the Johnson counter counts twice the number of states
the ring counter can count.

•The Johnson counter can also be designed by using D or JK flip flop.

•The data is count in a continuous loop in the Johnson ring counter.

•The circuit of the Johnson counter is self-decoding.