IT2014

Task Performance
Flip-flops
GERONILLA, MARK WILSON G. BSCPE G-501

Objectives:
At the end of the exercise, the students should be able to:

▪ Analyze the operation of a latch flip-flop made from NAND or NOR gates; and
▪ Constructed a latch flip-flop from NAND or NOR gates.

Materials:
▪ 1 logic trainer or equivalent
▪ 1 Quad 2 – input NAND Gate (7400) DIP IC
▪ 8 LED (Light Emitting Diode) indicator
▪ 1 2KΩ resistor at 0.5W
▪ 1 Dual JK master-slave flip-flop (7476) DIP IC
▪ 1 Dual D flip-flop (7474) DIP IC
▪ 1 Quad D flip-flop (7475) DIP IC
▪ Several hook-up wires
Procedures:
Note: Please observe safety precautions and proper handling of materials and equipment while conducting the
laboratory experiment. This experiment is to be performed under an instructor’s supervision.

Part 1: NAND Gate RS Flip-flop

1. Construct the circuit shown below. Use logic switches for inputs S and R.

2. Set the input switches according to the input conditions in the truth table and record the output Q and Q’
states.
3. Modify the circuit shown below to produce a clocked RS flip-flop.

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4. Set the switches S and R according to this truth table, then move the clocked switch up and then down.
5. Observe the output Q and Q’ and record their states in the truth table.
6. Construct the circuit shown below (S1 is directly connected to the ground)

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7. Set S1 according to the truth table and record the condition of LED1 and LED2 in the proper place.

Fill-in Questions (5 items x 3 points):

• Having both inputs at 1 is resulting to no change with RS flip-flop.
• A clocked pulse is needed at the same time together with either the S or the R input to cause the proper
action with a clocked RS flip-flop.
• The clocked RS flip-flop is a memory type operation.
• A NAND gate bounce less switch has two (2) outputs. One 3-output goes from low to High and the other
output goes from high to Low when the switch is actuated.

Part 2: Universal JK Flip-Flop (15 items x 2 points)

1. Connect the circuit shown below and initially set the logic switches. Thus, S1, S5 = 1; S2, S3, S4 = 0.

2. Move S5 (Clr) down and up. The flip-flop should now be off (Q = 0, Q’ = 1).

Part 2.1: RS Flip-Flop Operation

3. Move S1 (Ps) down and up. The flip-flop should now be on. Record the states of the outputs; Q =
0 , Q’ = _ 1_ ).
4. Move S5 (Clr) down and up. The flip-flop should now off. Record the states of the outputs; Q =
0 , Q’ = _ 1_ ).

Part 2.2: Clocked RS Flip-Flop Operation

5. Move S2 (J) up. Move S3 (Clk) up and down. (Notice that the flip-flop does not turn until S3 is brought
down). Move S2 (J) down. Record the states of the outputs; Q = 1 , Q’ = 0 ).
6. Move S4 up. Move S3 (Clk) up and down. (Again, notice that the flip-flop does not turn off until S3 is
brought down). Move S4 (K) down. Record the states of the outputs; Q = _ 0 , Q’ =
0 ).

Part 2.3: T-Type Flip-Flop Operation

7. Move S2 (J) and S4 (K) up. Move S3 (Clk) up and down. The flip-flop changes state when S3 went
up. Record the states of the outputs; Q = _ 0 , Q’ = 1 ).
8. Move S3 (Clk) up and down. Question: When does the flip-flop changes state? S3 went up or S3 went
down? The flipflip change when the elk went down. Record the states of the outputs; Q = 1 , Q’ =
_ 0 .
9. Move S5 (Clr) down. Move S2 (J). Move S3 (Clk) up and down.
10. Move S1 (Ps) down. Move S4 (K) up. Move S3 (Clk) up and down. Did the flip-flop turn off?
YES .
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Part 2.4: T-Type Flip-Flop with Outputs Connected to the Input

11. Connect the circuit shown below. The outputs are cross-connected to the inputs Q to K, Q’ to J, to
form a T-type flip-flop. The Ps pin 2 and Clr pin 3 inputs may not need to be wired since unconnected
TTL inputs float high or go to a logic 1.

12. Move S1 (Clk) up and down. Question: Did the flip-flop turn changed states? _ The flipflop did
changed states.
13. Repeat step 12 several times to better understand the operation of T-type flip-flop.

Fill-in Questions (5 items x 3 points):

• When inputs J = 1, K = 0, Ps = 1, Clr = 1, and the Clk is falling, a JK flip-flop will turn 1 _.
• When inputs J = 0, K = 1, Ps = 1, Clr = 1, and the Clk is falling, a JK flip-flop will turn 0 _.
• When inputs J = 1, K = 1, Ps = 1, Clr = 1, and the Clk is falling, a JK flip-flop acts like a T-type _ flip-
flop.
• When inputs J = 1, K = 0, Ps = 1, Clr = 0, and the Clk is falling, the outputs Q = 0 _ and Q’ =
1 .

Part 3: D-Type Flip-Flop (10 items x 2 points)

1. Connect the circuit shown below and initially set the logic switches; thus, S1, S2 = 0 and S3, S4 = 1.

2. Move S4 (Clr) down and up. The flip-flop should now be reset (Q = 0, Q’ = 1).
3. Move S1 (D) up. Move S2 (Clk) up and down. Question: When does the flip-flop changes state? S2 went
up or S2 went down? Went up . Record the states of the outputs; Q = 0 , Q’ = 1_ _.
4. Move S1 (D) down. Move S2 (D) up and down. Question: When does the flip-flop changes state? S2 went
up or S2 went down? Went up. Record the states of the outputs; Q = 0 , Q’ = _ 1 _.
5. Move S3 (Ps) down and up. Record the states of the outputs; Q = _ 1 _, Q’ = 0 .
6. Move S4 (Clr) down and up. Record the states of the outputs; Q = _ 0 _, Q’ = 1 .
7. Construct the circuit shown below to produce a T-type flip-flop. Pins 1 and 4 may not need to be
connected since they will float high.

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8. Move S1 (Clk) up and down several times. Notice that each time S1 goes up, the output changes state.
9. Construct the circuit shown. Select the logic switches; S1 = 1, S2 = 0, S3 = 1, S4 = 1 and S5 = 0. There
are four D-type flip-flops in this package. The first one input is marked D0, and its outputs are marked Q0
and Q’0. The other three flip-flops are identified similarly.

10. Move S5 (Clk) up and down. With a logic probe or LED indicator, test the output s and place 0s and 1s on
the figure at the respective output pins.

Fill-in Questions (5 items x 3 points):

• A T-type flip-flop can be made from a D-type flip-flop by connecting the Q output to the
D input.
• The D-type flip-flop can function like an RS flip-flop if only inputs D _ and CLK _ are used.
• The operation of the D-type flip-flop is that the output follows the data at the D input when a clock
pulse appears.

Other Observations (5 points):

Compared to the S-R flip-flop in terms of sequential operation via set and reset inputs is the commonly used J-
K flip-flop. When both inputs are set to logic 1, the J-K flip-flop does not have forbidden input states, in contrast
to the S-R latch. The J-K flip-flop can handle four different input combinations with its clocked input circuitry:
"logic 1," "logic 0," "no change," and "toggle."

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Conclusions and Recommendations (5 points):

Unlike the D flip-flop, the J-K flip-flop assumes the characteristics of input J when J and K are different,
updating its output Q at the next clock edge based on the value of J. It has inputs labeled J and K, and it operates
with four input combinations: "logic 1," "no change," and "toggle."

S_R FLIP FLOP USING NAND GATE

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S_R FLIP FLOP USING NOR GATE

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TRUTH TABLE

1 R QN QN+1

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 0

1 1 1 0

Grading Rubric (Essay):

Criteria Performance Indicator Points
Content Provided pieces of evidence, supporting details, and factual scenarios. 3
Organization Expressed the points in a clear and logical arrangement of ideas. 2
Total 5

Total Score:

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