Introduction to Digital System Design

Z. Navabi

Topic 3

Logic Minimization

Zain Navabi

Slides prepared by Katayoon Basharkhah 1

Outline
4-1 Logic circuit realization
4-1-1 Ad-hoc method
4-1-2 Boolean algebra
4-1-3 Examples
4-2 Karnaugh map
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Ad-hoc methods

• Recalling our previous discussion on constructing an overflow detector

• We wrote an expression and then realized that expression by constructing

the needed primitive gates.
A
B
S V

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Ad-hoc methods

• These are several alternatives using different gates

A
B
S V

A
B
S V

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Ad-hoc methods

• These are several alternatives using different gates

A
B
S V

A
B
S V

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Ad-hoc methods

• These are several alternatives using different gates

A
B
S V

A
B
V
S

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Ad-hoc methods

• There are a million ways to put the gates together to form the desired
function. There are many ad-hoc methods for logic realization.

• A question that arises here is which one of these structures is better to

use?

• Is it optimized in terms of the number of transistors and delays?

• Another thing to consider is that the word description of a problem is

not always simple enough for us to hope of reaching a simplified answer
through it.

• The solution is Boolean algebra.

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Outline
4-1 Logic circuit realization
4-1-1 Ad-hoc method
4-1-2 Boolean algebra
4-1-3 Examples
4-2 Karnaugh map
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Boolean Algebra

Just to see a real application of logic concept

• We can consider a relay as a controlled
switch

• Forces the output to be ON or OFF

• ON/OFF can be shown as 1/0 logic

Introduction to Digital System Design - Copyright Zainalabedin Navabi 9

Logic Circuit Realization
Boolean Algebra
Just to see a real application of logic concept
• Suppose two variables: A and B, which have only two probable values: 1 and 0.

• To understand the Boolean rules better, compare the variables with the
switches shown in the following circuits:

Introduction to Digital System Design - Copyright Zainalabedin Navabi 10

Logic Circuit Realization
Boolean Algebra
What is Boolean algebra
• We always aim to reduce and simplify a complex logic expression

• That helps to reduce the number of logic gates that is used in a circuit
realization.

• Boolean Algebra is therefore a system of mathematics based on logic that has its
own set of rules which are used to define and reduce Boolean expressions.

• Boolean variables : 0 and 1

• Boolean operators are : NOT, AND, OR

Introduction to Digital System Design - Copyright Zainalabedin Navabi 11

Logic Circuit Realization
Boolean Algebra
Boolean rules
Boolean Expression Description Equivalent Switching Boolean Algebra Rule
Circuit
𝐴 = 𝐴ҧ NOT NOT A Double Negation
𝐴+1=1 A in parallel with
closed = “CLOSED”
𝐴. 0 = 0 A in series with Annulment
open = “OPEN”
𝐴. 1 = 𝐴 A in series with
closed = “A”
𝐴+0=𝐴 A in parallel with Identity
open = “A”
𝐴. 𝐴 = 𝐴 A in series with
A = “A”
𝐴+𝐴 =𝐴 A in parallel with Idempotent
A = “A”

Introduction to Digital System Design - Copyright Zainalabedin Navabi 12

Logic Circuit Realization
Boolean Algebra

Boolean rules
Boolean Expression Description Equivalent Switching Boolean Algebra
Circuit Rule
𝐴. 𝐴ҧ = 0 A in series with
NOT A = “OPEN”
𝐴 + 𝐴ҧ = 1 A in parallel with Complement
NOT A = “CLOSED”
𝐴+𝐵 =𝐵+𝐴 A in parallel with B =
B in parallel with A
𝐴. 𝐵 = 𝐵. 𝐴 A in series with B = Commutative
B in series with A

Introduction to Digital System Design - Copyright Zainalabedin Navabi 13

Logic Circuit Realization
Boolean Algebra
Boolean rules
Boolean Expression Boolean Algebra Rule

𝐴. 𝐵. 𝐶 = 𝐴. 𝐵 . 𝐶
Associative
𝐴+ 𝐵+𝐶 = 𝐴+𝐵 +𝐶
𝐴. 𝐵 + 𝐶 = 𝐴. 𝐵 + 𝐴. 𝐶
Distributive
𝐴 + 𝐵. 𝐶 = 𝐴 + 𝐵 . (𝐴 + 𝐶)
𝐴. 𝐴. 𝐵 = 𝐴 Absorption
𝐴. 𝐴 + 𝐵 = 𝐴
𝐴. 𝐵 = 𝐴ҧ + 𝐵ത
𝐴 + 𝐵 = 𝐴.ҧ 𝐵ത De Morgans

• Duality: The dual of a true expression is also true and can be formed by
replacing and’s with or’s (and vice versa), 0’s with 1’s (and vice versa)

Introduction to Digital System Design - Copyright Zainalabedin Navabi 14

Outline
4-1 Logic circuit realization
4-1-1 Ad-hoc method
4-1-2 Boolean algebra
4-1-3 Examples
4-2 Karnaugh map
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Logic Circuit Realization
Examples

First Example: Overflow Detector

A
B
S V

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Logic Circuit Realization
Examples

First Example: Overflow Detector

• Let’s exercise our aim that is minimizing the overflow expression

• We use Boolean algebra and Boolean rules for this purpose .

v = a.b.c + a.b.c = a.b.c + a.b.c = a.b.c.a.b.c

A
B
S V

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Logic Circuit Realization
Examples
A
B 8
S V
2 6 28

2 2 Transistors

A
B 6
S 4 V
2 22
2 2 Transistors

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Logic Circuit Realization
Examples
Second Example
• Consider the following expression:
b
a
𝑤 = 𝑎. 𝑐 + 𝑏. 𝑐 + 𝑎. 𝑏 w

𝑤 = 𝑎. 𝑐 + 𝑏. 𝑐. (𝑎 + 𝑎) + 𝑎. 𝑏 = 𝑎. 𝑐 + 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏
= 𝑎. 𝑐. 1 + 𝑎. 𝑐. 𝑏 + 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏. 1 = 𝑎. 𝑐. 1 + 𝑏 + 𝑎. 𝑏. 1 + 𝑐 = 𝑎. 𝑐 + 𝑎. 𝑏

b
a
𝑤 = (𝑎. 𝑐) . (𝑎. 𝑏)
w

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Logic Circuit Realization
Examples
Third Example
• Consider the following expression:

𝑤 = 𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐 + 𝑎𝑏𝑑

𝑤 = 𝑐𝑑 𝑎 + 𝑎 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + 𝑑 + 𝑎𝑏𝑑 𝑐 + 𝑐 =

=𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 =
ad 𝑐 + 𝑐 + 𝑎𝑐 𝑑 + 𝑑 𝑏𝑐𝑑

=a𝑑 + 𝑎𝑐 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑏𝑐𝑑=

= 𝑎𝑑 1 + 𝑏𝑐 + 𝑎𝑐 1 + 𝑏𝑑 + 𝑏𝑐𝑑 =

=ad +𝑎𝑐 + 𝑏𝑐𝑑

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Logic Circuit Realization
Examples
Another Example

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Logic Circuit Realization
Verilog Examples

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Logic Circuit Realization
Verilog Examples

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Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable map
4-2-2 Definitions
4-2-3 Three variable map
4-2-4 Four variable map
4-2-5 Higher order variable map
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map

Here, seemingly random decisions are done

• Why are these decisions made?

𝑤 = 𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐 + 𝑎𝑏𝑑

𝑤 = 𝑐𝑑 𝑎 + 𝑎 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐 𝑑 + 𝑑 + 𝑎𝑏𝑑 𝑐 + 𝑐 =

=𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 =

=a𝑑 + 𝑎𝑐 + 𝑎𝑏𝑐𝑑 + 𝑎𝑏𝑐𝑑 + 𝑏𝑐𝑑=

= 𝑎𝑑 1 + 𝑏𝑐 + 𝑎𝑐 1 + 𝑏𝑑 + 𝑏𝑐𝑑 =

=ad +𝑎𝑐 + 𝑏𝑐𝑑

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Karnaugh Map
What is the problem with Boolean algebra?

• Using Boolean algebra for minimization is a trial and error process.

• For each expression, we are not sure if we have reached a minimal

representation.

• There is no guideline minimization.

• A graphical notation for the Boolean algebra smooths these problems

out.

• This graphical representation is called Karnaugh Map.

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Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable map
4-2-2 Definitions
4-2-3 Three variable map
4-2-4 Four variable map
4-2-5 Higher order variable map
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
2-Variable map
• All we need is a truth table.

• Each box of the Karnaugh map corresponds to a row of the truth table
and has been numbered accordingly.

a b w a 0 1
0 0 0 b
0 0 0
0 1 0
1 0 0 1 0 1
1 1 1 w
Truth Table Karnaugh Map
a w
b
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Karnaugh Map
2-Variable map
a b w a 1
0
0 0 0 b
0 0 1
0 1 1
1 0 1 1 1 1
1 1 1 w
Truth Table Karnaugh Map
a w
b

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Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable maps
4-2-2 Definitions
4-2-3 Three variable maps
4-2-4 Four variable maps
4-2-5 Higher order variable maps
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
Definitions
a b w
0 0 0
𝒘 = 𝒂𝒃 + 𝒂𝒃 + 𝒂𝒃 0 1 1
1 0 1
1 1 1

• Product Term: Any number of variables anded together is called a product term
• In this example : 𝒂𝒃 , 𝒂𝒃, 𝒂𝒃

• Minterm: A product term with all function variables.

• In this example : 𝒂𝒃 , 𝒂𝒃, 𝒂𝒃

• Sum of Products: Any number of variables or terms ored together.

• In this example :
𝑤 = ෍ 1,2,3
𝑚
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Karnaugh Map
Definitions
a b w
0 0 0
𝑤 = 𝑎𝑏 + 𝑎𝑏 + 𝑎𝑏 0 1 1
1 0 1
1 1 1

• Standard Sum of Products: In standard SOP, the products are obtained directly from the
Karnaugh map or truth table, so the SOP contains all of the variables of the function.
• Y is not a standard sum of products.
a b c 𝑌
w
0 0 0 0 0
𝑌 = 𝑎 + 𝑏𝑐 1 0 0 1 1
2 0 1 0 0
3 0 1 1 0
4 1 0 0 1
5 1 0 1 1
a
6 1 1 0 1
7 1 1 1 1

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Karnaugh Map
Definitions
• When attempting to minimize a function with Boolean algebra, writing the
expression in standard SOP form will make the rest of the process easier.

𝑤 = 𝑎𝑏 + 𝑎𝑏 + 𝑎𝑏

𝑤 = 𝑎. 𝑏 + 𝑎. 𝑏 + 𝑎. 𝑏 = 𝑎. 𝑏 + 𝑎. 𝑏 + 𝑎. 𝑏 + 𝑎. 𝑏 = 𝑎. 𝑏 + 𝑏 + 𝑏. 𝑎 + 𝑎
𝑤 = 𝑎+𝑏

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Karnaugh Map
Definitions
• Even by starting our process with a standard SOP form, the insight needed
for the next step is still considerable (in the above example for instance, to
recognize what term needs to be added).

• In Boolean algebra, we learnt that when two terms differed in only one
variable, that particular variable could have been eliminated in both terms.

• These terms are also called Boolean adjacent terms.

• With paying attention to the structure of the Karnaugh map, we can see that
we may combine physical adjacency and Boolean adjacency of the products.

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Karnaugh Map
Definitions
a b w
0 0 0
𝒘 = 𝒂𝒃 + 𝒂𝒃 + 𝒂𝒃 0 1 1
1 0 1
1 1 1

• Implicant: Any product term that when is 1, the function is 1.

• In this example : 𝑎𝑏 , 𝑎𝑏, 𝑎𝑏 , 𝑎, 𝑏

• Prime Implicant: Any Implicant that is not completely covered by any other implicant
• In this example : 𝑎, 𝑏

• Essential Prime Implicant: Implicant with at least a minterm not covered any other
PI.
• In this example : 𝑎, 𝑏
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Karnaugh Map
Definitions
• In order to use the Karnaugh maps for minimizing a function:

• List all EPIs

• Any uncovered minterm? If none, exit.
• Take PI covering most number of uncovered minterms.
a 0 1
b
0 0 1

1 1 1
w
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Outline

4-1 Logic circuit realization

4-2 Karnaugh map
4-2-1 Two variable maps
4-2-2 Definitions
4-2-3 Three variable maps
4-2-4 Four variable maps
4-2-5 Higher order variable maps
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
Three-variable maps
• For three variable maps, the number of each term in the map is based on gray
code.
• The reason is that physically adjacent 1s have to be Boolean adjacent terms
too.
𝑎𝑏𝑐 𝑎𝑏𝑐 𝑎𝑏𝑐 𝑎𝑏𝑐
ab ab
00 01 10 11 c 00 01 11 10
c
0 1 1 0 1 1
0 2 4 6 0 2 6 4

1 1
1 3 5 7 1 3 7 5
w w

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Karnaugh Map
Three-variable maps
• Example

# a b c w
0 0 0 0 0
1 0 0 1 0 ab
c 00 01 11 10
2 0 1 0 0
0 0 0 1 1
3 0 1 1 1
4 1 0 0 1 1 0 1 1 0
5 1 0 1 0 w
6 1 1 0 1 𝑤 = 𝑏𝑐 + 𝑎𝑐 + ab
7 1 1 1 1

𝑤 = ෍ 3,4,6,7
𝑚

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Karnaugh Map
Three-variable maps
• Example

# a b c w
0 0 0 0 0
1 0 0 1 1 ab
c 00 01 11 10
2 0 1 0 0
0 0 0 1 1
3 0 1 1 1
4 1 0 0 1 1 1 1 1 0
5 1 0 1 0 w
6 1 1 0 1
7 1 1 1 1
𝑎𝑏
𝑤 = 𝑎𝑐 + 𝑎𝑐 + ቊ
𝑏𝑐
𝑤 = ෍ 1,3,4,6,7
𝑚

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Karnaugh Map
Three-variable maps
• Example b
a
w
c

𝑎𝑏
𝑤 = 𝑎𝑐 + 𝑎𝑐 + ቊ
𝑏𝑐
a

b w
c

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Karnaugh Map
Three-variable maps
• Example
• Seeing 4 or 8 adjacent 1s must also result in a combination that only has
variables that don’t differ in any of the corresponding terms.
ab
c 00 01 11 10
0 1 1 1 1

1 0 1 0 0
w
𝑤 = 𝑐 + 𝑎𝑏
ab
c 00 01 11 10
0 1 1 0 0

1 1 1 0 0
w
𝑤=𝑎
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Karnaugh Map
Three-variable maps
• Example
• Consider this example:
ab
c 00 01 11 10
0 1 0 1 1
* *
1 1 1 0 1
* *
w

𝑤 = 𝑎𝑐 + 𝑎𝑐 + 𝑏

• We consider the top and bottom rows of the map adjacent.

• Like that the paper is rolled and two columns reach each other.

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Karnaugh Map
Three-variable maps

• The stars shown in the above Karnaugh map show that the
particular map containing those stars would be an essential
choice, because those terms aren’t covered by any other map.

• In covering the 1s of a Karnaugh map we look to satisfy three

aims:
❖Covering all minterms
❖Fewer maps
❖Larger maps (In order to cover more 1s in one map)

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Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable maps
4-2-2 Definitions
4-2-3 Three variable maps
4-2-4 Four variable maps
4-2-5 Higher order variable maps
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
Four-variable maps
• We are moving on a torus.
• The dot-marked cells are adjacent.

ab
cd 00 01 11 10
00
0 4 12 8
01 9
1 5 13

11 3 7 15 11

10 2 6 14 10

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Karnaugh Map # a b c d w

Four-variable maps 0
1
0
0
0
0
0
0
0
1
1
1

2 0 0 1 0 1
• Consider this example :
3 0 0 1 1 1

4 0 1 0 0 1
ab
cd 00 01 11 10 5 0 1 0 1 1

00 1 1 0 1 6 0 1 1 0 0

7 0 1 1 1 1
01 1 1 0 1
PI, EPI 8 1 0 0 0 1

11 1 1 1 1 9 1 0 0 1 1
PI, EPI
10 1 0 1 0 1

10 1 0 0 1 11 1 0 1 1 1
PI, EPI
w 12 1 1 0 0 0

13 1 1 0 1 0

𝑤 = 𝑎. 𝑐 + 𝑐. 𝑑 + 𝑏 14 1 1 1 0 0

15 1 1 1 1 1

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Karnaugh Map
Four-variable maps
• Let’s do another example: ab
00 01 11 10
cd
00 1 1 0 0

01 1 1 1 1

11 0 0 0 1

10 1 0 0 1

w
ab ab
00 01 11 10 00 01 11 10 00 01 11 10
cd cd
00 1 1 0 0 1 1 0 0 1 1 0 0
00
01 1 1 1 1 1 1 1 1 1 1 1 1
01
11 0 0 0 1 0 0 0 1 0 0 0 1
11

10 1 0 0 1 1 0 0 1 1 0 0 1
10
w w
𝑤 = 𝑐. 𝑑 + 𝑎. 𝑐 + 𝑎. 𝑏. 𝑑 + 𝑏. 𝑐. 𝑑 𝑤 = 𝑐. 𝑑 + 𝑎. 𝑐 + 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏. 𝑑 𝑤 = 𝑐. 𝑑 + 𝑎. 𝑐 + 𝑎. 𝑏. 𝑐 + 𝑏. 𝑐. 𝑑

48
Karnaugh Map
Four-variable maps
• Consider this example :

ab
cd 00 01 11 10

00 1 0 0 1

01 0 0 1 1

11 0 0 1 0

10 1 0 0 1

𝑤 = 𝑎. 𝑏. 𝑑 + 𝑎. 𝑐. 𝑑 + 𝑏. 𝑑

49
Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable maps
4-2-2 Definitions
4-2-3 Three variable maps
4-2-4 Four variable maps
4-2-5 Higher order variable maps
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
Higher order variable maps
• A 5-variable K-map is made using two 4-variable K-maps.

• Each corresponding squares (cells) of these 2 4-variable K-maps are adjacent.

bc bc
de 00 01 11 10 00 01 11 10
de
00 1 0 0 0 0 0 0 0
00

01 1 1 0 0 01 0 1 0 0

11 1 0 1 1 11 1 0 1 1

1 0 1 1 10 1 0 1 1
10
a=0 a=1

𝑤 = 𝑏. 𝑑 + 𝑐. 𝑑 + 𝑏. 𝑐. 𝑑. 𝑒 + 𝑎. 𝑏. 𝑐
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Karnaugh Map
Higher order variable maps
• Cells in 6-variable map are adjacent to each other in all direction in 3-dimensions.
cd cd
00 01 11 10 00 01 11 10
• It is difficult to draw the maps. ef ef
00 00

01 01

10 10

11 11
a=0 a=1
cd cd
ef 00 01 11 10 00 01 11 10
ef
00 00

01 01

10 10

11 11
b=0 b=1
52
Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-2-1 Two variable maps
4-2-2 Definitions
4-2-3 Three variable maps
4-2-4 Four variable maps
4-2-5 Higher order variable maps
4-2-6 Don’t care
4-3 Maxterm
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Karnaugh Map
Don’t care
• In some functions, not all combinations of the variables can occur.

• To show this, consider a system with BCD values from 0 to 9.

• The circuit displays the BCD numbers on a 7-segment.

4 7
BCD Converter
Number

54
Karnaugh Map
Don’t care
• Outputs are one for the input BCD values that force the function to 1 (Active high
output)

• For other valid BCD values, the outputs are 0.

• For the invalid BCD values, the outputs’ values are not important.These are called
don’t cares. Invalid : 10, 11, 12, 13, 14, 15

55
Karnaugh Map
Don’t care
yz
wx 00 01 11 10

00 1 0 1 1

yz 01 0 1 1 1
wx 00 01 11 10

00 1 0 1 1 11
0 1 1 1 1 1
01 10

11 yz
wx 00 01 11 10
1 1 00 1 0 1 1
10

01 0 1 1 1

11
1 1
10
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Karnaugh Map
Don’t care
• Put “_” for the don’t care values.

• These terms need not to be covered necessarily and are only considered to be 1 if
they help us in covering a larger arena with certain maps.

• Don’t care terms can not be used to distinguish between implicants and prime
implicants.
yz yz
wx 00 01 11 10 01 10
wx 00 11
00 1 0 1 1 1 0 1 1
00
01 0 1 1 1 0 1 1 1
01

11 _ _ _ _
11
1 1 1 1 _ _
10 10

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Karnaugh Map
Don’t care
• Consider a system that detects prime numbers between 2 and 11.

ab ab
cd 00 01 11 10 00 01 11 10
cd
00 _ 0 _ 0 _ 0 _ 0
00

01 _ 1 _ 0 01 _ 1 _ 0

1 1 _ 1 1 1 _ 1
11 11
1 0 _ 0 1 0 _ 0
10 10

𝑤 = c. d + 𝑎. 𝑏 + 𝒂. 𝒅 𝑤 = c. d + 𝑎. 𝑏 + 𝒃𝒅

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Outline
4-1 Logic circuit realization
4-2 Karnaugh map
4-3 Maxterms
4-4 Timing
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Maxterms
• Consider the following example:

• As you can see writting the expression for 𝑤 is much easier.

# a b c w 𝑤

0 0 0 0 0 1
1 0 0 1 1 0

2 0 1 0 0 1

3 0 1 1 1 0

4 1 0 0 1 0

5 1 0 1 1 0

6 1 1 0 0 1

7 1 1 1 1 0

𝑤 = 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏. 𝑐 + 𝑎. 𝑏. 𝑐
𝑤 = 𝑎 + 𝑏 + 𝑐 . + 𝑎 + 𝑏 + 𝑐 . (𝑎 + 𝑏 + 𝑐)
𝑤 = ෑ 𝑀(0,2,6)
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Maxterms
ab ab
c 00 01 11 10 00 01 11 10
c
0 1 1 1 0 0 0 0 0 1

1 0 0 0 0 1 1 1 1 1
𝑤 w

𝑤 = 𝑎. 𝑐 + 𝑏. 𝑐

𝑤 = (𝑎. 𝑐). (𝑏. 𝑐) 𝑤 = 𝑎 + 𝑐 . (𝑏 + 𝑐)

𝑤 = 𝑎 + 𝑐 . (𝑏 + 𝑐)
Product of Sums
(POS)

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Maxterms
Maxterm example
ab
c 00 01 11 10
1 1 0 0
0

1 0 0 1 0
w

𝑤 = 𝑎 + 𝑏 + 𝑐 . 𝑎 + 𝑏 + 𝑐 . (𝑎 + 𝑏 + 𝑐). 𝑎 + 𝑏 + 𝑐 . 𝑎 + 𝑏 + 𝑐
w= 𝑎+𝑐 . 𝑎+𝑐 . 𝑎+𝑏

𝑤 = ෑ 𝑀(1,3,4,5,6)

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Outline

4-1 Logic circuit realization

4-2 Karnaugh Maps
4-3 Maxterm
4-4 Timing
4-4-1 Hazards
4-5 Tabular minimization

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Timing
Hazards

1
a
0
1
b
0
1
c
0
5 5
1
v
0
1 12 12
x
0
1 7 7
w
0
1 5
y
0
3

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Timing
Hazards
• When the input of the circuit changes from 111 to 101, there shouldn’t be any change in the
circuit’s output theoretically.

• The delay of one of the two paths which ‘b’ is passing through to reach the output is more
than the other.
1
a
0
1
b
0
1
c
0
5 5
1
v
0
1 12 12
x
0
1 7 7
w
0
1 5
y
0
3

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Timing
Hazards
• Therefore an unwanted pulse known as a glitch (or a 1-hazard in this case) is occurring where
the output drops to 0 for 5ns.

• Hazards occur when moving from shorter delay path to longer delay path.

1
a
0

shorter delay path=10 ns b

1
0
1
c
0
5 5
1
v
0
1 12 12
x
0
1 7 7
w
Longer delay path=15 ns 0
1 5
y
0
3

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Timing
Hazards
• The Boolean expression could not show us the hazards.

• What we want to know is how to identify and solve such problems before
they occur, that is why they are still potential hazards.

• Consider the Karnaugh map of the last example that we have:

ab
c 00 01 11 10
0 0 1 0
0

1 1 0 1 1
w

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Timing
Hazards

• There can only be a hazard where an input passes through to the output
by more than one path.

• That is, on the KM, potential hazards only occur when we move from one
1 to another when they are not covered in one map

ab
c 00 01 11 10
0 0 1 0
0

1 1 0 1 1
w

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Timing
Hazards

• The hazard explained above, is a static-1 hazard.

• Static-1 hazard: The output is currently 1 and after the inputs change,
the output momentarily changes to 0 before settling on 1.

• Static-0 hazard: The output is currently 0 and after the inputs change,
the output momentarily changes to 1 before settling on 0.

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Timing
Hazards
• Dynamic hazard is the possibility of an output changing
more than once.

• Dynamic hazards often occur in larger logic circuits where there are
different routes to the output (from the input).

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Timing
Hazards

• Whether or not this potential hazards turn into reality depends on

the actual gate timings
Logical Hazard
Is a potential hazard that actually occurs.
Duration, when it occurs and the transition
causing it define this type of hazard.

• Delay of the last gate determines this possibility.

Electrical Hazard
Is a logical hazard with a duration that is
larger than the last gate delay.
I.e., hazard duration
> RC delay of last gate.

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Timing
Hazards
• Let’s show these definitions in an example:
ab
cd 00 01 11 10
Potential hazards:
00 1 1 1
0111→0110
01 1 1
0100→1100
1101→1111
1 1 1 1
11 1001→1011
1 c d
10 a b

2 2 2
3

3
5
5

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Timing
Hazards
• Let’s show these definitions in an example:
a b c d
Potential hazards:
2 2 2
3 0111→0110
8ns 0100→1100
3 1101→1111
5
1001→1011
5 12ns
ab
cd 00 01 11 10
8ns 1 1 1
00
0111→0110 01 1 1

1 1 1 1
4ns 11
Logical hazard, no electrical hazard 1
10
4 ns< 5ns
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Timing
Hazards
• Let’s show these definitions in an example:
a b c d
Potential hazards:
2 2 2
3 0111→0110
8ns 0100→1100
3 1101→1111
5
1001→1011
5 12ns
ab
cd 00 01 11 10
8ns 00 1 1 1

0100→1100 01 1 1

1 1 1 1
4ns 11
1
Logical hazard, no electrical hazard 10
4 ns< 5ns 74
Timing
Hazards
• Let’s show these definitions in an example:
a b c d
Potential hazards:
2 2 2
3 0111→0110
10ns 0100→1100
3 8ns 1101→1111
5
1001→1011
5
ab
cd 00 01 11 10
8ns
00 1 1 1
1101→1111
01 1 1
1001→1011
2ns 1 1 1 1
11
Logical hazard, no electrical hazard 1
10
2 ns< 5ns 75
Timing
Hazards
• Let’s show these definitions in an example:
a b c d
Potential hazards:
2 2 2
3 0111→0110
10ns 0100→1100
3 8ns 1101→1111
5
1001→1011
5

8ns

1101→1111
1001→1011
2ns
Logical hazard, no electrical hazard
2 ns< 5ns 76
Timing
Hazards
• Use two-input NANDs only
a b c d Potential hazards:

0111→0110
0100→1100
1101→1111
1001→1011

ab
cd 00 01 11 10

00 1 1 1

01 1 1

1 1 1 1
11
1
10

77
Outline

4-1 Logic circuit realization

4-2 Karnaugh Maps
4-3 Maxterm
4-4 Timing
4-4-1 Hazards
4-5 Tabular minimization (QM method)
4-5-1 Start with Karnaugh map
4-5-2 Cubical representation
4-5-3 Setting a procedure
4-5-4 Obtaining PIs
4-5-5 Minimal coverage

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Tabular minimization (QM method)

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Tabular minimization (QM method)

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Tabular minimization (QM method)

ECE 367 Online lecture 81 81

Introduction to Digital System Design - Copyright Zainalabedin Navabi
Tabular minimization (QM method)

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Tabular minimization (QM method)

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Introduction to Digital System Design - Copyright Zainalabedin Navabi
Conclusion
We have covered these topics:

• Logic circuit realization

• Boolean algebra
• Karnaugh map
• Don’t care
• Maxterm
• Timing
• Tabular minimization

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