ELECTRICAL ENGINEERING DEPARTMENT

PRACTICAL WORK 3

DEC 50143: CMOS INTEGRATED CIRCUIT DESIGN AND

FABRICATION

PROGRAM: DTK
CLO2: Construct the layout design of CMOS circuits using layout design software
based on specific CMOS layout design rules.

CLO3: Demonstrate elements of environmental sustainability in implementing reduce

and reuse techniques in design parameters and design consideration through practical
work

(LD2) Practical Skills

___________________________________________________________________________

Prepared by: Checked by: Verified by

Name: Name: Name:

Date: 19.08.2022 Date: 19.08.2022 Date: 19.08.2022

 ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: I 2022/2023

DEC 50143 – CMOS INTEGRATED CIRCUIT DESIGN AND

FABRICATION
(PRACTICAL EVALUATION FORM, RESULTS,
DISCUSSIONS AND REFLECTION)

PRACTICAL WORK 3 LAYOUT DESIGN OF INVERTER

(CLO2/PLO5; CLO3/PLO7)

LECTURER NAME

GROUP NO.

STUDENT ID NAME

(1)

(2)

(3)

DATE SUBMIT : DATE RETURN :

 TITLE: LAYOUT DESIGN OF INVERTER

1 OBJECTIVES:
i) draw static CMOS inverter circuit using schematic editor
ii) draw stick diagram using suitable tools.
iii) design an inverter layout using Microwind software.

2 EQUIPMENT/TOOLS:
PC Set & Microwind software.

3 THEORY:

3.1 Inverter

The symbol and the truth table of an inverter or NOT gate:

A F
A F
0 1
1 0

Figure 3.1: Symbol and the truth table of an inverter

The schematic diagram of a CMOS inverter:

Figure 3.2: CMOS inverter

PMOS is placed close to VDD to pull-up the output. NMOS is placed close to ground to
pull down the output. Both Gate terminals of PMOS and NMOS are tied together to be
the input. The Drain terminals of PMOS and NMOS are connected to become the
output.
When Vin is high and equal to VDD, the NMOS transistor is ON, while the PMOS is OFF.
A direct path exists between Vout and the ground node, resulting in a steady-state value
of 0V. When the input voltage is low (0V), NMOS transistor is OFF, while PMOS
transistor is in ON. A direct path exists between VDD and Vout, resulting in a steady-state
value of VDD.

3.2 Propagation delay

From figure 3.2, when the input rises to logic 1, the output falls to logic 0, with a 5ps
delay (tpHL). When the input falls to logic 0, the output rises to logic 1, with a 15ps
delay.
The propagation delay (tp) of the inverter is determined by using the following equation:
tp = ( tpHL + tpLH ) / 2 = ( 5 ps + 15ps ) / 2 = 10 ps where

tpHL = the fall time or the time it takes to change from logic 1 to logic 0. tpLH = the rise time or the time it
takes to change from logic 0 to logic 1.

3.3 Layout optimized area

The optimized area of the layout is determined by the following:

Area = Layout Width x Layout Length = 33 x 54 = 1782 2
View the Voltage Transfer Curve (VTC) of the inverter by clicking the voltage vs. voltage
tab as shown in figure 3.2. The VTC of the inverter is shown in figure 3.3.

Figure 3.3: VTC of vertical CMOS inverter layout

When the input voltage is low (logic 0), the output voltage is high (logic ‘1’). As input
voltage increases, the output voltage decreases, and at the input voltage = VDD/2
boundary, the output voltage decreases abruptly. At that point, the value of input voltage
is the commutation or interchange point of the inverter, designated as Vc. As input
voltage is further increased towards VDD, the output voltage decreases to 0 V, which
corresponds to the logic ‘0’ of the inverter.
From figure, it is determined that VDD/2 = 0.6V, which resulted in Vc = 0.541V.
4 PROCEDURE:

Part 1: INVERTER

a) Draw static CMOS circuit for inverter.

b) Make a sketch of stick diagram based on a) answer.

Figure 4.1: Stick diagram

c) Open the Microwind Editor window. Select the Foundry file from File menu. Select
“cmos012.rul” file.
d) Draw P+ diffusion and N+ diffusion boxes for active region.

Figure 4.2: P+ diffusion and N+ diffusion

e) Draw Polysilicon box used for transistor gate.

Figure 4.2: Polysilicon

f) Draw Metal1 boxes on top and bottom act as a Vdd and Gnd.

Figure 4.3: Metal1

g) Draw a connections using Metal1 layer.

Figure 4.4: Connection for Metal1

h) Put a contact on two overlapping layers (actives and metal1)

Figure 4.5: P diffusion/ metal 1 contacts

 Figure 4.6: N diffusion/ metal 1 contacts

i) Create an input and output pad.

Figure 4.7: Input and output pad

 Figure 4.8: Input and output pad

j) Finally, draw N Well box around P+diff.

Figure 4.9: N Well box around P+diff

5 SIMULATION

Figure 5.1: Inverter simulation

a) Save your layout.

Apply a clock to the input. Click on the clock icon, and then click on the metal at the
gate. The clock menu appears, change the name to <<A>>.

b) Set the value of the input pulse as the following:

Time low = 0.2 ns
Time high = 0.2 ns
Rise time = Fall time = 0.001 ns
Click OK.
To watch the output, click on the Visible icon, and then click on the metal that
connects the Drains. Change the name to <<Output>>. Click OK. The Visible
property is then sent to the node.

c) Put VDD on N Well and Metal 1, then GND/VSS as shown on figure.

d) Simulate the inverter layout by selecting:

>Simulate> Run Simulation>Voltage vs Time (default) on the main menu. The
timing diagram of the inverter appear, as shown in figure 5.2.

e) Measure the optimized area of the layout (the unit is 𝑙𝑎𝑚𝑏𝑑𝑎 2).
 Figure 5.2: Timing diagram of vertical CMOS inverter layout

6 RESULTS (15 marks)

In your report, include the following:

a) Inverter layout. (5 marks)
b) Input / output timing diagram (5 marks)
c) Switching threshold voltage, Vc (5 marks)

7 DISCUSSION (10 marks)

a) Calculate layout optimized area for the layout. (4 marks)

b) Get a Vc of the circuit (3 marks)
c) Calculate propagation delay (3 marks)

8 CONCLUSION (5 marks)

Give a conclusion obtained from the practical work 3

(Conclude in detail the findings and the outcomes of this practical work.)

END OF PRACTICAL WORK

 Appendix A : Design Rules

1. Nwell Design Rules

r101 Minimum well size : 12 λ

r102 Between wells : 12 λ
r110 Minimum surface : 144 λ2

2. Diffusion Design Rules

r201 Minimum N+ and P+ diffusion width : 4 λ

r202 Between two P+ and N+ diffusions : 4 λ
r203 Extra nwell after P+ diffusion : 6 λ
r204 Between N+ diffusion and nwell : 6 λ
r205 Border of well after N+ polarization 2 λ
r206 Distance between Nwell and P+ polarization 6 λ
r210 Minimum surface : 24 λ2

3. Polysilicon Design Rules

r301 Polysilicon width : 2 λ

r302 Polysilicon gate on diffusion: 2 λ
r303 Polysilicon gate on diffusion for high
voltage MOS: 4 λ
r304 Between two polysilicon boxes : 3 λ
r305 Polysilicon vs. other diffusion : 2 λ
r306 Diffusion after polysilicon : 4 λ
r307 Extra gate after polysilicium : 3 λ
r310 Minimum surface : 8 λ2
4. Contact Design Rules

r401 Contact width : 2 λ

r402 Between two contacts : 5 λ
r403 Extra diffusion over contact: 2 λ
r404 Extra poly over contact: 2 λ
r405 Extra metal over contact: 2 λ
r406 Distance between contact & poly gate: 3 λ

5. Metal & Via Design Rules

r501 Metal width : 4 λ

r502 Between two metals : 4 λ
r510 Minimum surface : 32 λ2

r601 Via width : 2 λ

r602 Between two Via: 5 λ
r603 Between Via and contact: 0 λ
r604 Extra metal over via: 2 λ
r605 Extra metal2 over via: 2 λ

When r603=0, stacked via over

contact is allowed
 PRACTICAL EVALUATION FORM
PRACTICAL WORK 3

A. RUBRIC FOR PRACTICAL SKILL MARKS – 70%

Excellent Moderate Poor
Aspects Weight S1: S2: S3:
(5) (3) (1)

A Technology feature Use correct Use incorrect Did not use any
technology feature for technology feature technology feature. ___x 1 ___/10 ___/10 ___/10
the transistor layout. for the transistor
layout.

B Design rule Follow lambda design Follow lambda Follow lambda design
rule for minimum design rule for rule for ONLY a few ___x 1 ___/10 ___/10 ___/10
width and spacing for MANY of the of the polygons.
ALL polygons. polygons.

C Transistor size Use correct PMOS Use acceptable Use incorrect PMOS
___x 2 ___/10 ___/10 ___/10
and NMOS transistor PMOS and NMOS and NMOS transistor
size. transistor size. size.
Use correct number Use correct metal Use incorrect metal
D Metal layers of metal layers and layers but incorrect layers and width. ___x 2 ___/10 ___/10 ___/10
width. width.

E ‘No DRC error’ display Able to produce ‘No Able to produce ‘No Not able to produce
DRC error’ Able to DRC error’ display ‘No DRC error’ ___x 2 ___/10 ___/10 ___/10
produce ‘No DRC for some of the display at ALL.
error’ layouts.

F Layout Design – input / output / Produce good Produce Produce acceptable

floorplan floorplan and input / appropriate floorplan and input /
___x 2 ___/10 ___/10 ___/10
output layout design. floorplan and input / output layout design.
output layout
design.

G Layout simulation Able to produce the Able to produce the Not able to produce
simulation of ALL simulation or some any simulation for ___x 2 ___/10 ___/10 ___/10
layouts correctly. of the layouts ALL of the layouts.
correctly.
 H Layout size (end product) Produce small layout Produce acceptable Produce large layout
___x 2 ___/10 ___/10 ___/10
size (end product). layout size (end size (end product).
product).

PERCENTAGE = 70%