ELECTRICAL ENGINEERING DEPARTMENT

PRACTICAL WORK 4

DEC 50143: CMOS INTEGRATED CIRCUIT DESIGN AND

FABRICATION

PROGRAM: DTK
CLO2: Construct the layout design of CMOS circuits using layout design software
based on specific CMOS layout design rules.

CLO3: Demonstrate elements of environmental sustainability in implementing reduce

and reuse techniques in design parameters and design consideration through practical
work

(LD2) Practical Skills

___________________________________________________________________________

Prepared by: Checked by: Verified by

Name: Name: Name:

Date: 19.08.2022 Date: 19.08.2022 Date: 19.08.2022

 ELECTRICAL ENGINEERING DEPARTMENT

ACADEMIC SESSION: I 2022/2023

DEC 50143 – CMOS INTEGRATED CIRCUIT DESIGN AND

FABRICATION
(PRACTICAL EVALUATION FORM, RESULTS,
DISCUSSIONS AND REFLECTION)

PRACTICAL WORK 4 LAYOUT DESIGN AND SIMULATION OF BASIC

(CLO2/PLO5; CLO3/PLO7) LOGIC GATES

LECTURER NAME

GROUP NO.

STUDENT ID NAME

(1)

(2)

(3)

DATE SUBMIT : DATE RETURN :

 TITLE: LAYOUT DESIGN AND SIMULATION OF BASIC LOGIC GATES

1 OBJECTIVES:
i) to design the layout of the following logic gates 2-input NAND gate and 2-input
AND gate
ii) to simulate the layout of each gate in (i)

2 EQUIPMENT/TOOLS:
PC Set & Microwind software.

3 THEORY:

3.1 Complementary CMOS

A static CMOS gate is a combination of two networks, called the pull-up network (PUN)
and the pull-down network (PDN) (Figure 3.1). The function of the PUN is to provide a
connection between the output and VDD anytime the output of the logic gate is meant
to be 1 (based on the inputs). Similarly, the function of the PDN is to connect the output
to VSS when the output of the logic gate is meant to be 0. The PUN and PDN networks
are constructed in a mutually exclusive fashion such that one and only one of the
networks is conducting in steady state. In this way, once the transients have settled, a
path always exists between VDD and the output F, realizing a high output (“one”), or,
alternatively, between VSS and F for a low output (“zero”). This is equivalent to stating
that the output node is always a low-impedance node in steady state.

Figure 3.1: Complementary logic gate as a combination of a PUN (pull-up network) and a
PDN (pull-down network)
4 PROCEDURE:

Part 1: Designing and simulating the layout of 2 input NAND gate.

Figure 4.1: Symbol of 2-input NAND gate

Figure 4.2: CMOS static logic diagram of

2-input NAND gate

a) Based on Figure 4.2, draw the stick diagram of 2 input NAND gate using Euler’s
path method.

Figure 4.3: Stick diagram of 2-input NAND gate

b) Open the Microwind Editor window.

c) Select the Foundry file from File menu. Select “cmos012.rul” file.

d) Draw the layout of 2-input NAND gate based on the stick diagram in Figure 4.3.

Use: NMOS size - W=6λ, L=2λ

PMOS size - W=12λ, L=2λ

Figure 4.4: Layout of 2 input NAND gate

e) Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker

f) Add clock to input A and input B of the layout. To observe the output, place a Visible
Node icon at the output.

g) Let’s set the value for of the pulse at input A as the following:
Time low = 0.2 ns
Time high = 0.2 ns
Rise time = Fall time = 0.001 ns

h) Click OK.

i) Let’s set the value for of the pulse at input B as the following:
Time low = 0.4 ns
Time high = 0.4 ns
 Rise time = Fall time = 0.001 ns

j) Click OK.

k) Save your layout.

l) Simulate the inverter layout by selecting:

>Simulate> Run Simulation>Voltage vs Time (default) on the main menu. The

timing diagram of the 2 input NAND gate appear, as shown in Figure 4.5.

Figure 4.2: Polysilicon

Figure 4.5: Timing diagram of 2-input NAND gate

m) Produce the truth table for 2-input NAND gate based on the timing diagram
produced in step 8. The truth table for 2-input NAND gate is shown in Figure 4.6.

A B F
0 0 1
0 1 1
1 0 1
1 1 0

Figure 4.6: Truth table of 2-input NAND gate

n) Measure the optimized area of the layout (the unit is λ2).

Part 2: Designing and simulating the layout of 2-input AND gate.

Figure 4.7: Symbol of 2-input AND gate

Figure 4.8: CMOS static logic diagram of 2-Input AND gate

a) Based on Figure 4.8, draw the stick diagram for 2-input AND gate using Euler’s path
method.

Figure 4.9: Stick diagram of 2-input AND gate

b) Open the Microwind Editor window.

c) Select the Foundry file from File menu. Select “cmos012.rul” file.

d) Draw the layout of 2-input NAND gate based on the stick diagram in Figure 4.3.

Use: NMOS size - W=6λ, L=2λ

PMOS size - W=12λ, L=2λ

Figure 4.10: Layout of 2 input AND gate

e) Make sure that your layout conforms to all the design rules.
Run DRC by selecting:
>Analysis>Design Rule Checker

f) Add clock to input A and input B of the layout. To observe the output, add Visible
Node icon at the output. (The settings of the clock pulses are the same as in Part
A)

g) Save your layout.

h) Simulate the inverter layout by selecting:

>Simulate> Run Simulation>Voltage vs Time (default) on the main menu.
The timing diagram of the 2-input AND gate appear, as shown in Figure 4.11.
 Figure 4.11: Timing diagram of 2-input AND gate

i) Produce the truth table for 2-input AND gate based on the timing diagram produced
in step 8. The truth table for 2-input AND gate is shown in Figure 4.12.

A B F
0 0 0
0 1 0
1 0 0
1 1 1

Figure 4.12: Truth table of 2-input AND gate

j) Measure the optimized area of the layout (the unit is 𝜆 2 ).

5 RESULTS (16 marks)

In your report, include the following:

1. 2-input NAND gate:
a) CMOS static logic diagram (1 mark)
b) Stick diagram (1 mark)
c) Layout (2 marks)
d) Timing diagram (1 mark)
e) Truth table (1 mark)
f) Optimized layout area = _________ 𝜆 x _________ 𝜆
_________ 𝜆 2 (2 marks)
 2. 2-input AND gate:
a) CMOS static logic diagram (1 mark)
b) Stick diagram (1 mark)
c) Layout (2 marks)
d) Timing diagram (1 mark)
e) Truth table (1 mark)
f) Optimized layout area = _________ 𝜆 x _________ 𝜆
_________ 𝜆 2 (2 marks)

6 DISCUSSION (9 marks)

a) Explain the terminology ‘technology feature’. (3 marks)

b) Describe the difference between micron and lambda unit in layout design process.
(4 marks)

c) Explain the function of Polysilicon layers in CMOS design layout?

(2 marks)

7 CONCLUSION (5 marks)

Give a conclusion obtained from the practical work 4

(Conclude in detail the findings and the outcomes of this practical work.)
 END OF PRACTICAL WORK
Appendix A : Design Rules

1. Nwell Design Rules

r101 Minimum well size : 12 λ

r102 Between wells : 12 λ
r110 Minimum surface : 144 λ2

2. Diffusion Design Rules

r201 Minimum N+ and P+ diffusion width : 4 λ

r202 Between two P+ and N+ diffusions : 4 λ
r203 Extra nwell after P+ diffusion : 6 λ
r204 Between N+ diffusion and nwell : 6 λ
r205 Border of well after N+ polarization 2 λ
r206 Distance between Nwell and P+ polarization 6
λ
r210 Minimum surface : 24 λ2

3. Polysilicon Design Rules

r301 Polysilicon width : 2 λ

r302 Polysilicon gate on diffusion: 2 λ
r303 Polysilicon gate on diffusion for high
voltage MOS: 4 λ
r304 Between two polysilicon boxes : 3 λ
r305 Polysilicon vs. other diffusion : 2 λ
r306 Diffusion after polysilicon : 4 λ
r307 Extra gate after polysilicium : 3 λ
r310 Minimum surface : 8 λ2
4. Contact Design Rules

r401 Contact width : 2 λ

r402 Between two contacts : 5 λ
r403 Extra diffusion over contact: 2 λ
r404 Extra poly over contact: 2 λ
r405 Extra metal over contact: 2 λ
r406 Distance between contact & poly gate: 3 λ

5. Metal & Via Design Rules

r501 Metal width : 4 λ

r502 Between two metals : 4 λ
r510 Minimum surface : 32 λ2

r601 Via width : 2 λ

r602 Between two Via: 5 λ
r603 Between Via and contact: 0 λ
r604 Extra metal over via: 2 λ
r605 Extra metal2 over via: 2 λ

When r603=0, stacked via over

contact is allowed
 PRACTICAL EVALUATION FORM
PRACTICAL WORK 4

A. RUBRIC FOR PRACTICAL SKILL MARKS – 70%

Excellent Moderate Poor
Aspects Weight S1: S2: S3:
(5) (3) (1)

A Technology feature Use correct Use incorrect Did not use any
technology feature for technology feature technology feature. ___x 1 ___/10 ___/10 ___/10
the transistor layout. for the transistor
layout.

B Design rule Follow lambda design Follow lambda Follow lambda design
rule for minimum design rule for rule for ONLY a few ___x 1 ___/10 ___/10 ___/10
width and spacing for MANY of the of the polygons.
ALL polygons. polygons.

C Transistor size Use correct PMOS Use acceptable Use incorrect PMOS
___x 2 ___/10 ___/10 ___/10
and NMOS transistor PMOS and NMOS and NMOS transistor
size. transistor size. size.
Use correct number Use correct metal Use incorrect metal
D Metal layers of metal layers and layers but incorrect layers and width. ___x 2 ___/10 ___/10 ___/10
width. width.

E ‘No DRC error’ display Able to produce ‘No Able to produce ‘No Not able to produce
DRC error’ Able to DRC error’ display ‘No DRC error’ ___x 2 ___/10 ___/10 ___/10
produce ‘No DRC for some of the display at ALL.
error’ layouts.

F Layout Design – input / output / Produce good Produce Produce acceptable

floorplan floorplan and input / appropriate floorplan and input /
___x 2 ___/10 ___/10 ___/10
output layout design. floorplan and input / output layout design.
output layout
design.

G Layout simulation Able to produce the Able to produce the Not able to produce
simulation of ALL simulation or some any simulation for ___x 2 ___/10 ___/10 ___/10
layouts correctly. of the layouts ALL of the layouts.
correctly.
 H Layout size (end product) Produce small layout Produce acceptable Produce large layout
___x 2 ___/10 ___/10 ___/10
size (end product). layout size (end size (end product).
product).

PERCENTAGE = 70%