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PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture Technical
Reference Manual (TRM) PSoC 61, PSoC 62 MCU

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture

Technical Reference Manual (TRM)

PSoC 61, PSoC 62 MCU

Document No. 002-24529 Rev. *I
September 6, 2023

Cypress Semiconductor
An Infineon Technologies Company
198 Champion Court
San Jose, CA 95134-1709
www.cypress.com
www.infineon.com
Copyrights
© Cypress Semiconductor Corporation, 2018-2023. This document is the property of Cypress Semiconductor Corporation, an
Infineon Technologies company, and its affiliates ("Cypress"). This document, including any software or firmware included or
referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United
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specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with
Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable
license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code
form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your
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solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
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TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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PRODUCTS, OR SYSTEMS CREATED USING CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK,
VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively,
"Security Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release
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Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other medical devices. "Critical
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or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of a
Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, including its affiliates,
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and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage
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Cypress has given you advance written authorization to use the product as a Critical Component in the specific High-Risk
Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, Traveo, WICED, and
ModusToolbox are trademarks or registered trademarks of Cypress or a subsidiary of Cypress in the United States or in other
countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as
property of their respective owners.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 2
 Content Overview

Section A: Overview 18
1. Introduction ........................................................................................................... 19
2. Getting Started ...................................................................................................... 25
3. Document Organization and Conventions ............................................................... 26

Section B: CPU Subsystem 30

4. CPU Subsystem (CPUSS) ..................................................................................... 32
5. SRAM Controller ................................................................................................... 39
6. Inter-Processor Communication ............................................................................. 41
7. Fault Monitoring .................................................................................................... 49
8. Interrupts .............................................................................................................. 56
9. Protection Units ..................................................................................................... 73
10. DMA Controller (DW) ............................................................................................. 91
11. DMAC Controller (DMAC) .................................................................................... 102
12. Cryptographic Function Block (Crypto) ................................................................. 111
13. Program and Debug Interface .............................................................................. 154
14. Nonvolatile Memory ............................................................................................. 164
15. Boot Code ........................................................................................................... 193
16. eFuse Memory .................................................................................................... 210
17. Device Security ................................................................................................... 212

Section C: System Resources Subsystem (SRSS) 217

18. Power Supply and Monitoring .............................................................................. 218
19. Device Power Modes ........................................................................................... 225
20. Backup System ................................................................................................... 235
21. Clocking System .................................................................................................. 242
22. Reset System ...................................................................................................... 257
23. I/O System .......................................................................................................... 261
24. Watchdog Timer .................................................................................................. 283
25. Trigger Multiplexer Block ..................................................................................... 294
26. Profiler ................................................................................................................ 299

Section D: Digital Subsystem 305

27. Secure Digital Host Controller (SDHC) ................................................................. 307
28. Serial Communications Block (SCB) .................................................................... 318
29. Serial Memory Interface (SMIF) ........................................................................... 375

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 Content Overview

30. Timer, Counter, and PWM (TCPWM) .................................................................... 392

31. Inter-IC Sound Bus .............................................................................................. 429
32. PDM-PCM Converter ........................................................................................... 441
33. Universal Serial Bus (USB) Device Mode ............................................................. 450
34. Universal Serial Bus (USB) Host .......................................................................... 466
35. LCD Direct Drive ................................................................................................. 483

Section E: Analog Subsystem 496

36. Analog Reference Block ...................................................................................... 497
37. Low-Power Comparator ....................................................................................... 501
38. SAR ADC ............................................................................................................ 506
39. Temperature Sensor ............................................................................................ 520
40. CapSense ........................................................................................................... 524

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 Contents

Section A: Overview 18
1. Introduction 19
1.1 Features..................................................................................................................................19
1.2 PSoC 61 and PSoC 62 MCU Series Differences ...................................................................22
1.3 Architecture.............................................................................................................................22
2. Getting Started 25
2.1 PSoC 6 MCU Resources ........................................................................................................25
3. Document Organization and Conventions 26
3.1 Major Sections ........................................................................................................................26
3.2 Documentation Conventions...................................................................................................26
3.2.1 Register Conventions.............................................................................................26
3.2.2 Numeric Naming ....................................................................................................26
3.2.3 Units of Measure....................................................................................................27
3.2.4 Acronyms and Initializations ..................................................................................27
Section B: CPU Subsystem 30
4. CPU Subsystem (CPUSS) 32
4.1 Features..................................................................................................................................32
4.2 Architecture.............................................................................................................................33
4.2.1 Address and Memory Maps ...................................................................................34
4.3 Registers.................................................................................................................................35
4.4 Operating Modes and Privilege Levels ...................................................................................37
4.5 Instruction Set.........................................................................................................................38
5. SRAM Controller 39
5.1 Features..................................................................................................................................39
5.2 Architecture.............................................................................................................................39
5.3 Wait States .............................................................................................................................40
6. Inter-Processor Communication 41
6.1 Features..................................................................................................................................42
6.2 Architecture.............................................................................................................................42
6.2.1 IPC Channel...........................................................................................................42
6.2.2 IPC Interrupt...........................................................................................................43
6.2.3 IPC Channels and Interrupts..................................................................................43
6.3 Implementing Locks................................................................................................................44
6.4 Message Passing ...................................................................................................................44
6.5 Typical Usage Models ............................................................................................................46
6.5.1 Full Duplex Communication ...................................................................................46
6.5.2 Half Duplex with Independent Event Handling.......................................................47
6.5.3 Half Duplex with Shared Event Handling ...............................................................47

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 Contents

7. Fault Monitoring 49
7.1 Features..................................................................................................................................49
7.2 Architecture.............................................................................................................................50
7.2.1 Fault Report ...........................................................................................................50
7.2.2 Signaling Interface .................................................................................................52
7.2.3 Monitoring ..............................................................................................................52
7.2.4 Low-power Mode Operation...................................................................................53
7.2.5 Using a Fault Structure ..........................................................................................53
7.2.6 CPU Exceptions Versus Fault Monitoring ..............................................................53
7.3 Fault Sources..........................................................................................................................54
7.4 Register List............................................................................................................................55
8. Interrupts 56
8.1 Features..................................................................................................................................56
8.2 Architecture.............................................................................................................................57
8.3 Interrupts and Exceptions - Operation ....................................................................................58
8.3.1 Interrupt/Exception Handling..................................................................................58
8.3.2 Level and Pulse Interrupts .....................................................................................59
8.3.3 Exception Vector Table ..........................................................................................59
8.4 Exception Sources..................................................................................................................60
8.4.1 Reset Exception.....................................................................................................60
8.4.2 Non-Maskable Interrupt Exception.........................................................................60
8.4.3 HardFault Exception ..............................................................................................61
8.4.4 Memory Management Fault Exception ..................................................................61
8.4.5 Bus Fault Exception ...............................................................................................61
8.4.6 Usage Fault Exception...........................................................................................61
8.4.7 Supervisor Call (SVCall) Exception .......................................................................62
8.4.8 PendSupervisory (PendSV) Exception ..................................................................62
8.4.9 System Tick (SysTick) Exception ...........................................................................62
8.5 Interrupt Sources ....................................................................................................................62
8.6 Interrupt/Exception Priority .....................................................................................................69
8.7 Enabling and Disabling Interrupts...........................................................................................69
8.8 Interrupt/Exception States ......................................................................................................70
8.8.1 Pending Interrupts/Exceptions ...............................................................................70
8.9 Stack Usage for Interrupts/Exceptions ...................................................................................71
8.10 Interrupts and Low-Power Modes...........................................................................................71
8.11 Interrupt/Exception – Initialization/ Configuration ...................................................................71
8.12 Register List............................................................................................................................72
9. Protection Units 73
9.1 Architecture.............................................................................................................................73
9.2 PSoC 6 Protection Architecture ..............................................................................................74
9.3 Register Architecture ..............................................................................................................76
9.3.1 Protection Structure and Attributes ........................................................................76
9.4 Bus Master Protection Attributes ............................................................................................79
9.5 Protection Context ..................................................................................................................79
9.6 Protection Contexts 0, 1, 2, 3 .................................................................................................80
9.7 Protection Structure ................................................................................................................81
9.7.1 Protection Violation ................................................................................................81
9.7.2 MPU .......................................................................................................................81
9.7.3 SMPU.....................................................................................................................81
9.7.4 PPU........................................................................................................................82
9.7.5 Protection of Protection Structures ........................................................................89

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 Contents

9.7.6 Protection Structure Types.....................................................................................89

10. DMA Controller (DW) 91
10.1 Features..................................................................................................................................91
10.2 Architecture.............................................................................................................................92
10.3 Channels.................................................................................................................................92
10.3.1 Channel Interrupts .................................................................................................93
10.4 Descriptors..............................................................................................................................94
10.4.1 Address Configuration ...........................................................................................96
10.4.2 Transfer Size..........................................................................................................97
10.4.3 Descriptor Chaining ...............................................................................................98
10.5 DMA Controller .......................................................................................................................99
10.5.1 Trigger Selection ....................................................................................................99
10.5.2 Pending Triggers....................................................................................................99
10.5.3 Output Triggers ......................................................................................................99
10.5.4 Status registers ......................................................................................................99
10.5.5 DMA Performance................................................................................................100
11. DMAC Controller (DMAC) 102
11.1 Features................................................................................................................................102
11.2 Architecture...........................................................................................................................103
11.3 Channels...............................................................................................................................103
11.3.1 Channel Interrupts ...............................................................................................104
11.4 Descriptors............................................................................................................................105
11.4.1 Address Configuration .........................................................................................107
11.4.2 Transfer Size........................................................................................................109
11.4.3 Descriptor Chaining .............................................................................................109
11.5 DMAC Controller...................................................................................................................110
11.5.1 Trigger Selection ..................................................................................................110
11.5.2 Channel Logic ......................................................................................................110
11.5.3 Output Triggers ....................................................................................................110
12. Cryptographic Function Block (Crypto) 111
12.1 Features................................................................................................................................111
12.2 Architecture...........................................................................................................................112
12.3 Instruction Controller.............................................................................................................113
12.3.1 Instructions...........................................................................................................113
12.3.2 Instruction Operands............................................................................................113
12.3.3 Load and Store FIFO Instructions........................................................................114
12.3.4 Register Buffer Instructions..................................................................................115
12.4 Hash Algorithms ...................................................................................................................119
12.4.1 SHA1 and SHA2 ..................................................................................................119
12.4.2 SHA3....................................................................................................................122
12.5 DES and TDES.....................................................................................................................123
12.6 AES.......................................................................................................................................125
12.7 CRC ......................................................................................................................................127
12.8 PRNG ...................................................................................................................................129
12.9 TRNG....................................................................................................................................130
12.10 Vector Unit ............................................................................................................................136
12.10.1 VU Register File...................................................................................................137
12.10.2 Stack ....................................................................................................................138
12.10.3 Memory Operands ...............................................................................................139
12.10.4 Datapath ..............................................................................................................139

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 Contents

12.10.5 Status Register ....................................................................................................140

12.10.6 Instructions...........................................................................................................141
12.10.7 Instruction Set ......................................................................................................141
13. Program and Debug Interface 154
13.1 Features................................................................................................................................154
13.2 Architecture...........................................................................................................................154
13.2.1 Debug Access Port (DAP)....................................................................................156
13.2.2 ROM Tables .........................................................................................................156
13.2.3 Trace ....................................................................................................................156
13.2.4 Embedded Cross Triggering ................................................................................157
13.3 Serial Wire Debug (SWD) Interface......................................................................................157
13.3.1 SWD Timing Details .............................................................................................158
13.3.2 ACK Details..........................................................................................................158
13.3.3 Turnaround (Trn) Period Details ..........................................................................159
13.4 JTAG Interface......................................................................................................................159
13.5 Programming the PSoC 6 MCU............................................................................................162
13.5.1 SWD Port Acquisition...........................................................................................162
13.5.2 SWD Programming Mode Entry...........................................................................162
13.5.3 SWD Programming Routine Executions ..............................................................162
13.6 Registers...............................................................................................................................163
14. Nonvolatile Memory 164
14.1 Flash Memory .......................................................................................................................164
14.1.1 Features...............................................................................................................164
14.1.2 Configuration........................................................................................................164
14.1.3 Flash Geometry ...................................................................................................165
14.1.4 Flash Controller....................................................................................................166
14.1.5 Read While Write (RWW) Support.......................................................................167
14.2 Flash Memory Programming ................................................................................................167
14.2.1 Features...............................................................................................................167
14.2.2 Architecture..........................................................................................................167
14.3 System Call Implementation .................................................................................................169
14.3.1 System Call via CM0+ or CM4.............................................................................169
14.3.2 System Call via DAP............................................................................................169
14.3.3 Exiting from a System Call...................................................................................169
14.3.4 SRAM Usage .......................................................................................................169
14.4 SROM API Library ................................................................................................................170
14.5 System Calls.........................................................................................................................171
14.5.1 Cypress ID ...........................................................................................................171
14.5.2 Blow eFuse Bit .....................................................................................................173
14.5.3 Read eFuse Byte .................................................................................................174
14.5.4 Write Row ............................................................................................................175
14.5.5 Program Row .......................................................................................................176
14.5.6 Erase All...............................................................................................................178
14.5.7 Checksum ............................................................................................................179
14.5.8 FmTransitionToLpUlp ...........................................................................................180
14.5.9 Compute Hash .....................................................................................................181
14.5.10 ConfigureRegionBulk ...........................................................................................182
14.5.11 DirectExecute.......................................................................................................183
14.5.12 Erase Sector ........................................................................................................183
14.5.13 Soft Reset ............................................................................................................184
14.5.14 Erase Row ...........................................................................................................185

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 Contents

14.5.15 Erase Subsector ..................................................................................................186

14.5.16 GenerateHash......................................................................................................187
14.5.17 ReadUniqueID .....................................................................................................188
14.5.18 CheckFactoryHash ..............................................................................................188
14.5.19 TransitionToRMA..................................................................................................189
14.5.20 ReadFuseByteMargin ..........................................................................................190
14.5.21 TransitionToSecure ..............................................................................................191
14.6 System Call Status ...............................................................................................................192
15. Boot Code 193
15.1 Features................................................................................................................................193
15.2 ROM Boot .............................................................................................................................193
15.2.1 Data Integrity Checks...........................................................................................193
15.2.2 Life-cycle Stages and Protection States ..............................................................196
15.2.3 Secure Boot in ROM Boot....................................................................................199
15.2.4 Protection Setting.................................................................................................199
15.2.5 SWD/JTAG Repurposing .....................................................................................201
15.2.6 Waking up from Hibernate ...................................................................................201
15.2.7 Disable Watchdog Timer ......................................................................................201
15.2.8 ROM Boot Flow Chart..........................................................................................201
15.3 Flash Boot.............................................................................................................................203
15.3.1 Overview ..............................................................................................................203
15.3.2 Features of Flash Boot.........................................................................................203
15.3.3 Using Flash Boot..................................................................................................203
15.3.4 Flash Boot Layout ................................................................................................203
15.3.5 Flash Boot Flow Chart .........................................................................................204
16. eFuse Memory 210
16.1 Features................................................................................................................................210
16.2 Architecture...........................................................................................................................210
17. Device Security 212
17.1 Features................................................................................................................................212
17.2 Architecture...........................................................................................................................212
17.2.1 Life Cycle Stages and Protection States..............................................................212
17.2.2 Flash Security ......................................................................................................216
17.2.3 Hardware-Based Encryption ................................................................................216
Section C: System Resources Subsystem (SRSS) 217
18. Power Supply and Monitoring 218
18.1 Features................................................................................................................................218
18.2 Architecture...........................................................................................................................219
18.3 Power Supply........................................................................................................................220
18.3.1 Regulators Summary ...........................................................................................220
18.3.2 Power Pins and Rails...........................................................................................222
18.3.3 Power Sequencing Requirements .......................................................................222
18.3.4 Backup Domain....................................................................................................222
18.3.5 Power Supply Sources.........................................................................................222
18.4 Voltage Monitoring................................................................................................................222
18.4.1 Power-On-Reset (POR) .......................................................................................222
18.4.2 Brownout-Detect (BOD) .......................................................................................222
18.4.3 Low-Voltage-Detect (LVD) ...................................................................................223
18.4.4 Over-Voltage Protection (OVP)............................................................................224

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 Contents

18.5 Register List .........................................................................................................................224

19. Device Power Modes 225
19.1 Features................................................................................................................................225
19.2 Architecture...........................................................................................................................225
19.2.1 CPU Power Modes ..............................................................................................227
19.2.2 System Power Modes ..........................................................................................227
19.2.3 System Deep Sleep Mode ...................................................................................227
19.2.4 System Hibernate Mode ......................................................................................228
19.2.5 Other Operation Modes .......................................................................................228
19.3 Power Mode Transitions .......................................................................................................229
19.3.1 Power-up Transitions ...........................................................................................230
19.3.2 Power Mode Transitions ......................................................................................230
19.3.3 Wakeup Transitions .............................................................................................232
19.4 Summary ..............................................................................................................................233
19.5 Register List..........................................................................................................................233
20. Backup System 235
20.1 Features................................................................................................................................235
20.2 Architecture...........................................................................................................................236
20.3 Power Supply........................................................................................................................236
20.4 Clocking ................................................................................................................................237
20.4.1 WCO with External Clock/Sine Wave Input .........................................................237
20.4.2 Calibration............................................................................................................237
20.5 Reset ....................................................................................................................................238
20.6 Real-Time Clock ...................................................................................................................238
20.6.1 Reading RTC User Registers ..............................................................................238
20.6.2 Writing to RTC User Registers.............................................................................238
20.7 Alarm Feature .......................................................................................................................239
20.8 PMIC Control ........................................................................................................................240
20.9 Backup Registers..................................................................................................................241
20.10 Register List..........................................................................................................................241
21. Clocking System 242
21.1 Features................................................................................................................................242
21.2 Architecture...........................................................................................................................243
21.3 Clock Sources.......................................................................................................................244
21.3.1 Internal Main Oscillator (IMO) ..............................................................................244
21.3.2 External Crystal Oscillator (ECO) ........................................................................244
21.3.3 External Clock (EXTCLK) ....................................................................................244
21.3.4 Internal Low-speed Oscillator (ILO) .....................................................................244
21.3.5 Watch Crystal Oscillator (WCO)...........................................................................245
21.4 Clock Generation ..................................................................................................................245
21.4.1 Phase-Locked Loop (PLL) ...................................................................................245
21.4.2 Frequency Lock Loop (FLL).................................................................................246
21.5 Clock Trees...........................................................................................................................251
21.5.1 Path Clocks..........................................................................................................251
21.5.2 High-Frequency Root Clocks ...............................................................................251
21.5.3 Low-Frequency Clock ..........................................................................................252
21.5.4 Timer Clock ..........................................................................................................252
21.5.5 Group Clocks (clk_sys) ........................................................................................252
21.5.6 Backup Clock (clk_bak) .......................................................................................252
21.6 CLK_HF[0] Distribution .........................................................................................................253

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21.6.1 CLK_FAST ...........................................................................................................253

21.6.2 CLK_PERI............................................................................................................253
21.6.3 CLK_SLOW .........................................................................................................253
21.7 Peripheral Clock Dividers .....................................................................................................253
21.7.1 Fractional Clock Dividers .....................................................................................253
21.7.2 Peripheral Clock Divider Configuration ................................................................253
21.8 Clock Calibration Counters ...................................................................................................256
22. Reset System 257
22.1 Features................................................................................................................................257
22.2 Architecture...........................................................................................................................257
22.2.1 Power-on Reset ...................................................................................................258
22.2.2 Brownout Reset ...................................................................................................258
22.2.3 Watchdog Timer Reset ........................................................................................258
22.2.4 Software Initiated Reset.......................................................................................259
22.2.5 External Reset .....................................................................................................259
22.2.6 Logic Protection Fault Reset................................................................................259
22.2.7 Clock-Supervision Logic Reset ............................................................................259
22.2.8 Hibernate Wakeup Reset .....................................................................................259
22.3 Identifying Reset Sources.....................................................................................................259
22.4 Register List..........................................................................................................................260
23. I/O System 261
23.1 Features................................................................................................................................261
23.2 Architecture...........................................................................................................................262
23.2.1 I/O Cell Architecture .............................................................................................263
23.2.2 Digital Input Buffer ...............................................................................................263
23.2.3 Digital Output Driver.............................................................................................264
23.3 High-Speed I/O Matrix ..........................................................................................................267
23.4 I/O State on Power Up..........................................................................................................269
23.5 Behavior in Low-Power Modes .............................................................................................269
23.6 Interrupt ................................................................................................................................269
23.7 Peripheral Connections ........................................................................................................270
23.7.1 Firmware-Controlled GPIO ..................................................................................270
23.7.2 Analog I/O ............................................................................................................271
23.7.3 LCD Drive ............................................................................................................271
23.7.4 CapSense ............................................................................................................271
23.8 Smart I/O .............................................................................................................................271
23.8.1 Overview ..............................................................................................................271
23.8.2 Block Components...............................................................................................272
23.8.3 Routing.................................................................................................................279
23.8.4 Operation .............................................................................................................281
23.9 Registers...............................................................................................................................282
24. Watchdog Timer 283
24.1 Features................................................................................................................................283
24.2 Architecture...........................................................................................................................283
24.3 Free-running WDT ................................................................................................................284
24.3.1 Overview ..............................................................................................................284
24.3.2 Watchdog Reset ..................................................................................................286
24.3.3 Watchdog Interrupt ..............................................................................................286
24.4 Multi-Counter WDTs .............................................................................................................287
24.4.1 Overview ..............................................................................................................287

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24.4.2 Enabling and Disabling WDT ...............................................................................290

24.4.3 Watchdog Cascade Options ................................................................................291
24.4.4 MCDWT Reset.....................................................................................................292
24.4.5 MCWDT Interrupt.................................................................................................292
24.5 Reset Cause Detection.........................................................................................................293
24.6 Register List..........................................................................................................................293
25. Trigger Multiplexer Block 294
25.1 Features................................................................................................................................294
25.2 Architecture...........................................................................................................................294
25.2.1 Trigger Multiplexer Group ....................................................................................295
25.2.2 One-to-one Trigger...............................................................................................295
25.2.3 Trigger Multiplexer Block .....................................................................................295
25.2.4 Software Triggers.................................................................................................297
25.3 Register List ........................................................................................................................298
26. Profiler 299
26.1 Features................................................................................................................................299
26.2 Architecture...........................................................................................................................300
26.2.1 Profiler Design .....................................................................................................300
26.2.2 Available Monitoring Sources ..............................................................................301
26.2.3 Reference Clocks.................................................................................................301
26.3 Using the Profiler ..................................................................................................................302
26.3.1 Enable or Disable the Profiler ..............................................................................302
26.3.2 Configure and Enable a Counter .........................................................................303
26.3.3 Start and Stop Profiling ........................................................................................303
26.3.4 Handle Counter Overflow.....................................................................................303
26.3.5 Get the Results ....................................................................................................304
26.3.6 Exit Gracefully......................................................................................................304
Section D: Digital Subsystem 305
27. Secure Digital Host Controller (SDHC) 307
27.1 Features................................................................................................................................307
27.1.1 Features Not Supported.......................................................................................308
27.2 Block Diagram ......................................................................................................................308
27.3 Clocking ................................................................................................................................309
27.3.1 Clock Gating ........................................................................................................309
27.3.2 Base Clock (CLK_HF[i]) Configuration ................................................................309
27.3.3 Card Clock (SDCLK) Configuration .....................................................................309
27.3.4 Timeout (TOUT) Configuration.............................................................................309
27.4 Bus Speed Modes ................................................................................................................310
27.5 Power Modes........................................................................................................................310
27.5.1 Standby Mode......................................................................................................310
27.6 Interrupts to CPU ..................................................................................................................310
27.6.1 SDIO Interrupt......................................................................................................311
27.7 I/O Interface ..........................................................................................................................311
27.7.1 Switching Signaling Voltage from 3.3 V to 1.8 V..................................................312
27.8 Packet Buffer SRAM.............................................................................................................312
27.8.1 Packet Buffer Full/Empty .....................................................................................312
27.9 DMA Engine..........................................................................................................................312
27.10 Initialization Sequence..........................................................................................................313
27.10.1 Enabling SDHC....................................................................................................313
27.10.2 Card Detection .....................................................................................................314

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 Contents

27.10.3 SDHC Initialization ...............................................................................................316

27.10.4 Clock Setup..........................................................................................................316
27.11 Error Detection......................................................................................................................316
28. Serial Communications Block (SCB) 318
28.1 Features................................................................................................................................318
28.2 Architecture...........................................................................................................................319
28.2.1 Buffer Modes........................................................................................................319
28.2.2 Clocking Modes ...................................................................................................319
28.3 Serial Peripheral Interface (SPI) ...........................................................................................320
28.3.1 Features...............................................................................................................320
28.3.2 General Description .............................................................................................321
28.3.3 SPI Modes of Operation.......................................................................................322
28.3.4 SPI Buffer Modes.................................................................................................327
28.3.5 Clocking and Oversampling .................................................................................332
28.3.6 Enabling and Initializing SPI ................................................................................334
28.3.7 I/O Pad Connection..............................................................................................335
28.3.8 SPI Registers .......................................................................................................337
28.4 UART ....................................................................................................................................338
28.4.1 Features...............................................................................................................338
28.4.2 General Description .............................................................................................338
28.4.3 UART Modes of Operation...................................................................................338
28.4.4 Clocking and Oversampling .................................................................................348
28.4.5 Enabling and Initializing the UART ......................................................................348
28.4.6 I/O Pad Connection..............................................................................................349
28.4.7 UART Registers ...................................................................................................351
28.5 Inter Integrated Circuit (I2C) .................................................................................................352
28.5.1 Features...............................................................................................................352
28.5.2 General Description .............................................................................................352
28.5.3 External Electrical Connections ...........................................................................353
28.5.4 Terms and Definitions ..........................................................................................354
28.5.5 I2C Modes of Operation.......................................................................................354
28.5.6 I2C Buffer Modes .................................................................................................356
28.5.7 Clocking and Oversampling .................................................................................360
28.5.8 Enabling and Initializing the I2C...........................................................................363
28.5.9 I/O Pad Connections............................................................................................364
28.5.10 I2C Registers .......................................................................................................365
28.6 SCB Interrupts ......................................................................................................................366
28.6.1 SPI Interrupts .......................................................................................................367
28.6.2 UART Interrupts ...................................................................................................369
28.6.3 I2C Interrupts .......................................................................................................373
29. Serial Memory Interface (SMIF) 375
29.1 Features................................................................................................................................375
29.2 Architecture...........................................................................................................................375
29.2.1 Tx and Rx FIFOs..................................................................................................378
29.2.2 Command Mode ..................................................................................................379
29.2.3 XIP Mode .............................................................................................................379
29.2.4 Cache...................................................................................................................380
29.2.5 Arbitration.............................................................................................................380
29.2.6 Deselect Delay.....................................................................................................380
29.2.7 Cryptography .......................................................................................................380
29.3 Memory Device Signal Interface...........................................................................................382

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 Contents

29.3.1 Specifying Memory Devices.................................................................................382

29.3.2 Connecting SPI Memory Devices ........................................................................382
29.3.3 SPI Data Transfer ................................................................................................387
29.3.4 Example of Setting up SMIF ................................................................................389
29.4 Triggers.................................................................................................................................390
29.5 Interrupts...............................................................................................................................391
29.6 Sleep Operation....................................................................................................................391
29.7 Performance .........................................................................................................................391
30. Timer, Counter, and PWM (TCPWM) 392
30.1 Features................................................................................................................................392
30.2 Architecture...........................................................................................................................393
30.2.1 Enabling and Disabling Counters in a TCPWM Block .........................................393
30.2.2 Clocking ...............................................................................................................393
30.2.3 Trigger Inputs .......................................................................................................394
30.2.4 Trigger Outputs ....................................................................................................396
30.2.5 Interrupts..............................................................................................................396
30.2.6 PWM Outputs.......................................................................................................397
30.2.7 Power Modes .......................................................................................................397
30.3 Operation Modes ..................................................................................................................398
30.3.1 Timer Mode ..........................................................................................................399
30.3.2 Capture Mode ......................................................................................................405
30.3.3 Quadrature Decoder Mode ..................................................................................408
30.3.4 Pulse Width Modulation Mode .............................................................................412
30.3.5 Pulse Width Modulation with Dead Time Mode ...................................................422
30.3.6 Pulse Width Modulation Pseudo-Random Mode (PWM_PR) ..............................425
30.4 TCPWM Registers ................................................................................................................428
31. Inter-IC Sound Bus 429
31.1 Features................................................................................................................................429
31.2 Architecture...........................................................................................................................430
31.3 Digital Audio Interface Formats ............................................................................................430
31.3.1 Standard I2S Format............................................................................................430
31.3.2 Left Justified (LJ) Format .....................................................................................433
31.3.3 Time Division Multiplexed (TDM) Format.............................................................433
31.4 Clocking Polarity and Delay Options ....................................................................................434
31.5 Interfacing with Audio Codecs ..............................................................................................435
31.6 Clocking Features.................................................................................................................435
31.7 FIFO Buffer and DMA Support .............................................................................................437
31.8 Interrupt Support...................................................................................................................439
31.9 Watchdog Timer ...................................................................................................................440
32. PDM-PCM Converter 441
32.1 Features................................................................................................................................441
32.2 Architecture...........................................................................................................................442
32.2.1 Enable/Disable Converter ....................................................................................442
32.2.2 Clocking Features ................................................................................................442
32.2.3 Over-Sampling Ratio............................................................................................443
32.2.4 Mono/Stereo Microphone Support .......................................................................443
32.2.5 Hardware FIFO Buffers and DMA Controller Support..........................................445
32.2.6 Interrupt Support ..................................................................................................446
32.2.7 Digital Volume Gain .............................................................................................447
32.2.8 Smooth Gain Transition .......................................................................................447

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 Contents

32.2.9 Soft Mute..............................................................................................................447

32.2.10 Word Length and Sign Bit Extension ...................................................................447
32.2.11 High-Pass Filter ...................................................................................................447
32.2.12 Enable/Disable Streaming ...................................................................................448
32.2.13 Power Modes .......................................................................................................448
32.3 Operating Procedure ............................................................................................................448
32.3.1 Initial Configuration ..............................................................................................448
32.3.2 Interrupt Service Routine (ISR) Configuration .....................................................448
32.3.3 Enabling / Disabling Streaming............................................................................449
33. Universal Serial Bus (USB) Device Mode 450
33.1 Features................................................................................................................................450
33.2 Architecture...........................................................................................................................451
33.2.1 USB Physical Layer (USB PHY) ..........................................................................451
33.2.2 Serial Interface Engine (SIE) ...............................................................................451
33.2.3 Arbiter ..................................................................................................................451
33.3 Operation ..............................................................................................................................452
33.3.1 USB Clocking Scheme.........................................................................................452
33.3.2 USB PHY .............................................................................................................452
33.3.3 Endpoints .............................................................................................................453
33.3.4 Transfer Types .....................................................................................................453
33.3.5 Interrupt Sources .................................................................................................453
33.3.6 DMA Support........................................................................................................455
33.4 Logical Transfer Modes ........................................................................................................456
33.4.1 Manual Memory Management with No DMA Access ...........................................458
33.4.2 Manual Memory Management with DMA Access.................................................458
33.4.3 Automatic DMA Mode ..........................................................................................460
33.4.4 Control Endpoint Logical Transfer........................................................................462
33.5 USB Power Modes ...............................................................................................................464
33.6 USB Device Registers ..........................................................................................................464
34. Universal Serial Bus (USB) Host 466
34.1 Features................................................................................................................................466
34.2 Architecture...........................................................................................................................467
34.2.1 USB Physical Layer (USB PHY) .........................................................................467
34.2.2 Clock Control Block..............................................................................................467
34.2.3 Interrupt Control Block .........................................................................................467
34.2.4 Endpoint n (n=1, 2) ..............................................................................................467
34.2.5 DMA Request (DREQ) Control ............................................................................467
34.3 USB Host Operations ...........................................................................................................468
34.3.1 Detecting Device Connection...............................................................................468
34.3.2 Obtaining Transfer Speed of the USB Device......................................................468
34.3.3 USB Bus Reset ....................................................................................................469
34.3.4 USB Packets........................................................................................................470
34.3.5 Retry Function......................................................................................................474
34.3.6 Error Status..........................................................................................................474
34.3.7 End of Packet (EOP)............................................................................................475
34.3.8 Interrupt Sources .................................................................................................475
34.3.9 DMA Transfer Function ........................................................................................477
34.3.10 Suspend and Resume Operations.......................................................................481
34.3.11 Device Disconnection ..........................................................................................481
34.4 USB Host Registers..............................................................................................................482

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 Contents

35. LCD Direct Drive 483

35.1 Features................................................................................................................................483
35.2 Architecture...........................................................................................................................483
35.2.1 LCD Segment Drive Overview .............................................................................483
35.2.2 Drive Modes.........................................................................................................484
35.2.3 Recommended Usage of Drive Modes ................................................................493
35.2.4 Digital Contrast Control........................................................................................493
35.3 PSoC 6 MCU Segment LCD Direct Drive.............................................................................494
35.3.1 High-Speed and Low-Speed Master Generators.................................................494
35.3.2 Multiplexer and LCD Pin Logic.............................................................................495
35.3.3 Display Data Registers ........................................................................................495
35.4 Register List .........................................................................................................................495
Section E: Analog Subsystem 496
36. Analog Reference Block 497
36.1 Features................................................................................................................................497
36.2 Architecture...........................................................................................................................498
36.2.1 Bandgap Reference Block ...................................................................................499
36.2.2 VREF Reference Voltage Selection Multiplexer Options .....................................499
36.2.3 Zero Dependency To Absolute Temperature Current Generator (IZTAT).............499
36.2.4 Startup Modes......................................................................................................499
36.3 Registers...............................................................................................................................500
37. Low-Power Comparator 501
37.1 Features................................................................................................................................501
37.2 Architecture...........................................................................................................................502
37.2.1 Input Configuration...............................................................................................502
37.2.2 Output and Interrupt Configuration ......................................................................502
37.2.3 Power Mode and Speed Configuration ................................................................503
37.2.4 Hysteresis ............................................................................................................504
37.2.5 Wakeup from Low-Power Modes .........................................................................505
37.2.6 Comparator Clock ................................................................................................505
37.3 Register List .........................................................................................................................505
38. SAR ADC 506
38.1 Features................................................................................................................................506
38.2 Architecture...........................................................................................................................507
38.2.1 SAR ADC Core ....................................................................................................508
38.2.2 SARMUX..............................................................................................................513
38.2.3 SARREF ..............................................................................................................514
38.2.4 SARSEQ ..............................................................................................................515
38.2.5 SAR Interrupts .....................................................................................................516
38.2.6 Trigger..................................................................................................................518
38.2.7 SAR ADC Status ..................................................................................................518
38.3 Registers...............................................................................................................................519
39. Temperature Sensor 520
39.1 Features................................................................................................................................520
39.2 Architecture...........................................................................................................................520
39.3 SAR ADC Configuration for Measurement ...........................................................................522
39.4 Algorithm...............................................................................................................................522
39.5 Registers...............................................................................................................................523

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 Contents

40. CapSense 524

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 Section A: Overview

This section encompasses the following chapters:

■ Introduction chapter on page 19
■ Getting Started chapter on page 25
■ Document Organization and Conventions chapter on page 26

Document Revision History

Revision Issue Date Description of Change
** 07/09/2018 Initial version of CY8C62x8, CY8C62xA TRM
Minor edits in Non-volatile memory Programming and USB device mode chapters, updated Figure 31-2 and I/O
*A 10/04/2018 System. Major rewrite in Protection Units chapter. Updated figure 20-1 in Clocking System and figure 24-3 in
Peripheral Trigger.
*B 10/31/2018 Initial version of CY8C6xx8, CY8C6xxA TRM for public release
Added section “Enabling and Disabling the FLL” on page 250
Added the “I2C Master Clock Synchronization” subsection in “Oversampling and Bit Rate” on page 361
*C 12/14/2018 Added a few minor updates to the Watchdog chapter
Modified the number of backup domain registers to 16 in “Backup Registers” on page 241
Added section “SRAM Usage” on page 169
Modified the document title
Added Boot Code chapter
Deleted the Chip Operational Mode chapter
Updated the Nonvolatile Memory and SAR ADC chapters
*D 09/30/2019
Minor updates throughout the document
Renamed all instances of energy profiler as “profiler”
Updated Secure Digital Host Controller (SDHC), Protection Units, Clocking System, and Interrupts chapters
based on review comments
Updated the Trigger Multiplexer Block, Timer, Counter, and PWM (TCPWM), I/O System, Inter-Processor Com-
*E 03/27/2020 munication, DMA Controller (DW), CPU Subsystem (CPUSS), Nonvolatile Memory, and Clocking System
chapters as part of the PSoC 6 collateral review effort
Added the SRAM Controller chapter.
Aligned the introduction section with the datasheet.
*F 06/30/2020
Added information about CY8C61x8 and CY8C61xA devices
Updates throughout the document to address review comments.
*G 12/01/2020 Fixed an error in PDF bookmark.
Fixed typos: Sflash to SFlash, AUXflash and EE emulation to AUXFlash.
*H 05/11/2023
Updated PSoC 6 Programming Specification weblink.
Updated Table 15-3, Table 15-4, and Table 16-1.
*I 09/06/2023 Updated SWD/JTAG Repurposing, Configure SWD/JTAG Pins (12), and Life Cycle Stages and Protection
States sections.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 18
 1. Introduction

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC™ MCU is a scalable and reconfigurable platform architecture that supports a family of programmable embedded
system controllers with Arm® Cortex® CPUs (single and multi-core). The CY8C6xx8/CY8C6xxA product family(CY8C61x8,
CY8C62x8, CY8C61xA, and CY8C62xA), based on the PSoC 6 MCU platform, is a combination of a dual-core
microcontroller with built-in programmable peripherals. It incorporates integrated low-power flash technology, high-
performance analog-to-digital conversion, low-power comparators, touch sensing, serial memory interface with encryption,
secure digital host controller (SDHC), and standard communication and timing peripherals.

1.1 Features
32-bit Dual CPU Subsystem
■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU)
■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU
■ User-selectable core logic operation at either 1.1 V or 0.9 V
■ Active CPU current slope with 1.1-V core operation
■ Active CPU current slope with 0.9-V core operation
■ Three DMA controllers

Memory Subsystem
■ 2048-KB application flash, 32-KB auxiliary flash (AUXFlash), and 32-KB supervisory flash (SFlash); read-while-write
(RWW) support. Two 8-KB flash caches, one for each CPU
■ 1024-KB SRAM with three independent blocks for power and data retention control
■ One-time-programmable (OTP) 1-Kb eFuse array

Low-Power 1.7-V to 3.6-V Operation

■ Six power modes for fine-grained power management
■ Deep Sleep mode with SRAM retention
■ On-chip DC-DC Buck converter
■ Backup domain and real-time clock

Flexible Clocking Options

■ On-chip crystal oscillators
■ Two Phase-locked loops (PLL) for multiplying clock frequency

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 19
 Introduction

■ Internal main oscillator (IMO)

■ Ultra-low-power internal low-speed oscillator (ILO)
■ Frequency locked loop (FLL) for multiplying IMO frequency

Quad-SPI (QSPI)/Serial Memory Interface (SMIF)

■ Execute-In-Place (XIP) from external Quad SPI Flash
■ On-the-fly encryption and decryption
■ 4-KB cache for greater XIP performance with lower power
■ Supports single, dual, quad, dual-quad, and octal interfaces

Serial Communication
■ Thirteen run-time configurable serial communication blocks (SCBs)
❐ Eight SCBs: configurable as SPI, I2C, or UARTs
❐ Four SCBs: configurable as I2C or UART
❐ One Deep Sleep SCB: configurable as SPI or I2C
■ USB full-speed device interface
■ Two independent SD Host Controller/eMMC/SD controllers

Audio Subsystem
■ Two PDM channels and one I2S channel with TDM mode

Timing and Pulse-Width Modulation

■ Thirty-two timer/counter pulse-width modulators (TCPWMs)
■ Center-aligned, Edge, and Pseudo-random modes
■ Comparator-based triggering of Kill signals

Programmable Analog
■ 12-bit 2-Msps SAR ADC with differential and single-ended modes and 16-channel sequencer with result averaging
■ Two low-power comparators available in Deep Sleep and Hibernate modes
■ Two opamps
■ Always-on low frequency Deep Sleep operation
■ Built-in temp sensor connected to ADC

Up to 102 Programmable GPIOs

■ Two Smart I/O ports (16 I/Os) enable Boolean operations on GPIO pins; available during system Deep Sleep
■ Programmable drive modes, strengths, and slew rates
■ Six overvoltage-tolerant (OVT) pins

LCD
■ LCD segment direct block support up to 61 segments and up to 8 commons
■ Operates in Active, Sleep, and Deep Sleep modes

Capacitive Sensing
■ CapSense Sigma-Delta (CSD) provides best-in-class SNR, liquid tolerance, and proximity sensing
■ Enables dynamic usage of both self and mutual sensing
■ Automatic hardware tuning (SmartSense™)

Security Built into Platform Architecture

■ ROM-based root of trust via uninterruptible Secure Boot

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 20
 Introduction

■ Step-wise authentication of execution images

■ Secure execution of code in execute-only mode for protected routines
■ All Debug and Test ingress paths can be disabled
■ Up to eight Protection Contexts

Cryptography Accelerators
■ Hardware acceleration for symmetric and asymmetric cryptographic methods and hash functions
■ True Random Number Generator (TRNG) function

Profiler
■ Eight counters provide event or duration monitoring of on-chip resources

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 21
 Introduction

1.2 PSoC 61 and PSoC 62 MCU Series Differences

There is only one difference between the PSoC 61 (CY8C61x8, CY8C61xA) and the PSoC 62 (CY8C62x8, CY8C62xA)
series MCUs.
■ In the PSoC 62 series, both the CPUs (Cortex-M4F and Cortex M0+) are available for applications.
■ In the PSoC 61 series, only the Cortex-M4F CPU is available for applications. The Cortex M0+ is reserved for system
functions. When not executing the system functions, the CM0+ will be in CPU Deep Sleep mode.

1.3 Architecture
Figure 1-1 shows the major components of the PSoC 6 MCU architecture.

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 Introduction

Figure 1-1. PSoC 6 MCU Architecture Block Diagram

PSoC 61, PSoC 62 MCU

CY8C6xx8, CY8C6xxA
Programmable Analog

2x Smart I/O Ports

Color Key:
Power Modes and
System Resources SAR ADC 12 bit

SARMUX
Peripheral clock (PCLK)
Domains Power Clocks
Temperature
System LP/ULP Mode OVP LVD IMO ECO Sensor
CPUs Active/Sleep POR BOD FLL 2x PLL

System Buck Regulator 2x MCWDT

DeepSleep Mode ILO WDT
XRES Reset
RTC WCO
System
Hibernate Mode
Backup Regs PMIC Control

I/O Subsystem: Up to 102 GPIOs (including 6 OVT), 128-TQFP Package

Backup

Peripheral Interconnect (MMIO, PPU)

Domain

CPU Subsystem
SCB

Cortex M4F CPU

150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI

Boundary Scan
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI

Audio Subsystem
3x DMA
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Controller

Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator

Flash
2048 KB + 32 KB + 32 KB
8 KB cache for each CPU

SRAM0
512 KB USB
PHY

SRAM1
256 KB

SRAM2
256 KB

ROM
64 KB

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 23
 Introduction

The block diagram shows the device subsystems and gives a simplified view of their interconnections. The color-code shows
the lowest power mode where the particular block is still functional (for example, LP comparator is functional in Deep Sleep
and Hibernate modes).
Note: In the PSoC 61 series (CY8C61x8, CY8C61xA), only the Arm Cortex-M4F CPU is available for applications. The
Cortex M0+ is reserved for system functions, and is not available for applications. When not executing the system functions,
the CM0+ will be in CPU Deep Sleep mode.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 24
 2. Getting Started

2.1 PSoC 6 MCU Resources

This chapter provides the complete list of PSoC 6 MCU resources that helps you get started with the device and design your
applications with them. If you are new to PSoC, Cypress provides a wealth of data at www.cypress.com to help you to select
the right PSoC device and quickly and effectively integrate it into your design.
The following is an abbreviated list of PSoC 6 MCU resources:
■ Overview: PSoC Portfolio, PSoC 6 MCU webpage
■ Product Selectors: See the PSoC 6 MCU Product Selector Guide to choose a part that suits your application. In addition,
ModusToolbox includes a similar device selection tool to select devices for ModusToolbox projects.
■ Datasheets describe and provide electrical specifications for each device family.
■ Application Notes and Code Examples cover a broad range of topics, from basic to advanced level. Many of the
application notes include code examples, which can be opened from ModusToolbox.
■ Technical Reference Manuals (TRMs) provide detailed descriptions of the architecture and registers in each device family.
■ CapSense Design Guide: Learn how to design capacitive touch-sensing applications with PSoC devices.
■ Development Tools
❐ ModusToolbox is a free integrated design environment (IDE). It enables you to design hardware and firmware systems
concurrently with PSoC devices.
❐ PSoC 6 Kits offer an easy-to-use, inexpensive platform that enables prototyping of wide variety of designs including
IoT applications requiring Wi-Fi/Bluetooth/Bluetooth LE using the PSoC 6 MCU at its center.
■ Additional Resources: Visit the PSoC 6 MCU webpage for additional resources such as IBIS, BSDL models, CAD Library
Files, and Programming Specifications.
■ Technical Support
❐ Forum: See if your question is already answered by fellow developers of the PSoC 6 community.
❐ Cypress support: Visit our support page or contact a local sales representative.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 25
 3. Document Organization and Conventions

This document includes the following sections:

■ Section B: CPU Subsystem on page 30
■ Section C: System Resources Subsystem (SRSS) on page 217
■ Section D: Digital Subsystem on page 305
■ Section E: Analog Subsystem on page 496

3.1 Major Sections

For ease of use, information is organized into sections and chapters that are divided according to device functionality.
■ Section – Presents the top-level architecture, how to get started, and conventions and overview information of the
product.
■ Chapter – Presents the chapters specific to an individual aspect of the section topic. These are the detailed
implementation and use information for some aspect of the integrated circuit.
■ Glossary – Defines the specialized terminology used in this technical reference manual (TRM). Glossary terms are
presented in bold, italic font throughout.
■ Registers Technical Reference Manual – Supplies all device register details summarized in the technical reference
manual. This is an additional document.

3.2 Documentation Conventions

This document uses only four distinguishing font types, besides those found in the headings.
■ The first is the use of italics when referencing a document title or file name.
■ The second is the use of bold italics when referencing a term described in the Glossary of this document.
■ The third is the use of Times New Roman font, distinguishing equation examples.
■ The fourth is the use of Courier New font, distinguishing code examples.

3.2.1 Register Conventions

Register conventions are detailed in the registers TRM.

3.2.2 Numeric Naming

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
3Ah) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b or 01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.

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 Document Organization and Conventions

3.2.3 Units of Measure 3.2.4 Acronyms and Initializations

This table lists the units of measure used in this document. This table lists the acronyms and initializations used in this
document
Table 3-1. Units of Measure
Table 3-2. Acronyms and Initializations
Abbreviation Unit of Measure
bps bits per second Acronym Definition
ABUS analog output bus
°C degrees Celsius
AC alternating current
dB decibels
ADC analog-to-digital converter
dBm decibels-milliwatts
ADV advertising
fF femtofarads
AES Advanced Encryption Standard
G Giga
AMBA (advanced microcontroller bus architecture)
Hz Hertz AHB
high-performance bus, an Arm data transfer bus
k kilo, 1000
API application programming interface
K kilo, 2^10
APOR analog power-on reset
KB 1024 bytes, or approximately one thousand bytes
BC broadcast clock
Kbit 1024 bits
BCD binary coded decimal
kHz kilohertz (32.000)
BESL best effort service latency
k kilohms
BOD brownout detect
MHz megahertz
BOM bill of materials
M megaohms
BR bit rate
µA microamperes
BRA bus request acknowledge
µF microfarads
BRQ bus request
µs microseconds
CAN controller area network
µV microvolts
CI carry in
µVrms microvolts root-mean-square
CIC cascaded integrator comb
mA milliamperes
CMAC cipher-based message authentication code
ms milliseconds
CMP compare
mV millivolts
CO carry out
nA nanoamperes
COM LCD common signal
ns nanoseconds
CPHA clock phase
nV nanovolts
CPOL clock polarity
 ohms
CPU central processing unit
pF picofarads
CPUSS CPU subsystem
pp peak-to-peak
CRC cyclic redundancy check
ppm parts per million
CSD CapSense sigma delta
SPS samples per second
CSX CapSense cross-point
 sigma: one standard deviation
CT cipher text
V volts
CTI cross triggering interface
CTM cross triggering matrix
ESR equivalent series resistance
DAC digital-to-analog converter
DAP debug access port
DC direct current
DES Data Encryption Standard
DFF D flip-flop

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 27
 Document Organization and Conventions

Table 3-2. Acronyms and Initializations (continued) Table 3-2. Acronyms and Initializations (continued)
Acronym Definition Acronym Definition
DI digital or data input IRQ interrupt request
DL drive level ISA instruction set architecture
DMA direct memory access ISR interrupt service routine
DMIPS Dhrystone million instructions per second ITM instrumentation trace macrocell
DNL differential nonlinearity IVR interrupt vector read
DO digital or data output IZTAT zero dependency to absolute temperature
DSP digital signal processing JWT JSON web token
DSM Deep Sleep mode L2CAP logical link control and adaptation protocol
DU data unit LCD liquid crystal display
DW data wire LFCLK low-frequency clock
ECO external crystal oscillator LFSR linear feedback shift register
electrically erasable programmable read only LIN local interconnect network
EEPROM
memory
LJ left justified
EMIF external memory interface
LL link layer
ETM embedded trace macrocell LNA low-noise amplifier
FB feedback
LP system low-power mode
FIFO first in first out
LPCOMP Low-Power comparator
FPU floating point unit LPM link power management
FSR full scale range
LR link register
GAP generic access profile
LRb last received bit
GATT generic attribute profile LRB last received byte
GFSK Gaussian frequency-shift keying
LSb least significant bit
GPIO general-purpose I/O
LSB least significant byte
HCI host-controller interface LUT lookup table
HFCLK high-frequency clock
MAC message authentication code
HMAC hashed message authentication code
MISO master-in-slave-out
HPF high-pass filter MMIO memory mapped input/output
HSIOM high-speed I/O matrix
MOSI master-out-slave-in
I2 C inter-integrated circuit MPU memory protection unit
I2 S inter-IC sound MSb most significant bit
IDE integrated development environment MSB most significant byte
ILO internal low-speed oscillator MSP main stack pointer
ITO indium tin oxide MTB micro trace buffer
IMO internal main oscillator NI next instant
INL integral nonlinearity NMI non-maskable interrupt
I/O input/output NVIC nested vectored interrupt controller
IOR I/O read OE output enable
IOW I/O write OSR over-sampling ratio
IPC inter-processor communication OVP over-voltage protection
IPTAT proportional to absolute temperature PA power amplifier
IRES initial power on reset PC program counter
IRA interrupt request acknowledge PCB printed circuit board
IRK identity resolution key PCH program counter high

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 Document Organization and Conventions

Table 3-2. Acronyms and Initializations (continued) Table 3-2. Acronyms and Initializations (continued)
Acronym Definition Acronym Definition
PCL program counter low SP stack pointer
PD power down SPD sequential phase detector
PDU protocol data unit SPI serial peripheral interconnect
PGA programmable gain amplifier SPIM serial peripheral interconnect master
PHY physical layer SPIS serial peripheral interconnect slave
PLD programmable logic device SRAM static random-access memory
PM power management SROM supervisory read only memory
PMA PSoC memory arbiter SRSS system resources subsystem
POR power-on reset SSADC single slope ADC
PPOR precision power-on reset SSC supervisory system call
PPU peripheral protection units SVCall supervisor call
PRNG pseudo random number generator SYSCLK system clock
PRS pseudo random sequence SWD single wire debug
PSA Platform Security Architecture SWV serial wire viewer

PSoC Programmable System-on-Chip TAR turn-around time

PSP process stack pointer TC terminal count

PSR program status register TCPWM timer, counter, PWM

PSRR power supply rejection ratio TD transaction descriptors

PSSDC power system sleep duty cycle TDM time division multiplexed

PWM pulse width modulator TFF toggle flip-flop

RAM random-access memory TIA trans-impedance amplifier

RETI return from interrupt TPIU trace port interface unit

RF radio frequency TRM technical reference manual

RNG random number generator TRNG True random number generator

ROM read only memory UART universal asynchronous receiver/transmitter

ROT root of trust ULB system ultra low-power mode

RPA resolvable private address USB universal serial bus

RMS root mean square USBIO USB I/O

RW read/write VTOR vector table offset register

SAR successive approximation register WCO watch crystal oscillator

SARSEQ SAR sequencer WDT watchdog timer

SEG LCD segment signal WDR watchdog reset

SE0 single-ended zero WIC wakeup interrupt controller

SC switched capacitor XRES external reset

SCB serial communication block XRES_N external reset, active low

SHA-256 Secure Hash Algorithm

SIE serial interface engine
SIMO single input multiple output
SIO special I/O
SNR signal-to-noise ratio
SMPU shared memory protection units
SOF start of frame
SOI start of instruction

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 Section B: CPU Subsystem

This section encompasses the following chapters:

■ CPU Subsystem (CPUSS) chapter on page 32
■ SRAM Controller chapter on page 39
■ Inter-Processor Communication chapter on page 41
■ Fault Monitoring chapter on page 49
■ Interrupts chapter on page 56
■ Protection Units chapter on page 73
■ DMA Controller (DW) chapter on page 91
■ DMAC Controller (DMAC) chapter on page 102
■ Cryptographic Function Block (Crypto) chapter on page 111
■ Program and Debug Interface chapter on page 154
■ Nonvolatile Memory chapter on page 164
■ Boot Code chapter on page 193
■ eFuse Memory chapter on page 210
■ Device Security chapter on page 212

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 30
 CPU Subsystem

Top Level Architecture

Figure 3-1. CPU System Block Diagram

CPU Subsystem

Cortex M4F CPU

150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI

Cortex M0+ CPU

100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI

3x DMA

System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Controller

Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator

Flash
2048 KB + 32 KB + 32 KB
Color Key: 8 KB cache for each CPU
Power Modes and
Domains

System LP/ULP Mode SRAM0

512 KB
CPUs Active/Sleep

System SRAM1
DeepSleep Mode 256 KB

System SRAM2
Hibernate Mode 256 KB

Backup
Domain ROM
64 KB

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 31
 4. CPU Subsystem (CPUSS)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The CPU subsystem is based on dual 32-bit Arm Cortex CPUs, as Figure 4-1 shows. The Cortex-M4 is the main CPU. It is
designed for short interrupt response time, high code density, and high 32-bit throughput while maintaining a strict cost and
power consumption budget. A secondary Cortex-M0+ CPU implements security, safety, and protection features.
This section provides only an overview of the Arm Cortex CPUs in PSoC 6 MCUs. For details, see the Arm documentation
sets for Cortex-M4 and Cortex-M0+.
Some PSoC 6 MCU parts have only one CPU. See the PSoC 61 datasheet/PSoC 62 datasheet for details.

4.1 Features
The PSoC 6 MCU Arm Cortex CPUs have the following features:
■ Cortex-M4 has a floating-point unit (FPU) that supports single-cycle digital signal processing (DSP) instructions, and a
memory protection unit (MPU). Cortex-M0+ has an MPU.
■ Both CPUs have 8-KB instruction caches with four-way set associativity.1
■ Maximum clock frequency of 150 MHz for the Cortex-M4 and 100 MHz for the Cortex-M0+.
■ The Cortex-M4 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the Armv7-M
Architecture Reference Manual). The Cortex-M0+ supports the Armv6-M Thumb instruction set (defined in the Armv6-M
Architecture Reference Manual). See “Instruction Set” on page 38.
■ Both CPUs have nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response. For details,
see the Interrupts chapter on page 56
■ Both CPUs have extensive debug support. For details, see the Program and Debug Interface chapter on page 154.
❐ SWJ: combined serial wire debug (SWD) and Joint Test Action Group (JTAG) ports
❐ Serial wire viewer (SWV): provides real-time trace information through the serial wire output (SWO) interface
❐ Breakpoints
❐ Watchpoints
❐ Trace: Cortex-M4: embedded trace macrocell (ETM). Cortex-M0+: 4-KB micro trace buffer (MTB)
■ Inter-processor communication (IPC) hardware – see the Inter-Processor Communication chapter on page 41.

1. PSoC 6 does not support cache coherency. As a result when a particular row of flash that executes instructions is written/updated, the updated information will
not be reflected in the cache. The cache should be cleared in the firmware during such instances. This is applicable for both CM4 and CM0+ cache – the ap-
propriate (CM0+ and/or CM4) cache should be invalidated.

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 CPU Subsystem (CPUSS)

4.2 Architecture
Figure 4-1. CPU Subsystem Block Diagram

CPU Subsystem

Cortex M4F CPU

150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI

Cortex M0+ CPU

100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI

3x DMA

System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Controller

Crypto
DES/TDES, AES, SHA,
CRC, TRNG, RSA/ECC
Accelerator

Flash
2048 KB + 32 KB + 32 KB
Color Key: 8 KB cache for each CPU
Power Modes and
Domains

System LP/ULP Mode SRAM0

512 KB
CPUs Active/Sleep

System SRAM1
DeepSleep Mode 256 KB

System SRAM2
Hibernate Mode 256 KB

Backup
Domain ROM
64 KB

Each CPU is a 32-bit processor with its own 32-bit datapath and a 32-bit memory interface. Each CPU has its own set of 32-
bit registers. They support a wide variety of instructions in the Thumb instruction set. They support two operating modes (see
“Operating Modes and Privilege Levels” on page 37).
The Cortex-M4 instruction set includes:
■ Signed and unsigned, 32×32  32-bit and 32×32  64-bit, multiply and multiply-accumulate, all single-cycle
■ Signed and unsigned 32-bit divides that take two to 12 cycles
■ DSP instructions, including single instruction multiple data (SIMD) instructions
■ Complex memory-load and store access
■ Complex bit manipulation; see the bitfield instructions in Table 4-6
The Cortex-M4 FPU has its own set of registers and instructions. It is compliant with the ANSI/IEEE Std 754-2008, IEEE
Standard for Binary Floating-Point Arithmetic.
The Cortex-M0+ has a single cycle 32x32  32-bit signed multiplication instruction.

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 CPU Subsystem (CPUSS)

4.2.1 Address and Memory Maps

Both CPUs have a fixed address map, with shared access to memory and peripherals. The 32-bit (4 GB) address space is
divided into the regions shown in Table 4-1. Note that code can be executed from the code and SRAM regions.

Table 4-1. Address Map for Cortex-M4 and Cortex-M0+

Address Range Region Name Use
Program code region. You can also put data here. It includes the exception vector
0x0000 0000 – 0x1FFF FFFF Code
table, which starts at address 0.
0x2000 0000 – 0x3FFF FFFF SRAM Data region. This region is not supported in PSoC 6.
All peripheral registers. Code cannot be executed from this region. Note that the
0x4000 0000 – 0x5FFF FFFF Peripheral
Cortex-M4 bit-band in this region is not supported in PSoC 6.
0x6000 0000 – 0x9FFF FFFF External RAM Not used
0xA000 0000 – 0xDFFF FFFF External Device Not used
Private Peripheral
0xE000 0000 – 0xE00F FFFF Provides access to peripheral registers within the CPU core.
Bus (PPB)
0xE010 0000 – 0xFFFF FFFF Device Device-specific system registers.

The device memory map shown in Table 4-2 applies to both CPUs. That is, the CPUs share access to all PSoC 6 MCU
memory and peripheral registers.

Table 4-2. PSoC 6 Memory Map

Address Range Name Comments
0x0000 0000 –0x0001 0000 SROM 64 Kbytes
0x0800 0000 – 0x0810 0000 SRAM Up to 1 Mbyte
0x1000 0000 – 0x1020 0000 User Application Flash Up to 2 Mbytes
0x1600 0000 – 0x1600 8000 Supervisory Flash (SFlash) 32K for secure access
0x1800 0000 – 0x0800 0000 External memory 128 Mbyte execute-in-place (XIP) region

SRAM is located in the code region for both CPUs (see Table 4-1). This facilitates executing code out of SRAM. There is no
physical memory located in the CPUs’ SRAM region.
Note: The CPUSS_CM0_VECTOR_TABLE_BASE and CPUSS_CM4_VECTOR_TABLE_BASE registers determine the
location of the vector table for each CPU. A number of LS bits in each register are set to 0. As a result, there are restrictions
on the location of vector tables – they must be on a 256-byte boundary for CM0+ and a 1024-byte boundary for CM4.

4.2.1.1 Wait State Lookup Tables

The wait state lookup tables show the wait states for Flash, SRAM, and ROM based on the Clk_HF0 frequency and the
current power mode. SRAM and ROM have two domains for the wait states – fast clock domain (Clk_Fast) and slow clock
domain (Clk_Slow); both domains are based off Clk_HF0. The following tables show the wait states for the slow clock
domain. All wait states for the fast clock domain are zero. For more information on clocking see the Clocking System chapter
on page 242.

Ultra-Low Power Clk_HF0 (MHz)

Mode Clk_HF0 25 25 < Clk_HF0  100 100 < Clk_HF0
True 0 1 1
ROM/SRAM
False 0 0 1

Ultra-Low Power
Clk_HF0 (MHz)
Mode
Clk_HF0  16 16 < Clk_HF0  33 33 < Clk_HF0
True
0 1 2
Flash
Clk_HF0  29 29 < Clk_HF0  58 58 < Clk_HF0  87 87 < Clk_HF0  120 120 < Clk_HF0  150
False
0 1 2 3 4

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 CPU Subsystem (CPUSS)

4.3 Registers
Both CPUs have sixteen 32-bit registers, as Table 4-3 shows. See the Arm documentation for details.
■ R0 to R12 – General-purpose registers. R0 to R7 can be accessed by all instructions; the other registers can be accessed
by a subset of the instructions.
■ R13 – Stack pointer (SP). There are two stack pointers, with only one available at a time. In thread mode, the CONTROL
register indicates the stack pointer to use – Main Stack Pointer (MSP) or Process Stack Pointer (PSP).
■ R14 – Link register. Stores the return program counter during function calls.
■ R15 – Program counter. This register can be written to control program flow.

Table 4-3. Cortex-M4 and Cortex-M0+ Registers

Name Typea Reset Value Description

R0 – R12 RW Undefined R0–R12 are 32-bit general-purpose registers for data operations.
The stack pointer (SP) is register R13. In thread mode, bit[1] of the CONTROL register
MSP (R13) indicates the stack pointer to use:
RW [0x0000 0000] 0 = Main stack pointer (MSP). This is the reset value.
PSP (R13) 1 = Process stack pointer (PSP).
On reset, the processor loads the MSP with the value from the vector address.
The link register (LR) is register R14. It stores the return information for subroutines, function
LR (R14) RW See noteb calls, and exceptions.
The program counter (PC) is register R15. It contains the current program address. On reset,
PC (R15) RW [0x0000 0004] the processor loads the PC with the value from the vector address plus 0x0000 0004. Bit[0]
of the value is loaded into the EPSR T-bit (see Table 4-4) at reset; it must always be 1.
The program status register (PSR) combines:
Application Program Status Register (APSR).
PSR RW Undefined
Execution Program Status Register (EPSR).
Interrupt Program Status Register (IPSR).
The APSR contains the current state of the condition flags from previous instruction
APSR RW Undefined
executions.
On reset, the EPSR Thumb state bit is loaded with the value bit[0] of the register
[0x0000 0004]. It must always be 1.
EPSR RO 0x0100 0000
In Cortex-M4, other bits in this register control the state of interrupt-continuable instructions
and the if-then (IT) instruction.
IPSR RO 0 The IPSR contains the current exception number.
PRIMASK RW 0 The PRIMASK register prevents activation of all exceptions with configurable priority.
The CONTROL register controls:
- The privilege level in Thread mode; see 4.4 Operating Modes and Privilege Levels.
CONTROL RW 0
- The currently active stack pointer, MSP or PSP.
- Cortex-M4 only: whether to preserve the floating-point state when processing an exception.
FAULTMASK RW 0 Cortex-M4 only. Bit 0 = 1 prevents the activation of all exceptions except NMI.
Cortex-M4 only. When set to a nonzero value, prevents processing any exception with a
BASEPRI RW 0
priority greater than or equal to the value.
a. Describes access type during program execution in thread mode and handler mode. Debug access can differ.
b. LR reset value is 0xFFFF FFFF in Cortex-M4, undefined in Cortex-M0+.

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 CPU Subsystem (CPUSS)

The Cortex-M4 floating-point unit (FPU) also has the following registers:
■ Thirty-two 32-bit single-precision registers, S0 to S31. These registers can also be addressed as sixteen 64-bit double-
precision registers, D0 to D15.
■ Five FPU control and status registers:
❐ CPACR – Coprocessor Access Control Register
❐ FPCCR – Floating-point Context Control Register
❐ FPCAR – Floating-point Context Address Register
❐ FPSCR – Floating-point Status Control Register
❐ FPDSCR – Floating-point Default Status Control Register
For more information on how these registers are used, see the Arm Cortex-M4 documentation.
Use the MSR and MRS instructions to access the PSR, PRIMASK, CONTROL, FAULTMASK, and BASEPRI registers.
Table 4-4 and Table 4-5 show how the PSR bits are assigned.

Table 4-4. Cortex-M4 PSR Bit Assignments

Bit PSR Register Name Usage
31 APSR N Negative flag
30 APSR Z Zero flag
29 APSR C Carry or borrow flag
28 APSR V Overflow flag
27 APSR Q DSP overflow and saturation flag
26 – 25 EPSR IC/IT Control interrupt-continuable and IT instructions
Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0
24 EPSR T
results in a HardFault exception.
23 – 20 – – Reserved
19 – 16 APSR GE Greater than or equal flags, for the SEL instruction
15 – 10 EPSR IC/TI Control interrupt-continuable and IT instructions
9 – – Reserved
Exception number of current ISR:
0 = thread mode
1 = reserved
2 = NMI
3 = HardFault
4 = MemManage
5 = BusFault
6 = UsageFault
8–0 IPSR ISR_NUMBER 7 – 10 = reserved
11 = SVCall
12 = reserved for debug
13 = reserved
14 = PendSV
15 = SysTick (see “System Tick (SysTick) Exception” on page 62)
16 = IRQ0
…
255 = IRQ240

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 CPU Subsystem (CPUSS)

Table 4-5. Cortex-M0+ PSR Bit Assignments

Bit PSR Register Name Usage

31 APSR N Negative flag
30 APSR Z Zero flag
29 APSR C Carry or borrow flag
28 APSR V Overflow flag
27 – 25 – – Reserved
Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0 results in
24 EPSR T
a HardFault exception.
23 – 6 – – Reserved
Exception number of current ISR:
0 = thread mode
1 = reserved
2 = NMI
3 = HardFault
4 – 10 = reserved
Exception
5–0 IPSR 11 = SVCall
Number
12, 13 = reserved
14 = PendSV
15 = SysTick
16 = IRQ0
…
47 = IRQ31

4.4 Operating Modes and Privilege Levels

Both CPUs support two operating modes and two privilege levels:
■ Operating Modes:
❐ Thread Mode – used to execute application software. The processor enters Thread mode when it comes out of reset.
❐ Handler Mode – used to handle exceptions. The processor returns to Thread mode when it has finished all exception
processing.
■ Privilege Levels:
❐ Unprivileged – the software has limited access to the MSR and MRS instructions, and cannot use the CPSID and
CPSIE instructions. It cannot access the system timer, NVIC, or system control block. It may have restricted access to
memory or peripherals.
❐ Privileged – the software can use all the instructions and has access to all resources.
In Thread mode, the CONTROL register controls whether software execution is privileged or unprivileged. In Handler mode,
software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level. Unprivileged software can use the
SVC instruction to transfer control to privileged software.
In Handler mode, the MSP is always used. The exception entry and return mechanisms automatically update the CONTROL
register, which may change whether MSP/PSP is used.
In Thread mode, use the MSR instruction to set the stack pointer bit in the CONTROL register. When changing the stack
pointer, use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer.

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 CPU Subsystem (CPUSS)

4.5 Instruction Set

Both CPUs implement subsets of the Thumb instruction set, as Table 4-6 shows. The table does not show the large number
of variants and conditions of the instructions. For details, see one of the Arm Cortex Generic User Guides or Technical
Reference Manuals.
An instruction operand can be a register, a constant, or another instruction-specific parameter. Instructions act on the
operands and often store the result in a destination register. Many instructions have restrictions on using the PC or SP for the
operands or destination register. See the Arm documentation for details.

Table 4-6. Instruction Set Summary – Cortex-M4 and Cortex-M0+

Functional Group Cortex-M4 Cortex-M0+ Brief List of Instruction Mnemonics

Memory access ✔ ✔ LDR, STR, ADR, PUSH, POP
Cortex-M0+: ADD, ADC, AND, ASR, BICS, CMN, CMP, EOR, LSL, LSR, MOV,
MVNS, ORR, REV, ROR, RSB, SBC, SUB, SXT, UXT, TST
General data processing ✔ ✔
Cortex-M4 has all of the above plus: CLZ, ORN, RRX, SADD, SAS, SSA, SSUB,
TEQ, UADD, UAS, USA, USUB
MLA, MLS, MUL, SDIV, SMLA, SMLS, SMMLA, SMMLS, SMUA, SMUL, SMUS,
Multiply and divide ✔ MUL only
UDIV, UMAAL, UMLAL, UMULL
SSAT, USAT, QADD, QSUB, QASX, QSAX, QDADD, QDSUB, UQADD, UQASX,
Saturating ✔ –
UQSAX, UQSUB
Packing and unpacking ✔ – PKH, SXT, SXTA, UXT, UXTA
Bitfield ✔ – BFC, BFI, SBFX, UBFX
Cortex-M0+: B{cc}, BL, BLX, BX
Branch and control ✔ ✔
Cortex-M4 has all of the above plus: CBNZ, CBZ, IT, TB
CPSID, CPSIE, DMB, DSB, ISB, MRS, MSR, NOP, SEV, SVC, WFE, WFI
Miscellaneous ✔ ✔
Cortex-M4 has all of the above plus BKPT
VABS, VADD, VCMP, VCVT, VDIV, VFMA, VFNMA, VFMS, VFNMS, VLD, VLMA,
Floating-point ✔ – VLMS, VMOV, VMRS, VMSR, VMUL, VNEG, VNMLA, VNMLS, VNMUL, VPOP,
VPUSH, VSQRT, VST, VSUB

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 38
 5. SRAM Controller

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

This chapter explains the PSoC 6 MCU SRAM Controller, its features, architecture, and wait states. The SRAM controller
enables the CPU to read and write parts of the PSoC 6 SRAM.

5.1 Features
The CPUSS has up to three identical SRAM controllers; see the PSoC 61 datasheet/PSoC 62 datasheet for details.
The SRAM controller has the following features:
■ Consists of two AHB-Lite interfaces:
❐ An AHB-Lite bus interface on clk_fast that connects to the fast bus infrastructure
❐ An AHB-Lite bus interface on clk_slow that connects to the slow bus infrastructure
■ Supports programmable number of clk_hf wait states
■ Supports 8-, 16-, and 32-bit accesses

5.2 Architecture
The design has two AHB-Lite interfaces that connect to the AHB-Lite infrastructure. Each AHB-Lite interface is connected to
a synchronization component that translates between the interface clock (either clk_fast or clk_slow) and the high-frequency
clock (clk_hf).
Arbitration is performed on the AHB-Lite transfers from the two ports (AHB-Lite interface). Arbitration uses device-wide bus
master specific arbitration priorities. Therefore, although two AHB-Lite interfaces are provided, only one AHB-Lite transfer is
accepted by the port arbitration component.
The AHB-Lite transfers are the origin for all SRAM accesses; that is, the write buffer and SRAM repair requests result from
AHB-Lite transfers. The SRAM controller differentiates between the following three types of AHB-Lite transfers:
■ AHB-Lite read transfers
■ 32-bit AHB-Lite write transfers
■ 8-bit and 16-bit AHB-Lite write transfers (also referred to as partial AHB-Lite write transfers)
Each type is described in more detail here.

AHB-Lite read transfers. An AHB-Lite read transfer is translated into an SRAM read access. If the read address matches
in the write buffer, the SRAM has stale data and the write data provides the requested read data (this functionality is provided
by the read merge component).

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 39
 SRAM Controller

32-bit AHB-Lite write transfers. A 32-bit AHB-Lite write access. If the entry valid field is ‘0’, no SRAM access is
transfer is translated into an SRAM write access. If the write performed.
address matches in the write buffer, the matching write
On an SRAM read access, a matching entry provides write
buffer entries have stale data and these entries are
buffer merge data for the read merge component.
invalidated.
On an SRAM write access resulting from a 32-bit AHB-Lite
Partial AHB-Lite write transfers. A partial AHB-Lite write write transfer, a matching entry invalidated field is set to ‘1’.
transfer is translated into an SRAM read access and an
SRAM write access. The SRAM read access is the direct The state of the write buffer is reflected by
result of the partial write transfer and the SRAM write RAMi_STATUS.WB_EMPTY. The write buffer is not retained
access is the result of a write buffer request. A partial write in Deep Sleep power mode. Therefore, when transitioning to
transfer requires an SRAM read access to retrieve the system Deep Sleep power mode, the write buffer should be
“missing” data bytes from the SRAM. If the read address empty. Note that this requirement is typically met, because a
matches in the write buffer, the SRAM has stale data and transition to Deep Sleep power mode also requires that
the write data provides the requested read data (this there are no outstanding AHB-Lite transfers. If there are no
functionality is provided by the read merge component). The outstanding AHB-Lite transfers, the write buffer gets SRAM
requested read data is merged with the partial write data to access.
provide a complete 32-bit data word (this functionality is
provided by the write merge component). The address and
the merged write data are written to the write buffer. A future
5.3 Wait States
write buffer request results in an SRAM write access with The programmable wait states represent the number of
the merged write data. clk_hf cycles for a read path through the SRAM memory to
Only the partial AHB-Lite write transfers use the write buffer. flipflops in either the fast domain (CM4 CPU) or slow domain
(such as CM0+ CPU, DataWire, and DMA controller).
Write buffer. The write buffer is a temporary holding As the wait states are represented in clk_hf cycles, the wait
station for future SRAM write accesses. states do not have to be reprogrammed when the fast clock
The buffer allows SRAM write accesses to be postponed. domain frequency (clk_fast) or slow clock domain frequency
This allows for more performance critical AHB-Lite requests (clk_slow) is changed. However, it may be necessary to
to “overtake” write buffer requests. Memory consistency is reprogram the wait states when the high-frequency clock
guaranteed by matching the SRAM access address with the domain (clk_hf) is changed. This means the required
write buffer entries' addresses: a “matching” SRAM read number of wait states is a function of the clk_hf frequency.
access uses the read merge component and a matching The fast clock domain is timing closed at a higher frequency
SRAM write access invalidates the matching write buffer than the slow clock domain. Therefore, the read path
entries. through the SRAM memory to flipflops in the fast domain is
When the write buffer is full, an entry needs to be freed to faster than the read path through the SRAM memory to
accommodate future partial AHB-Lite write transfers. flipflops in the slow domain. In other words, the required
Therefore, a full write buffer raises the priority of the write number of “fast” wait states (RAMi_CTL.FAST_WS) should
buffer request path. be less than or equal to the required number of “slow” wait
states (RAMi_CTL.SLOW_WS).
The write buffer is constructed as a FIFO with four entries
(the order in which entries are written is the same as the The SRAM controller also has internal SRAM read paths.
order in which entries are read). Each entry consists of: These paths are to flipflops in the SRAM controller in the
high-frequency clock domain (clk_hf). For these SRAM
■ A valid field accesses (for example, an SRAM read access to support a
■ An invalidated field partial AHB-Lite write transfer), the fast wait states are used.
■ A word address This is because the maximum fast domain frequency
(clk_fast) equals the high-frequency domain frequency
■ A 32-bit data word
(clk_hf).
Note that the merged write data written to the write buffer
is always a 32-bit data word. Therefore, no byte mask is
required.
When the write buffer is written (an entry is added): the entry
valid field is set to ‘1’ and the invalidated field is set to ‘0’.
When the write buffer is read (an entry is removed): the
entry valid field is set to ‘0’. If the entry invalidate field is ‘1’,
the write buffer request path is selected for an SRAM write

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 40
 6. Inter-Processor Communication

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

Inter-processor communication (IPC) provides the functionality for multiple processors to communicate and synchronize their
activities. IPC hardware is implemented using two register structures.
■ IPC Channel: Communication and synchronization between processors is achieved using this structure.
■ IPC Interrupt: Each interrupt structure configures an interrupt line, which can be triggered by a ‘notify’ or ‘release’ event of
any IPC channel.
The Channel and Interrupt structures are independent and have no correlation to each other as shown in Figure 6-1. This
allows for building varying models of interface shown in Typical Usage Models on page 46.
Figure 6-1. IPC Register Architecture

System bus

Acquire Notify events from

Notify IPCChannel 0-N
Release Release events for
Data register(s) IPC channels 0-N
Notify and
Status To
Release Events IPC Interrupt 0
Structure interrupt
IPC Channel 0 Structure to IPC interrupt
controller
structures IPC Interrupt 1
IPC Channel 1 Structure
Structure

IPC Channel N IPC Interrupt N

Structure Structure

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 41
 Inter-Processor Communication

6.1 Features
The features of IPC are as follows:
■ Implements locks for mutual exclusion between processors
■ Allows sending messages between processors
■ Supports up to 16 channels for communication
■ Supports up to 16 interrupts, which can be triggered using notify or release events from the channels

6.2 Architecture
6.2.1 IPC Channel
An IPC channel is implemented as six hardware registers, as shown in Figure 6-2. The IPC channel registers are accessible
to all the processors in the system.
■ IPC_STRUCTx_ACQUIRE: This register determines the lock feature of the IPC. The IPC channel is acquired by reading
this register. If the SUCCESS field returns a ‘1’, the read acquired the lock.
If the SUCCESS field returns a ‘0’, the read did not acquire the lock.
Note that a single read access performs two functions:
❐ The attempt to acquire a lock.
❐ Return the result of the acquisition attempt (SUCCESS field).
The atomicity of these two functions is essential in a CPU with multiple tasks that can preempt each other.
The register also has bitfields that provide information about the processor that acquired it. When acquired, this register is
released by writing any value into the IPC_STRUCTx_RELEASE register. If the register was already in an acquired state
another attempt to read the register will not be able to acquire it.
■ IPC_STRUCTx_NOTIFY: This register is used to generate an IPC notify event. Each bit in this register corresponds to an
IPC interrupt structure. The notify event generated from an IPC channel can trigger any or multiple interrupt structures.
■ IPC_STRUCTx_RELEASE: Any write to this register will release the IPC channel. This register also has a bit that
corresponds to each IPC interrupt structure. The release event generated from an IPC channel can trigger any or multiple
interrupt structures. To only release the IPC channel and not generate an interrupt, you can write a zero into the IPC
release register.
■ IPC_STRUCTx_DATA0 and IPC_STRUCTx_DATA1: These are two 32-bit registers with a combined size of 64 bits that
are meant to hold data. These registers can be considered as the shared data memory for the channel. Typically, these
registers will hold messages that need to be communicated between processors. If the messages are larger than the
combined 64-bit size, place pointers in one or both of these registers.
■ IPC_STRUCTx_LOCK_STATUS: This register provides the instantaneous lock status for the IPC channel. The register
provides details if the channel is acquired. If acquired, it provides the processor’s ID, protection context, and other details.
The reading of lock status provides only an instantaneous status, which can be changed in the next cycle based on the
activity of other processors on the channel.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 42
 Inter-Processor Communication

Figure 6-2. IPC Channel Structure

IPC_STRUCTx_ACQUIRE IPC_STRUCTx_NOTIFY
31

31
0

0
INTR_NOT15
INTR_NOT14
INTR_NOT13
INTR_NOT12
INTR_NOT11
INTR_NOT10
INTR_NOT9
INTR_NOT8
INTR_NOT7
INTR_NOT6
INTR_NOT5
INTR_NOT4
INTR_NOT3
INTR_NOT2
INTR_NOT1
INTR_NOT0
SUCCESS

MS[3:0]

PC[3:0]

NS
P
IPC_STRUCTx_RELEASE IPC_STRUCTx_DATA0
31

31
0

0
INTR_REL15
INTR_REL14
INTR_REL13
INTR_REL12
INTR_REL11
INTR_REL10
INTR_REL9
INTR_REL8

INTR_REL6

INTR_REL4
INTR_REL3
INTR_REL7

INTR_REL5

INTR_REL2
INTR_REL1
INTR_REL0

DATA[31:0]
IPC_STRUCTx_LOCK_STATUS IPC_STRUCTx_DATA1

31
31

0
ACQUIRED
ACQUIRED

DATA[31:0]
MS[3:0]

PC[3:0]

NS
P
6.2.2 IPC Interrupt
Each IPC interrupt line in the system has a corresponding IPC interrupt structure. An IPC interrupt can be triggered by a notify
or a release event from any of the IPC channels in the system. You can choose to mask any of the sources of these events
using the IPC interrupt registers. Figure 6-3 shows the registers in an IPC Interrupt structure.
IPC_INTR_STRUCTx_INTR: This register provides the instantaneous status of the interrupt sources. Note that there are 16
notify and 16 release event bits in this register. These are the notify and release events corresponding to the 16 IPC
channels. When a notify event is triggered in the IPC channel 0, the corresponding Notify0 bit is activated in the interrupt
registers. A write of ‘1’ to a bit will clear the interrupt.
IPC_INTR_STRUCTx_INTR_MASK: The bit in this register masks the interrupt sources. Only the interrupt sources with their
masks enabled can trigger the interrupt.
IPC_INTR_STRUCTx_INTR_SET: A write of ‘1’ into this register will set the interrupt.
IPC_INTR_STRUCTx_INTR_MASKED: This register provides the instantaneous value of the interrupts after they are
masked. The value in this register is (IPC_INTR_STRUCTx_INTR AND IPC_INTR_STRUCTx_INTR_MASK).
Figure 6-3. IPC Interrupt Structure
IPC_INTR_STRUCTx_INTR IPC_INTR_STRUCTx_INTR_MASK
31

31
0

0
RELEASE15
RELEASE14
RELEASE13
RELEASE12

RELEASE15
RELEASE14
RELEASE13
RELEASE12
RELEASE11

RELEASE11
RELEASE10

RELEASE10
RELEASE9

RELEASE9
NOTIFY15
NOTIFY14
NOTIFY13
NOTIFY12
NOTIFY11
NOTIFY10

RELEASE8

RELEASE6

RELEASE4
RELEASE3

RELEASE8

RELEASE6

RELEASE4
RELEASE3
RELEASE7

RELEASE5

NOTIFY15
NOTIFY14
NOTIFY13
NOTIFY12
NOTIFY11
NOTIFY10

RELEASE7

RELEASE5
RELEASE2
RELEASE1
RELEASE0

RELEASE2
RELEASE1
RELEASE0
NOTIFY9
NOTIFY8
NOTIFY7
NOTIFY6
NOTIFY5
NOTIFY4
NOTIFY3
NOTIFY2
NOTIFY1
NOTIFY0

NOTIFY9
NOTIFY8
NOTIFY7
NOTIFY6
NOTIFY5
NOTIFY4
NOTIFY3
NOTIFY2
NOTIFY1
NOTIFY0

IPC_INTR_STRUCTx_INTR_SET IPC_INTR_STRUCTx_INTR_MASKED
31

31
0

0
RELEASE15
RELEASE14
RELEASE13
RELEASE12

RELEASE15
RELEASE14
RELEASE13
RELEASE12
RELEASE11
RELEASE10

RELEASE11
RELEASE10
RELEASE9
NOTIFY15
NOTIFY14
NOTIFY13
NOTIFY12
NOTIFY11
NOTIFY10

RELEASE8

RELEASE6

RELEASE4
RELEASE3

RELEASE9
RELEASE7

RELEASE5

NOTIFY15
NOTIFY14
NOTIFY13
NOTIFY12
NOTIFY11
NOTIFY10

RELEASE8

RELEASE6

RELEASE4
RELEASE3
RELEASE7

RELEASE5
RELEASE2
RELEASE1
RELEASE0

RELEASE2
RELEASE1
RELEASE0
NOTIFY9
NOTIFY8
NOTIFY7
NOTIFY6
NOTIFY5
NOTIFY4
NOTIFY3
NOTIFY2
NOTIFY1
NOTIFY0

NOTIFY9
NOTIFY8
NOTIFY7
NOTIFY6
NOTIFY5
NOTIFY4
NOTIFY3
NOTIFY2
NOTIFY1
NOTIFY0

6.2.3 IPC Channels and Interrupts

The IPC block has a set of IPC interrupts associated with it. Each IPC interrupt register structure corresponds to an IPC
interrupt line. This interrupt can trigger an interrupt on any of the processors in the system. The interrupt routing for
processors are dependent on the device architecture.
Each IPC channel has a release and notify register, which can drive events on any of the IPC interrupts. An illustration of this
relation between the IPC channels and the IPC interrupt structure is shown in Figure 6-4.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 43
 Inter-Processor Communication

Figure 6-4. IPC Channels and Interrupts

IPC 0 IPC 1 IPC N

Release Notify Release Notify Release Notify

INTR N INTR N INTR N INTR N INTR N INTR N

INTR 3 INTR 3 INTR 3 INTR 3 INTR 3 INTR 3

INTR 2 INTR 2 INTR 2 INTR 2 INTR 2 INTR 2
INTR 1 INTR 1 INTR 1 INTR 1 INTR 1 INTR 1
INTR 0 INTR 0 INTR 0 INTR 0 INTR 0 INTR 0

INTR 0 INTR 1 INTR 2 INTR 3

INTR_NOT N INTR_NOT N INTR_NOT N INTR_NOT N

INTR _NOT 6 INTR _NOT 6 INTR _NOT 6 INTR _NOT 6

INTR_NOT 5 INTR_NOT 5 INTR_NOT 5 INTR_NOT 5
INTR_NOT 4 INTR_NOT 4 INTR_NOT 4 INTR_NOT 4
INTR_NOT 3 INTR_NOT 3 INTR_NOT 3 INTR_NOT 3
INTR _NOT 2 INTR _NOT 2 INTR _NOT 2 INTR _NOT 2
INTR_NOT 1 INTR_NOT 1 INTR_NOT 1 INTR_NOT 1
INTR_NOT 0 INTR_NOT 0 INTR_NOT 0 INTR_NOT 0

INTR_REL N INTR_REL N INTR_REL N INTR_REL N

INTR_REL 6 INTR_REL 6 INTR_REL 6 INTR_REL 6

INTR_REL 5 INTR_REL 5 INTR_REL 5 INTR_REL 5
INTR_REL 4 INTR_REL 4 INTR_REL 4 INTR_REL 4
INTR_REL 3 INTR_REL 3 INTR_REL 3 INTR_REL 3
INTR_REL 2 INTR_REL 2 INTR_REL 2 INTR_REL 2
INTR_REL 1 INTR_REL 1 INTR_REL 1 INTR_REL 1
INTR_REL 0 INTR_REL 0 INTR_REL 0 INTR_REL 0

Interrupt to Interrupt to Interrupt to Interrupt to

processors processors processors processors

6.3 Implementing Locks 6.4 Message Passing

The IPC channels can be used to implement locks. Locks IPC channels can be used to communicate messages
are typically used in multi-core systems to implement some between processors. In this use case, the channel is used in
form of mutually exclusive access to a shared resource. conjunction with the interrupt structures. The IPC channel is
When multiple processors share a resource, the processors used to lock the access to the data registers. The IPC
are capable of acquiring and releasing the IPC channel. So channel is acquired by the sender and used to populate the
the processor can assume an IPC channel as a lock. The message. The receiver reads the message and then
semantics of this code is that access to the shared resource releases the channel. Thus, between the sender putting
is gated by the processor’s ownership of the channel. So the data into the channel and receiver reading it, the channel is
processors will need to acquire the IPC channel before they locked for all other task access. The sender uses a notify
access the shared resource. event on the receiver’s IPC interrupt to denote a send
operation. The receiver acts on this interrupt and reads the
A failure to acquire the IPC channel signifies a lock on the
data from the data registers. After the reception is complete,
shared resource because another processor has control of
the receiver releases the channel and can also generate a
it. Note that the IPC channel will not enforce which
release event to the senders IPC interrupt. Note that the
processor acquires or releases the channel. All processors
action of locking the channel does not, in hardware, restrict
can acquire or release the IPC channel and the semantics of
access to the data registers. This is a semantic that should
the code must make sure that the processor that acquires
be enforced by software.
the channel is the one that releases it.
Figure 6-5 portrays an example of a sender (Processor A)
sending data to a receiver (Processor B). IPC interrupt A is

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 44
 Inter-Processor Communication

configured to interrupt Processor A. IPC interrupt B is notify event was enabled by setting the mask bit
configured to interrupt Processor B. (IPC_INTR_STRUCTx_INTR_MASK [31:23]) in the IPC
1. The sender will attempt to acquire the IPC channel by interrupt B, this will generate an interrupt in the receiver.
reading the IPC_STRUCTx_ACQUIRE register. If the 4. When it receives IPC interrupt B, the receiver can poll
channel was acquired, the sender has ownership of the the IPC_INTR_STRUCTx_INTR_MASKED register to
channel for data transmission. This also changes the understand which IPC channel had triggered the notify
status of the channel and its corresponding event. Based on this, the receiver identifies the channel
IPC_STRUCTx_LOCK_STATUS register. If the channel to read and reads from the IPC channel’s
was not acquired, the processor should wait until the IPC_STRUCTx_DATA0 and IPC_STRUCTx_DATA1
channel is free for acquisition. This can be done by registers. The receiver has now received the data sent
polling the IPC channel’s by the sender. It needs to release the channel so that
IPC_STRUCTx_LOCK_STATUS register. other processors/processes can use it.
2. After the IPC channel is acquired, the sender has control 5. The receiver releases the channel. It also optionally
of the channel for communication and places the 64-bit generates a release event on the sender’s IPC interrupt
message data in the IPC_STRUCTx_DATA0 and A. This will generate a release event interrupt on the
IPC_STRUCTx_DATA1 registers. sender if the corresponding channel release event was
3. Now that the message is placed in the IPC channel, the masked.
sender generates a notify event on the receiver’s On receiving the release interrupt, the sender can act on the
interrupt line. It does this by setting the corresponding bit event based on the application requirement. It can either try
in the IPC channel’s IPC_STRUCTx_NOTIFY register. to reacquire the channel for further transmission or go on to
This event creates a notify event at IPC interrupt B other tasks because the transmission is complete.
(IPC_INTR_STRUCTx_INTR). If the IPC channel’s
Figure 6-5. Sending Messages using IPC
IPC Channel Receiver
Sender (Processor B)
(4)
(Processor A) (1) Acquire
(3) Notify (3) (3)
(5)
(5) Release
(2) Data
IPC
IPC interrupt B
interrupt A
(1) Status (5)

Hardware action

User action

In the previous example, the size of the data being transmitted was just 64 bits. Larger messages can be sent as pointers.
The sender can allocate a larger message structure in memory and pass the pointers in the data registers. Figure 6-6 shows
the usage. Note that the user code must implement the synchronization of the message read process.
■ The implementation can stall the channel until the receiver has used up all the data in the message packet and the
message packet can be rewritten. This is wasteful because it will stall other inter-process communications as the number
of IPC channels is limited.
■ The receiver can release the channel as soon as it receives the pointer to the message packet. It implements the
synchronization logic in the message packet as a flag, which the sender sets on write complete and receiver clears on a
read complete.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 45
 Inter-Processor Communication

Figure 6-6. Communicating Larger Messages

Message
Packet

Write Read

Sender Pointer Receiver

IPC
Interrupt
Release
Data Registers

6.5 Typical Usage Models

The unique channel and interrupt architecture of the PSoC 6 IPC allows for a range of usage models for multicore
communication. Some of these are listed here as an example. Note that the communication models possible based on the
IPC architecture are not restricted to the ones listed in this document. Also note that, this document only provides a high-level
usage model and does not go into details of data management in the communication. This will need to be determined based
on the specific application use case.

6.5.1 Full Duplex Communication

In this usage model, an IPC channel is used according to the direction of communication between cores. For managing
events an IPC interrupt is used per core. In a dual core system this will translate to what is shown in Figure 6-7.
In this example, the IPC channel X is dedicated to data communication from Core 0 to Core 1 and IPC channel Y is for data
communication from Core 1 to core 0. The IPC interrupt X will signal events on Core 1. Hence its interrupt output is connected
to Core 1's system interrupts. The events are triggered by writing into the IPC interrupts register structure over the system
bus. Similarly, IPC interrupt Y is dedicated to Core 0.
Figure 6-7. Full Duplex IPC for Dual Core Communication
IPC
System Interrupt
Interrupt X

IPC Channel X
Core 0 Core 1
IPC Channel Y

System IPC
Interrupt Interrupt Y

Data transfer/register updates over system bus

Digital signals such as triggers or interrupts

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 46
 Inter-Processor Communication

6.5.2 Half Duplex with Independent Event Handling

In this case only one IPC channel is used to set up the transfer between the two cores. This means that only one side controls
data transfer at a time. The channels Lock register must be used to avoid contention of the one shared IPC channel. Two
independent events are supported due to the two IPC interrupt structures being used. This model is shown in Figure 6-8.
Figure 6-8. Half Duplex with Independent Event Handling

IPC
System Interrupt
Interrupt X

Core 0 IPC Channel X Core 1

System IPC
Interrupt Interrupt Y

Data transfer/register updates over system bus

Digital signals such as triggers or interrupts

6.5.3 Half Duplex with Shared Event Handling

In this model both the IPC channel and interrupt are shared between the two cores. Since the interrupt is also shared, the
access to the interrupt registers must be managed using the IPC lock of the channel. As shown in Figure 6-9, the IPC
interrupt will be set up to trigger interrupts in both cores. Hence the individual core interrupts should have logic in its ISR to
check which core is in control of the IPC and determine if the message and event was for that core.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 47
 Inter-Processor Communication

Figure 6-9. Half Duplex with Shared Event Handling

System Interrupt
IPC
Interrupt
X
System Interrupt

Core 0 IPC Channel X Core 1

Data transfer/register updates over system bus

Digital signals such as triggers or interrupts

Note: Some IPC channel and interrupt structures are reserved as part of the SROM code. Refer to the SROM architecture
and API in Flash Memory Programming on page 167 for a list IPC channels and interrupts being used by this API.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 48
 7. Fault Monitoring

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

Fault monitoring allows you to monitor various faults generated within the device and take actions based on the fault reported.
The fault structures present in the PSoC 6 MCU monitor access violation faults at protection units (MPU, SMPU, or PPU) and
flash controller bus error/fault. In addition to reporting faults, the fault structures in PSoC 6 MCUs provide a mechanism to log
data from the fault sources and optionally perform soft reset.
The PSoC 6 MCU family supports two centralized fault report/monitoring structures that monitor faults generated within the
device. Each fault report structure can monitor and report faults from up to 96 sources.

7.1 Features
Each PSoC 6 MCU fault report structure supports:
■ Monitoring protection unit access violation faults and flash controller bus errors
■ Four 32-bit data registers to record fault information
■ Soft reset on fault detection while retaining the fault information
■ Interrupt on fault detection
■ Trigger output to DMA for fault data transfer
■ Fault detected output to a pin for external fault handling

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 49
 Fault Monitoring

7.2 Architecture
Figure 7-1. Fault Report Structure
Fault report Structure [x]
FAULT_CTL interrupt_fault[x]

FAULT_STATUS tr_fault[x]
FAULT_DATA0 fault_out[x]
Fault source 0 Fault Data
...

FAULT_DATA3 fault_reset_req[x]
Fault report
‫ ﺫ‬up to 96 ... Pending faults Fault report
Structure[0]
FAULT_PENDING0
Structure[1]
Retained during
Fault source 95 Fault Data FAULT_PENDING1 soft reset
FAULT_PENDING2

FAULT_MASK0
Single structure,
used by all fault FAULT_MASK1
report structures. FAULT_MASK2

INTR_FAULT

INTR_FAULT_SET

INTR_FAULT_MASK

INTR_FAULT_MASKED

The PSoC 6 MCU family uses centralized fault report structures. This centralized nature allows for a system wide handling of
faults simplifying firmware development. Only a single fault interrupt handler is required to monitor multiple faults. The fault
report structure provides the fault source and additional fault specific information through a single set of registers; no iterative
search for the fault source and fault information is required.
The fault structure can be configured to capture one or more faults as listed in Table 7-2. When a fault structure is configured
to capture a specific fault, an occurrence of that fault will be recorded as a pending fault. If the fault structure has finished
processing all other faults or if there are no other pending faults, the fault data will be captured into the fault structure
registers. In addition, a successful capture can trigger an interrupt and be processed by either Cortex-M4 or Cortex-M0+
depending on the application requirement.
It should be noted that each fault structure is capable of capturing only one fault at a time and as long as that fault is not
serviced, subsequent faults will not be captured by the fault structure. In addition to capturing faults, the fault structure can
optionally perform a soft reset while retaining the fault information. This reset results in RESET_ACT_FAULT reset cause in
the SRSS_RES_CAUSE register.

7.2.1 Fault Report

The PSoC 6 MCU family supports two fault report structures. Each fault report structure has a dedicated set of control and
status registers. Each fault report structure captures a single fault. The captured fault information includes:
■ Fault validity bit that indicates a fault is captured (VALID bit [31] of the FAULT_STRUCTx_STATUS register). This bit is set
whenever a fault is captured. The bit should be cleared after processing the fault information. New faults are captured only
when this bit is ‘0’.
■ Fault index, as shown in Table 7-2, identifies the fault source (IDX bits [6:0] of FAULT_STRUCTx_STATUS)
■ Additional fault information describing fault specifics (FAULT_STRUCTx_DATA0 through FAULT_STRUCTx_DATA3
registers). This additional information is fault source specific. For example, an MPU protection violation provides

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 Fault Monitoring

information on the violating bus address, the bus master identifier, and bus access control information in only two
FAULT_DATA registers. The details of the fault information for various faults is explained in Table 7-1.

Table 7-1. Fault Information

Fault Source Fault Information
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
MPU/SMPU violation DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
Master interface PPU violation DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0': PPU violation, '1': peripheral bus error.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
Peripheral group PPU violation DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:30]: ‘0’: PPU violation, ‘1’: timeout detected, ‘2’: peripheral bus error.
FAULT_DATA0[31:0]: Violating address.
FAULT_DATA1[31]: '0': FLASH macro interface bus error; '1': memory hole.
Flash controller bus error
FAULT_DATA1[15:12]: Protection context identifier.
FAULT_DATA1[11:8]: Master identifier.

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 Fault Monitoring

7.2.2 Signaling Interface FAULT_STRUCTx_STATUS register. See the Trigger

Multiplexer Block chapter on page 294 for more details.
In addition to captured fault information, each fault report
■ A chip output signal (fault_out[x]). The fault structure
structure supports a signaling interface to notify the system
generates an output signal, which is set when VALID bit
about the captured fault. The interface of fault report
[31] of the FAULT_STRUCTx_STATUS register is set.
structure ‘x’ supports the following:
This signal can be routed out of the device through the
■ A fault interrupt (interrupt_fault[x]). Use the HSIOM (refer to the PSoC 61 datasheet/PSoC 62
FAULT_STRUCTx_INTR, datasheet). The output signal is enabled by setting the
FAULT_STRUCTx_INTR_SET, OUT_EN bit [1] of the FAULT_STRUCTx_CTL register.
FAULT_STRUCTx_INTR_MASK and The output signal can be used to communicate non-
FAULT_STRUCTx_INTR_MASKED registers to monitor, recoverable faults to off-chip components (possibly
set, and mask the FAULT_STRUCTURE[x]’s interrupt. resulting in a reset of the chip).
Only a single interrupt cause is available, which
■ A fault reset request signal (fault_reset_req[x]). The fault
indicates that a fault is detected. The fault report
structure generates a soft reset when VALID bit [31] of
registers can be read in the interrupt handler to deduce
the FAULT_STRUCTx_STATUS register is set. The
the fault. The FAULT bit [0] of the
reset capability is enabled by setting RESET_REQ_EN
FAULT_STRUCTx_INTR_MASK register provides a
bit [2] of FAULT_STRUCTx_CTL. The reset request
mask/enable for the interrupt. The FAULT bit [0] of the
performs a soft reset. This reset is captured as
FAULT_STRUCTx_INTR register is set to ‘1’ when a
RESET_ACT_FAULT in the SRSS_RES_CAUSE
fault is captured. Setting this bit in firmware clears the
register. The fault information in
interrupt.
FAULT_STRUCTx_STATUS and
■ A DMA trigger (tr_fault[x]). The fault structure generates FAULT_STRUCTx_DATA registers is retained through
a DMA trigger when VALID bit [31] of the this reset.
FAULT_STRUCTx_STATUS register is set. To enable
the trigger, set the TR_EN bit [0] of the Because the device has a single fault_reset_req signal, the
FAULT_STRUCTx_CTL register. The trigger can be individual fault_reset_req[x] signals from the fault structures
connected to a DMA controller, which can transfer are combined into a single fault_reset_req signal as shown
captured fault information from the fault report structure in Figure 7-2.
to memory and can clear the VALID bit [31] of the
Figure 7-2. Fault Reset Request

fault_reset_req[0]
fault_reset_req
fault_reset_req[1] (to device soft reset line)

7.2.3 Monitoring FAULT_STRUCTx_MASK1, FAULT_STRUCTx_MASK2

registers of a fault structure decide the pending faults that it
A central structure, which is shared by all fault report captures. These faults are referred to as “enabled” faults.
structures, keeps track of all pending faults in the system. The FAULT_STRUCTx_MASK registers are unique to each
The FAULT_STRUCTx_PENDINGx registers reflect what fault structure. This allows for the following:
fault sources are pending and provide a single pending bit
■ One fault report structure is used to capture recoverable
for up to 96 fault sources. The registers are mirrored in all
faults and one fault report structure is used to capture
the fault report structures; that is, they read the same value
non-recoverable faults. The former can be used to
in all fault structures. The bit indexing in the registers follow
generate a fault interrupt and the latter can be used to
the fault index captured in Table 7-2. For instance, bit [0] of
activate a chip output signal and/or activate a reset
FAULT_STRUCTx_PENDING0 captures a CM0+ MPU/
request.
SMPU violation and bit [1] of
FAULT_STRUCTx_PENDING1 captures a peripheral ■ Two fault report structures are used to capture the same
group#1 PPU violation. faults. The first fault is captured by the structure with the
lower index (for example, fault structure 0) and the
The pending faults are faults that are not yet captured by a second fault is captured by the structure with the higher
fault structure. When a pending fault is captured by a fault index (for example, fault structure 1). Note that both
structure, the associated pending bit is cleared to ‘0’. structures cannot capture the same fault at the same
Each fault report structure is selective in the faults it time. As soon as a fault is captured, the pending bit is
captures. The FAULT_STRUCTx_MASK0, cleared and the other structure will not be aware of the

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 Fault Monitoring

fault. Fault structure 0 has precedence over fault c. Enable the FAULTx interrupt to the CPU by configur-
structure 1. ing the appropriate ISER register. Refer to the
Interrupts chapter on page 56.
The fault structure captures “enabled” faults only when
VALID bit [31] of FAULT_STRUCTx_STATUS register is ‘0’. 3. For fault handling through DMA
When a fault is captured, hardware sets the VALID bit [31] of a. Set the TR_EN bit [0] of the FAULT_STRUCTx_CTL
the FAULT_STRUCTx_STATUS register. In addition, register.
hardware clears the associated pending bit to ‘0’. When a b. Route the tr_fault[x] signal to the trigger input DMA
fault structure is processed, firmware or a DMA transfer controller. Refer to the Trigger Multiplexer
should clear the VALID bit [31] of the Block chapter on page 294.
FAULT_STRUCTx_STATUS register. Note that fault
c. Configure and enable the DMA controller to transfer
capturing does not consider FAULT bit [0] of
FAULT_STRUCTx_STATUS and FAULT_STRUCTx-
FAULT_STRUCTx_INTR register and firmware should clear
_DATA registers to memory and write back ‘0’ to
the bit after servicing the interrupt, if the interrupt is enabled.
FAULT_STRUCTx_STATUS register after the trans-
fer is complete. Refer to the DMA Controller
7.2.4 Low-power Mode Operation (DW) chapter on page 91.
The fault report structure functionality is available in Active 4. For fault handling outside the device
and Sleep (and their LP counterparts) power modes only. a. Set the OUT_EN bit [1] of FAULT_STRUCTx_CTL
The interfaces between the fault sources and fault report register.
structures are reset in the Deep Sleep power mode.
b. Route the fault_out[x] signal to a pin through HSIOM.
Because the fault report structure is an active functionality,
Refer to the PSoC 61 datasheet/PSoC 62 datasheet.
pending faults (in the FAULT_STRUCTx_PENDING
registers) are not retained when transitioning to Deep Sleep c. Use the signal externally for processing the fault –
power mode. The fault structure’s registers can be generate external reset, power cycle, or log fault
partitioned based on the reset domain and their retention information.
capability as follows: 5. Set the RESET_REQ_EN bit [2] of the FAULT_-
■ Active reset domain: FAULT_STRUCTx_PENDING, STRUCTx_CTL register, if a soft reset is required on any
FAULT_STRUCTx_INTR, fault detection in the structure.
FAULT_STRUCTx_INTR_SET, and 6. Clear VALID bit [31] of the FAULT_STRUCTx_STATUS
FAULT_STRUCTx_INTR_MASKED registers. These register to clear any fault captured.
registers are not retained in Deep Sleep power mode. 7. Set the fault index bits in the FAULT_STRUCTx_MASK
■ Deep Sleep reset domain: FAULT_STRUCTx_CTL, registers for faults that need to be captured by the fault
FAULT_STRUCTx_MASK, and structure as explained in 7.2.3 Monitoring.
FAULT_STRUCTx_INTR_MASK registers. These
registers are retained in Deep Sleep power mode but 7.2.6 CPU Exceptions Versus Fault
any system reset will reset these registers to the default
state.
Monitoring
■ Hard reset domain: FAULT_STRUCTx_STATUS and Some faults captured in Table 7-2 also result in bus errors or
FAULT_STRUCTx_DATA registers. These registers are CPU exceptions (Cortex-M4 Bus/Usage/Memory/Hard
retained through soft resets (detectable in faults). The faults can be communicated in two ways:
SRSS_RES_CAUSE registers). However, hard resets ■ As a bus error to the master of the faulting bus transfer.
such as XRES/POR/BOD will reset the registers. This will result in Bus, Usage, Memory, or Hard fault
exceptions in the CPU.
7.2.5 Using a Fault Structure ■ As a fault in a fault report structure. This fault can be
communicated as a fault interrupt to any processor in the
Follow these steps to configure and use a fault structure:
system. This allows fault handling on a processor that is
1. Identify the faults from Table 7-2 to be monitored in the not the master of the faulting bus transfer. It is useful for
system. faults that cause the master of the faulting transfer to
2. For firmware fault handling through interrupts become unresponsive or unreliable.
a. Set the FAULT bit [0] of the FAULT_STRUCTx_IN-
TR_MASK register.
b. Set the FAULT bit [0] of the FAULT_STRUCTx_INTR
register to clear any pending interrupt.

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 Fault Monitoring

7.3 Fault Sources

The fault sources can vary between device families. Table 7-2 provides the list of fault sources available in PSoC 6 MCUs.

Table 7-2. Fault Sources

Fault Index Source Description
0 cpuss.mpu_vio[0] CM0+ MPU/SMPU violation
1 cpuss.mpu_vio[1] CRYPTO MPU/SMPU violation
2 cpuss.mpu_vio[2] DW0 MPU/SMPU violation
3 cpuss.mpu_vio[3] DW1 MPU/SMPU violation
4 cpuss.mpu_vio[4] DMAC MPU/SMPU violation
5 cpuss.mpu_vio[5] SDHC0 MPU/SMPU violation
6
7 to 15 Reserved
16 cpuss.mpu_vio[16] CM4 MPU/SMPU violation (System bus)
17 cpuss.mpu_vio[17] CM4 code error
18 cpuss.mpu_vio[18] CM4 code flash controller errors
19 to 27 Reserved
28 peri.ms_vio[0] CM0+ Peripheral Master Interface PPU violation
29 peri.ms_vio[1] CM4 Peripheral Master Interface PPU violation
30 peri.ms_vio[2] DW0 Peripheral Master Interface PPU violation
31 peri.ms_vio[3] DW1 Peripheral Master Interface PPU violation
Peripheral group #0 (Peripheral Clock dividers, Trigger Mux etc) PPU violation
32 peri.group_vio[0]
Register address range: 0x40000000 to 0x40100000
Peripheral group #1 (Crypto block) PPU violation
33 peri.group_vio[1]
Register address range: 0x40100000 to 0x40200000
Peripheral group #2 (CPUSS, SRSS, EFUSE) PPU violation
34 peri.group_vio[2]
Register address range: 0x40200000 to 0x40300000
Peripheral group #3 (IOSS, LPCOMP, CSD, TCPWM, LCD, Bluetooth LE) PPU violation
35 peri.group_vio[3]
Register address range: 0x40300000 to 0x40400000
Peripheral group #4 (SMIF) PPU violation
36 peri.group_vio[4]
Register address range: 0x40400000 to 0x40500000
37
Peripheral group #6 (SCB) PPU violation
38 peri.group_vio[6]
Register address range: 0x40600000 to 0x40700000
39 Reserved
40 Reserved
Peripheral group #9 (PASS) PPU violation
41 peri.group_vio[9]
Register address range: 0x41000000 to 0x42000000
42
43 to 47 Reserved
48 cpuss.flashc_main_bus_err Flash controller bus error
49 to 95 Reserved

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 Fault Monitoring

7.4 Register List

Name Description
FAULT_STRUCTx_CTL Fault control register for enabling DMA trigger, fault output, and fault reset signals
FAULT_STRUCTx_STATUS Fault status register that stores the validity and fault index of the currently captured fault
FAULT_STRUCTx_DATA0 Fault data register 0 that stores fault information associated with the currently captured fault
FAULT_STRUCTx_DATA1 Fault data register 1 that stores fault information associated with the currently captured fault
FAULT_STRUCTx_DATA2 Fault data register 2 that stores fault information associated with the currently captured fault
FAULT_STRUCTx_DATA3 Fault data register 3 that stores fault information associated with the currently captured fault
FAULT_STRUCTx_PENDING0 Fault pending register 0 that stores pending (not captured) faults with fault index from 0 to 31
FAULT_STRUCTx_PENDING1 Fault pending register 1 that stores pending (not captured) faults with fault index from 32 to 63
FAULT_STRUCTx_PENDING2 Fault pending register 2 that stores pending (not captured) faults with fault index from 64 to 95
Fault mask register 0 that enables the capture of pending faults with fault index from 0 to 31 by the
FAULT_STRUCTx_MASK0
fault structure
Fault mask register 1 that enables the capture of pending faults with fault index from 32 to 63 by the
FAULT_STRUCTx_MASK1
fault structure
Fault mask register 2 that enables the capture of pending faults with fault index from 64 to 95 by the
FAULT_STRUCTx_MASK2
fault structure
FAULT_STRUCTx_INTR Fault interrupt register that stores the unmasked status of the fault structure's interrupt
FAULT_STRUCTx_INTR_SET Fault interrupt set register used to set the fault structure's interrupt through firmware
FAULT_STRUCTx_INTR_MASK Fault interrupt mask register that masks fault interrupt
FAULT_STRUCTx_INTR_MASKED Fault interrupt register that stores the masked status of the fault structure's interrupt

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 55
 8. Interrupts

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU family supports interrupts and CPU exceptions on both Cortex-M4 and Cortex-M0+ cores. Any condition
that halts normal execution of instructions is treated as an exception by the CPU. Thus an interrupt request is treated as an
exception. However, in the context of this chapter, interrupts refer to those events generated by peripherals external to the
CPU such as timers, serial communication block, and port pin signals; exceptions refer to those events that are generated by
the CPU such as memory access faults and internal system timer events. Both interrupts and exceptions result in the current
program flow being stopped and the exception handler or interrupt service routine (ISR) being executed by the CPU. Both
Cortex-M4 and Cortex-M0+ cores provide their own unified exception vector table for both interrupt handlers/ISR and
exception handlers.

8.1 Features
The PSoC 6 MCU supports the following interrupt features:
■ Supports 168 system interrupts
❐ 168 Arm Cortex-M4 interrupts
❐ Eight Arm Cortex-M0+ external interrupts and eight Arm Cortex-M0+ internal (software only) interrupts. The CPU sup-
ports up to 32 interrupts, but only 16 interrupts are used by PSoC 6 interrupt infrastructure. The eight external CPU
interrupts support deep sleep (WIC) functionality
❐ Four system interrupts can be mapped to each of the CPU non-maskable interrupt (NMI)
❐ Up to 39 interrupt sources capable of waking the device from Deep Sleep power mode
■ Nested vectored interrupt controller (NVIC) integrated with each CPU core, yielding low interrupt latency
■ Wakeup interrupt controller (WIC) enabling interrupt detection (CPU wakeup) in Deep Sleep power mode
■ Vector table may be placed in either flash or SRAM
■ Configurable priority levels (eight levels for Cortex-M4 and four levels for Cortex-M0+) for each interrupt
■ Level-triggered and pulse-triggered interrupt signals

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 56
 Interrupts

8.2 Architecture
Figure 8-1. PSoC 6 MCU Interrupts Block Diagram

PSoC 6 Interrupt Architecture M0+ interrupt settings

Enable / Disable Interrupt
Set Priority
CPUSS_CM0_SYSTEM_INT_CTLx Mask Interrupt
Set NMI source
Each IRQn can be Software trigger
connected to one or
more of the 168
interrupt sources

INT Source 0 M0+ processor

INT Source 1
168 M0+ Cortex M0+
Interrupt sources
INT Source 2 Interrupt Processor core
(Peripherals)
gen NVIC
Wakeup
Wakeup Interrupt
INT Source 167 168 Controller (WIC)1

M0+ Wakeup
System Wakeup
M4 Wakeup

IRQn is connected 39 (IRQ0 – IRQ38)

to INT source n
Wakeup Interrupt
Controller (WIC)1
Wakeup
NVIC
Cortex M4
Processor core
Available in Deep Sleep

Register control M4 processor

M4 interrupt settings
Enable / Disable Interrupt
Set Priority
Mask Interrupt
Set NMI source
Software Trigger
Note1 - Input IRQn lines to the WIC are unsynchronized

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 Interrupts

Figure 8-1 shows the PSoC 6 MCU interrupt architecture. 2. On detecting the signal from the NVIC, the CPU stores
The PSoC 6 MCU has 168 system interrupts that are its current context by pushing the contents of the CPU
generated by various peripherals. These interrupt signals registers onto the stack.
are processed by the NVIC of the individual core. In the 3. The CPU also receives the exception number of the
Cortex-M4 core, the system interrupt source ‘n’ is directly triggered interrupt from the NVIC. All interrupts and
connected to IRQn. The Cortex-M0+ interrupt architecture exceptions have a unique exception number, as given in
uses eight CPU interrupts IRQ[7:0] out of the 32 available Table 8-1. By using this exception number, the CPU
IRQn lines of the core. In the Cortex-M0+ core, the system fetches the address of the specific exception handler
interrupt source connection to a particular IRQn of the core from the vector table.
is configurable and any of the 168 system interrupts can be
4. The CPU then branches to this address and executes
mapped to any of the IRQ[7:0]. This ensures that all the
the exception handler that follows.
system interrupts can be mapped onto any CPU interrupt
simultaneously. Refer to Interrupt Sources on page 62 for 5. Upon completion of the exception handler, the CPU
more details about the system interrupt to CPU interrupt registers are restored to their original state using stack
mapping. The NVIC takes care of enabling/disabling pop operations; the CPU resumes the main code
individual interrupt IRQs, priority resolution, and execution.
communication with the CPU core. The other exceptions Figure 8-2. Interrupt Handling When Triggered
such as NMI and hard faults are not shown in Figure 8-1
because they are part of CPU core generated events, unlike Rising Edge on Interrupt Line is
interrupts, which are generated by peripherals external to registered by the NVIC
the CPU.
In addition to the NVIC, the PSoC 6 MCU supports wakeup
interrupt controllers (WIC) for each CPU and a shared CPU detects the request signal
from NVIC and stores its
interrupt synchronization block that synchronizes the current context by pushing
interrupts to CLK_HF domain (adds two CLK_HF cycles contents onto the stack
delay for synchronization). The WIC provides detection of
Deep Sleep interrupts in the Deep Sleep CPU power mode.
Each CPU can individually be in Deep Sleep mode; the
CPU receives exception
device is said to be in Deep Sleep mode only when both the number of triggered interrupt
CPUs are in Deep Sleep mode. Refer to the Device Power and fetches the address of the
Modes chapter on page 225 for details. The Cortex-M4 WIC specific exception handle from
vector table.
block supports up to 39 interrupts that can wake up the CPU
from Deep Sleep power mode. The Cortex-M0+ WIC block
supports all eight interrupts. The device exits Deep Sleep
mode (System Wakeup signal in Figure 8-1) as soon as one CPU branches to the received
CPU wakes up. The synchronization blocks synchronize the address and executes
exception handler
interrupts to the CPU clock frequency as the peripheral
interrupts can be asynchronous to the CPU clock frequency.

CPU registers are restored

8.3 Interrupts and Exceptions - using stack upon completion of
exception handler.
Operation
When the NVIC receives an interrupt request while another
8.3.1 Interrupt/Exception Handling interrupt is being serviced or receives multiple interrupt
The following sequence of events occurs when an interrupt requests at the same time, it evaluates the priority of all
or exception event is triggered: these interrupts, sending the exception number of the
highest priority interrupt to the CPU. Thus, a higher priority
1. Assuming that all the interrupt and exception signals are interrupt can block the execution of a lower priority ISR at
initially low (idle or inactive state) and the processor is any time.
executing the main code, a rising edge on any one of the
signals is registered by the NVIC, if the interrupt or Exceptions are handled in the same way that interrupts are
exception is enabled to be serviced by the CPU. The handled. Each exception event has a unique exception
signal is now in a pending state waiting to be serviced by number, which is used by the CPU to execute the
the CPU. appropriate exception handler.

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 Interrupts

8.3.2 Level and Pulse Interrupts is initially inactive (logic low), the following sequence of
events explains the handling of level and pulse interrupts:
Both CM0+ and CM4 NVICs support level and pulse signals
1. On a rising edge event of the interrupt signal, the NVIC
on the interrupt lines (IRQn). The classification of an
registers the interrupt request. The interrupt is now in the
interrupt as level or pulse is based on the interrupt source.
pending state, which means the interrupt requests have
Figure 8-3. Level Interrupts not yet been serviced by the CPU.
2. The NVIC then sends the exception number along with
IRQn the interrupt request signal to the CPU. When the CPU
CPU
IRQn is still high starts executing the ISR, the pending state of the
Execution ISR ISR ISR interrupt is cleared.
main main main
State
3. For pulse interrupts, when the ISR is being executed by
the CPU, one or more rising edges of the interrupt signal
are logged as a single pending request. The pending
Figure 8-4. Pulse Interrupts interrupt is serviced again after the current ISR
execution is complete (see Figure 8-4 for pulse
IRQn interrupts).
CPU 4. For level interrupts, if the interrupt signal is still high after
Execution ISR ISR ISR
main main main completing the ISR, it will be pending and the ISR is
State
executed again. Figure 8-3 illustrates this for level
triggered interrupts, where the ISR is executed as long
Figure 8-3 and Figure 8-4 show the working of level and as the interrupt signal is high.
pulse interrupts, respectively. Assuming the interrupt signal

8.3.3 Exception Vector Table

The exception vector tables (Table 8-1 and Table 8-2) store the entry point addresses for all exception handlers in Cortex-
M0+ and Cortex-M4 cores. The CPU fetches the appropriate address based on the exception number.

Table 8-1. M0+ Exception Vector Table

Exception Number Exception Exception Priority Vector Address
– Initial Stack Pointer Value Not applicable (NA) Start_Address = 0x0000 or CM0P_SCS_VTORa
1 Reset –3, the highest priority Start_Address + 0x04
2 Non Maskable Interrupt (NMI) –2 Start_Address + 0x08
3 HardFault –1 Start_Address + 0x0C
4-10 Reserved NA Start_Address + 0x10 to Start_Address + 0x28
11 Supervisory Call (SVCall) Configurable (0 – 3) Start_Address + 0x2C
12-13 Reserved NA Start_Address + 0x30 to Start_Address + 0x34
14 PendSupervisory (PendSV) Configurable (0 – 3) Start_Address + 0x38
15 System Timer (SysTick) Configurable (0 – 3) Start_Address + 0x3C
16 External Interrupt (IRQ0) Configurable (0 – 3) Start_Address + 0x40
… … Configurable (0 – 3) …
31 External Interrupt (IRQ15) Configurable (0 – 3) Start_Address + 0x7C
a. Start Address = 0x0000 on reset and is later modified by firmware by updating the CM0P_SCS_VTOR register.

Table 8-2. Cortex-M4 Exception Vector Table

Exception Number Exception Exception Priority Vector Address
– Initial stack pointer value – Start_Address = 0x0000 or CM4_SCS_VTORa
1 Reset –3, highest priority Start _Address + 0x0004
2 Non Maskable Interrupt (NMI) –2 Start _Address + 0x0008
3 Hard fault –1 Start _Address + 0x000C
4 Memory management fault Configurable (0 – 7) Start _Address + 0x0010
5 Bus fault Configurable (0 – 7) Start _Address + 0x0014

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 Interrupts

Table 8-2. Cortex-M4 Exception Vector Table (continued)

Exception Number Exception Exception Priority Vector Address
6 Usage fault Configurable (0 – 7) Start _Address + 0x0018
7–10 Reserved – –
11 Supervisory call (SVCall) Configurable (0 – 7) Start _Address + 0x002C
12–13 Reserved – –
14 Pend Supervisory (PendSV) Configurable (0 – 7) Start _Address + 0x0038
15 System Tick timer (SysTick) Configurable (0 – 7) Start _Address + 0x003C
16 External interrupt (IRQ0) Configurable (0 – 7) Start _Address + 0x0040
…. …. …. ….
182 External interrupt (IRQ166) Configurable (0 – 7) Start _Address + 0x02D8
183 External interrupt (IRQ167) Configurable (0 – 7) Start _Address + 0x02DC
a. Start Address = 0x0000 on reset and is later modified by firmware by updating CM4_SCS_VTOR register.

In Table 8-1 and Table 8-2, the first word (4 bytes) is not CM0+ core executes the ROM boot code and can enable
marked as exception number zero. This is because the first Cortex-M4 core from the application code. The reset
word in the exception table is used to initialize the main exception of the CM0+ core is tied to the device reset or
stack pointer (MSP) value on device reset; it is not startup. When the Cortex-M0+ core releases the Cortex-M4
considered as an exception. In the PSoC 6 MCU, both the reset, the M4 reset exception is executed. A device reset
vector tables can be configured to be located either in flash can occur due to multiple reasons, such as power-on-reset
memory or SRAM. The vector table offset register (VTOR) (POR), external reset signal on XRES pin, or watchdog
present as part of Cortex-M0+ and Cortex-M4 system reset. When the device is reset, the initial boot code for
control space registers configures the vector table offset configuring the device is executed by the Cortex-M0+ out of
from the base address (0x0000). The CM0P_SCS_VTOR supervisory read-only memory (SROM). The boot code and
register sets the vector offset address for the CM0+ core other data in SROM memory are programmed by Cypress,
and CM4_SCS_VTOR sets the offset for the M4 core. The and are not read/write accessible to external users. After
VTOR value determines whether the vector table is in flash completing the SROM boot sequence, the Cortex-M0+ code
memory (0x10000000 to 0x10100000) or SRAM execution jumps to flash memory. Flash memory address
(0x08000000 to 0x08048000). Note that the VTOR registers 0x10000004 (Exception#1 in Table 8-1) stores the location
can be updated only in privilege CPU mode. The advantage of the startup code in flash memory. The CPU starts
of moving the vector table to SRAM is that the exception executing code out of this address. Note that the reset
handler addresses can be dynamically changed by exception address in the SRAM vector table will never be
modifying the SRAM vector table contents. However, the used because the device comes out of reset with the flash
nonvolatile flash memory vector table must be modified by a vector table selected. The register configuration to select the
flash memory write. Note that the exception table must be SRAM vector table can be done only as part of the startup
256 byte-aligned for Cortex-M0+ and 1024 byte-aligned for code in flash after the reset is de-asserted. Note that the
Cortex-M4. reset exception flow for Cortex-M4 is the same as Cortex-
M0+. However, Cortex-M4 execution begins only after
The exception sources (exception numbers 1 to 15) are
CM0+ core de-asserts the M4 reset.
explained in 8.4 Exception Sources. The exceptions marked
as Reserved in Table 8-1 are not used, although they have
addresses reserved for them in the vector table. The 8.4.2 Non-Maskable Interrupt Exception
interrupt sources (exception numbers 16 to 183) are Non-maskable interrupt (NMI) is the highest priority
explained in 8.5 Interrupt Sources. exception next to reset. It is always enabled with a fixed
priority of –2. Both the cores have their own NMI exception.
8.4 Exception Sources There are three ways to trigger an NMI exception in a CPU
core:
This section explains the different exception sources listed ■ NMI exception from a system interrupt: Both Cortex-
in Table 8-1 and Table 8-2 (exception numbers 1 to 15). M0+ and Cortex-M4 provide an option to trigger an NMI
exception from up to four of the 168 system interrupts.
8.4.1 Reset Exception The NMI exception triggered due to the interrupt will
execute the NMI handler pointed to by the active
Device reset is treated as an exception in PSoC 6 MCUs. exception vector table. The CPUSS_CM4_NMI_CTLx
Reset exception is always enabled with a fixed priority of –3, and CPUSS_CM0P_NMI_CTLx registers select the
the highest priority exception in both the cores. When the interrupt source that triggers the NMI from hardware.
device boots up, only the Cortex-M0+ core is available. The

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 Interrupts

The registers have a default value of 1023; that is, if the the NMI. NMI is triggered when any of the four interrupts
register is set to 1023, then that particular register does are triggered; that is, the interrupts are logically ORed.
not map any interrupt source to the NMI. There are four See Figure 8-5.
such registers and each can map one interrupt vector to
Figure 8-5. NMI Trigger
CPUSS_CM4_NMI_CTLx
Or
CPUSS_CM0P_NMI_CTLx

10
0

0
INT Source 0 n
1023
System interrupt
sources INT Source 1 1
n CM4 NMI
INT Source 2 1023
Or
n <= 1023
CM0+ NMI
(device n
2

dependent) 1023

INT Source n-1 n

3

1023

■ NMI exception by setting NMIPENDSET bit (user NMI because of an error during normal or exception processing.
exception): An NMI exception can be triggered in HardFault has a fixed priority of –1, meaning it has higher
software by setting the NMIPENDSET bit in the interrupt priority than any exception with configurable priority. A
control state registers (CM0P_SCS_ICSR and HardFault exception is a catch-all exception for different
CM4_SCS_ICSR). Setting this bit will execute the NMI types of fault conditions, which include executing an
handler pointed to by the active vector table in the undefined instruction and accessing an invalid memory
respective CPU cores. addresses. The CPU does not provide fault status
■ System Call NMI exception: This exception is used for information to the HardFault exception handler, but it does
nonvolatile programming and other system call permit the handler to perform an exception return and
operations such as flash write operation and flash continue execution in cases where software has the ability
checksum operation. Inter processor communication to recover from the fault situation.
(IPC) mechanism is used to implement a system call in
PSoC 6 MCUs. A dedicated IPC mailbox is associated 8.4.4 Memory Management Fault
with each core (M0+ and M4) and the debug access port Exception
(DAP) to trigger a system call. The CPU or DAP A memory management fault is an exception that occurs
acquires this dedicated mailbox, writes the system call because of a memory protection-related fault. The fixed
opcode and argument to the mailbox, and notifies a memory protection constraints determine this fault, for both
dedicated IPC structure. Typically, the argument is a instruction and data memory transactions. This fault is
pointer to a structure in SRAM. This results in an NMI always used to abort instruction accesses to Execute Never
interrupt in the CM0+ core. Note that all the system calls (XN) memory regions. The memory management fault is
are serviced by Cortex-M0+ core. A Cortex-M0+ NMI only supported by the M4 core. The priority of the exception
exception triggered by this method executes the NMI is configurable from 0 (highest) to 7 (lowest).
exception handler code that resides in SROM. Note that
the NMI exception handler address is automatically
initialized to the system call API located in SROM (at 8.4.5 Bus Fault Exception
0x0000000D) by the boot code. The value should be A Bus Fault is an exception that occurs because of a
retained during vector table relocations; otherwise, no memory-related fault for an instruction or data memory
system call will be executed. The NMI handler code in transaction. This might be from an error detected on a bus in
SROM is not read/write accessible because it contains the memory system. The bus fault is supported only by the
nonvolatile programming routines that cannot be M4 core. The priority of the exception is configurable from 0
modified by the user. The result of the system call is (highest) to 7 (lowest).
passed through the same IPC mechanism. For details,
refer to the Inter-Processor Communication chapter on 8.4.6 Usage Fault Exception
page 41.
A Usage Fault is an exception that occurs because of a fault
8.4.3 HardFault Exception related to instruction execution. This includes:
■ an undefined instruction
Both CM0+ and CM4 cores support HardFault exception.
■ an illegal unaligned access
HardFault is an always-enabled exception that occurs

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 Interrupts

■ invalid state on instruction execution 8.4.9 System Tick (SysTick) Exception

■ an error on exception return
Both CM0+ and CM4 cores in PSoC 6 MCUs support a
The following can cause a usage fault when the core is system timer, referred to as SysTick, as part of their internal
configured to report them: architecture. SysTick provides a simple, 24-bit decrementing
■ an unaligned address on word and halfword memory counter for various timekeeping purposes such as an RTOS
access tick timer, high-speed alarm timer, or simple counter. The
SysTick timer can be configured to generate an interrupt
■ division by zero
when its count value reaches zero, which is referred to as a
The usage fault is supported only by the M4 core. The SysTick exception. The exception is enabled by setting the
priority of the exception is configurable from 0 (highest) to 7 TICKINT bit in the SysTick Control and Status Register
(lowest). (CM0P_SCS_SYST_CSR and CM4_SCS_SYST_CSR).
The priority of a SysTick exception can be configured to a
8.4.7 Supervisor Call (SVCall) Exception value between 0 and 3 for CM0+ and 0 to 7 for M4 by writing
to the bitfields PRI_15 of the System Handler Priority
Both CM0+ and CM4 cores support SVCall exception. Register 3 (SHPR3). The SysTick exception can always be
Supervisor Call (SVCall) is an always-enabled exception generated in software at any instant by writing a one to the
caused when the CPU executes the SVC instruction as part PENDSTSET bit in the Interrupt Control State Register.
of the application code. Application software uses the SVC Similarly, the pending state of the SysTick exception can be
instruction to make a call to an underlying operating system cleared by writing a one to the PENDSTCLR bit in the
and provide a service. This is known as a supervisor call. Interrupt Control State Register.
The SVC instruction enables the application to issue an
SVCall that requires privileged access to the system.
8.5 Interrupt Sources
The priority of an SVCall exception can be configured to a
value between 0 and 3 for CM0+ and 0 to 7 for CM4 core by The PSoC 6 MCU supports 168 interrupts from peripherals.
writing to the bitfields PRI_11 of the System Handler Priority The source of each interrupt is listed in Table 8-3. These
Register 2 (CM0P_SCS_SHPR2 and CM4_SCS_SHPR2). system interrupts are mapped directly to Cortex-M4 core
When the SVC instruction is executed, the SVCall exception (IRQ0 to IRQ167 or exception 16 to 183). For Cortex-M0+
enters the pending state and waits to be serviced by the core, any of the 168 interrupts can be routed to any of the
CPU. The SVCALLPENDED bit in the System Handler available eight interrupts (IRQ0 to IRQ7 or exception 16 to
Control and State Register (CM0P_SCS_SHCSR and 23). The CPUSS_CM0_SYSTEM_INT_CTLx registers are
CM4_SCS_SHCSR) can be used to check or modify the used to make this interrupt selection in CM0+.
pending status of the SVCall exception.
There are 168 CPUSS_CM0_SYSTEM_INT_CTLx
registers. The CPU_INT_IDX bits [2:0] of the register selects
8.4.8 PendSupervisory (PendSV) which IRQn line of CM0+, the xth system interrupt is mapped
Exception to. The CPU_INT_VALID bit [31] of the register decides
whether the xth interrupt is enabled for the core. For Cortex-
Both CM0+ and CM4 cores support PendSV exception. M0+, multiple system interrupts can be mapped on the
PendSV is another supervisor call related exception similar same CPU interrupt. Therefore, an active CPU interrupt may
to SVCall, normally being software-generated. PendSV is indicate one or multiple active system interrupts. For
always enabled and its priority is configurable similar to instance to connect Port 0 (IDX = 0) and Port 2 (IDX = 2)
SVCall. The PendSV exception is triggered by setting the GPIO interrupts to IRQ0 of CM0+, CPU_INT_IDX bits
PENDSVSET bit in the Interrupt Control State Register should be set to ‘0’ and CPU_INT_VALID bit should be set
(CM0P_SCS_ICSR and CM4_SCS_ICSR). On setting this to ‘1’ in CPUSS_CM0_SYSTEM_INT_CTL0 and
bit, the PendSV exception enters the pending state, and CPUSS_CM0_SYSTEM_INT_CTL2 registers. Note that this
waits to be serviced by the CPU. The pending state of a only connects and enables the interrupts; configuration and
PendSV exception can be cleared by setting the masking of the interrupt to the NVIC should be done as part
PENDSVCLR bit in the Interrupt Control State Register. The of source peripheral configuration.
priority of a PendSV exception can be configured to a value
between 0 and 3 for CM0+ and 0 to 7 for M4 by writing to the As a result of the reduction functionality in the Cortex-M0+
bitfields PRI_14 of the System Handler Priority Register 3. core, multiple system interrupts share a CPU interrupt
See the Armv6-M Architecture Reference Manual for more handler as provided by the CPU’s vector table. Each CPU
details. interrupt has an associated CPUSS_CM0_INTx_STATUS
register:
■ SYSTEM_INT_VALID bit[31] of the register specifies if
any system interrupt is active for the CPU interrupt. This

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 Interrupts

bit remains set until all the system interrupts connected SYSTEM_INT_VALID bit set. After Port 0 interrupt is
to the CPU interrupts are cleared at the source. serviced and cleared, IRQ0 will be triggered again with
■ SYSTEM_INT_IDX bits[9:0] of the register specifies the SYSTEM_INT_IDX bit set to 2 (Port 2 interrupt) in the
index (a number in the range [0, 1022]) of the lowest CPUSS_CM0_INT0_STATUS register. Only after servicing
active system interrupt mapped to the corresponding Port 2 interrupt and clearing, the SYSTEM_INT_VALID bit
CPU interrupt. will be cleared.

For instance, say CM0+ IRQ0 is connected to Port 0 and The CPU interrupt handler should use the
Port 2 GPIO interrupts. When an interrupt in both Port 0 and SYSTEM_INT_IDX field to index a system interrupt lookup
Port 2 are triggered simultaneously, IRQ0 in CM0+ will be table and jump to the system interrupt handler. The lookup
triggered with CPUSS_CM0_INT0_STATUS reading 0 (Port table is typically located in one of the system memories. The
0 interrupt) in SYSTEM_INT_IDX bit and following code illustrates the approach:

typedef void (* SystemIntr_Handler)(void);

void CM0_CpuIntr0_Handler (void)
{
uint32_t system_int_idx;
SystemIntr_Handler handler;
if(CPUSS_CM0_INT0_STATUS.SYSTEM_INT_VALID)
{
system_int_idx = CPUSS_CM0_INT0_STATUS.SYSTEM_INT_IDX;
handler = SystemIntr_Table[system_int_idx];
handler(); // jump to system interrupt handler
}
else
{
// Triggered by SW or due to SW clear error (SW cleared a peripheral
// interrupt flag but didn't clear the Pending flag at NVIC)
}
}
…
void CM0_CpuIntr7_Handler (void)
{
uint32_t system_int_idx;
SystemIntr_Handler handler;
if(CPUSS_CM0_INT7_STATUS.SYSTEM_INT_VALID)
{
system_int_idx = CPUSS_CM0_INT7_STATUS.SYSTEM_INT_IDX;
handler = SystemIntr_Table[system_int_idx];
handler(); // jump to system interrupt handler
}
else
{
// Triggered by SW or due to SW clear error (SW cleared a peripheral
// interrupt flag but didn't clear the Pending flag at NVIC)
}
}
void CM0_SystemIntr0_Handler (void)
{
// Clear the peripheral interrupt request flag by register write
// Read back the register, to ensure the completion of register write access
// Handle system interrupt 0.
}
…
void CM0_SystemIntr167_Handler (void)
{
// Clear the peripheral interrupt request flag by register write
// Read back the register, to ensure the completion of register write access

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 Interrupts

// Handle system interrupt 167.

}
The interrupts include standard interrupts from the on-chip the ISR will be executed continuously. See the I/O
peripherals such as TCPWM, serial communication block, System chapter on page 261 for details on GPIO interrupts.
CSD block, watchdog, ADC, and so on. The interrupt
As seen from Table 8-3, 39 interrupts (IRQ0 to IRQ38) are
generated is usually the logical OR of the different
capable of waking up the device from Deep Sleep power
peripheral states. The peripheral interrupt status register
mode. For Cortex-M4, IRQ0 to IRQ38 directly map to these
should be read in the ISR to detect which condition
sources. However, in the Cortex-M0+, all the eight IRQ lines
generated the interrupt. These interrupts are usually level
support Deep Sleep wakeup if they are connected to a deep
interrupts. The appropriate interrupt registers should be
sleep capable interrupt. This means the 39 Deep Sleep
cleared in the ISR to deassert the interrupt. Usually a write
wakeup-capable interrupts can be connected to any of the
'1' is required to clear the registers. If the interrupt register is
eight IRQ lines of Cortex-M0+, if such a wakeup is desired.
not cleared in the ISR, the interrupt will remain asserted and

Table 8-3. List of PSoC 6 Interrupts

Cortex M4 Exception
System Interrupt Power Mode Interrupt Source
Number
NMI 2 Active Any of the below 168 IRQ source
IRQ0 16 DeepSleep GPIO Interrupt - Port 0
IRQ1 17 DeepSleep GPIO Interrupt - Port 1
IRQ2 18 DeepSleep GPIO Interrupt - Port 2
IRQ3 19 DeepSleep GPIO Interrupt - Port 3
IRQ4 20 DeepSleep GPIO Interrupt - Port 4
IRQ5 21 DeepSleep GPIO Interrupt - Port 5
IRQ6 22 DeepSleep GPIO Interrupt - Port 6
IRQ7 23 DeepSleep GPIO Interrupt - Port 7
IRQ8 24 DeepSleep GPIO Interrupt - Port 8
IRQ9 25 DeepSleep GPIO Interrupt - Port 9
IRQ10 26 DeepSleep GPIO Interrupt - Port 10
IRQ11 27 DeepSleep GPIO Interrupt - Port 11
IRQ12 28 DeepSleep GPIO Interrupt - Port 12
IRQ13 29 DeepSleep GPIO Interrupt - Port 13
IRQ14 30 DeepSleep GPIO Interrupt - Port 14
IRQ15 31 DeepSleep GPIO Interrupt - All Ports
IRQ16 32 DeepSleep GPIO Supply Detect Interrupt
IRQ17 33 DeepSleep Low Power Comparator Interrupt
IRQ18 34 DeepSleep Serial Communication Block #8 (DeepSleep capable)
IRQ19 35 DeepSleep Multi Counter Watchdog Timer interrupt
IRQ20 36 DeepSleep Multi Counter Watchdog Timer interrupt
IRQ21 37 DeepSleep Backup domain interrupt
IRQ22 38 DeepSleep Other combined Interrupts for SRSS (LVD, WDT, CLKCAL)
IRQ23 39 DeepSleep CPUSS Inter Process Communication Interrupt #0
IRQ24 40 DeepSleep CPUSS Inter Process Communication Interrupt #1
IRQ25 41 DeepSleep CPUSS Inter Process Communication Interrupt #2
IRQ26 42 DeepSleep CPUSS Inter Process Communication Interrupt #3
IRQ27 43 DeepSleep CPUSS Inter Process Communication Interrupt #4
IRQ28 44 DeepSleep CPUSS Inter Process Communication Interrupt #5
IRQ29 45 DeepSleep CPUSS Inter Process Communication Interrupt #6

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 Interrupts

Table 8-3. List of PSoC 6 Interrupts

Cortex M4 Exception
System Interrupt Power Mode Interrupt Source
Number
IRQ30 46 DeepSleep CPUSS Inter Process Communication Interrupt #7
IRQ31 47 DeepSleep CPUSS Inter Process Communication Interrupt #8
IRQ32 48 DeepSleep CPUSS Inter Process Communication Interrupt #9
IRQ33 49 DeepSleep CPUSS Inter Process Communication Interrupt #10
IRQ34 50 DeepSleep CPUSS Inter Process Communication Interrupt #11
IRQ35 51 DeepSleep CPUSS Inter Process Communication Interrupt #12
IRQ36 52 DeepSleep CPUSS Inter Process Communication Interrupt #13
IRQ37 53 DeepSleep CPUSS Inter Process Communication Interrupt #14
IRQ38 54 DeepSleep CPUSS Inter Process Communication Interrupt #15
IRQ39 55 Active Serial Communication Block #0
IRQ40 56 Active Serial Communication Block #1
IRQ41 57 Active Serial Communication Block #2
IRQ42 58 Active Serial Communication Block #3
IRQ43 59 Active Serial Communication Block #4
IRQ44 60 Active Serial Communication Block #5
IRQ45 61 Active Serial Communication Block #6
IRQ46 62 Active Serial Communication Block #7
IRQ47 63 Active Serial Communication Block #9
IRQ48 64 Active Serial Communication Block #10
IRQ49 65 Active Serial Communication Block #11
IRQ50 66 Active Serial Communication Block #12
IRQ51 67 Active CSD (Capsense) interrupt
IRQ52 68 Active CPUSS DMAC, Channel #0
IRQ53 69 Active CPUSS DMAC, Channel #1
IRQ54 70 Active CPUSS DMAC, Channel #2
IRQ55 71 Active CPUSS DMAC, Channel #3
IRQ56 72 Active CPUSS DataWire #0, Channel #0
IRQ57 73 Active CPUSS DataWire #0, Channel #1
IRQ58 74 Active CPUSS DataWire #0, Channel #2
IRQ59 75 Active CPUSS DataWire #0, Channel #3
IRQ60 76 Active CPUSS DataWire #0, Channel #4
IRQ61 77 Active CPUSS DataWire #0, Channel #5
IRQ62 78 Active CPUSS DataWire #0, Channel #6
IRQ63 79 Active CPUSS DataWire #0, Channel #7
IRQ64 80 Active CPUSS DataWire #0, Channel #8
IRQ65 81 Active CPUSS DataWire #0, Channel #9
IRQ66 82 Active CPUSS DataWire #0, Channel #10
IRQ67 83 Active CPUSS DataWire #0, Channel #11
IRQ68 84 Active CPUSS DataWire #0, Channel #12
IRQ69 85 Active CPUSS DataWire #0, Channel #13
IRQ70 86 Active CPUSS DataWire #0, Channel #14
IRQ71 87 Active CPUSS DataWire #0, Channel #15
IRQ72 88 Active CPUSS DataWire #0, Channel #16

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 Interrupts

Table 8-3. List of PSoC 6 Interrupts

Cortex M4 Exception
System Interrupt Power Mode Interrupt Source
Number
IRQ73 89 Active CPUSS DataWire #0, Channel #17
IRQ74 90 Active CPUSS DataWire #0, Channel #18
IRQ75 91 Active CPUSS DataWire #0, Channel #19
IRQ76 92 Active CPUSS DataWire #0, Channel #20
IRQ77 93 Active CPUSS DataWire #0, Channel #21
IRQ78 94 Active CPUSS DataWire #0, Channel #22
IRQ79 95 Active CPUSS DataWire #0, Channel #23
IRQ80 96 Active CPUSS DataWire #0, Channel #24
IRQ81 97 Active CPUSS DataWire #0, Channel #25
IRQ82 98 Active CPUSS DataWire #0, Channel #26
IRQ83 99 Active CPUSS DataWire #0, Channel #27
IRQ84 100 Active CPUSS DataWire #0, Channel #28
IRQ85 101 Active CPUSS DataWire #1, Channel #0
IRQ86 102 Active CPUSS DataWire #1, Channel #1
IRQ87 103 Active CPUSS DataWire #1, Channel #2
IRQ88 104 Active CPUSS DataWire #1, Channel #3
IRQ89 105 Active CPUSS DataWire #1, Channel #4
IRQ90 106 Active CPUSS DataWire #1, Channel #5
IRQ91 107 Active CPUSS DataWire #1, Channel #6
IRQ92 108 Active CPUSS DataWire #1, Channel #7
IRQ93 109 Active CPUSS DataWire #1, Channel #8
IRQ94 110 Active CPUSS DataWire #1, Channel #9
IRQ95 111 Active CPUSS DataWire #1, Channel #10
IRQ96 112 Active CPUSS DataWire #1, Channel #11
IRQ97 113 Active CPUSS DataWire #1, Channel #12
IRQ98 114 Active CPUSS DataWire #1, Channel #13
IRQ99 115 Active CPUSS DataWire #1, Channel #14
IRQ100 116 Active CPUSS DataWire #1, Channel #15
IRQ101 117 Active CPUSS DataWire #1, Channel #16
IRQ102 118 Active CPUSS DataWire #1, Channel #17
IRQ103 119 Active CPUSS DataWire #1, Channel #18
IRQ104 120 Active CPUSS DataWire #1, Channel #19
IRQ105 121 Active CPUSS DataWire #1, Channel #20
IRQ106 122 Active CPUSS DataWire #1, Channel #21
IRQ107 123 Active CPUSS DataWire #1, Channel #22
IRQ108 124 Active CPUSS DataWire #1, Channel #23
IRQ109 125 Active CPUSS DataWire #1, Channel #24
IRQ110 126 Active CPUSS DataWire #1, Channel #25
IRQ111 127 Active CPUSS DataWire #1, Channel #26
IRQ112 128 Active CPUSS DataWire #1, Channel #27
IRQ113 129 Active CPUSS DataWire #1, Channel #28
IRQ114 130 Active CPUSS Fault Structure Interrupt #0
IRQ115 131 Active CPUSS Fault Structure Interrupt #1

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 Interrupts

Table 8-3. List of PSoC 6 Interrupts

Cortex M4 Exception
System Interrupt Power Mode Interrupt Source
Number
IRQ116 132 Active CRYPTO Accelerator Interrupt
IRQ117 133 Active FLASH Macro Interrupt
IRQ118 134 Active Floating Point operation fault
IRQ119 135 Active CM0+ CTI #0
IRQ120 136 Active CM0+ CTI #1
IRQ121 137 Active CM4 CTI #0
IRQ122 138 Active CM4 CTI #1
IRQ123 139 Active TCPWM #0, Counter #0
IRQ124 140 Active TCPWM #0, Counter #1
IRQ125 141 Active TCPWM #0, Counter #2
IRQ126 142 Active TCPWM #0, Counter #3
IRQ127 143 Active TCPWM #0, Counter #4
IRQ128 144 Active TCPWM #0, Counter #5
IRQ129 145 Active TCPWM #0, Counter #6
IRQ130 146 Active TCPWM #0, Counter #7
IRQ131 147 Active TCPWM #1, Counter #0
IRQ132 148 Active TCPWM #1, Counter #1
IRQ133 149 Active TCPWM #1, Counter #2
IRQ134 150 Active TCPWM #1, Counter #3
IRQ135 151 Active TCPWM #1, Counter #4
IRQ136 152 Active TCPWM #1, Counter #5
IRQ137 153 Active TCPWM #1, Counter #6
IRQ138 154 Active TCPWM #1, Counter #7
IRQ139 155 Active TCPWM #1, Counter #8
IRQ140 156 Active TCPWM #1, Counter #9
IRQ141 157 Active TCPWM #1, Counter #10
IRQ142 158 Active TCPWM #1, Counter #11
IRQ143 159 Active TCPWM #1, Counter #12
IRQ144 160 Active TCPWM #1, Counter #13
IRQ145 161 Active TCPWM #1, Counter #14
IRQ146 162 Active TCPWM #1, Counter #15
IRQ147 163 Active TCPWM #1, Counter #16
IRQ148 164 Active TCPWM #1, Counter #17
IRQ149 165 Active TCPWM #1, Counter #18
IRQ150 166 Active TCPWM #1, Counter #19
IRQ151 167 Active TCPWM #1, Counter #20
IRQ152 168 Active TCPWM #1, Counter #21
IRQ153 169 Active TCPWM #1, Counter #22
IRQ154 170 Active TCPWM #1, Counter #23
IRQ155 171 Active SAR ADC interrupt
IRQ156 172 Active I2S0 Audio interrupt
IRQ157 173 Active PDM0/PCM0 Audio interrupt
IRQ158 174 Active I2S1 Audio interrupt

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 Interrupts

Table 8-3. List of PSoC 6 Interrupts

Cortex M4 Exception
System Interrupt Power Mode Interrupt Source
Number
IRQ159 175 Active Profiler interrupt
IRQ160 176 Active Serial Memory Interface interrupt
IRQ161 177 Active USB Interrupt
IRQ162 178 Active USB Interrupt
IRQ163 179 Active USB Interrupt
IRQ164 180 Active SDIO wakeup interrupt for mxsdhc
IRQ165 181 Active Consolidated interrupt for mxsdhc for everything else
IRQ166 182 Active EEMC wakeup interrupt for mxsdhc, not used
IRQ167 183 Active Consolidated interrupt for mxsdhc for everything else

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 Interrupts

8.6 Interrupt/Exception Priority 8.7 Enabling and Disabling

Exception priority is useful for exception arbitration when
Interrupts
there are multiple exceptions that need to be serviced by the The NVICs of both CM0+ andCM4 core provide registers to
CPU. Both M4 and M0+ cores in PSoC 6 MCUs provide individually enable and disable the interrupts in software. If
flexibility in choosing priority values for different exceptions. an interrupt is not enabled, the NVIC will not process the
All exceptions other than Reset, NMI, and HardFault can be interrupt requests on that interrupt line. The Interrupt Set-
assigned a configurable priority level. The Reset, NMI, and Enable Register (CM0P_SCS_ISER and CM4_SCS_ISER)
HardFault exceptions have a fixed priority of –3, –2, and –1, and the Interrupt Clear-Enable Register (CM0P_SCS_ICER
respectively. In PSoC 6 MCUs, lower priority numbers and CM4_SCS_ICER) are used to enable and disable the
represent higher priorities. This means that the Reset, NMI, interrupts respectively. These registers are 32-bit wide and
and HardFault exceptions have the highest priorities. The each bit corresponds to the same numbered interrupt in
other exceptions can be assigned a configurable priority CM0+. For CM4 core, there are eight ISER/ICER registers.
level between 0 and 3 for Cortex-M0+ and 0 to 7 for Cortex- These registers can also be read in software to get the
M4. enable status of the interrupts. Table 8-6 shows the register
Both M0+ and M4 support nested exceptions in which a access properties for these two registers. Note that writing
higher priority exception can obstruct (interrupt) the zero to these registers has no effect.
currently active exception handler. This pre-emption does For CM0+, the first 16 bits of the ISER and ICER registers
not happen if the incoming exception priority is the same as are valid. Refer to Interrupt Sources on page 62 for details
or lower than the active exception. The CPU resumes on how to map a CPU interrupt to a system interrupt in
execution of the lower priority exception handler after CM0+.
servicing the higher priority exception. The CM0+ core in the
Table 8-6. Interrupt Enable/Disable Registers
PSoC 6 MCU allows nesting of up to four exceptions; the
CM4 core allows up to eight exceptions. When the CPU Register Operation Bit Value Comment
receives two or more exceptions requests of the same 1 To enable the interrupt
Write
priority, the lowest exception number is serviced first. Interrupt Set 0 No effect
Enable Register 1 Interrupt is enabled
The registers to configure the priority of exception numbers Read
1 to 15 are explained in Exception Sources on page 60. 0 Interrupt is disabled
1 To disable the interrupt
The priority of the 32 CM0+ and 168 CM4 interrupts can be Write
Interrupt Clear 0 No effect
configured by writing to the respective Interrupt Priority Enable Register 1 Interrupt is enabled
registers (CM0P_SCS_IPR and CM4_SCS_IPR). This is a Read
0 Interrupt is disabled
group of eight (CM0+) and 60 (CM4) 32-bit registers with
each register storing the priority values of four interrupts, as
given in Table 8-4 and Table 8-5. For CM0+, the first 16 bits The ISER and ICER registers are applicable only for the
of the ISER and ICER registers are valid. Refer to Interrupt interrupts. These registers cannot be used to enable or
Sources on page 62 for details on how to map a CPU disable the exception numbers 1 to 15. The 15 exceptions
interrupt to a system interrupt in CM0+. have their own support for enabling and disabling, as
explained in Exception Sources on page 60.
The PRIMASK register in the CPUs (both CM0+ and CM4)
Table 8-4. Interrupt Priority Register Bit Definitions for can be used as a global exception enable register to mask
Cortex-M0+ (CM0P_SCS_IPR) all the configurable priority exceptions irrespective of
Bits Name Description whether they are enabled. Configurable priority exceptions
7:6 PRI_N0 Priority of interrupt number N. include all the exceptions except Reset, NMI, and HardFault
15:14 PRI_N1 Priority of interrupt number N+1. listed in Table 8-1. When the PM bit (bit 0) in the PRIMASK
23:22 PRI_N2 Priority of interrupt number N+2. register is set, none of the configurable priority exceptions
31:30 PRI_N3 Priority of interrupt number N+3.
can be serviced by the CPU, though they can be in the
pending state waiting to be serviced by the CPU after the
Table 8-5. Interrupt Priority Register Bit definitions for PM bit is cleared.
Cortex-M4 (CM4_SCS_IPR)
Bits Name Description
7:5 PRI_N0 Priority of interrupt number N
15:13 PRI_N1 Priority of interrupt number N+1
23:21 PRI_N2 Priority of interrupt number N+2
31:29 PRI_N3 Priority of interrupt number N+3

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 Interrupts

8.8 Interrupt/Exception States

Each exception can be in one of the following states.

Table 8-7. Exception States

Exception State Meaning
The exception is not active and not pending. Either the exception is disabled or the enabled exception has not been
Inactive
triggered.
Pending The exception request has been received by the CPU/NVIC and the exception is waiting to be serviced by the CPU.
An exception that is being serviced by the CPU but whose exception handler execution is not yet complete. A high-
Active priority exception can interrupt the execution of lower priority exception. In this case, both the exceptions are in the
active state.
The exception is being serviced by the processor and there is a pending request from the same source during its
Active and Pending
exception handler execution.

The Interrupt Control State Register (CM0P_SCS_ICSR and CM4_SCS_ICSR) contains status bits describing the various
exceptions states.
■ The VECTACTIVE bits ([8:0]) in the ICSR store the exception number for the current executing exception. This value is
zero if the CPU does not execute any exception handler (CPU is in thread mode). Note that the value in VECTACTIVE
bitfields is the same as the value in bits [8:0] of the Interrupt Program Status Register (IPSR), which is also used to store
the active exception number.
■ The VECTPENDING bits ([20:12]) in the ICSR store the exception number of the highest priority pending exception. This
value is zero if there are no pending exceptions.
■ The ISRPENDING bit (bit 22) in the ICSR indicates if a NVIC generated interrupt is in a pending state.

8.8.1 Pending Interrupts/Exceptions

When a peripheral generates an interrupt request signal to the NVIC or an exception event occurs, the corresponding
exception enters the pending state. When the CPU starts executing the corresponding exception handler routine, the
exception is changed from the pending state to the active state. The NVIC allows software pending of the 32 (CM0+) or 168
(CM4) interrupt lines by providing separate register bits for setting and clearing the pending states of the interrupts. The
Interrupt Set-Pending register (CM0P_SCS_ISPR and CM4_SCS_ISPR) and the Interrupt Clear-Pending register
(CM0P_SCS_ICPR and CM4_SCS_ICPR) are used to set and clear the pending status of the interrupt lines. These registers
are 32 bits wide, and each bit corresponds to the same numbered interrupt. In the case of CM4, there are eight sets of such
registers to accommodate all 168 interrupts. Table 8-8 shows the register access properties for these two registers. Note that
writing zero to these registers has no effect.
Table 8-8. Interrupt Set Pending/Clear Pending Registers
Register Operation Bit Value Comment
1 To put an interrupt to pending state
Write
Interrupt Set-Pending Register 0 No effect
(ISPR) 1 Interrupt is pending
Read
0 Interrupt is not pending
1 To clear a pending interrupt
Write
Interrupt Clear-Pending Register 0 No effect
(ICPR) 1 Interrupt is pending
Read
0 Interrupt is not pending

Setting the pending bit when the same bit is already set Note that the ISPR and ICPR registers are used only for the
results in only one execution of the ISR. The pending bit can peripheral interrupts. These registers cannot be used for
be updated regardless of whether the corresponding pending the exception numbers 1 to 15. These 15
interrupt is enabled. If the interrupt is not enabled, the exceptions have their own support for pending, as explained
interrupt line will not move to the pending state until it is in Exception Sources on page 60.
enabled by writing to the ISER register.

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 Interrupts

8.9 Stack Usage for Interrupts/ Chip low-power modes have two categories of interrupt
sources:
Exceptions ■ Interrupt sources that are available in the Active, Sleep,
When the CPU executes the main code (in thread mode) and Deep Sleep modes (watchdog timer interrupt, RTC,
and an exception request occurs, the CPU stores the state GPIO interrupts, and Low-Power comparators)
of its general-purpose registers in the stack. It then starts ■ Interrupt sources that are available only in the Active and
executing the corresponding exception handler (in handler Sleep modes
mode). The CPU pushes the contents of the eight 32-bit
When using the WFE instruction in CM4, make sure to call
internal registers into the stack. These registers are the
the WFE instruction twice to properly enter and exit Sleep/
Program and Status Register (PSR), ReturnAddress, Link
Deep Sleep modes. This behavior comes from the event
Register (LR or R14), R12, R3, R2, R1, and R0. Both
register implementation in Arm v7 architecture used in
Cortex-M4 and Cortex-M0+ have two stack pointers - MSP
Cortex-M4. According to the ARM V7 architecture reference
and PSP. Only one of the stack pointers can be active at a
manual (Section B1.5.18 Wait For Event and Send Event):
time. When in thread mode, the Active Stack Pointer bit in
the Control register is used to define the current active stack ■ A reset clears the event register.
pointer. When in handler mode, the MSP is always used as ■ Any WFE wakeup event, or the execution of an
the stack pointer. The stack pointer always grows exception return instruction, sets the event register.
downwards and points to the address that has the last ■ A WFE instruction clears the event register.
pushed data.
■ Software cannot read or write the value of the event
When the CPU is in thread mode and an exception request register directly.
comes, the CPU uses the stack pointer defined in the
Therefore, the first WFE instruction puts CM4 to sleep and
control register to store the general-purpose register
second WFE clears the event register after a WFE wakeup,
contents. After the stack push operations, the CPU enters
which sets the event register. So the next WFE will put the
handler mode to execute the exception handler. When
core to sleep.
another higher priority exception occurs while executing the
current exception, the MSP is used for stack push/pop Note that this behavior is not present in Arm v6 architecture
operations, because the CPU is already in handler mode. used in Cortex-M0+. Therefore, in CM0+ only one WFE
See the CPU Subsystem (CPUSS) chapter on page 32 for instruction is sufficient to successfully enter or exit Sleep
details. and Deep Sleep modes.

8.10 Interrupts and Low-Power 8.11 Interrupt/Exception –

Modes Initialization/ Configuration
This section covers the different steps involved in initializing
The PSoC 6 MCU family allows device (CPU) wakeup from
and configuring exceptions in the PSoC 6 MCU.
low-power modes when certain peripheral interrupt requests
are generated. The Wakeup Interrupt Controller (WIC) block 1. Configuring the Exception Vector Table Location: The
generates a wakeup signal that causes the CPU to enter first step in using exceptions is to configure the vector
Active mode when one or more wakeup sources generate table location as required - either in flash memory or
an interrupt signal. After entering Active mode, the ISR of SRAM. This configuration is done as described in
the peripheral interrupt is executed. Exception Vector Table on page 59.
The vector table should be available in SRAM if the
The Wait For Interrupt (WFI) or Wait For Event (WFE)
application must change the vector addresses
instruction, executed by the CPU, triggers the transition into
dynamically. If the table is located in flash, then a flash
Sleep, and Deep Sleep modes. Both the WFI and WFE
write operation is required to modify the vector table
instructions are capable of waking up on interrupts.
contents. The ModusToolbox IDE uses the vector table
However, the WFE requires the interrupts to be unmasked in
in SRAM by default.
the CPU’s Priority Mask register. Refer to the PRIMASK
register definition on the Arm website. In addition, the WFE 2. Configuring Individual Exceptions: The next step is to
instruction puts the CPU to sleep based on the status of an configure individual exceptions required in an
event bit and wakes up from an event signal, typically sent application, as explained in earlier sections.
by the other CPU. WFI does not require PRIMASK a. Configure the exception or interrupt source; this
unmasking and can wake up the CPU from any pending includes setting up the interrupt generation
interrupt masked to the NVIC or WIC. However, WFI cannot conditions. The register configuration depends on
wake up the CPU from event signals from other CPUs. The the specific exception required. Refer to the
sequence of entering the different low-power modes is respective peripheral chapter to know more about
detailed in the Device Power Modes chapter on page 225. the interrupt configuration supported by them.

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 Interrupts

b. Define the exception handler function and write the c. For Cortex-M0+, define and enable the additional
address of the function to the exception vector table. system interrupt handler table and functions as
Table 8-1 gives the exception vector table format; the explained in Interrupt Sources on page 62.
exception handler address should be written to the d. Set up the exception priority, as explained in
appropriate exception number entry in the table. Interrupt/Exception Priority on page 69.
e. Enable the exception, as explained in Enabling and
Disabling Interrupts on page 69.

8.12 Register List

Table 8-9. Register List
Register Name Description
CPUSS_CM0_NMI_CTLx Cortex-M0+ NMI control registers (4 registers)
CPUSS_CM0_SYSTEM_INT_CTLx Cortex-M0+ interrupt control registers for xth system interrupt (168 registers)
CPUSS_CM0_SYSTEM_INTx_STATUS Cortex-M0+ interrupt status registers for xth CPU interrupt (8 registers)
CPUSS_CM4_NMI_CTLx Cortex-M4 NMI control registers (4 registers)
SYSTEM_CM0P_SCS_ISER Cortex-M0+ interrupt set-enable register
SYSTEM_CM0P_SCS_ICER Cortex-M0+ interrupt clear enable register
SYSTEM_CM0P_SCS_ISPR Cortex-M0+ interrupt set-pending register
SYSTEM_CM0P_SCS_ICPR Cortex-M0+ interrupt clear-pending register
SYSTEM_CM0P_SCS_IPR Cortex-M0+ interrupt priority register
SYSTEM_CM0P_SCS_ICSR Cortex-M0+ interrupt control state register
SYSTEM_CM0P_SCS_VTOR Cortex-M0+ vector table offset register
SYSTEM_CM0P_SCS_AIRCR Cortex-M0+ application interrupt and reset control register
SYSTEM_CM0P_SCS_SHPR2 Cortex-M0+ system handler priority register 2
SYSTEM_CM0P_SCS_SHPR3 Cortex-M0+ system handler priority register 3
SYSTEM_CM0P_SCS_SHCSR Cortex-M0+ system handler control and state register
SYSTEM_CM4_SCS_ISER Cortex-M4 interrupt set-enable register
SYSTEM_CM4_SCS_ICER Cortex-M4 interrupt clear enable register
SYSTEM_CM4_SCS_ISPR Cortex-M4 interrupt set-pending register
SYSTEM_CM4_SCS_ICPR Cortex-M4 interrupt clear-pending register
SYSTEM_CM4_SCS_IPR Cortex-M4 interrupt priority registers
SYSTEM_CM4_SCS_ICSR Cortex-M4 interrupt control state register
SYSTEM_CM4_SCS_VTOR Cortex-M4 vector table offset register
SYSTEM_CM4_SCS_AIRCR Cortex-M4 application interrupt and reset control register
SYSTEM_CM4_SCS_SHPR2 Cortex-M4 system handler priority register 2
SYSTEM_CM4_SCS_SHPR3 Cortex-M4 system handler priority register 3
SYSTEM_CM4_SCS_SHCSR Cortex-M4 system handler control and state register

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 9. Protection Units

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

Protection units are implemented in the PSoC 6 MCU to enforce security based on different operations. A protection unit
allows or restricts bus transfers. The rules are enforced based on specific properties of a transfer. The rules that determine
protection are implemented in protection structures (a register structure). A protection structure defines the protected address
space and the protection attributes. The hardware that evaluates these protection structures, to restrict or permit access, is
the protection unit. The PSoC device has different types of protection units such as MPU, SMPU, and PPU. Each have a
distinct set of protection structures, which helps define different protection regions and their attributes.

9.1 Architecture
Figure 9-1 shows a conceptual view of implementation of the PSoC protection system.
Figure 9-1. Conceptual View of PSoC Protection System
Bus Masters

Test
CPU1 CPU2 DMA
Controller
Bus Master’s Bus Master’s Bus Master’s Bus Master’s
Protection Protection Protection Protection
Attribute Attribute Attribute Attribute

Sets rules to
Protection check against
Unit

Flash External Peripheral Protection

SRAM
Memory Memory Memory Structures
Memory
Region

Protection
Attribute
PSoC 6 Memory Map

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 Protection Units

The functioning of a secure system is based on the Each bus master is qualified by its own protection attribute.
following: For every bus transfer, the protection unit compares the bus
■ Bus masters: This term refers to the bus masters in the master's protection attribute and accessed address against
architecture. In a PSoC 6 device, an example of a bus the rules set in the protection structures and decides on
master is a Cortex-M core, DMA, or a test controller. providing or denying access.
■ Protection units: Protection units are the hardware
engines that enforce the protection defined by protection 9.2 PSoC 6 Protection
structures. There are three types of protection units,
acting at different levels of memory access with different Architecture
precedence and priority of protection – MPU, SMPU,
When there is a memory (SRAM/flash/peripheral) access by
and PPU.
a bus master, the access is evaluated by a protection unit
■ Protection structure: A protection structure is a register against the protection attributes set in protection structures
structure in memory that sets up the rules based on for the memory location being accessed. If the bus master’s
which each protection unit will evaluate a transfer. Each protection attributes satisfy the protection attributes set in
protection unit associates itself to multiple protection the protection structures, then access is allowed by the
structures. The protection structure associated with a protection unit. If there is an access restriction, a fault
protection unit are evaluated in the order starting with condition is triggered and a bus error occurs. Thus
the protection structure with the largest index. For protection units secure bus transfer address range either in
example, if there are 16 protection structures associated memory locations (SRAM/flash) or peripheral registers.
with a protection unit, then the evaluation of a transfer From an architectural perspective, there is no difference
starts from protection structure 15 and counts down. between memory protection and peripheral protection.
Physically a protection structure is a register structure in However, from an implementation perspective, separate
the memory map that defines a protection rule. Each memory and peripheral protection is provided.
protection structure constitutes the following:
Two types of protection units, memory protection units
❐ Defines a memory region on which the rule is
(MPU) and shared memory protection units (SMPU), are
applied. It designates what the bus transfer needs to
provided in the CPU subsystem (CPUSS) to protect memory
be evaluated against this protection structure.
locations. A separate protection unit type is provided for
- Base address peripheral protection (PPU) in the PERI:
- Size of memory block ■ A bus master may have a dedicated MPU. In a CPU bus
❐ A set of protection attributes master, the MPU is typically implemented as part of the
- R/W/X CPU and is under control of the OS/kernel. In a non-
CPU bus master, the MPU is typically implemented as
- User/privilege
part of the bus infrastructure and under control of the
- Secure/non Secure OS/kernel of the CPU that “owns or uses” the bus
- Protection context master. If a CPU switches tasks or if a non-CPU
■ Protection attributes: These are properties based on switches ownership, the MPU settings are typically
which a transfer is evaluated. There are multiple updated by OS/kernel software. The different MPU types
protection attributes. The set of protection attributes are:
available for a protection structure depends on the ❐ An MPU that is implemented as part of the CPU. This
protection unit it is associated with. Protection attributes type is found in the Arm CM0+ and CM4 CPUs.
appear in two places: ❐ An MPU that is implemented as part of the bus infra-
❐ Protection structures: Protection attributes associ- structure. This type is found in bus masters such as
ated with a protection structure set the rules for crypto and test controller. The definition of this MPU
access based on these attributes. type follows the Arm MPU definition (in terms of
❐ Bus master's protection attribute: Each bus master memory region and access attribute definition) to
has its own access attributes, which define the bus ensure a consistent software interface.
master's access privileges. Some of these attributes, ■ SMPUs are intended for implementing protection in a
such as secure/non-secure, are set for a master. situation with multiple bus masters. These protection
Other attributes such as protection context and user/ units implement a concept called Protection Context. A
privilege attribute are dynamic attributes, which protection context is a pseudo state of a bus master,
change based on bus master's context and state. which can be used to determine access attributes across
multiple masters. The protection context is a protection
In summary, a PSoC 6 device has protection units that act attribute not specific to a bus master. The SMPUs can
as a gate for any access to the PSoC memory map. The distinguish between different protection contexts; they
rules for protection are set by the protection structures. can also distinguish secure from non-secure accesses.

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 Protection Units

This allows for an effective protection in a multi-core occurrence of a fault. This is useful if the violating bus
scenario. master cannot resolve the bus error by itself, but requires
■ PPUs are protection units provided in the PERI register another CPU bus master to resolve the bus error on its
space for peripheral protection. The PPU attributes are behalf.
similar to the SMPU, except that they are intended for For a buffered mode of transfer
protecting the peripheral space. Refer to the registers (CPUSS_BUFF_CTL[WRITE_BUFF]), the behavior during
TRM for details. The PPUs are intended to distinguish protection violation is different. When
between different protection contexts and to distinguish CPUSS_BUFF_CTL[WRITE_BUFF] is set to ‘1’, the write
secure from non-secure accesses and user mode transfers on the bus are buffered. So the transfer is first
accesses from privileged mode accesses. There are two acknowledged when the buffer receives the transfer. A
types of PPU structures. protection violation will be only evaluated when the actual
❐ Fixed PPUs implement protection for fixed address write happens at the destination register. This leads to the
regions that typically correspond to a specific periph- write transfer not generating a bus error for buffered mode.
eral However, a fault will be registered as soon as the transfer
❐ Programmable PPUs allows the user to program the tries to write the destination location. Therefore, for buffered
address region to be protected writes, the user must verify the fault structure to make sure
no violations have occurred.
The platform’s DMA controller does not have an MPU.
Instead, a DMA controller channel inherits the access A protection violation results in a bus error and the bus
control attributes of the bus transfer that programmed the transfer will not reach its target. An MPU or SMPU violation
channel. that targets a peripheral will not reach the associated
protection evaluation (PPU). In other words, MPU and
The definition of SMPU and PPU follows the MPU definition SMPU have a higher priority over PPU.
and adds the capability to distinguish accesses from
different protection contexts (the MPU does not include Protection unit addresses the following:
support for a protection context). If security is required, the ■ Security requirements. This includes prevention of
SMPU and possibly PPUs MMIO registers must be malicious attacks to access secure memory or
controlled by a secure CPU that enforces system-wide peripherals. For example, a non-secure master should
protection. not be able to access key information in a secure
memory region.
Figure 9-2 gives an overview of the location of MPUs,
SMPUs, and PPUs in the system. Note that a peripheral ■ Safety requirements. This includes detection of
group PPU needs to provide access control only to the accidental (non-malicious) software errors and random
peripherals within a peripheral group (group of peripherals hardware errors. Enabling failure analysis is important
with a shared bus infrastructure). so the root cause of a safety violation can be
investigated. For example, analyzing a flash memory
As mentioned, the MPU, SMPU, and PPU protection failure on a device that is returned from the field should
functionality follows the Arm MPU definition: be possible.
■ Multiple protection structures are supported.
To address security requirements, the Cortex M0+ is used
■ Each structure specifies an address range in the unified as a ‘secure CPU’. This CPU is considered a trusted entity.
memory architecture and access attributes. An address Any access by the CPU tagged as “secure” will be called
range can be as small as 32 bytes. “secure access”.
A protection violation is caused by a mismatch between a
bus master’s access attributes and the protection structure
and access attributes for the memory region configured in
the protection structure.
A bus transfer that violates a protection structure results in a
bus error.
For AXI transfers, the complete address range is matched. If
a transfer references multiple 32-byte regions (the smallest
protection structure address range is 32 bytes), multiple
cycles are required for matching – one cycle per 32-byte
region.
Protection violations are captured in the fault report
structure to allow for failure analysis. The fault report
structures can generate an interrupt to indicate the

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 Protection Units

Figure 9-2. PSoC 6 Protection Architecture

Bus Masters

DMA Test
CM0+ CM4 Crypto
(DataWire) Controller
Arm MPU Arm MPU

MPU MPU

Flash SRAM SMPU MPU: Memory Protection Unit

SMPU: Shared Memory Protection Unit
PPU: Peripheral Protection Unit

AHB

PPU PPU PPU

GPIO
Fixed Programmable
Function Analog and Digital
Blocks Blocks

The different types of protection units cater to different use cases for protection.

Table 9-1. Protection Use Cases

Protection Unit Type Use
Used to protect memory between tasks within in a single Arm core. A task in one of the Arm cores can
Arm MPU
protect its memory from access by another task in the same core.
Same as the Arm MPU, but for other bus masters such as the test controller or crypto, which do not have a
MPU
built-in MPU in their block IP.
SMPU Used to protect memory addresses that are shared between multiple bus masters.
Fixed PPU protection These protect specific peripheral memory space. The protection structures have a preprogrammed memory
structures region and can be used only to protect the peripheral it was intended for.
Programmable PPU These protect the peripheral space but the memory region is not fixed. So users can easily program it to
protection structures protect any space in the peripheral memory region.

9.3 Register Architecture

The protection architecture has different conceptual pieces and different sets of registers correspond to each of these
concepts.

9.3.1 Protection Structure and Attributes

The MPU, SMPU, and PPU protection structure definition follows the Arm definition. Each protection structure is defined by:
■ An address region
■ Access control attributes
A protection structure is always aligned on a 32-byte boundary in the memory space. Two registers define a protection
structure: ADDR (address register) and ATT (attribute register). This structure alignment and organization allow
straightforward protection of the protection structures by the protection scheme. This is discussed later in this chapter.
Address region: The address region is defined by:
■ The base address of a region as specified by ADDR.ADDR.
■ The size of a region as specified by ATT.REGION_SIZE.
■ Individual disables for eight subregions within the region, as specified by ADDR.SUBREGION_DISABLE.

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 Protection Units

The REGION_SIZE field specifies the size of a region. The region size is a power of 2 in the range of [256 B, 4 GB]. The base
address ADDR specifies the start of the region, which must be aligned to the region size. A region is partitioned into eight
equally sized sub-regions. The SUBREGION_DISABLE field specifies individual enables for the sub-regions within a region.
For example, a REGION_SIZE of “0x08” specifies a region size of 512 bytes. If the start address is 0x1000:5400 (512-byte
aligned), the region ranges from 0x1000:5400 to 0x1000:55ff. This region is partitioned into the following eight 64-byte
subregions:
subregion 0 from 0x1000:5400 to 0x1000:543f
subregion 1 from 0x1000:5440 to 0x1000:547f
…
subregion 7 from 0x1000:55c0 to 0x1000:55ff.
If the SUBREGION_DISABLE is 0x82 (bitfields 1 and 7 are ‘1’), subregions 1 and 7 are disabled; subregions 0, 2, 3, 4, 5, and
6 are enabled.
In addition, an ATT.ENABLED field specifies whether the region is enabled. Only enabled regions participate in the protection
“matching” process. Matching identifies if a bus transfer address is contained within an enabled subregion
(SUBREGION_DISABLE) of an enabled region (ENABLED).
Protection attributes: The protection attributes specify access control to the region (shared by all subregions within the
region). Access control is performed by comparing against a bus master's protection attributes of the bus master performing
the transfer. The following access control fields are supported:
■ Control for read accesses in user mode (ATT.UR field).
■ Control for write accesses in user mode (ATT.UW field).
■ Control for execute accesses in user mode (ATT.UX field).
■ Control for read accesses in privileged mode (ATT.PR field).
■ Control for write accesses in privileged mode (ATT.PW field).
■ Control for execute accesses in privileged mode (ATT.PX field).
■ Control for secure access (ATT.NS field).
■ Control for individual protection contexts (ATT.PC_MASK[15:0], with MASK[0] always constant at 1). This protection
context control field is present only for the SMPU and PPU.
The execute and read access control attributes are orthogonal. Execute transfers are typically read transfers. To allow
execute and read transfers in user mode, both ATT.UR and ATT.UX must be set to ‘1’. To allow data and read transfers in user
mode, only ATT.UR must be set to ‘1’. In addition, the ATT.PC_MATCH control field is supported, which controls “matching”
and “access evaluation” processes. This control field is present only for the SMPU and PPU protection structures.
For example, only protection context 2 can access a specific address range. These accesses are restricted to read and write
secure accesses in privileged mode. The access control fields are programmed as follows:
■ ATT.UR is 0: read accesses in user mode not allowed.
■ ATT.UW is 0: write accesses in user mode not allowed.
■ ATT.UX is 0: execute accesses in user mode not allowed.
■ ATT.PR is 1: read accesses in privileged mode allowed.
■ ATT.PW is 1: write accesses in privileged mode allowed.
■ ATT.PX is 0: execute accesses in privileged mode not allowed.
■ ATT.NS is 0: secure access required.
■ ATT.PC_MASK is 0x0005: protection context 1 and 3 accesses enabled (all other protection contexts are disabled).
■ ATT.PC_MATCH is 0: the PC_MASK field is used for access evaluation. Three separate access evaluation subprocesses
are distinguished:
❐ A subprocess that evaluates the access based on read/write, execute, and user/privileged access attributes.
❐ A subprocess that evaluates the access based on the secure/non-secure attribute.
❐ A subprocess that evaluates the access based on the protection context index (used only by the SMPU and PPU
when ATT.PC_MATCH is 0).

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 Protection Units

If all access evaluations are successful, access is allowed. If any process evaluation is unsuccessful, access is not allowed.
Matching the bus transfer address and access evaluation of the bus transfer (based on access attributes) are two
independent processes:
■ Matching process. For each protection structure, the process identifies whether a transfer address is contained within the
address range. This identifies the “matching” regions.
■ Access evaluation process. For each protection structure, the process evaluates the bus transfer access attributes
against the access control attributes.
A protection unit typically has multiple protection structures and evaluates the protection structures in decreasing order. The
first matching structure provides the access control attributes for the evaluation of the transfer's access attributes. In other
words, higher-indexed structures take precedence over lower-indexed structures.
The following pseudo code illustrates the process.
match = 0;
for (i = n-1; i >= 0; i--)// n: number of protection regions
if (Match (“transfer address”, “protection context”
“MMIO registers ADDR and ATT of protection structure i”)) {
match = 1; break;
}
|

if (match)
AccessEvaluate (“transfer access attributes”, “protection context”
“MMIO register ATT of protection structure i”);
else
“access allowed”
Notes:
■ If no protection structure provides a match, the access is allowed.
■ If multiple protection structures provide a match, the access control attributes for the access evaluation are provided by
the protection structure with the highest index.
An example of using the PC_MATCH feature is as follows. Two SMPU structures are configured to protect the same address
range:
■ Case 1: SMPU#2: PC = 3, PC_MATCH = 0 SMPU#1: PC = 2, PC_MATCH = 0
To access the master of protection context 2, SMPU#2 has the highest index and address match, but attributes do not
match; therefore, access is restricted. The SMPU#1 is not evaluated because the PC_MATCH is 0.
■ Case 2: SMPU#2: PC = 3, PC_MATCH = 1 SMPU#1: PC = 2, PC_MATCH = 0
The SMPU#2 address matches but PC does not match and is skipped because PC_MATCH is 1. SMPU#1 is evaluated
and the address and attributes match; therefore, access is allowed.
As mentioned, the protection unit evaluates the protection structures in decreasing order. From a security requirements
perspective, this is of importance: a non-secure protection context must not be able to add protection structures that have a
higher index than the protection structures that provide secure access. The protection structure with a higher index can be
programmed to allow non-secure accesses. Therefore, in a secure system, the higher programmable protection structures
are protected to only allow restricted accesses

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 78
 Protection Units

9.4 Bus Master Protection Attributes

The protection structures set up the rules for different memory regions and their access attributes. The bus master’s own
protection attributes are used by the protection units to regulate access, based on rules set by the protection structures. Not
all bus masters provide all protection attributes that are associated with a bus transfer. Some examples are:
■ None of the bus masters has a native protection context attribute. This must be set dynamically based on the task being
executed by the bus master.
■ The Arm Cortex M4 and Arm Cortex M0+ CPUs provide a user/privilege attribute, but do not provide a secure/non-secure
attribute natively. This must be set at a system level.
To ensure system-wide restricted access, missing attributes are provided by register fields. These fields may be set during the
boot process or by the secure CPU.
■ The SMPU MS_CTL.PC_MASK[] and MPU MS_CTL.PC[] register fields provide protection context functionality.
■ The SMPU MS_CTL.P register field provides the user/privileged attribute for those masters that do not provide their own
attribute.
■ The SMPU MS_CTL.NS register provides the secure/non-secure attribute for those masters that do not provide their own
attribute.
■ Masters that do not provide an execute attribute have the execute attribute set to ‘0’.
The DMA controller channels inherit the access control attributes of the bus transfers that configured the DMA channel.
■ All the bus masters in the system have SMPU and MPU MS_CTL registers associated with them.
■ The MPU MS_CTL.PC_SAVED field (and associated protection context 0 functionality, which is discussed later in the
chapter) is only present for the CM0+ master.
■ The SMPU MS_CTL.P, MS_CTL.NS, and MS_CTL.PC_MASK fields are not present for the DMA. The bus transfer
attributes are provided through “inheritance”: the bus transfer attributes are from the master that owns the DMA channel
that initiated the bus transfer.
■ The MPU MS_CTL register is not present for the DMA masters. The protection context (PC) bus transfer attribute is
provided through inheritance.

9.5 Protection Context

Each bus master has a MPU MS_CTL.PC[3:0] protection context field. This protection context is used as the protection
context attribute for all bus transfers that are initiated by the master. The SMPUs and PPUs allow or restrict bus transfers
based on the protection context attribute.
Multiple masters can share a protection context. For example, a CPU and a crypto controlled by the CPU may share a
protection context (the CPU and crypto PC[] fields are the same). Therefore, the CPU and crypto share the SMPU and PPU
access restrictions.
A bus master protection context is changed by reprogramming the master’s PC[] field. Changing a protection context is
required for CPU bus masters that may transition between multiple tasks, each catering to different protection contexts. As
the protection context allows or restricts bus transfers, changes to the protection context should be controlled and should not
compromise security. Furthermore, changes to the protection context should incur limited CPU overhead to allow for frequent
protection context changes. Consider a case in which a CPU executes two software stacks with different protection contexts.
To this end, each bus master has an SMPU MS_CTL.PC_MASK[15:0] protection context mask field that identifies what
protection contexts can be programmed for the bus master:
■ The protection context field MS_CTL.PC[3:0]. This register is controlled by the associated bus master and has the same
access restrictions as the bus master’s MPU registers.
■ The protection context mask field MS_CTL.PC_MASK[15:0]. This register is controlled by the secure CPU and has the
same access restrictions as the SMPU registers.
The PC_MASK[] field is a “hot-one” field that specifies whether the PC[] field can be programmed with a specific protection
context. Consider an attempt to program PC[] to ‘3’:
■ If PC_MASK[3] is ‘1’, PC[] is set to “3”.
■ If PC_MASK[3] is ‘0’, PC[] is not changed.

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 Protection Units

9.6 Protection Contexts 0, 1, 2, 3

The PSoC 6 MCU supports protection contexts to isolate software execution for security and safety purposes. Protection
contexts are used to restrict access to memory and peripheral resources.
Out of a maximum of 16 protections contexts (PCs), four PCs are treated special: the entry to special PCs 0, 1, 2, and 3 is
hardware-controlled. For each PC i, a programmable exception handler address is provided (CM0_PCi_HANDLER.ADDR
[31:0]). A CPU exception handler fetch, which returns a handler address that matches the programmed
CM0_PCi_HANDLER.ADDR[31:0] address value, causes the CM0+ PC to be changed to PC i by hardware. However, if the
current PC is already 0, 1, 2, or 3, the current PC is not changed (an attempt to change the PC results in an AHB-Lite bus
error). This ensures that CPU execution in PC 0, 1, 2, or 3 cannot be interrupted/preempted by CPU execution in another PC
0, 1, 2, or 3. In other words, CPU execution in PC 0, 1, 2, or 3 requires cooperative multi-tasking between the different PCs.
This means that hand-overs between different PCs are software-scheduled/controlled. A security implementation requires PC
software to clean/zeroize information that it wants to keep confidential from other PC software.
The following pseudo code gives a description of the hardware control over the CM0+ current PC “pc”:
if (CM0_PC_CTL.VALID[0] & (addr == CM0_PC0_HANDLER. ADDR)) {match_new, pc_new} = {1, 0};
else if (CM0_PC_CTL.VALID[1] & (addr == CM0_PC1_HANDLER.ADDR)) {match_new, pc_new} = {1, 1};
else if (CM0_PC_CTL.VALID[2] & (addr == CM0_PC2_HANDLER.ADDR)) {match_new, pc_new} = {1, 2};
else if (CM0_PC_CTL.VALID[3] & (addr == CM0_PC3_HANDLER.ADDR)) {match_new, pc_new} = {1, 3};
else match_new = 0;

if ("exception handler fetch")

begin
if (match_new)
begin
if (pc == pc_new) ;
else if (CM0_PC_CTL.VALID[pc]) "AHB-Lite bus error";
else {pc, pc_saved} = {pc_new, pc}; // "push"
end
else
begin
{pc, pc_saved} = {pc_saved, pc_saved}; // "pop"
end
end
Note that each of the protection special PCs 0, 1, 2, and 3 have a dedicated CM0_PC_CTL.VALID[i] field to specify that the
PC's exception handler address is provided through CM0_PCi_HANDLER.ADDR[31:0]. If a PC's exception handler address
is not provided, the PC is treated as an ordinary PC (PCs 4, 5, ..., 15). Note that the current PC “pc” and a saved PC
“pc_saved” implement a two-entry stack. Hardware pushes the current PC to the stack upon entry of a special exception
handler. Hardware then pushes the saved PC from the stack upon entry of an ordinary exception handler. An attempt to enter
a special exception handler from a special exception handler with a different PC results in an AHB-Lite bus error (which
causes the CPU to enter the bus fault exception handler). This scenario should not occur in a carefully designed cooperative
multi-tasking software implementation.
Of the four special PCs, PC 0 is treated differently:
■ It is the default PC value after a Deep Sleep reset.
■ It has unrestricted access; that is, it is not affected by the CPUSS and PERI protection schemes. Therefore, the Cypress
boot code software always starts execution in PC 0. The boot code software initializes the protection structures and
initializes the CM0_PCi_HANDLER registers. The boot code is considered “trusted” software and its unrestricted access
in PC 0 is not considered a protection concern. After initialization of the protection information, the access to the
protection information itself is typically restricted for all other PCs (the boot code software deploys the restrictions) and the
protection information provides specific restricted access to the other special PCs and ordinary PCs (1, 2, ..., 15). As part
of the boot process configuration, the following things happen:
❐ The boot process sets MPUn.MS_CTL.PC_SAVED to a context that is not a special. context. This is required to pre-
vent accidental/malicious incorrect entry into a special context.
❐ If the system configuration does not use PC=0 after boot is complete, the boot process disables all future use of PC=0
by making ineffective CPUSS.CM0_PC0_HANDLER by clearing CPUSS.CM0_PC_CTL.VALID[0]. Furthermore, the

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 80
 Protection Units

protection region CPUSS.BOOT is assigned to be accessible from PC=0 only, which ensures these settings can no
longer be changed after boot.
❐ The boot process then changes the current PC by changing MPUn.MS_CTL.PC to a protection context that is not a
special context. This is done for all currently active masters (which typically is only the CM0+).
❐ When the above is complete, the system executes a regular (not special) context and can enter into special contexts
only through the use of interrupts using the special handler addresses.

9.7 Protection Structure

9.7.1 Protection Violation
If an MPU, SMPU, or PPU detects a not-allowed transfer, the bus transfer results in a bus error. The bus transfer does not
reach its target memory location or peripheral register. In addition, information on the violating bus transfer is communicated
to the fault report structure.

9.7.2 MPU
The MPUs are situated in the CPUSS and are associated to a single master. An MPU distinguishes user and privileged
accesses from a single bus master. However, the capability exists to perform access control on the secure/non-secure
attribute.
As an MPU is associated to a single master, the MPU protection structures do not provide protection context control
attributes.
Figure 9-3. MPU Functionality
Protection structures

transfer address
are 32 B aligned

transfer access
Two MMIO registers

attributes
per protection structure MPU protection
ADDR structures
31

0
SUBREGION_

MPU protection
ADDR[23:0]

DISABLE

structure 0

MPU protection fault_req

structure 1 fault_ack
ATT fault_data
31

Memory
0

protection
MPU protection
REGION_
ENABLED

No protection structure 2 unit (MPU)

SIZE

PW

UW
NS
PX

PR
UX

UR

Interface to fault
context attributes structures
...

9.7.3 SMPU
The SMPU is situated in the CPUSS and is shared by all bus masters. The SMPU distinguishes between different protection
contexts and distinguishes secure from non-secure accesses. However, the capability exists to perform access control on the
user/privileged mode attribute.

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 Protection Units

Figure 9-4. SMPU Functionality

Protection structures

transfer address
(pairs) are 64 B aligned

transfer access
Two MMIO registers

attributes
per protection structure
SMPU protection
ADDR structures
31

0
SUBREGION_
SMPU protection

ADDR[23:0]

DISABLE
structure pair 0

SMPU protection fault_req

structure pair 1 fault_ack
ATT Shared fault_data
31

0
Shared
memory
SMPU protection Shared
memory
protection
PC_MATCH

REGION_

PC_MASK
ENABLED

structure pair 2 memory

unitprotection
SIZE

(SMPU)
[15:1]

PW

UW
Interface to fault

PR

UR
NS
PX

UX
unitprotection
(SMPU) structures
... unit (SMPU)

Shared SMPU protection structures

for all SMPUs in the system

Note that a single set of SMPU region structures provides the same protection information to all SMPUs in the systems.

9.7.4 PPU
■ The PPUs are situated in the PERI block and are associated with a peripheral group (a group of peripherals with a shared
AHB-Lite bus infrastructure). A PPU is shared by all bus masters. The PPU distinguishes between different protection
contexts; it also distinguishes secure from non-secure accesses and user mode from privileged mode accesses.
Figure 9-5. PPU Functionality

transfer address

transfer access
Six MMIO registers per

attributes
protection structure
PPU protection
ADDR structures
31

ADDR[31:2]
PPU protection
Size structure pair 0
31

Size [28:24]
PPU protection fault_req
structure pair 1 fault_ack
ATT0 fault_data
31

Peripheral
0

protection
PPU protection
unit (PPU)
PC3_PW

PC2_PW

PC1_PW

PC0_PW
PC3_UW

PC2_UW

PC1_UW

PC0_UW
PC3_PR

PC2_PR

PC1_PR

PC0_PR
PC3_UR

PC2_UR

PC1_UR

PC0_UR
PC3_NS

PC2_NS

PC1_NS

PC0_NS

structure pair 2
Interface to fault
structures
...

ATT1
31

0
PC7_PW

PC6_PW

PC5_PW

PC4_PW
PC7_UW

PC6_UW

PC5_UW

PC4_UW
PC7_PR

PC6_PR

PC5_PR

PC4_PR
PC7_UR

PC6_UR

PC5_UR

PC4_UR
PC7_NS

PC6_NS

PC5_NS

PC4_NS

ATT2
31

0
PC11_UW

PC10_UW
PC11_PW

PC10_PW
PC11_UR

PC10_UR
PC11_NS

PC10_NS
PC11_PR

PC10_PR

PC9_PW

PC8_PW
PC9_UW

PC8_UW
PC9_PR

PC8_PR
PC9_UR

PC8_UR
PC9_NS

PC8_NS

ATT3
31

0
PC14_UW

PC14_UW

PC13_UW

PC12_UW
PC14_PW

PC14_PW

PC13_PW

PC12_PW
PC14_NS

PC14_NS

PC13_NS

PC12_NS
PC14_UR

PC14_UR

PC13_UR

PC12_UR
PC14_PR

PC14_PR

PC13_PR

PC12_PR

There are two types of PPU structures: fixed and programmable.

■ The fixed PPU structures protect fixed areas of memory and hence a specific predetermined peripheral region. In other
words, the ADDR, SUBREGION_DISABLE, and REGION_SIZE fields are fixed for a specific device. Refer to the
registers TRM for a definition of fixed PPUs and the address regions they protect. Their protection attributes can be

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 82
 Protection Units

configured for each protection context. The following table summarizes the different fixed PPU structures in CY8C62xx
devices and details the regions they protect.

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX0 0x40000000 8 KB PERI
PERI_MS_PPU_FX1 0x40004010 4B PERI_GR0
PERI_MS_PPU_FX2 0x40004030 4B PERI_GR1
PERI_MS_PPU_FX3 0x40004050 4B PERI_GR2
PERI_MS_PPU_FX4 0x40004060 32 B PERI_GR3
PERI_MS_PPU_FX5 0x40004080 32 B PERI_GR4
PERI_MS_PPU_FX6 0x400040C0 32 B PERI_GR6
PERI_MS_PPU_FX7 0x40004120 32 B PERI_GR9
PERI_MS_PPU_FX8 0x40004140 32 B PERI_GR10
PERI_MS_PPU_FX9 0x40008000 32 KB PERI_TR
PERI_MS_PPU_FX10 0x40100000 1 KB CRYPTO
PERI_MS_PPU_FX11 0x40101000 2 KB CRYPTO
PERI_MS_PPU_FX12 0x40102000 256 B CRYPTO
PERI_MS_PPU_FX13 0x40102100 4B CRYPTO
PERI_MS_PPU_FX14 0x40102120 4B CRYPTO
PERI_MS_PPU_FX15 0x40108000 4 KB CRYPTO
PERI_MS_PPU_FX16 0x40200000 1 KB CPUSS
PERI_MS_PPU_FX17 0x40201000 4 KB CPUSS
PERI_MS_PPU_FX18 0x40202000 512 B CPUSS
PERI_MS_PPU_FX19 0x40208000 1 KB CPUSS_CM0_SYSTEM_INT
PERI_MS_PPU_FX20 0x4020A000 1 KB CPUSS_CM4_SYSTEM_INT
PERI_MS_PPU_FX21 0x40210000 256 B FAULT_STRUCT0
PERI_MS_PPU_FX22 0x40210100 256 B FAULT_STRUCT1
PERI_MS_PPU_FX23 0x40220000 32 B IPC_STRUCT0
PERI_MS_PPU_FX24 0x40220020 32 B IPC_STRUCT1
PERI_MS_PPU_FX25 0x40220040 32 B IPC_STRUCT2
PERI_MS_PPU_FX26 0x40220060 32 B IPC_STRUCT3
PERI_MS_PPU_FX27 0x40220080 32 B IPC_STRUCT4
PERI_MS_PPU_FX28 0x402200A0 32 B IPC_STRUCT5
PERI_MS_PPU_FX29 0x402200C0 32 B IPC_STRUCT6
PERI_MS_PPU_FX30 0x402200E0 32 B IPC_STRUCT7
PERI_MS_PPU_FX31 0x40220100 32 B IPC_STRUCT8
PERI_MS_PPU_FX32 0x40220120 32 B IPC_STRUCT9
PERI_MS_PPU_FX33 0x40220140 32 B IPC_STRUCT10
PERI_MS_PPU_FX34 0x40220160 32 B IPC_STRUCT11
PERI_MS_PPU_FX35 0x40220180 32 B IPC_STRUCT12
PERI_MS_PPU_FX36 0x402201A0 32 B IPC_STRUCT13
PERI_MS_PPU_FX37 0x402201C0 32 B IPC_STRUCT14
PERI_MS_PPU_FX38 0x402201E0 32 B IPC_STRUCT15
PERI_MS_PPU_FX39 0x40221000 16 B IPC_INTR_STRUCT0
PERI_MS_PPU_FX40 0x40221020 16 B IPC_INTR_STRUCT1

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 Protection Units

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX41 0x40221040 16 B IPC_INTR_STRUCT2
PERI_MS_PPU_FX42 0x40221060 16 B IPC_INTR_STRUCT3
PERI_MS_PPU_FX43 0x40221080 16 B IPC_INTR_STRUCT4
PERI_MS_PPU_FX44 0x402210A0 16 B IPC_INTR_STRUCT5
PERI_MS_PPU_FX45 0x402210C0 16 B IPC_INTR_STRUCT6
PERI_MS_PPU_FX46 0x402210E0 16 B IPC_INTR_STRUCT7
PERI_MS_PPU_FX47 0x40221100 16 B IPC_INTR_STRUCT8
PERI_MS_PPU_FX48 0x40221120 16 B IPC_INTR_STRUCT9
PERI_MS_PPU_FX49 0x40221140 16 B IPC_INTR_STRUCT10
PERI_MS_PPU_FX50 0x40221160 16 B IPC_INTR_STRUCT11
PERI_MS_PPU_FX51 0x40221180 16 B IPC_INTR_STRUCT12
PERI_MS_PPU_FX52 0x402211A0 16 B IPC_INTR_STRUCT13
PERI_MS_PPU_FX53 0x402211C0 16 B IPC_INTR_STRUCT14
PERI_MS_PPU_FX54 0x402211E0 16 B IPC_INTR_STRUCT15
PERI_MS_PPU_FX55 0x40230000 64 B PROT_SMPU
PERI_MS_PPU_FX56 0x40234000 4B PROT_MPU0
PERI_MS_PPU_FX57 0x40235400 1 KB PROT_MPU5
PERI_MS_PPU_FX58 0x40235800 1 KB PROT_MPU6
PERI_MS_PPU_FX59 0x40237800 4B PROT_MPU14
PERI_MS_PPU_FX60 0x40237C00 1 KB PROT_MPU15
PERI_MS_PPU_FX61 0x40240000 8B FLASHC_FLASH
PERI_MS_PPU_FX62 0x40240008 4B FLASHC_FLASH
PERI_MS_PPU_FX63 0x40240200 256 B FLASHC
PERI_MS_PPU_FX64 0x40240400 128 B FLASHC_CM0
PERI_MS_PPU_FX65 0x40240480 128 B FLASHC_CM4
PERI_MS_PPU_FX66 0x40240500 4B FLASHC_CRYPTO
PERI_MS_PPU_FX67 0x40240580 4B FLASHC_DW0
PERI_MS_PPU_FX68 0x40240600 4B FLASHC_DW1
PERI_MS_PPU_FX69 0x40240680 4B FLASHC_DMAC
PERI_MS_PPU_FX70 0x40240700 4B FLASHC_EXT_MS0
PERI_MS_PPU_FX71 0x40240780 4B FLASHC_EXT_MS1
PERI_MS_PPU_FX72 0x4024F000 4 KB FLASHC_FM
PERI_MS_PPU_FX73 0x40260000 256 B PWR
PERI_MS_PPU_FX74 0x40260100 16 B
PERI_MS_PPU_FX75 0x40260180 16 B WDT
PERI_MS_PPU_FX76 0x40260200 128 B MCWDT
PERI_MS_PPU_FX77 0x40260300 256 B CLK
PERI_MS_PPU_FX78 0x40260400 1 KB CLK
PERI_MS_PPU_FX79 0x40260800 8B RES
PERI_MS_PPU_FX80 0x40267000 4 KB PWR_TRIM, CLK_TRIM
PERI_MS_PPU_FX81 0x4026FF00 128 B PWR_TRIM, CLK_TRIM
PERI_MS_PPU_FX82 0x40270000 64 KB BACKUP
PERI_MS_PPU_FX83 0x40280000 128 B DW00

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 Protection Units

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX84 0x40290000 128 B DW10
PERI_MS_PPU_FX85 0x40280100 128 B DW0_CRC
PERI_MS_PPU_FX86 0x40290100 128 B DW1_CRC
PERI_MS_PPU_FX87 0x40288000 64 B DW0_CH_STRUCT0
PERI_MS_PPU_FX88 0x40288040 64 B DW0_CH_STRUCT1
PERI_MS_PPU_FX89 0x40288080 64 B DW0_CH_STRUCT2
PERI_MS_PPU_FX90 0x402880C0 64 B DW0_CH_STRUCT3
PERI_MS_PPU_FX91 0x40288100 64 B DW0_CH_STRUCT4
PERI_MS_PPU_FX92 0x40288140 64 B DW0_CH_STRUCT5
PERI_MS_PPU_FX93 0x40288180 64 B DW0_CH_STRUCT6
PERI_MS_PPU_FX94 0x402881C0 64 B DW0_CH_STRUCT7
PERI_MS_PPU_FX95 0x40288200 64 B DW0_CH_STRUCT8
PERI_MS_PPU_FX96 0x40288240 64 B DW0_CH_STRUCT9
PERI_MS_PPU_FX97 0x40288280 64 B DW0_CH_STRUCT10
PERI_MS_PPU_FX98 0x402882C0 64 B DW0_CH_STRUCT11
PERI_MS_PPU_FX99 0x40288300 64 B DW0_CH_STRUCT12
PERI_MS_PPU_FX100 0x40288340 64 B DW0_CH_STRUCT13
PERI_MS_PPU_FX101 0x40288380 64 B DW0_CH_STRUCT14
PERI_MS_PPU_FX102 0x402883C0 64 B DW0_CH_STRUCT15
PERI_MS_PPU_FX103 0x40288400 64 B DW0_CH_STRUCT16
PERI_MS_PPU_FX104 0x40288440 64 B DW0_CH_STRUCT17
PERI_MS_PPU_FX105 0x40288480 64 B DW0_CH_STRUCT18
PERI_MS_PPU_FX106 0x402884C0 64 B DW0_CH_STRUCT19
PERI_MS_PPU_FX107 0x40288500 64 B DW0_CH_STRUCT20
PERI_MS_PPU_FX108 0x40288540 64 B DW0_CH_STRUCT21
PERI_MS_PPU_FX109 0x40288580 64 B DW0_CH_STRUCT22
PERI_MS_PPU_FX110 0x402885C0 64 B DW0_CH_STRUCT23
PERI_MS_PPU_FX111 0x40288600 64 B DW0_CH_STRUCT24
PERI_MS_PPU_FX112 0x40288640 64 B DW0_CH_STRUCT25
PERI_MS_PPU_FX113 0x40288680 64 B DW0_CH_STRUCT26
PERI_MS_PPU_FX114 0x402886C0 64 B DW0_CH_STRUCT27
PERI_MS_PPU_FX115 0x40288700 64 B DW0_CH_STRUCT28
PERI_MS_PPU_FX116 0x40298000 64 B DW1_CH_STRUCT0
PERI_MS_PPU_FX117 0x40298040 64 B DW1_CH_STRUCT1
PERI_MS_PPU_FX118 0x40298080 64 B DW1_CH_STRUCT2
PERI_MS_PPU_FX119 0x402980C0 64 B DW1_CH_STRUCT3
PERI_MS_PPU_FX120 0x40298100 64 B DW1_CH_STRUCT4
PERI_MS_PPU_FX121 0x40298140 64 B DW1_CH_STRUCT5
PERI_MS_PPU_FX122 0x40298180 64 B DW1_CH_STRUCT6
PERI_MS_PPU_FX123 0x402981C0 64 B DW1_CH_STRUCT7
PERI_MS_PPU_FX124 0x40298200 64 B DW1_CH_STRUCT8
PERI_MS_PPU_FX125 0x40298240 64 B DW1_CH_STRUCT9
PERI_MS_PPU_FX126 0x40298280 64 B DW1_CH_STRUCT10

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 Protection Units

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX127 0x402982C0 64 B DW1_CH_STRUCT11
PERI_MS_PPU_FX128 0x40298300 64 B DW1_CH_STRUCT12
PERI_MS_PPU_FX129 0x40298340 64 B DW1_CH_STRUCT13
PERI_MS_PPU_FX130 0x40298380 64 B DW1_CH_STRUCT14
PERI_MS_PPU_FX131 0x402983C0 64 B DW1_CH_STRUCT15
PERI_MS_PPU_FX132 0x40298400 64 B DW1_CH_STRUCT16
PERI_MS_PPU_FX133 0x40298440 64 B DW1_CH_STRUCT17
PERI_MS_PPU_FX134 0x40298480 64 B DW1_CH_STRUCT18
PERI_MS_PPU_FX135 0x402984C0 64 B DW1_CH_STRUCT19
PERI_MS_PPU_FX136 0x40298500 64 B DW1_CH_STRUCT20
PERI_MS_PPU_FX137 0x40298540 64 B DW1_CH_STRUCT21
PERI_MS_PPU_FX138 0x40298580 64 B DW1_CH_STRUCT22
PERI_MS_PPU_FX139 0x402985C0 64 B DW1_CH_STRUCT23
PERI_MS_PPU_FX140 0x40298600 64 B DW1_CH_STRUCT24
PERI_MS_PPU_FX141 0x40298640 64 B DW1_CH_STRUCT25
PERI_MS_PPU_FX142 0x40298680 64 B DW1_CH_STRUCT26
PERI_MS_PPU_FX143 0x402986C0 64 B DW1_CH_STRUCT27
PERI_MS_PPU_FX144 0x40298700 64 B DW1_CH_STRUCT28
PERI_MS_PPU_FX145 0x402A0000 16 B DMAC
PERI_MS_PPU_FX146 0x402A1000 256 B DMAC_CH0
PERI_MS_PPU_FX147 0x402A1100 256 B DMAC_CH1
PERI_MS_PPU_FX148 0x402A1200 256 B DMAC_CH2
PERI_MS_PPU_FX149 0x402A1300 256 B DMAC_CH3
PERI_MS_PPU_FX150 0x402C0000 128 B EFUSE
PERI_MS_PPU_FX151 0x402C0800 512 B EFUSE
PERI_MS_PPU_FX152 0x402D0000 64 KB PROFILE
PERI_MS_PPU_FX153 0x40300000 8B HSIOM_PRT0_PORT
PERI_MS_PPU_FX154 0x40300010 8B HSIOM_PRT1_PORT
PERI_MS_PPU_FX155 0x40300020 8B HSIOM_PRT2_PORT
PERI_MS_PPU_FX156 0x40300030 8B HSIOM_PRT3_PORT
PERI_MS_PPU_FX157 0x40300040 8B HSIOM_PRT4_PORT
PERI_MS_PPU_FX158 0x40300050 8B HSIOM_PRT5_PORT
PERI_MS_PPU_FX159 0x40300060 8B HSIOM_PRT6_PORT
PERI_MS_PPU_FX160 0x40300070 8B HSIOM_PRT7_PORT
PERI_MS_PPU_FX161 0x40300080 8B HSIOM_PRT8_PORT
PERI_MS_PPU_FX162 0x40300090 8B HSIOM_PRT9_PORT
PERI_MS_PPU_FX163 0x403000A0 8B HSIOM_PRT10_PORT
PERI_MS_PPU_FX164 0x403000B0 8B HSIOM_PRT11_PORT
PERI_MS_PPU_FX165 0x403000C0 8B HSIOM_PRT12_PORT
PERI_MS_PPU_FX166 0x403000D0 8B HSIOM_PRT13_PORT
PERI_MS_PPU_FX167 0x403000E0 8B HSIOM_PRT14_PORT
PERI_MS_PPU_FX168 0x40302000 32 B HSIOM_AMUX_SPLIT
PERI_MS_PPU_FX169 0x40302200 16 B

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 86
 Protection Units

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX170 0x40310000 64 B GPIO_PRT0
PERI_MS_PPU_FX171 0x40310080 64 B GPIO_PRT1
PERI_MS_PPU_FX172 0x40310100 64 B GPIO_PRT2
PERI_MS_PPU_FX173 0x40310180 64 B GPIO_PRT3
PERI_MS_PPU_FX174 0x40310200 64 B GPIO_PRT4
PERI_MS_PPU_FX175 0x40310280 64 B GPIO_PRT5
PERI_MS_PPU_FX176 0x40310300 64 B GPIO_PRT6
PERI_MS_PPU_FX177 0x40310380 64 B GPIO_PRT7
PERI_MS_PPU_FX178 0x40310400 64 B GPIO_PRT8
PERI_MS_PPU_FX179 0x40310480 64 B GPIO_PRT9
PERI_MS_PPU_FX180 0x40310500 64 B GPIO_PRT10
PERI_MS_PPU_FX181 0x40310580 64 B GPIO_PRT11
PERI_MS_PPU_FX182 0x40310600 64 B GPIO_PRT12
PERI_MS_PPU_FX183 0x40310680 64 B GPIO_PRT13
PERI_MS_PPU_FX184 0x40310700 64 B GPIO_PRT14
PERI_MS_PPU_FX185 0x40310040 16 B GPIO_PRT0
PERI_MS_PPU_FX186 0x403100C0 16 B GPIO_PRT1
PERI_MS_PPU_FX187 0x40310140 16 B GPIO_PRT2
PERI_MS_PPU_FX188 0x403101C0 16 B GPIO_PRT3
PERI_MS_PPU_FX189 0x40310240 16 B GPIO_PRT4
PERI_MS_PPU_FX190 0x403102C0 16 B GPIO_PRT5
PERI_MS_PPU_FX191 0x40310340 16 B GPIO_PRT6
PERI_MS_PPU_FX192 0x403103C0 16 B GPIO_PRT7
PERI_MS_PPU_FX193 0x40310440 16 B GPIO_PRT8
PERI_MS_PPU_FX194 0x403104C0 16 B GPIO_PRT9
PERI_MS_PPU_FX195 0x40310540 16 B GPIO_PRT10
PERI_MS_PPU_FX196 0x403105C0 16 B GPIO_PRT11
PERI_MS_PPU_FX197 0x40310640 16 B GPIO_PRT12
PERI_MS_PPU_FX198 0x403106C0 16 B GPIO_PRT13
PERI_MS_PPU_FX199 0x40310740 8B GPIO_PRT14
PERI_MS_PPU_FX200 0x40314000 64 B GPIO_INTR
PERI_MS_PPU_FX201 0x40315000 8B
PERI_MS_PPU_FX202 0x40320800 256 B SMARTIO_PRT8
PERI_MS_PPU_FX203 0x40320900 256 B SMARTIO_PRT9
PERI_MS_PPU_FX204 0x40350000 64 KB LPCOMP
PERI_MS_PPU_FX205 0x40360000 4 KB CSD
PERI_MS_PPU_FX206 0x40380000 64 KB TCPWM0
PERI_MS_PPU_FX207 0x40390000 64 KB TCPWM1
PERI_MS_PPU_FX208 0x403B0000 64 KB LCD0
PERI_MS_PPU_FX209 0x403F0000 64 KB USBFS0
PERI_MS_PPU_FX210 0x40420000 64 KB SMIF0
PERI_MS_PPU_FX211 0x40460000 64 KB SDHC0
PERI_MS_PPU_FX212 0x40470000 64 KB SDHC1

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 87
 Protection Units

Table 9-2. Fixed PPU Structures

Protection Structure Base Address of Protected Region Size of Protected Region Protected Peripheral/Block(s)
PERI_MS_PPU_FX213 0x40600000 64 KB SCB0
PERI_MS_PPU_FX214 0x40610000 64 KB SCB1
PERI_MS_PPU_FX215 0x40620000 64 KB SCB2
PERI_MS_PPU_FX216 0x40630000 64 KB SCB3
PERI_MS_PPU_FX217 0x40640000 64 KB SCB4
PERI_MS_PPU_FX218 0x40650000 64 KB SCB5
PERI_MS_PPU_FX219 0x40660000 64 KB SCB6
PERI_MS_PPU_FX220 0x40670000 64 KB SCB7
PERI_MS_PPU_FX221 0x40680000 64 KB SCB8
PERI_MS_PPU_FX222 0x40690000 64 KB SCB9
PERI_MS_PPU_FX223 0x406A0000 64 KB SCB10
PERI_MS_PPU_FX224 0x406B0000 64 KB SCB11
PERI_MS_PPU_FX225 0x406C0000 64 KB SCB12
PERI_MS_PPU_FX226 0x40A00000 4 KB PDM0
PERI_MS_PPU_FX227 0x40A10000 4 KB I2S0
PERI_MS_PPU_FX228 0x40A11000 4 KB I2S1

■ The programmable PPU structures can have Each peripheral group has a dedicated PPU. The
configurable address regions. Similar to fixed-PPU protection information is provided by peripheral group
structures, the protection attributes of programmable MMIO registers. A peripheral group PPU uses fixed
PPU structures can be configured for each protection protection structure pairs for two purposes.
context. Programmable PPU structures are similar to ❐ Fixed protection structure pairs protect peripherals
SMPU structures but are intended to be used with the (one pair for each peripheral). The master structure
peripheral register space. These protection structures protects the MMIO registers of the pair (the memory
are typically used to protect registers in a specific block, region encompasses the MMIO registers of the pair’s
which are not covered by the resolution of fixed PPU master structure and slave structure). The slave
structures. structure protects the peripheral (the memory region
Note that the memory regions of the fixed master encompasses the peripheral address region).
structures, fixed slave structures, and programmable ❐ Fixed protection structure pairs protect specific
master structures are fixed by hardware and are peripheral subregions (one pair for each subregion).
mutually exclusive; that is, they do not overlap. The The master structure protects the MMIO registers of
memory regions of the programmable slave structure the pair. The slave structure protects the peripheral
are software-programmable and can potentially overlap. subregion. These pairs can be used to protect, for
Therefore, it is important to assign priority to the example, individual DW channels in the DW periph-
protection structure matching process. The order in eral or individual IPC structures in the IPC periph-
which these are evaluated are as follows: eral.
❐ The fixed master structures are evaluated in Note that the memory regions of the fixed peripheral
decreasing order. master structures, fixed peripheral slave structures, and
❐ The fixed slave structures are evaluated in decreas- fixed peripheral subregion master structures are fixed by
ing order. hardware and are mutually exclusive; that is, they do not
❐ The programmable master structures are evaluated overlap. The memory regions of the fixed peripheral
in decreasing order. subregion slave structures are fixed by hardware and
typically are a subset of a peripheral address region, and
❐ The programmable slave structures are evaluated in
therefore overlap with a fixed peripheral slave structure.
decreasing order.
Therefore, it is important to assign priority to how the
The programmable slave structures are evaluated last. protection structure matching process:
These structures are software-programmable and can
❐ The fixed peripheral subregion master structures are
potentially overlap (overlapping should not allow
evaluated in decreasing order.
software to circumvent the protection as provided by the
fixed protection structure pairs). ❐ The fixed peripheral subregion slave structures are
evaluated in decreasing order.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 88
 Protection Units

❐ The fixed peripheral master structures are evaluated PPU protection information (the master and slave protection
in decreasing order. structures are registers).
❐ The fixed peripheral slave structures are evaluated in
decreasing order. 9.7.6 Protection Structure Types
It is important to evaluate the fixed peripheral subregion Different protection structure types are used because some
master structures first. This allows software to assign resources, such as peripheral registers, have a fixed
different protection for a subregion of a peripheral. address range. Protection of protection structures requires
pairs of neighboring protection structures.
9.7.5 Protection of Protection Structures
Three types of protection structures with a consistent
The MPU, SMPU, and PPU-based protection architecture is register interface are described here:
consistent and provides the flexibility to implement different ■ Programmable protection structures. These are 32-byte
system-wide protection schemes. Protection structures can protection structures with a programmable address
be set once at boot time or can be changed dynamically range. These structures are used by the MPUs.
during device execution. For example, a CPU RTOS can
■ Fixed protection structure pairs. These are 64-byte
change the CPU’s MPU settings; a secure CPU can change
master/slave protection structure pairs, consisting of two
the SMPU and PPUs settings. But such a system will be left
32-byte protection structures. These structures are used
insecure if there is no way to protect the protection
by the PPUs. Both structures have a fixed, constant
structures themselves. There must be a way to restrict
address region. The master structure has the UX and PX
access to the protection structures.
attributes as constant ‘0’ (execution is never allowed)
The protection of protection structures is achieved using and the UR and PR attributes as constant ‘1’ (reading is
another protection structure. For this reason, protection always allowed). The slave structure has the UX and PX
structures are defined in pairs of master and slave. We refer attributes as constant ‘1’.
to the slave and master protection structures as a protection ■ Programmable protection structure pairs. These are 64-
pair. Note that the address range of the master protection byte master/slave protection structure pairs, consisting
structure is known, that is, it is constant. of two 32-byte protection structures. These structures
The first (slave) protection structure protects the resource are used by the PPU and SMPU. The master structure
and the second (master) protection structure protects the has a fixed, constant address region. The slave structure
protection (address range of the second protection structure has a programmable address region. The master
includes both the master and slave protection structures). structure has the UX and PX attributes as constant ‘0’
(execution is never allowed) and the UR and PR
The protection architecture is flexible enough to allow for attributes as constant ‘1’ (reading is always allowed).
variations: The PPU slave structure has the UX and PX attributes
■ Exclusive peripheral ownership can be shared by more as constant ‘1’. The SMPU slave structure has
than two protection contexts. programmable UX and PX attributes.
■ The ability to change ownership is under control of a Note that the master protection structure in a protection
single protection context, and exclusive or non-exclusive structure pair is required only to address security
peripheral ownership is shared by multiple protection requirements. The distinction between the three protection
contexts. structure types is an implementation optimization. From an
Note that in secure systems, typically a single secure CPU architectural perspective, all PPU protection structures are
is used. In these systems, the ability to change ownership is the same, with the exception that for some protection
assigned to the secure CPU at boot time and not structures the address range is fixed and not programmable.
dynamically changed. Therefore, you must assign the As mentioned earlier, a protection unit evaluates the
secure CPU its own, dedicated protection context. protection regions in decreasing protection structure index
Both PPU and SMPU is intended to distinguish between order. The protection structures are evaluated in the
different protection contexts and to distinguish secure from following order:
non-secure accesses. Therefore, both PPU and SMPU ■ Fixed protection structures for specific peripherals or
protection use protection structure pairs. In the SMPU, the peripheral register address ranges.
slave protection structure provides SMPU protection ■ Programmable protection structures.
information and the master protection structure provides

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 89
 Protection Units

Figure 9-6. PPU and SMPU Pairs

PPU, programmable protection structure pair SMPU, programmable protection structure pair
Slave Structure Slave Structure ADDR

3
1

0
ADDR

SUBREGI

DISABLE
3
1

ADDR[
23:0]

ON_
Programmable ADDR Encompassing Peripheral Slave MMIO Registers
SIZE
3
1

0
Programmable REGION SIZE ATT

3
1

0
PC_MATCH

REGION_

PC_MASK
ENABLED
3
1

0
ATT0,1,2&3

SIZE

[15:1]

PW

UW
PR
PX

UR
NS

UX
1
Programmable PC Attributes

Master Structure Master Structure

3
1

0
ADDR Constant
3
1

0
Constant ADDR[23:0], encompassing
Constant ADDR Encompassing Peripheral Slave MMIO Registers SUBREGION_DISA
master and slave protection structures
BLE
SIZE
3
1

0
Constant REGION SIZE ATT

3
1

0
PC_MATCH

PC_MASK
ENABLED

REGION_
3
1

0
ATT0,1,2&3

Constant

UR = 1
PX = 0

PR = 1
UX = 0
[15:1]

PW

UW
SIZE

NS
1
Programmable PC Attributes

PPU, fixed protection structure pair

Slave Structure ADDR
3
1

Constant ADDR Encompassing Peripheral Slave MMIO Registers

SIZE
3
1

Constant REGION SIZE

3
1

ATT0,1,2&3
Programmable PC Attributes

Master Structure

ADDR
3
1

Constant ADDR Encompassing Peripheral Slave MMIO Registers

SIZE
3
1

Constant REGION SIZE

3
1

ATT0,1,2&3
Programmable PC Attributes

Note: By default, both CPUs (CM0+ and CM4) are in protection context 0 when they come out of reset. In protection context
0, the master is able to access all memory regardless of its protection settings. The master’s protection context will need to be
changed from protection context 0 to make any protection structure configuration effective. Multiple protection structures may
be preconfigured as part of the boot code, which sets up a secure environment at boot time. See the Boot Code chapter on
page 193 for details of these configurations.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 90
 10. DMA Controller (DW)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The DMA transfers data to and from memory, peripherals, and registers. These transfers occur independent from the CPU.
The DMA can be configured to perform multiple independent data transfers. All data transfers are managed by a channel.
There can be up to 32 channels in the DMA. The number of channels in the DMA controller can vary with devices. Refer to
the PSoC 61 datasheet/PSoC 62 datasheet for the number of channels supported in the device. A channel has an associated
priority; channels are arbitrated according to their priority.

10.1 Features
The DMA controller has the following features:
■ Supports up to 29 channels per DMA controller; see the PSoC 61 datasheet/PSoC 62 datasheet for details
■ Supports multiple DMA controller instances in a device
■ Four levels of priority for each channel
■ Descriptors are defined in memory and referenced to the respective channels
■ Supports single, 1D, or 2D transfer modes for a descriptor
■ Supports transfer of up to 65536 data elements per descriptor
■ Configurable source and destination address increments
■ Supports 8-bit, 16-bit, and 32-bit data widths at both source and destination
■ Configurable input trigger behavior for each descriptor
■ Configurable interrupt generation in each descriptor
■ Configurable output trigger generation for each descriptor
■ Descriptors can be chained to other descriptors in memory

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 91
 DMA Controller (DW)

10.2 Architecture
Figure 10-1. DMA Controller

DMA

System Pending Priority Data Transfer Engine Trigger out

Triggers triggers Decoder (active request) Interrupt

Trigger Bus slave DMA Bus master

Multiplexer interface registers interface

Descriptors
Descriptors
Descriptors

Memory

A data transfer is initiated by an input trigger. This trigger connects to a specific system trigger through a trigger
may originate from the source peripheral of the transfer, the multiplexer that is outside the DMA controller.
destination peripheral of the transfer, CPU software, or from
Channel priority: A channel is assigned a priority
another peripheral. Triggers provide Active/Sleep
(CHi_CTL.PRIO) between 0 and 3, with 0 being the highest
functionality and are not available in Deep Sleep and
priority and 3 being the lowest priority. Channels with the
Hibernate power modes.
same priority constitute a priority group. Priority decoding
The data transfer details are specified by a descriptor. determines the highest priority pending channel, which is
Among other things, this descriptor specifies: determined as follows.
■ The source and destination address locations and the ■ The highest priority group with pending channels is
size of the transfer. identified first.
■ The actions of a channel; for example, generation of ■ Within this priority group, round-robin arbitration is
output triggers and interrupts. See the Interrupts chapter applied.
on page 56 for more details.
Channel state: At any given time, one channel actively
■ Data transfer types can be single, 1D, or 2D as defined performs a data transfer. This channel is called the active
in the descriptor structure. These types define the channel. A channel can be in one of four channel states.
address sequences generated for source and The active channel in a DW controller can be determined by
destination. 1D and 2D transfers are used for “scatter reading the DWx_STATUS[ACTIVE] and
gather” and other useful transfer operations. DWx.STATUS[CH_IDX].
Pending state of a channel is determined by reading the
10.3 Channels DW_CH_STRUCT_CH_STATUS[PENDING] associated
with that channel. If a channel is enabled and is not in the
The DMA controller supports multiple independent data Pending or Active state, then it is considered blocked.
transfers that are managed by a channel. Each channel

Table 10-1. Channel States

Channel State Description
Disabled The channel is disabled by setting CHi_CTL.ENABLED to ‘0’. The channel trigger is ignored in this state.
Blocked The channel is enabled and is waiting for a trigger to initiate a data transfer.
The channel is enabled and has received an active trigger. In this state, the channel is ready to initiate a data transfer but
Pending
waiting for it to be scheduled.
The channel is enabled, has received an active trigger and has been scheduled. It is actively performing data transfers. If
Active
there are multiple channels pending, the highest priority pending channel is scheduled.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 92
 DMA Controller (DW)

The data transfer associated with a trigger is made up of event that will trigger the interrupt for the channel. In
one or more ‘atomic transfers’ or ‘single transfers’; see addition each DMA channel has INTR, INTR_SET,
Table 10-2 for a better understanding. A single trigger could INTR_MASK, and INTR_MASKED registers to control their
be configured to transfer multiple “single transfers”. respective interrupt lines. INTR_MASK can be used to mask
the interrupt from the DMA channel. The INTR and
A channel can be marked preemptable
INTR_SET can be used to clear and set the interrupt,
(CHi_CTL.PREEMPTABLE). If preemptable, and there is a
respectively, for debug purposes.
higher priority pending channel, then that higher priority
channel can preempt the current channel between single The DW_CH_STRUCT_CH_STATUS[INTR_CAUSE] field
transfers. If a channel is preempted, the existing single provides the user a means to determine the cause of the
transfer is completed; the current channel goes to pending interrupt being generated. The following are different values
state and the higher priority channel is serviced. On for this register:
completion of the higher priority channel's transfer, the ■ 0: No interrupt generated
pending channel is resumed. Note that preemption has an
■ 1: Interrupt based on transfer completion configured
impact on the data transfer rates of the channel being
based on INTR_TYPE field in the descriptor
preempted. Refer to “DMA Performance” on page 100 for
these performance implications. ■ 2: Source bus error
■ 3: Destination bus error
A channel has two access control attributes that are used by
the shared memory protection units (SMPUs) and peripheral ■ 4: Misaligned source address
protection units (PPUs) for access control. These fields are ■ 5: Misaligned destination address
typically inherited from the master that modified the ■ 6: Current descriptor pointer is null
channel’s control register.
■ 7: Active channel is in disabled state
■ The Privileged Mode (CHi_CTL.P) attribute can be set to
privileged or user. ■ 8: Descriptor bus error

■ The Non-secure (CHi_CTL.NS) attribute can be set to ■ 9-15: Not used.

secure or non-secure. For error related interrupt causes (INTR_CAUSE is 2, 3,...,
A descriptor associated with each channel describes the 8), the channel is disabled (hardware sets
data transfer. The descriptor is stored in memory and CH_CTL.ENABLED to ‘0’).
CHi_CURR_PTR provides the descriptor address The bus errors are typically caused by incompatible
associated with channel “i” and Chi_IDX provides the accesses to the addresses in question. This may be due to
current X and Y indices into the descriptor. those addresses being protected or having read or write
A channel’s descriptor state is encoded as part of the restrictions. Source and destination bus errors can also
channel’s register state. The following registers provide a occur due to mismatch in data sizes (see “Transfer Size” on
channel’s descriptor state: page 97).
■ CH_CTL. This register provides generic channel control
information.
■ CH_CURR_PTR. This register provides the address of
the memory location where the current descriptor is
located. The user firmware must initialize this register. If
the descriptors are chained, the DMA hardware
automatically sets this register to the next descriptor
pointer.
■ CH_IDX. This register provides the current X and Y
indices of the channel into the current descriptor. User
firmware must initialize this register. DMA hardware sets
the X and Y indices to 0, when advancing from the
current descriptor to the next descriptor in a descriptor
list.
Note that channel state is retained in Deep Sleep power
mode.

10.3.1 Channel Interrupts

Every DMA channel has an interrupt line associated with it.
The INTR_TYPE parameter in the descriptor determines the

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 93
 DMA Controller (DW)

10.4 Descriptors
The data transfer between a source and destination in a channel is configured using a descriptor. Descriptors are stored in
memory. The descriptor pointer is specified in the DMA channel registers. The DMA controller does not modify the descriptor
and treats it as read only. A descriptor is a set of up to six 32-bit registers that contain the configuration for the transfer in the
associated channel. There are three types of descriptors.

Table 10-2. Descriptor Types

Descriptor Type Description
Transfers a single data element
Single transfer A B

Performs a one-dimensional “for loop”. This transfer is made up of X number of single transfers

A B
A+1 B+1
1D transfer A+2 B+2

A+X-1 B+ X-1

Performs a two-dimensional “for loop”. This transfer is made up of Y number of 1D transfers

A B
1st 1D transfer A+1 B+1
A+2 B+2

A+X-1 B+X-1
A+X B+X
A+X+1 B+X+1
2nd 1D transfer A+X+2 B+X+2

2D transfer A+2X-1 B+2X-1

th
Y 1D transfer

A+(X*Y)-1 B+X*Y-1

This performs a one-dimensional “for loop” similar to the 1D transfer. However, the source data is not trans-
ferred to a destination. Instead, a CRC is calculated over the source data. The CRC configuration is provided
through a set of registers that is shared by all DMA channels. The assumption is that the DMA channels use
CRC transfer
the CRC functionality mutually exclusively in time. These registers are: CRC_CTL, CRC_DATA_CTL,
CRC_POL_CTL, CRC_LFSR_CTL, CRC_REM_CTL, and CRC_REM_RESULT. Note that the CRC configu-
ration is the same as the Crypto CRC configuration.

Single Transfer:
The following pseudo code illustrates a single transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
DST_ADDR[0] = (t_DATA_SIZE) SRC_ADDR[0];

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 94
 DMA Controller (DW)

1D Transfer:
The following pseudo code illustrates a 1D transfer. Note that the 1D transfer is represented by a loop with each iteration
executing a single transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[X_IDX * DST_X_INCR] =
(t_DATA_SIZE) SRC_ADDR[X_IDX * SRC_X_INCR];
}

2D Transfer:
The following pseudo code illustrates a 2D transfer. Note that the 2D transfer is represented by a loop with each iteration
executing an inner loop, which is the 1D transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
for (Y_IDX = 0; Y_IDX <= Y_COUNT; Y_IDX++) {
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[X_IDX * DST_X_INCR + Y_IDX * DST_Y_INCR ] =
(t_DATA_SIZE) SRC_ADDR[X_IDX * SRC_X_INCR + Y_IDX * SRC_Y_INCR];
}
}

CRC Transfer:
The following pseudo code illustrates CRC transfer.
// DST_ADDR is a pointer to an address location where the calculated CRC is stored.
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
CRC_STATE = CRC_LFSR_CTL;
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
Update_CRC (CRC_STATE, (t_DATA_SIZE) SRC_ADDR[X_IDX * SRC_X_INCR];
}
DST_ADDR = CRC_STATE;

The parameters in the descriptor help configure the different aspects of the transfers explained.
Figure 10-2 shows the structure of a descriptor.

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 DMA Controller (DW)

Figure 10-2. Descriptor Structure

Descriptor
DESCR_SRC
Source Address
DESCR_DST
Destination Address
DESCR_CTL
DESCR_TYPE
TR_IN_TYPE TR_OUT_TYPE
SCR_TRANSFER_SIZE DST_TRANSFER_SIZE
DATA_SIZE
INTR_TYPE CH_DISABLE WAIT_FOR_DEACT

X Size
SRC_X_INR DST_X_INCR

Y Size
SRC_Y_INR DST_Y_INCR

DESCR_NEXT_PTR
Next Descriptor Address

10.4.1 Address Configuration trigger setting will not automatically trigger the next
descriptor.
Source and Destination Address: The source and
■ Type 3: A trigger results in execution of the current
destination addresses are set in the respective registers in
descriptor and also triggering the next descriptor. The
the descriptor. These set the base addresses for the source
execution of the next descriptor from this point will be
and destination location for the transfer. In case the
determined by the TR_IN_TYPE setting of the next
descriptor is configured to transfer a single element, this
descriptor.
field holds the source/destination address of the data
element. If the descriptor is configured to transfer multiple Trigger out type, TR_OUT_TYPE: This field determines
elements with source address or destination address or both what completion event will generate the output trigger
in an incremental mode, this field will hold the address of the signal. This field can be configured to one of the following
first element that is transferred. modes:
DESCR_TYPE: This field configures whether the descriptor ■ Type 0: Generates a trigger output for completion of
has a single, 1D, or 2D type. every single element transfer.
■ Type 1: Generates a trigger output for completion of a
Trigger input type, TR_IN_TYPE: This field determines
1D transfer
how the DMA engine responds to input trigger signal. This
field can be configured for one of the following modes: ■ Type 2: Generates a trigger output for completion of the
current descriptor. This trigger output is generated
■ Type 0: A trigger results in execution of a single transfer.
independent of the state of the DESCR_NEXT_PTR.
Regardless of the DESCR_TYPE setting, a trigger input
will trigger only a single element transfer. For example, ■ Type 3: Generates a trigger output on completion of the
in a 1D transfer, the DMA will transfer only one data current descriptor, when the current descriptor is the last
element in every trigger. descriptor in the descriptor chain. This means a trigger is
generated when the descriptor execution is complete
■ Type 1: A trigger results in the execution of a single 1D
and the DESCR_NEXT_PTR is ‘0’.
transfer. If the DESCR_TYPE was set to single transfer,
the trigger signal will trigger the single transfer specified Interrupt Type, INTR_TYPE: This field determines which
by the descriptor. For a DESCR_TYPE set to 1D completion event will generate the output interrupt signal.
transfer, the trigger signal will trigger the entire 1D This field can be configured to one of the following modes:
transfer configured in the descriptor. For a 2D transfer, ■ Type 0: Generates an interrupt output for completion of
the trigger signal will trigger only a single iteration of the every single element transfer.
Y loop transfer.
■ Type 1: Generates an interrupt output for completion of a
■ Type 2: A trigger results in execution of the current 1-D transfer.
descriptor. Regardless of DESCR_TYPE, the trigger will
execute the entire descriptor. If there was a next
descriptor configured for the current descriptor, this

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 DMA Controller (DW)

■ Type 2: Generates an interrupt output for completion of that has a trigger going to the DMA when its not full.
the current descriptor. This interrupt output is generated Free space in FIFO will trigger a DMA transfer to the
independent of the state of the DESCR_NEXT_PTR. FIFO, which in turn will deactivate the trigger. However,
■ Type 3: Generates an interrupt output on completion of there can be a delay in this deactivation by the agent,
the current descriptor, when the current descriptor is the which may cause the DMA to have initiated another
last descriptor in the descriptor chain. This means an transfer that can cause a FIFO overflow. This can be
interrupt is generated when the descriptor execution is avoided by using the four or 16 clock cycle delays.
complete and the DESCR_NEXT_PTR is ‘0’. X Count: This field determines the number of single
WAIT_FOR_DEACT: When the DMA transfer based on the element transfers present in the X loop (inner loop). This
TR_IN_TYPE is completed, the data transfer engine checks field is valid when the DESCR_TYPE is set to 1D or 2D
the state of trigger deactivation. The data transfer on the transfer.
second trigger is initiated only after deactivation of the first. Source Address Increment (X loop) (SCR_X_INCR): This
The WAIT_FOR_DEACT parameter will determine when the field configures the index by which the source address is to
trigger signal is considered deactivated. The first DMA be incremented for every iteration in an X loop. The field is
transfer is activated when the trigger is activated, but the expressed in multiples of SRC_TRANSFER_SIZE. This field
transfer is not considered complete until the trigger is is a signed number and hence may be decrementing or
deactivated. This field is used to synchronize the controller’s incrementing. If the source address does not need to be
data transfers with the agent that generated the trigger. This incremented, you can set this parameter to zero.
field has four settings:
Destination Address Increment (X loop) (DST_X_INCR):
■ 0 – Pulse Trigger: Do not wait for deactivation. When a
This field configures the index by which the destination
trigger is detected, the transfer is initiated. After
address is to be incremented, for every iteration in an X
completing the transfer, if the trigger is still active then it
loop. The field is expressed in multiples of
is considered as another trigger and the subsequent
DST_TRANSFER_SIZE. This field is a signed number and
transfer is initiated immediately.
hence may be decrementing or incrementing. If the
■ 1 – Level-sensitive waits four slow clock cycles after the destination address does not need to be incremented, you
transfer to consider as a deactivation. When a trigger is can set this parameter to zero.
detected, the transfer is initiated. After completing the
transfer, if the trigger is still active then it is considered Y Count: This field determines the number of 1-D transfers
as another trigger after waiting for four cycles. Then, a present in the Y loop (outer loop). This field is valid when the
subsequent transfer is initiated. The transfer DESCR_TYPE is set to 2-D transfer.
corresponding to the trigger is considered complete only Source Address Increment (Y loop) (SCR_Y_INCR): This
at the end of the four additional cycles. Even trigger field configures the index by which the source address is to
output events will be affected based on this delay. This be incremented, for every iteration in a Y loop. The field is
parameter adds a four-cycle delay in each trigger expressed in multiples of SRC_TRANSFER_SIZE. This field
transaction and hence affects throughput. is a signed number and hence may be decrementing or
■ 2 – Level-sensitive waits 16 slow clock cycles after the incrementing. If the source address does not need to be
transfer to consider as a deactivation. When a trigger is incremented, you can set this parameter to zero.
detected, the transfer is initiated. After completing the
transfer, if the trigger is still active then it is considered Destination Address Increment (X loop) (DST_Y_INCR):
as another trigger after waiting for 16 cycles. Then, a This field configures the index by which the destination
subsequent transfer is initiated. The transfer address is to be incremented, for every iteration in a Y loop.
corresponding to the trigger is considered complete only The field is expressed in multiples of
at the end of the 16 additional cycles. Even trigger DST_TRANSFER_SIZE. This field is a signed number and
output events will be affected based on this delay. This hence may be decrementing or incrementing. If the
parameter adds a 16-cycle delay in each trigger destination address does not need to be incremented, you
transaction and hence affects throughput. can set this parameter to zero.
■ 3 – Pulse trigger waits indefinitely for deactivation. The Channel Disable (CH_DISABLE): This field specifies
DMA transfer is initiated after the trigger signal whether the channel is disabled or not after completion of
deactivates. The next transfer is initiated only if the the current descriptor (independent of the value of the
trigger goes low and then high again. A trigger signal DESCR_NEXT_PTR). A disabled channel will ignore its
that remains active or does not transition to zero input triggers.
between two transaction will simply stall the DMA
channel. 10.4.2 Transfer Size
The WAIT_FOR_DEACT field is used in a system to
The word width for a transfer can be configured using the
cater to delayed response of other parts of the system to
transfer/data size parameter in the descriptor. The settings
actions of the DMA. Consider an example of a TX FIFO

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 DMA Controller (DW)

are diversified into source transfer size, destination transfer be set to 32 bit to match the width of the PWM register,
size, and data size. The data size parameter (DATA_SIZE) because the peripheral register width for the TCPWM block
sets the width of the bus for the transfer. The source and (and most PSoC 6 MCU peripherals) is always 32-bit wide.
destination transfer sizes set by SCR_TRANSFER_SIZE However, in this example the DATA_SIZE for the destination
and DST_TRANSFER_SIZE can have a value either the may still be set to 16 bit because the 16-bit PWM only uses
DATA_SIZE or 32 bit. DATA_SIZE can have a 32-bit, 16-bit, two bytes of data. SRAM and Flash are 8-bit, 16-bit, or 32-
or 8-bit setting. bit addressable and can use any source and destination
transfer sizes to match the needs of the application.
The source and destination transfer size for the DMA must
match the addressable width of the source and destination, Table 10-3 summarizes the possible combinations of the
regardless of the width of data that must be moved. The transfer size settings and its description.
DATA_SIZE parameter will correspond to the width of the
actual data. For example, if a 16-bit PWM is used as a
destination for DMA data, the DST_TRANSFER_SIZE must

Table 10-3. Transfer Size Settings

SCR_TRANSFER_ DST_TRANSFER_
DATA_SIZE Typical Usage Description
SIZE SIZE
8-bit 8-bit 8-bit Memory to Memory No data manipulation
8-bit 32-bit 8-bit Peripheral to Memory Higher 24 bits from the source dropped
8-bit 8-bit 32-bit Memory to Peripheral Higher 24 bits zero padded at destination
Higher 24 bits from the source dropped and
8-bit 32-bit 32-bit Peripheral to Peripheral
higher 24 bits zero padded at destination
16-bit 16-bit 16-bit Memory to Memory No data manipulation
16-bit 32-bit 16-bit Peripheral to Memory Higher 16 bits from the source dropped
16-bit 16-bit 32-bit Memory to Peripheral Higher 16 bits zero padded at destination
Higher 16 bits from the source dropped and
16-bit 32-bit 32-bit Peripheral to Peripheral
higher 16-bit zero padded at destination
32-bit 32-bit 32-bit Peripheral to Peripheral No data manipulation

10.4.3 Descriptor Chaining

Descriptors can be chained together. The DESCR_NEXT_PTR field contains a pointer to the next descriptor in the chain. A
channel executes the next descriptor in the chain when it completes executing the current descriptor. The last descriptor in
the chain has DESCR_NEXT_PTR set to ‘0’ (NULL pointer). A descriptor chain is also referred to as a descriptor list. It is
possible to have a circular list; in a circular list, the execution continues indefinitely until there is an error or the channel or the
controller is disabled by user code.

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 DMA Controller (DW)

10.5 DMA Controller

Figure 10-3. DMA Controller Overview

DMA

System Pending Priority Data Transfer Engine Trigger out

Triggers triggers Decoder (active request) Interrupt

Trigger Bus slave DMA Bus master

Multiplexer interface registers interface

Descriptors
Descriptors
Descriptors

Memory

10.5.1 Trigger Selection highest priority activated channel. It is also responsible for
reading the channel descriptor from memory.
Trigger signals can be generated from different sections of
the chips. A trigger multiplexer block helps route these Master I/F is an AHB-Lite bus master that allows the DMA
trigger signals to the destination. The DMA is one such controller to initiate AHB-Lite data transfers to the source
destination of triggers. The trigger multiplexer block is and destination locations as well as to read the descriptor
outside the DMA block and is discussed in the Trigger from memory.
Multiplexer Block chapter on page 294. Slave I/F is an AHB-Lite bus slave that allows the main CPU
to access DMA controller control/status registers.
10.5.2 Pending Triggers
Pending triggers keep track of activated triggers by locally 10.5.3 Output Triggers
storing them in pending bits. This is essential because Each channel has an output trigger. This trigger is high for
multiple channel triggers may be activated simultaneously, two slow clock cycles. The trigger is generated on the
whereas only one channel can be served by the data completion of a data transfer. At the system level, these
transfer engine at a time. This component enables the use output triggers can be connected to the trigger multiplexer
of both level-sensitive (high/‘1’) and pulse-sensitive (two component. This connection allows a DMA controller output
high/‘1’ clk_slow cycles) triggers. trigger to be connected to a DMA controller input trigger. In
■ Level-sensitive triggers are associated with a certain other words, the completion of a transfer in one channel can
state, for example, a FIFO being full. These triggers activate another channel or even reactivate the same
remain active as long as the state is maintained. It is not channel.
required to track pending level-sensitive triggers in the
DMA output triggers routing to other DMA channels or other
DMA controller because the triggers are maintained
peripheral trigger inputs is achieved using the trigger
outside the controller.
multiplexer. Refer to the Trigger Multiplexer Block chapter
■ Pulse-sensitive triggers are associated with a certain on page 294.
event, for example, sample has become available. It is
essential to track these triggers in the DMA controller
because the trigger pulse may disappear before it is
10.5.4 Status registers
served by the data transfer engine. Pulse triggers should The controller status register (DWx_STATUS) contains the
be high/‘1’ for two clk_slow cycles. following information.
The priority decoder determines the highest priority ■ ACTIVE – Active channel present, yes/no.
pending channel. ■ P – Active channel's access control user/privileged
The data transfer engine is responsible for the data ■ NS – Active channel's access control secure/non-secure
transfer from a source location to a destination location. ■ CH_IDX – Active channel index if there is an active
When idle, the data transfer engine is ready to accept the channel

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 DMA Controller (DW)

■ PRIO – Active channel priority 10.5.5 DMA Performance

■ PREEMPTABLE – Active channel preemptable or not
The DMA block works on the clk_slow domain and hence all
■ STATE – State of the DW controller state machine. The clocks described in this section are in clk_slow units.
following states are specified:
Every time a DMA channel is triggered the DMA hardware
❐ Default/inactive state
goes through the following steps:
❐ Loading descriptor: This state is when the controller
■ Trigger synchronization
has recognized the channel that was triggered and
become active and is now loading its respective ■ Detection, priority decoding, and making channel
descriptor. pending
❐ Loading data element: Reading data from source ■ Start state machine and load channel configuration
address ■ Load DMA descriptor
❐ Storing data element: Writing data into the destina- ■ Load next DMA descriptor pointer
tion address ■ Moving first element of data from source to destination.
❐ Update of active channel control information
Each of these steps involve multiple cycles for completion.
❐ Waiting for input trigger deactivation Table 10-4 shows the number of cycles needed for each
step.

Table 10-4. DMA Steps and Performance

Operation Cycles
Trigger Synchronization 2
Detection, priority decoding and making channel pending 1
Start state machine and load channel config 3
4 for single transfer
Load descriptors 5 for 1-D transfer
6 for 2-D transfer
Load next pointer 1
Moving data from source to destination 3
Total 14 for single transfer

For subsequent transfers on a preloaded descriptor, cycles are needed only to move the data from source to destination.
Therefore, transfers such as 1-D and 2-D, which are not preempted, incurs all the cycles only for the first transfer; subsequent
transfers will cost three cycles.
Based on the configuration of TRIG_IN_TYPE, the trigger synchronization cycles may be incurred for each single element
transfer or for each 1-D transfer.
The descriptor is four words long for a single transfer type, five words for 1-D transfer, and six words for a 2-D transfer. Hence,
the number of cycles needed to fetch a descriptor will vary based on its type.
Another factor to note is the latency in data or descriptor fetch due to wait states or bus latency.
The DMA performance for different types of transfers can be summarized as follows.
■ Single transfer
❐ 14 cycles per transfer + latency due to wait states or bus latency
■ 1D transfer
❐ To transfer n data elements
Number of cycles = 12 + n * 3 + m
m is the total number of wait states seen by DMA while loading or storing descriptors or data. An additional cycle is
required for the first transfer, to load the X-Loop configuration register.
■ 2D transfer
❐ If the 2 D transfer is transferring n elements then
Number of cycles = 13 + n * 3 + m

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 DMA Controller (DW)

m is total number of wait states seen by DMA while loading or storing descriptors or data. Two additional cycles are
required for the first transfer, to load the X-loop and Y-Loop configuration register.
Note: Descriptors in memory and memory wait states will also affect the descriptor load delay.
■ Wait states: Memory accesses can have a wait state associated with them. These wait states need to be accounted into
the calculation of throughput.
■ Channel arbitration: Some time channels are not immediately made active after reception of trigger. This is due to other
active channels in the system. This can lead to multiple cycles being lost before the channel is even made active.
■ Preemption: The choice of making a DMA channel preemptable impacts its performance. This is because every time a
channel is preempted:
❐ The channel is in a pending state for as long as the higher priority channel is running
❐ On resumption, the channel descriptor needs to be fetched again. This is additional cycles for every resume. So if
there are a large number of high-priority channels, making a low-priority channel preemptable can have adverse
effects on its throughput. On the other hand, if there is a low-priority channel that is transferring a large amount of data,
then not making it preemptable can starve other high-priority channels for too long.
Sometimes, users can also distribute channels across multiple DW blocks to avoid conditions of preemption and deal with
the contention at the bus arbitration level.
■ Bus arbitration: Several bus masters access the bus, including the CPU cores and multiple DMA (DW) and DMAC. This
makes any access to data movement over the bus subject to arbitration with other masters. Actions such as fetching the
descriptor or data can be stalled by arbitration. The arbitration of the bus is based on the arbitration scheme configured in
PROT_SMPU_MSx_CTL[PRIO]
■ Transfer width: The width of the transfer configured by the Data_size parameter in the descriptor is important in the
transfer throughput calculation. 32-bit transfers are four times faster than 8-bit transfers.

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 11. DMAC Controller (DMAC)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The DMAC transfers data to and from memory, peripherals, and registers. These transfers occur independent from the CPU.
The DMAC can be configured to perform multiple independent data transfers. All data transfers are managed by a channel.
There can be up to 32 channels in the DMAC. The number of channels in the DMAC controller can vary with devices. Refer to
the PSoC 61 datasheet/PSoC 62 datasheet for the number of channels supported in the device. A channel has an associated
priority; channels are arbitrated according to their priority. The main difference between the DMA (DW) and DMAC relate to
their usage. The DMA (DW) is meant as a small data size, transactional DMA, which would typically be used to transfer bytes
between peripherals such as, from ADC to RAM. Using the DMA (DW) for large transaction is expensive on a system due to
its relatively low performance. The DMAC is a transitional DMA. It is more efficient than the DMA (DW) and should be used to
transfer large amounts of data. The DMAC has dedicated channel logic for all channels. Furthermore, the DMAC also
includes a 12-byte FIFO for temporary data storage. This results in increased memory bandwidth for the DMAC. The DMAC
also supports an additional transfer mode called memory copy and scatter transfer.

11.1 Features
The DMAC controller has the following features:
■ Supports up to 32 channels per DMAC controller; see the PSoC 61 datasheet/PSoC 62 datasheet for details
■ Four levels of priority for each channel
■ Descriptors are defined in memory and referenced to the respective channels
■ Supports single, 1D, 2D, Memory-copy, or Scatter-transfer modes for a descriptor
■ Supports transfer of up to 2^32 data elements per descriptor
■ Configurable source and destination address increments
■ Supports 8-bit, 16-bit, and 32-bit data widths at both source and destination
■ Configurable input trigger behavior for each descriptor
■ Configurable interrupt generation in each descriptor
■ Configurable output trigger generation for each descriptor
■ Descriptors can be chained to other descriptors in memory

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 DMAC Controller (DMAC)

11.2 Architecture ■ CH_IDX. This register provides the current X and Y

indices of the channel into the current descriptor.
A data transfer is initiated by an input trigger. This trigger Software needs to initialize this register. Hardware sets
may originate from the source peripheral of the transfer, the the X and Y indices to 0, when advancing from the
destination peripheral of the transfer, CPU software, or from current descriptor to the next descriptor in a descriptor
another peripheral. Triggers provide Active/Sleep list.
functionality and are not available in Deep Sleep and ■ CH_SRC. This register provides the current address of
Hibernate power modes. the source location.
The data transfer details are specified by a descriptor. ■ CH_DST. This register provides the current address of
Among other things, this descriptor specifies: the destination location.
■ The source and destination address locations and the ■ CH_DESCR_STATUS. This register provides the validity
size of the transfer. of other CH_DESCR registers.
■ The actions of a channel; for example, generation of ■ CH_DESCR_CTL. This register contains a copy of
output triggers and interrupts. See the Interrupts chapter DESCR_CTL of the currently active descriptor.
on page 56 for more details. ■ CH_DESCR_SRC. This register contains a copy of
■ Data transfer types can be single, 1D, or 2D as defined DESCR_SRC of the currently active descriptor.
in the descriptor structure. These types define the ■ CH_DESCR_DST. This register contains a copy of
address sequences generated for source and DESCR_DST of the currently active descriptor.
destination. 1D and 2D transfers are used for “scatter
■ CH_DESCR_X_INCR. This register contains a copy of
gather” and other useful transfer operations.
DESCR_X_INCR of the currently active descriptor.
■ CH_DESCR_X_SIZE. This register contains a copy of
11.3 Channels DESCR_X_SIZE of the currently active descriptor.
■ CH_DESCR_Y_INCR. This register contains a copy of
The DMAC controller supports multiple independent data
DESCR_Y_INCR of the currently active descriptor.
transfers that are managed by a channel. Each channel
connects to a specific system trigger through a trigger ■ CH_DESCR_Y_SIZE. This register contains a copy of
multiplexer that is outside the DMAC controller. DESCR_Y_SIZE of the currently active descriptor.
■ CH_DESCR_NEXT_PTR. This register contains a copy
Channel priority: A channel is assigned a priority
of DESCR_NEXT_PTR of the currently active descriptor.
(CHi_CTL.PRIO) between 0 and 3, with 0 being the highest
priority and 3 being the lowest priority. Channels with the ■ INTR. This register contains the interrupts that are
same priority constitute a priority group. Priority decoding currently activated for this channel
determines the highest priority pending channel, which is ■ INTR_SET. Writing ‘1’ to the appropriate bit in this
determined as follows. register sets the corresponding INTR field to 1.
■ The highest priority group with pending channels is ■ INTR_MASK. Mask for corresponding field in the INTR
identified first. register.
■ Within this priority group, round-robin arbitration is ■ INTR_MASKED. Logical AND of corresponding INTR
applied. Round-robin arbitration within a priority group and INTR_MASK fields.
gives the highest priority to the lower channel indices in
Note that channel state is retained in Deep Sleep power
the priority group.
mode.
The data transfer associated with a trigger is made up of
A channel has three access control attributes that are used
one or more ‘atomic transfers’ or ‘single transfers’; see
by the shared memory protection units (SMPUs) and
Table 11-1 for a better understanding. A single trigger could
peripheral protection units (PPUs) for access control. These
be configured to transfer multiple “single transfers”.
fields are typically inherited from the master that modified
Channel Registers: the channel’s control register.
■ CH_CTL. This register provides generic channel control ■ The Privileged Mode (CHi_CTL.P) attribute can be set to
information. privileged or user.
■ CH_CURR_PTR. This register provides the memory ■ The Non-secure (CHi_CTL.NS) attribute can be set to
location address where the current descriptor is located. secure or non-secure.
Software needs to initialize this register. Hardware sets ■ The Protection context (CHi.CTL.PC) attribute can be
this register to the current descriptor’s next descriptor set to one of the protection contexts.
pointer, when advancing from the current descriptor to
the next descriptor in a chained descriptor list. When this
field is “0”, there is no valid descriptor.

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 DMAC Controller (DMAC)

11.3.1 Channel Interrupts

Every DMAC channel has an interrupt line associated with it. The INTR_TYPE parameter in the descriptor determines the
event that will trigger the interrupt for the channel. In addition, each DMAC channel has INTR, INTR_SET, INTR_MASK, and
INTR_MASKED registers to control their respective interrupt lines. INTR_MASK can be used to mask the interrupt from the
DMA channel. The INTR and INTR_SET can be used to clear and set the interrupt, respectively, for debug purposes.
The DMAC_CHx_INTR registers allow the user to set different interrupt causes. The following causes are available to
configure:
■ bit 0: Interrupt based on transfer completion configured based on INTR_TYPE field in the descriptor
■ bit 1: Source bus error
■ bit 2: Destination bus error
■ bit 3: Misaligned source address
■ bit 4: Misaligned destination address
■ bit 5: Current descriptor pointer is null
■ bit 6: Active channel is in disabled state
■ bit 7: Descriptor bus error
For error-related interrupt causes (every state other than Completion), the channel is disabled (hardware sets
CH_CTL.ENABLED to ‘0’).

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 DMAC Controller (DMAC)

11.4 Descriptors
The data transfer between a source and destination in a channel is configured using a descriptor. Descriptors are stored in
memory. The descriptor pointer is specified in the DMAC channel registers. The DMAC controller does not modify the
descriptor and treats it as read only. A descriptor is a set of up to six 32-bit registers that contain the configuration for the
transfer in the associated channel. There are three types of descriptors.

Table 11-1. Descriptor Types

Descriptor Type Description
Transfers a single data element
Single transfer A B

Performs a one-dimensional “for loop”. This transfer is made up of X number of single transfers

A B
A+1 B+1
1D transfer A+2 B+2

A+X-1 B+ X-1

Performs a two-dimensional “for loop”. This transfer is made up of Y number of 1D transfers

A B
1st 1D transfer A+1 B+1
A+2 B+2

A+X-1 B+X-1
A+X B+X
A+X+1 B+X+1
2nd 1D transfer A+X+2 B+X+2

2D transfer A+2X-1 B+2X-1

th
Y 1D transfer

A+(X*Y)-1 B+X*Y-1

This is a special case of 1D transfer; DESCR_X_INCR.SRC_X_INCR and DESCR_X_INCR.DST_X_INCR

are implicitly set to 1 and not as part of the descriptor (source and destinations data are consecutive). The
descriptor type assumes that both source and destination locations are memory locations. Therefore, 8-bit,
16-bit, and 32-bit transfers can be used (as long as alignment requirements are met), rather than using trans-
fer of a specific type (as specified by SRC_TRANSFER_SIZE and DST_TRANSFER_SIZE).
Memory copy The size of the descriptor is five 32-bit words. DESCR_CTL, DESCR_SRC, DESCR_DST, DESCR_X_SIZE,
and DESCR_NEXT_PTR (note that the descriptor size is one word less than the 1D transfer descriptor size).
Scatter: This descriptor type is intended to write a set of 32-bit data elements, whose addresses are
“scattered” around the address space.
The size of the descriptor is four 32-bit words. DESCR_CTL, DESCR_SRC, DESCR_X_SIZE, and
DESCR_NEXT_PTR.
This descriptor type is intended to write a set of 32-bit data elements, whose addresses are “scattered”
around the address space.
Scatter transfer
The size of the descriptor is four 32-bit words. DESCR_CTL, DESCR_SRC, DESCR_X_SIZE, and
DESCR_NEXT_PTR.

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 DMAC Controller (DMAC)

Single Transfer:
The following pseudo code illustrates a single transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
DST_ADDR[0] = (t_DATA_SIZE) SRC_ADDR[0];

1D Transfer:
The following pseudo code illustrates a 1D transfer. Note that the 1D transfer is represented by a loop with each iteration
executing a single transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[X_IDX * DST_X_INCR] =
(t_DATA_SIZE) SRC_ADDR[X_IDX * SRC_X_INCR];
}

2D Transfer:
The following pseudo code illustrates a 2D transfer. Note that the 2D transfer is represented by a loop with each iteration
executing an inner loop, which is the 1D transfer.
// DST_ADDR is a pointer to an object of type defined by DST_TRANSFER_SIZE
// SRC_ADDR is a pointer to an object of type defined by SRC_TRANSFER_SIZE
// t_DATA_SIZE is the type associated with the DATA_SIZE
for (Y_IDX = 0; Y_IDX <= Y_COUNT; Y_IDX++) {
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[X_IDX * DST_X_INCR + Y_IDX * DST_Y_INCR ] =
(t_DATA_SIZE) SRC_ADDR[X_IDX * SRC_X_INCR + Y_IDX * SRC_Y_INCR];
}
}

Memory copy:
The following pseudo code illustrates a memory copy.
// DST_ADDR is a pointer to an object of type uint8_t
// SRC_ADDR is a pointer to an object of type uint8_t
// This transfer type uses 8-bit, 16-bit an 32-bit transfers. The HW ensures that
// alignment requirements are met.
for (X_IDX = 0; X_IDX <= X_COUNT; X_IDX++) {
DST_ADDR[X_IDX] = SRC_ADDR[X_IDX];
}

Scatter:
The following pseudo code illustrates the scatter transfer
// SRC_ADDR is a pointer to an object of type uint32_t
for (X_IDX = 0; X_IDX < X_COUNT; X_IDX += 2) {
address = SRC_ADDR[X_IDX];
data = SRC_ADDR[X_IDX + 1];
*address = data;
}

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 DMAC Controller (DMAC)

The parameters in the descriptor help configure the different aspects of the transfers explained.
Figure 11-2 shows the structure of a descriptor.
Figure 11-1. Descriptor Structure

Descriptor
DESCR_SRC
Source Address
DESCR_DST
Destination Address
DESCR_CTL
DESCR_TYPE
TR_IN_TYPE TR_OUT_TYPE
SCR_TRANSFER_SIZE DST_TRANSFER_SIZE
DATA_SIZE
INTR_TYPE CH_DISABLE WAIT_FOR_DEACT

X Size
SRC_X_INR DST_X_INCR

Y Size
SRC_Y_INR DST_Y_INCR

DESCR_NEXT_PTR
Next Descriptor Address

11.4.1 Address Configuration will trigger only a single element transfer. For example,
in a 1D transfer, the DMAC will transfer only one data
Source and Destination Address: The source and element in every trigger.
destination addresses are set in the respective registers in
■ Type 1: A trigger results in the execution of a single 1D
the descriptor. These set the base addresses for the source
transfer. If the DESCR_TYPE was set to single transfer,
and destination location for the transfer. In case the
the trigger signal will trigger the single transfer specified
descriptor is configured to transfer a single element, this
by the descriptor. For a DESCR_TYPE set to 1D
field holds the source/destination address of the data
transfer, the trigger signal will trigger the entire 1D
element. If the descriptor is configured to transfer multiple
transfer configured in the descriptor. For a 2D transfer,
elements with source address or destination address or both
the trigger signal will trigger only a single iteration of the
in an incremental mode, this field will hold the address of the
Y loop transfer. If the descriptor type is “memory copy”,
first element that is transferred.
the trigger results in the execution of a memory copy
DESCR_TYPE: This field configures whether the descriptor transfer.
has a single, 1D, 2D type, memory copy, or scatter transfer. ■ Type 2: A trigger results in execution of the current
Source data prefetch, DATA_PREFETCH: When enabled, descriptor. Regardless of DESCR_TYPE, the trigger will
source data transfers are initiated as soon as the channel is execute the entire descriptor. If there was a next
enabled; the current descriptor pointer is not “0” and there is descriptor configured for the current descriptor, this
space available in the channel's data FIFO. When the input trigger setting will not automatically trigger the next
trigger is activated, the trigger can initiate destination data descriptor.
transfers with data that is already in the channel's data ■ Type 3: A trigger results in execution of the current
FIFO. This effectively shortens the initial delay of the data descriptor and also triggering the next descriptor. The
transfer. execution of the next descriptor from this point will be
determined by the TR_IN_TYPE setting of the next
Note: Data prefetch should be used with care to ensure that descriptor.
data coherency is guaranteed and that prefetches do not
cause undesired side effects.
Trigger input type, TR_IN_TYPE: This field determines
how the DMAC engine responds to input trigger signal. This
field can be configured for one of the following modes:
■ Type 0: A trigger results in execution of a single transfer.
Regardless of the DESCR_TYPE setting, a trigger input

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 DMAC Controller (DMAC)

Trigger out type, TR_OUT_TYPE: This field determines ■ 2 – Level-sensitive waits 16 SYSCLK cycles: The DMAC
what completion event will generate the output trigger transfer is initiated if the input trigger is seen to be
signal. This field can be configured to one of the following activated after 16 clock cycles.
modes: ■ 3 – Pulse trigger waits indefinitely for deactivation. The
■ Type 0: Generates a trigger output for completion of DMAC transfer is initiated after the trigger signal
every single element transfer. deactivates. The next transfer is initiated only if the
■ Type 1: Generates a trigger output for completion of a trigger goes low and then high again.
1D transfer. If the descriptor type is “memory copy”, the X Size: This field determines the number of single element
output trigger is generated after the execution of a transfers present in the X loop (inner loop). This field is valid
memory copy transfer. If the descriptor type is “scatter”, when the DESCR_TYPE is set to 1D or 2D transfer. For the
the output trigger is generated after the execution of a “memory copy” descriptor type, (X_COUNT + 1) is the
scatter transfer. number of transferred Bytes. For the “scatter” descriptor
■ Type 2: Generates a trigger output for completion of the type, ceiling (X_COUNT/2) is the number of (address, write
current descriptor. This trigger output is generated data) initialization pairs processed.
independent of the state of the DESCR_NEXT_PTR.
Source Address Increment (X loop) (SCR_X_INCR): This
■ Type 3: Generates a trigger output on completion of the field configures the index by which the source address is to
current descriptor, when the current descriptor is the last be incremented for every iteration in an X loop. The field is
descriptor in the descriptor chain. This means a trigger is expressed in multiples of SRC_TRANSFER_SIZE. This field
generated when the descriptor execution is complete is a signed number and hence may be decrementing or
and the DESCR_NEXT_PTR is ‘0’. incrementing. If the source address does not need to be
Interrupt Type, INTR_TYPE: This field determines which incremented, you can set this parameter to zero.
completion event will generate the output interrupt signal. Destination Address Increment (X loop) (DST_X_INCR):
This field can be configured to one of the following modes: This field configures the index by which the destination
■ Type 0: Generates an interrupt output for completion of address is to be incremented, for every iteration in an X
every single element transfer. loop. The field is expressed in multiples of
■ Type 1: Generates an interrupt output for completion of a DST_TRANSFER_SIZE. This field is a signed number and
1-D transfer. If the descriptor type is “memory copy”, the hence may be decrementing or incrementing. If the
interrupt is generated after the execution of a memory destination address does not need to be incremented, you
copy transfer. If the descriptor type is “scatter” the can set this parameter to zero.
interrupt is generated after the execution of a scatter Y Size: This field determines the number of 1-D transfers
transfer. present in the Y loop (outer loop). This field is valid when the
■ Type 2: Generates an interrupt output for completion of DESCR_TYPE is set to 2-D transfer.
the current descriptor. This interrupt output is generated
Source Address Increment (Y loop) (SCR_Y_INCR): This
independent of the state of the DESCR_NEXT_PTR.
field configures the index by which the source address is to
■ Type 3: Generates an interrupt output on completion of be incremented, for every iteration in a Y loop. The field is
the current descriptor, when the current descriptor is the expressed in multiples of SRC_TRANSFER_SIZE. This field
last descriptor in the descriptor chain. This means an is a signed number and hence may be decrementing or
interrupt is generated when the descriptor execution is incrementing. If the source address does not need to be
complete and the DESCR_NEXT_PTR is ‘0’. incremented, you can set this parameter to zero.
WAIT_FOR_DEACT: When the DMAC transfer based on Destination Address Increment (X loop) (DST_Y_INCR):
the TR_IN_TYPE is completed, the data transfer engine This field configures the index by which the destination
checks the state of trigger deactivation. The data transfer on address is to be incremented, for every iteration in a Y loop.
the second trigger is initiated only after deactivation of the The field is expressed in multiples of
first. The WAIT_FOR_DEACT parameter will determine DST_TRANSFER_SIZE. This field is a signed number and
when the trigger signal is considered deactivated. The first hence may be decrementing or incrementing. If the
DMAC transfer is activated when the trigger is activated, but destination address does not need to be incremented, you
the transfer is not considered complete until the trigger is can set this parameter to zero.
deactivated. This field is used to synchronize the controller’s
data transfers with the agent that generated the trigger. This Channel Disable (CH_DISABLE): This field specifies
field has four settings: whether the channel is disabled or not after completion of
the current descriptor (independent of the value of the
■ 0 – Pulse Trigger: Do not wait for deactivation.
DESCR_NEXT_PTR). A disabled channel will ignore its
■ 1 – Level-sensitive waits four SYSCLK cycles: The input triggers.
DMAC trigger is deactivated after the level trigger signal
is detected for four cycles.

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 DMAC Controller (DMAC)

11.4.2 Transfer Size actual data. For example, if a 16-bit PWM is used as a
destination for DMAC data, the DST_TRANSFER_SIZE
The word width for a transfer can be configured using the must be set to 32 bit to match the width of the PWM register,
transfer/data size parameter in the descriptor. The settings because the peripheral register width for the TCPWM block
are diversified into source transfer size, destination transfer (and most PSoC 6 MCU peripherals) is always 32-bit wide.
size, and data size. The data size parameter (DATA_SIZE) However, in this example the DATA_SIZE for the destination
sets the width of the bus for the transfer. The source and may still be set to 16 bit because the 16-bit PWM only uses
destination transfer sizes set by SCR_TRANSFER_SIZE two bytes of data. SRAM and Flash are 8-bit, 16-bit, or 32-
and DST_TRANSFER_SIZE can have a value either the bit addressable and can use any source and destination
DATA_SIZE or 32 bit. DATA_SIZE can have a 32-bit, 16-bit, transfer sizes to match the needs of the application.
or 8-bit setting.
Table 11-2 summarizes the possible combinations of the
The source and destination transfer size for the DMAC must transfer size settings and its description.
match the addressable width of the source and destination,
regardless of the width of data that must be moved. The
DATA_SIZE parameter will correspond to the width of the

Table 11-2. Transfer Size Settings

DATA_SIZE SCR_TRANSFER_SIZE DST_TRANSFER_SIZE Description
8-bit 8-bit 8-bit No data manipulation
8-bit 32-bit 8-bit Higher 24 bits from the source dropped
8-bit 8-bit 32-bit Higher 24 bits zero padded at destination
Higher 24 bits from the source dropped and higher 24 bits
8-bit 32-bit 32-bit
zero padded at destination
16-bit 16-bit 16-bit No data manipulation
16-bit 32-bit 16-bit Higher 16 bits from the source dropped
16-bit 16-bit 32-bit Higher 16 bits zero padded at destination
Higher 16 bits from the source dropped and higher 16-bit
16-bit 32-bit 32-bit
zero padded at destination
32-bit 32-bit 32-bit No data manipulation

11.4.3 Descriptor Chaining

Descriptors can be chained together. The DESCR_NEXT_PTR field contains a pointer to the next descriptor in the chain. A
channel executes the next descriptor in the chain when it completes executing the current descriptor. The last descriptor in
the chain has DESCR_NEXT_PTR set to ‘0’ (NULL pointer). A descriptor chain is also referred to as a descriptor list. It is
possible to have a circular list; in a circular list, the execution continues indefinitely until there is an error or the channel or the
controller is disabled by user code.

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 DMAC Controller (DMAC)

11.5 DMAC Controller

Figure 11-2. DMAC Controller Overview
DMA controller

Trigger Channel0 logic

multiplexers tr_in[0]
Pending trigger
Data transfer engine tr_out[]
System Triggers Channel state
Priority
decoder
tr_in[1]
Channel2 logic
...
tr_in[CH_NR- 1]
Channel31 logic

Bus slave Bus master

DMAC registers
interface interface

Memory holds channel

descriptor structure Memory

11.5.1 Trigger Selection Slave I/F is an AHB-Lite bus slave that allows the main CPU
to access DMAC controller control/status registers.
Trigger signals can be generated from different sections of
the chips. A trigger multiplexer block helps route these
11.5.3 Output Triggers
trigger signals to the destination. The DMAC is one such
destination of triggers. The trigger multiplexer block is Each channel has an output trigger. This trigger is high for
outside the DMAC block and is discussed in the Trigger two slow clock cycles. The trigger is generated on the
Multiplexer Block chapter on page 294. completion of a data transfer. At the system level, these
output triggers can be connected to the trigger multiplexer
11.5.2 Channel Logic component. This connection allows a DMAC controller
output trigger to be connected to a DMAC controller input
The channel logic keeps track of pending triggers for each trigger. In other words, the completion of a transfer in one
channel and initiates the transfer corresponding to the active channel can activate another channel or even reactivate the
descriptor, based on availability of the bus and arbitration by same channel.
priority decoder.
DMAC output triggers routing to other DMAC channels or
The priority decoder determines the highest priority other peripheral trigger inputs is achieved using the trigger
pending channel. multiplexer. Refer to the Trigger Multiplexer Block chapter
Master I/F is an AHB-Lite bus master that allows the DMAC on page 294.
controller to initiate AHB-Lite data transfers to the source
and destination locations as well as to read the descriptor
from memory.

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 12. Cryptographic Function Block (Crypto)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Cryptographic block (Crypto) provides hardware implementation and acceleration of cryptographic functions.
Implementation in hardware takes less time and energy than the equivalent firmware implementation. In addition, the block
provides True Random Number generation functionality in silicon, which is not available in firmware.

12.1 Features
■ Advanced encryption standard (AES)
■ Data Encryption and Triple Data Encryption Standards (DES, TDES)
■ Secure Hash Algorithm (SHA)
■ Cyclic redundancy checking (CRC)
■ Pseudo random number generator (PRNG)
■ True random number generator (TRNG)
■ Vector unit (VU) to support asymmetric key cryptography, such as RSA and ECC.

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 Cryptographic Function Block (Crypto)

12.2 Architecture
The following figure gives an overview of the cryptographic block.
Figure 12-1. Crypto Block Diagram

AHB-Lite infrastructure

AHB-Lite Master
AHB-Lite Slave Interface
Interface

Memory Buffer
Control (up to 16KB)
Interrupt Instruction & clk_sys
FIFO Status
(MMIO)
Memory interface

Symmetric Hashing Others

Asymmetric
DES SHA1 TRNG
RSA
TDES SHA2 PRNG
ECC
AES SHA3 CRC

The crypto block has the following interfaces:

■ An AHB-Lite slave interface connects the block to the AHB-Lite infrastructure. This interface supports 8/16/32-bit AHB-Lite
transfers. MMIO register accesses are 32-bit only. Memory buffer accesses can be 8/16/32-bit.
■ An AHB-Lite master interface connects the block to the AHB-Lite infrastructure. This interface supports 8/16/32-bit AHB-
Lite transfers. The interface enables the crypto block to access operation operand data from system memories, such as
Flash or SRAM.
■ A single interrupt signal “interrupt” is used to signal the completion of an operation.
■ A clock signal “clk_sys” interface connects to the SRSS.
The block has the following components:
■ An AHB-Lite slave interface.
■ An AHB-Lite master interface.
■ A component that contains MMIO control and status registers.
■ A memory buffer, for internal operation operand data.
■ A memory interface that directs operation operand data requests to either the block internal memory buffer or to the AHB-
Lite master interface.
■ An instruction controller component that decodes instructions from an instruction FIFO. The controller issues the
instructions to the function specific components.
■ Cryptographic function specific components.
The following sections explain each component in detail.

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 Cryptographic Function Block (Crypto)

12.3 Instruction Controller

The instruction controller consists of an instruction FIFO, an instruction decoder, and a general-purpose register file.
■ The instruction FIFO is software-programmable through MMIO registers that are accessed through the AHB-Lite slave
interface. Software writes instructions and instruction operand data to the instruction FIFO. The FIFO consists of eight 32-
bit FIFO entries.
■ The instruction decoder decodes the instructions (and the associated instruction operand data) from the instruction FIFO.
The instruction decoder issues the decoded instruction to a specific functional component. The functional component is
responsible for instruction execution.
■ The general-purpose register file consists of sixteen 32-bit registers. An instruction specifies the specific use of register-
file registers. Registers are used to specify instruction operand data, such as memory locations (for example, for DES,
AES, and SHA instructions) or immediate data operations (for example, for vector unit instructions).

12.3.1 Instructions
An instruction consists of a sequence of one, two, or three instruction words. Most instructions are encoded by a single
instruction word.
The instruction FIFO can hold up to eight 32-bit instruction words. A CPU writes instruction words to the instruction FIFO
(INSTR_FF_WR register) and the crypto block decodes the instruction words to execute the instructions.
INSTR_FF_STATUS.USED specifies how many of the eight instruction FIFO entries are used. The instruction FIFO
decouples the progress of CPU execution from the crypto block execution: the CPU can write new instruction words to the
FIFO, while the block executes previously written instructions.
There are multiple interrupt causes associated with the instruction FIFO and the instruction decoder:
■ The INTR.INSTR_FF_OVERFLOW interrupt cause is activated on a write to a full instruction FIFO.
■ THE INTR.INSTR_FF_LEVEL interrupt cause is activated when the number of used FIFO entries
(INSTR_FF_STATUS.USED) is less than a specified number of FIFO entries (INSTR_FF_CTL.LEVEL).
■ The INTR.INSTR_OPC_ERROR interrupt cause is activated when an instruction's operation code is not defined.
■ The INTR.INSTR_CC_ERROR interrupt cause is activated when a vector unit instruction has an undefined condition
code.
Most instructions perform specific cryptographic functionality. For example, the AES instruction performs and Advanced
Encryption Standard (AES) block cipher operation. Some instructions perform more generic functionality: most generic
instructions move operand data between different locations. Higher level symmetric cipher and hash functionality is
implemented using a combination of cryptographic instructions and generic instructions. Higher level asymmetric cipher
functionality is implemented using a set of vector unit (VU) instructions.

12.3.2 Instruction Operands

The instruction operands are found in one of the following locations:
■ System memory
■ Memory buffer
■ Instruction FIFO instruction words
■ Load and store FIFOs
■ Register buffer
■ Vector unit register-file
System memory. The system memory includes all memory-mapped memories attached to the bus infrastructure that are
accessible by the crypto block through the master bus interface.
Memory buffer. The crypto block memory buffer is an internal SRAM with a capacity of up to 16 KB. This internal SRAM
provides better latency and bandwidth characteristics than the system memory. Therefore, frequently accessed vector unit
instruction operand data is typically located in the memory buffer.

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 Cryptographic Function Block (Crypto)

Both the block’s external system memory and internal memory buffer are accessed through the same memory interface
component. The access address specifies if the access is to the system memory or the internal memory buffer (also see
VU_CTL.ADDR[31:14]).
External bus masters can access both the system memory and the crypto’s internal memory. The external bus masters
access the internal memory through the slave bus interface.
Instruction FIFO. For some instructions, immediate operand data is provided by the instruction words. The limited 32-bit
instruction words only allow for limited immediate operand data.
Load and store FIFOs. Most instructions have stream-like operand data: sequences of bytes that are specified by the access
address of the start byte. The two load FIFOs provide access to source operand data and the single store FIFO provides
access to destination operand data. Typically, vector unit instruction operand data is “streamed” from the crypto block memory
buffer.
Register buffer. Most symmetric and hash cryptographic instructions benefit from a large (2048-bit) register buffer. This
register buffer provides access flexibility that is not provided by the load and store FIFOs. The register buffer is shared by
different instructions to amortize its cost (silicon area). After an Active reset or a crypto block reset (CTL.ENABLED), the
register buffer is set to ‘0’.
Vector unit register file. Most vector unit instructions perform large integer arithmetic functionality. For example, the VU
ADD instruction can add two 4096-bit numbers. Typically, operand data is “streamed” from the memory buffer. In addition, a
vector unit register file with sixteen registers is provided. Each register specifies the location of a number (start word access
address) and the size of the number (the size is in bits).

12.3.3 Load and Store FIFO Instructions

The load and store FIFOs provide access to operand data in a “streaming” nature. Operand data is streamed through the
memory interface from or to either the internal memory buffer or the system memory.
Two independent load FIFOs provide access to streamed source operand data. Each FIFO has a multi-byte buffer to prefetch
operand data.
One store FIFO provides access to streamed destination operand data. The FIFO has a multi-byte buffer to temporarily hold
the data before it is written to the memory interface.
Streamed operand data is specified by a memory start address and an operand size in bytes.
Three FIFO instructions are supported: FF_START, FF_STOP, and FF_CONTINUE. The FF_START and FF_STOP
instructions are supported for both the load and store FIFOs. The FF_CONTINUE instruction is only supported for the load
FIFOs. The FF_START and FF_CONTINUE instructions consist of three instruction words. The FF_STOP instruction consists
of a single instruction word.

Table 12-1. FF_START Instruction

Instruction Format FF_START (ff_identifier, address[31:0], size[31:0])
IW0[31:24] = “operation code”
IW0[3:0] = ff_identifier // “8”: load FIFO 0,
// “9”: load FIFO 1,
Encoding
// “12”: store FIFO
IW1[31:0] = address[31:0]
IW2[31:0] = size[31:0]
Mnemonic Operation Code Functionality
Clear the FIFO multi-byte buffer. Start streaming size[31:0] operand data bytes,
starting at address[31:0].
This instruction is supported by both load and store FIFOs. For load FIFOs, data
FF_START 0x70 bytes are read through the memory interface. For the store FIFO, data bytes are
written to the memory interface.
The INSTR_OPC_ERROR interrupt cause is set when the ff_identifier is not a legal
value.

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 Cryptographic Function Block (Crypto)

Table 12-2. FF_STOP instruction

Instruction Format FF_STOP (ff_identifier)
IW0[31:24] = “operation code”
IW0[3:0] = ff_identifier // “8”: load FIFO 0,
Encoding
// “9”: load FIFO 1,
// “12”: store FIFO
Mnemonic Operation Code Functionality
Stop streaming
This instruction is supported by both load and store FIFOs. For load FIFOs, the multi-
byte buffer is cleared. For the store FIFO, the multi-byte buffer is written to the mem-
FF_STOP 0x72
ory interface; that is, the buffer is flushed.
The INSTR_OPC_ERROR interrupt cause is set when the ff_identifier is not a legal
value.

Table 12-3. FF_CONTINUE Instruction

Instruction Format FF_CONTINUE (ff_identifier, address[31:0], size[31:0])
IW0[31:24] = “operation code”
IW0[3:0] = ff_identifier // “8”: load FIFO 0,
Encoding // “9”: load FIFO 1,
IW1[31:0] = address[31:0]
IW2[31:0] = size[31:0]
Mnemonic Operation Code Functionality
Do not clear the FIFO multi-byte buffer. Continue streaming size[31:0] oper-
and data bytes, starting at address[31:0]. This instruction can only be started
when a previous FF_START or FF_CONTINUE instruction for the same load
FIFO has read all its operand data bytes from the memory interface (see
FF_CONTINUE 0x71 LOAD01/_FF_STATUS.BUSY).
This instruction is only supported by the load FIFOs.
The INSTR_OPC_ERROR interrupt cause is set when the ff_identifier is not a
legal value.

The status of the load and store FIFOs is provided through the LOAD0_FF_STATUS, LOAD1_FF_STATUS, and
STORE_FF_STATUS registers.

12.3.4 Register Buffer Instructions

The 2048-bit register buffer has two 1024-bit partitions: reg_buff[1023:0] and reg_buff[2047:1024]. The reg_buff[1023:0]
partition has eight 128-bit subpartitions:
■ block0[127:0] = reg_buff[0*128+127:0*128]
■ block1[127:0] = reg_buff[1*128+127:1*128]
■ block2[127:0] = reg_buff[2*128+127:2*128]
■ block3[127:0] = reg_buff[3*128+127:3*128]
■ block4[127:0] = reg_buff[4*128+127:4*128]
■ block5[127:0] = reg_buff[5*128+127:5*128]
■ block6[127:0] = reg_buff[6*128+127:6*128]
■ block7[127:0] = reg_buff[7*128+127:7*128]
The reg_buff[1023:0] partition consists of 128 bytes: Byte offset 0 identifies reg_buff[7:0] and Byte offset 127 identifies
reg_buff[1023:1016].

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Some instructions work on the complete register buffer and some instructions work on 128-bit subpartitions.

Table 12-4. CLEAR Instruction

Instruction Format CLEAR ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
reg_buff[2047:0] = 0;
This instruction is used to set the register buffer to ‘0’. This instruction is useful to
CLEAR 0x64
prevent information leakage from the register buffer.
The instruction also sets DEV_KEY_STATUS.LOADED to '0'.

Table 12-5. SWAP Instruction

Instruction Format SWAP ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
temp = reg_buff[1023:0];
reg_buff[1023:0] = reg_buff[2047:1024];
SWAP 0x65
reg_buff[2047:1024] = temp;
This instruction swaps/exchanges the two register buffer partitions.

Table 12-6. XOR Instruction

Instruction Format XOR (offset[6:0], size[7:0])
IW[31:24] = “operation code”
Encoding IW[14:8] = offset
IW[7:0] = size // in the range [0,128]
Mnemonic Operation Code Functionality
data = GetFifoData (LOAD0_FIFO, size);
data = data << (offset*8);
XOR 0x66 reg_buff[1023:0] = reg_buff[1023:0] ^ data;
This instruction always uses load FIFO 0.
Note: This instruction can only access the lower register buffer partition.

Table 12-7. STORE Instruction

Instruction Format STORE (offset[6:0], size[7:0])
IW[31:24] = “operation code”
Encoding IW[14:8] = offset
IW[7:0] = size // in the range [0,128]
Mnemonic Operation Code Functionality
data = reg_buff[1023:0]
STORE 0x67 data = data >> (offset*8);
SetFifoData (STORE_FIFO, size, data)

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Table 12-8. BYTE_SET Instruction

Instruction Format BYTE_SET (offset[6:0], byte[7:0])
IW[31:24] = “operation code”
Encoding IW[14:8] = offset
IW[7:0] = byte
Mnemonic Operation Code Functionality
BYTE_SET 0x68 reg_buff[offset*8 + 7: offset*8] = byte;

Some instructions work on (up to) 128-bit subpartitions or blocks. In addition, these instructions can work on the load and
store FIFOs. The instructions' source and destination operand identifiers are encoded as follows:
■ 0: block0[127:0] = reg_buff[0*128+127:0*128]
■ 1: block1[127:0] = reg_buff[1*128+127:1*128]
■ 2: block2[127:0] = reg_buff[2*128+127:2*128]
■ 3: block3[127:0] = reg_buff[3*128+127:3*128]
■ 4: block4[127:0] = reg_buff[4*128+127:4*128]
■ 5: block5[127:0] = reg_buff[5*128+127:5*128]
■ 6: block6[127:0] = reg_buff[6*128+127:6*128]
■ 7: block7[127:0] = reg_buff[7*128+127:7*128]
■ 8: load FIFO 0
■ 9: load FIFO 1
■ 12: store FIFO

Table 12-9. BLOCK_MOV Instruction

Instruction Format BLOCK_MOV (reflect[1], size[3:0], dst[3:0], src0[3:0])
IW[31:24] = “operation code”
IW[23] = reflect
Encoding IW[19:16] = size
IW[15:12] = dst
IW[3:0] = src0
Mnemonic Operation Code Functionality
size = (size == 0) ? 16 : size;
data1 = data0 = GetBlock (src0, size);
if (reflect) { // assume size of 16 B / 128 bit
temp = data0;
for (i = 0; i < 16; i += 1) {
for (j = 0; j < 8; j += 1) {
BLOCK_MOV 0x40
// reflection of bits in a byte
data1[8*i + j] = data0[8*i + 7-j];
}
}
}
SetBlock (dst, size, data1);

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Table 12-10. BLOCK_XOR Instruction

Instruction Format BLOCK_XOR (size[3:0], dst[3:0], src1[3:0], src0[3:0])
IW[31:24] = “operation code”
IW[19:16] = size
Encoding IW[15:12] = dst
IW[7:4] = src1
IW[3:0] = src0
Mnemonic Operation Code Functionality
size = (size == 0) ? 16 : size;
data0 = GetBlock (src0, size);
BLOCK_XOR 0x41
data1 = GetBlock (src1, size);
SetBlock (dst, size, data0 ^ data1);

Table 12-11. BLOCK_SET Instruction

Instruction Format BLOCK_SET (size[3:0], dst[3:0], byte[7:0])
IW[31:24] = “operation code”
IW[19:16] = size
Encoding
IW[15:12] = dst
IW[7:0] = byte
Mnemonic Operation Code Functionality
size = (size == 0) ? 16 : size;
BLOCK_SET 0x42
SetBlock (dst, size, {16{byte[7:0]}})

Table 12-12. BLOCK_CMP Instruction

Instruction Format BLOCK_CMP (size[3:0], src1[3:0], src0[7:0])
IW[31:24] = “operation code”
IW[19:16] = size
Encoding
IW[7:4] = src1
IW[3:0] = src0
Mnemonic Operation Code Functionality
size = (size == 0) ? 16 : size;
data0 = GetSourceBlock (src0, size);
BLOCK_CMP 0x43
data1 = GetSourceBlock (src1, size);
RESULT.DATA |= (data0[size*8-1:0] != data1[size*8-1:0]);

Table 12-13. BLOCK_GCM Instruction

Instruction Format BLOCK_GCM (when GCM parameter is '1')
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a GCM multiplication:
■ {block2, block1} = XMUL (block1, block3)

BLOCK_GCM 0x43 ■ block1 = GCM_Reduce ({block2, block1})

The instruction uses three specific 128-bit blocks. The XMUL operation is
part of the BLOCK_GCM instruction and is a carry-less multiplication. The
reduction is specific for the GCM cipher mode.

GetBlock is defined as follows:

GetBlock (src, size) {
switch (src) {
0: return block0[127:0];
1: return block1[127:0];
2: return block2[127:0];

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3: return block3[127:0];
4: return block4[127:0];
5: return block5[127:0];
6: return block6[127:0];
7: return block7[127:0];
default: return GetFifoData (src, size);
}
}

SetBlock is defined as follows:

SetBlock (dst, size, data) {
switch (dst) {
0: block0[127:0] = data;
1: block1[127:0] = data;
2: block2[127:0] = data;
3: block3[127:0] = data;
4: block4[127:0] = data;
5: block5[127:0] = data;
6: block6[127:0] = data;
7: block7[127:0] = data;
default: SetFifoData (dst, size, data);
}
}
The GetFifoData function is defined as loading “size” bytes from a load FIFO. Up to 16 bytes can be loaded as data[127:0].
The first (top) loaded FIFO entry is mapped on data[7:0], the second loaded FIFO entry is mapped on data[15:8], and so on.
The SetFifoData function is defined as storing size bytes from a load FIFO. Up to 16 bytes can be stored as data[127:0]. The
first stored FIFO entry is mapped on data[7:0], the second stored FIFO entry is mapped on data[15:8], and so on.

12.4 Hash Algorithms

12.4.1 SHA1 and SHA2
The SHA1 and SHA2 functionality includes three hash instructions per the SHA standard (FIPS 180-4).
■ The SHA1 instruction provides all SHA1 functionality (SHA1 always uses 512-bit blocks).
■ The SHA2_256 instruction provides SHA2 functionality for 512-bit blocks.
■ The SHA2_512 instruction provides SHA2 functionality for 1024-bit blocks.
The instructions support different block sizes and hash sizes:

Instruction Block Size Hash Size

SHA1 512 bits 160 bits
SHA2_256 512 bits 256 bits
SHA2_512 1024 bits 512 bits

The SHA1 instruction supports a single algorithm with a specific message digest size. The SHA2_256 and SHA2_512
instructions support multiple algorithms with different message digest sizes.

Instruction Algorithm Hash Size Message Digest Size

SHA1 SHA-1 160 bits 160 bits
SHA-224 256 bits 224 bits
SHA2_256
SHA-256 256 bits 256 bits

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Instruction Algorithm Hash Size Message Digest Size

SHA-384 512 bits 384 bits
SHA-512 512 bits 512 bits
SHA2_512
SHA-512/224 512 bits 224 bits
SHA-512/256 512 bits 256 bits

A SHA algorithm calculates a fixed-length hash value from a variable length message. The hash value is used to produce a
message digest or signature. It is computationally impossible to change the message without changing the hash value. The
algorithm is stateless: a given message always produces the same hash value. To prevent “replay attacks”, a counter may be
included in the message.
The variable length message must be preprocessed: a ‘1’ bit must be appended to the message followed by ‘0’s and a bit size
field. The preprocessed message consists of an integer multiple of 512 bit or 1024 bit blocks. The SHA component processes
a single block at a time:
■ The first SHA instruction on the first message block uses an initial hash value as defined by the standard (each SHA
algorithm has a specific initial hash value).
■ Subsequent SHA instructions on successive message blocks use the produced hash value of the previous SHA
operation.
The SHA instruction of the last message block produces the final hash value. The message digest is a subset of this final
hash value.
The SHA instructions do not perform the following functionality:
■ Preprocessing of a message.
■ Initialization of the register buffer with the algorithm’s specific initial hash value.
■ Copy the algorithm’s message digest to memory.
Software is required to preprocess the message. The FIFO_START instruction can be used to load (load FIFO) the register
buffer with the initial hash value and to store (store FIFO) the message digest.
A SHA instruction uses “round weights” that are derived from the message block. Each SHA round uses a dedicated round
weight. The “round weights” are derived on-the-fly (a new round weight is calculated when needed, and replaces a round
weight from a previous round). The following table provides the number of rounds.

Instruction Rounds
SHA1 80
SHA2_256 64
SHA2_512 80

The instructions use register buffer operands. Specifically, the instructions use reg_buff[2047:0]:
■ reg_buff[1023:0] is used for the round weights. Before an instruction, this region is written with the message block. The
SHA1 and SHA2_256 instructions use reg_buff[511:0] and the SHA2_512 instruction uses reg_buff[1023:0].
■ reg_buff[1535:1024] is used for the hash value. Before the first SHA instruction, this region is written with the algorithm’s
initial hash value. The algorithms with hash values smaller than 512 bits only use the lower bits of this region.
■ reg_buff[2047:1536] is used as a working copy of the hash value. This working copy is updated during the SHA rounds
and copied to reg_buff[1535:1024] at the end of the instruction.

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The instructions are described in the following tables.

Table 12-14. SHA1 Instruction

Instruction Format SHA1 ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a SHA1 function on a 512-bit message block in reg_buff[511:0] with
the current 160-bit hash value in reg_buff[1183:1024]. The resulting hash
SHA1 0x69
value is provided in reg_buff[1183:1024]. At the end of the instruction,
reg_buff[1023:0] is set to ‘0’.

Table 12-15. SHA2_256 Instruction

Instruction Format SHA2_256 ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a SHA2 function on a 512-bit message block in reg_buff[511:0] with
the current 256-bit hash value in reg_buff[1279:1024]. The resulting hash
SHA2_256 0x6a
value is provided in reg_buff[1279:1024]. At the end of the instruction,
reg_buff[1023:0] is set to ‘0’.

Table 12-16. SHA2_512 Instruction

Instruction Format SHA2_512 ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a SHA2 function on a 1024-bit message block in reg_buff[1023:0]
with the current 512-bit hash value in reg_buff[1535:1024]. The resulting hash
SHA2_512 0x6b
value is provided in reg_buff[1535:1024]. At the end of the instruction,
reg_buff[1023:0] is set to ‘0’.

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12.4.2 SHA3
The Secure Hash Algorithm-3 (SHA-3) is a family of six algorithms:
■ SHA3-224
■ SHA3-256
■ SHA3-384
■ SHA3-512
■ SHAKE128
■ SHAKE256
Each of these algorithms relies on a specific instance of the Keccak-p[b, nr] permutation, with b = 1600 and nr = 24. The
parameter b specifies the permutation bit width (1600 bits) and the parameter nr specifies the number of permutation rounds
(24 rounds).
The permutation bit width b is the sum of:
■ The rate r, which is the number of consumed message bits or produced digest bits per application of the Keccak
permutation (SHA3 instruction).
■ The capacity c, which is defined as b-r.
All six hash algorithms are constructed by padding a message M and applying the Keccak-p[1600, 24] permutation
repeatedly. The algorithms differ in terms of the rate r and the padding.
The permutation’s rate r determines the speed of the algorithm: a higher rate requires less applications of the permutation
function (SHA3 instruction).
The permutation’s capacity c determines the security of the algorithm: a higher capacity provides higher security.
Table 12-17 lists the algorithms’ rate and capacity. In addition, it lists the size of the message digest. Note: The SHA3 hash
algorithms have fixed-length digests and the SHAKE extendable output functions have variable-length digests.

Table 12-17. Algorithm Rate and Capacity

Algorithm Rate, Capacity Digest Length
SHA3-224 r = 1152 b, c = 448 b 224 b (28 B)
SHA3-256 r = 1088 b, c = 512 b 256 b (32 B)
SHA3-384 r = 832 b, c = 768 b 384 b (48 B)
SHA3-512 r = 576 b, c = 1024 b 512 b (64 B)
SHAKE128 r = 1344 b, c = 256 b Variable length
SHAKE256 r = 1088 b, c = 512 b Variable length

The padded message has a length that is an integer multiple of the rate r. The message is processed by repeatedly applying
the SHA3 permutation instruction. Each instruction application uses a message block of r bits. The permutation function
combines the message block of r bits with the current permutation state of b bits and calculates a new permutation state of b
bits.
■ The first SHA3 instruction on the first message block uses the first message block as the initial permutation state.
■ Subsequent SHA3 instructions on successive message blocks first combine the message block with an exclusive or
(XOR) with the current state and calculate a new permutation state.
The message digest is produced in a similar way as the message is consumed: each application of the permutation
instruction produces a message digest of r bits.
The SHA3 functionality includes a SHA3 instruction. The instruction performs a permutation on the 1600-bit state in
reg_buf[1599:0].
The instruction implements the permutation, all other functionality is implemented in software (combination of message block
with the permutation state and copying the message digest to memory).

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Table 12-18 describes the instruction.

Table 12-18. SHA3 Instruction

Instruction Format SHA3 ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a SHA3 permutation on a 1600-bit state reg_buff[1599:0]. The result-
SHA3 0x6c
ing state is provided in reg_buff[1599:0].

12.5 DES and TDES

The (T)DES functionality includes block ciphers and inverse block ciphers according to the DES and triple DES standard
(FIPS 46-3). Note that this standard was withdrawn, because it no longer provides the security that is needed to protect
federal government information.
(T)DES is supported for backward compatibility.
■ The DES block cipher encrypts a 64-bit block of plaintext data into a 64-bit block of ciphertext data.
■ The DES inverse block cipher decrypts a 64-bit block of ciphertext data into a 64-bit block of plaintext data.
The DES symmetric key consists of 64 bit. Only 56 bits are used by the algorithm, the other 8 bits are used for parity
checking.
Tripple-DES applies the DES block cipher three times. Each application uses a different key, which results in a 192-bit TDES
key bundle consisting of three 64-bit keys SK1, SK2 and SK3.
■ The TDES block cipher uses the DES block cipher with key SK1 to encrypt a 64-bit plaintext into a 64-bit block T1. Next, it
uses the DES inverse block cipher with key SK2 to decrypt the 64-bit block T1 into a 64-bit block T2. Next, it uses the DES
block cipher with key SK3 to encrypt the 64-bit block T2 into a 64-bit ciphertext.
■ The TDES inverse block cipher uses the DES inverse block cipher with key SK3 to decrypt a 64-bit ciphertext into a 64-bit
block T2. Next, it uses the DES block cipher with key SK2 to encrypt the 64-bit block T2 into a 64-bit block T1. Next, it
uses the DES inverse block cipher with key SK1 to decrypt the 64-bit block T1 into a 64-bit plaintext.
There are four instructions: DES, DES_INV, TDES and TDES_INV, which use register buffer operands. Specifically, the
instructions use the 128-bit subpartitions block0, block1, block4, block5, block6, and block7.
■ Subpartitions block0 and block1 are used for plaintext and ciphertext data.
■ Subpartitions block4, block5, block6, and block7 are used for key information (block5 and block7 are only used by the
TDES and TDES_INV instructions).
Unlike the BLOCK_MOV instruction, the (T)DES instructions use predetermined/fixed subpartitions.
The instructions are described in the following tables.

Table 12-19. DES Instruction

Instruction Format DES ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a DES block cipher.
■ The 64-bit plaintext is in block0[63:0].
■ The resulting 64-bit ciphertext is in block1[63:0].

DES 0x52 ■ The 64-bit input key is in block4[63:0].

■ The 64-bit output key (round key of the final cipher round) is in
block6[63:0].
The instruction is non-destructive: block0 and block4 are not changed by the
instruction.

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Table 12-20. DES_INV Instruction

Instruction Format DES_INV ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a DES inverse block cipher.
■ The 64-bit ciphertext is in block0[63:0].
■ The resulting 64-bit plaintext is in block1[63:0].

DES_INV 0x53 ■ The 64-bit input key is in block4[63:0].

■ The 64-bit output key (round key of the final inverse cipher round) is in
block6[63:0].
The instruction is non-destructive: block0 and block4 are not changed by the
instruction.

Table 12-21. TDES Instruction

Instruction Format TDES ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a TDES block cipher.
■ The 64-bit plaintext is in block0[63:0].
■ The resulting 64-bit ciphertext is in block1[63:0].
■ The 192-bit input key is in {block5[63:0], block4[127:0]} (= {SK3[63:0],
TDES 0x54 SK2[63:0], SK1[63:0]}).
■ The 192-bit output key (round key of the final cipher round) is in
{block7[63:0], block6[127:0]}.
The instruction is non-destructive: block0, block4 and block5 are not changed
by the instruction.

Table 12-22. TDES_INV Instruction

Instruction Format TDES_INV ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform a TDES inverse block cipher.
■ The 64-bit ciphertext is in block0[63:0].
■ The resulting 64-bit plaintext is in block1[63:0].
■ The 192-bit input key is in {block5[63:0], block4[127:0]} (= {SK3[63:0],
TDES_INV 0x55 SK2[63:0], SK1[63:0]}).
■ The 192-bit output key (round key of the final cipher round) is in
{block7[63:0], block6[127:0]}.
The instruction is non-destructive: block0, block4 and block5 are not changed
by the instruction.

The (T)DES instructions are used with the FF_START, FF_CONTINUE, FF_STOP, BLOCK_MOV, BLOCK_XOR, and
BLOCK_SET instructions to implement different block cipher modes, such as EBC, CBC, OFB, CTR, and CMAC.

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12.6 AES
The AES functionality includes a block cipher and an inverse block cipher per the AES standard (FIPS 197):
■ The block cipher (AES instruction) encrypts a 128-bit block of plaintext data into a 128-bit block of ciphertext data.
■ The inverse block cipher (AES_INV instruction) decrypts a 128-bit block of ciphertext data into a 128-bit block of plaintext
data.
AES is a symmetric block cipher: it uses the same symmetric key for the block cipher and inverse block cipher. The (inverse)
block cipher consists of multiple rounds. Each round uses a round key that is generated from the symmetric key.
The block cipher uses the symmetric key as the (start) round key for the first cipher round. The round key for second cipher
round is generated from the symmetric key. The round key for the third cipher round is generated from the round key of the
second cipher round, and so forth. The round key for the last cipher round is generated from the round key of the one-before-
last cipher round.
The inverse block cipher uses the round key of the final block cipher round as the (start) round key for the first inverse cipher
round. The round key for the second inverse cipher round is generated from the round key of the first inverse cipher round,
and so forth. The round key for the last inverse cipher round is generated from the round key of the one-before-last inverse
cipher round. The round key of the last inverse cipher round is the same as the round key of the first cipher round (the
symmetric key).
Round key generation is independent of the plaintext data or ciphertext data. The AES instruction requires the symmetric key
as input to the block cipher. The AES_INV instruction requires the round key of the final cipher round as input to the inverse
block cipher.
The component supports 128 bit, 192 bit, and 256 bit keys. The key size is specified by AES_CTL.KEY_SIZE[1:0]. The key
size determines the number of rounds. Table 12-23 gives the number of rounds.

Table 12-23. AES Cipher Rounds

AES Key Size Rounds
AES128 10 rounds
AES192 12 rounds
AES256 14 rounds

AES and AES_INV are the two different AES instructions; they use register buffer operands. Specifically, the instructions use
the 128-bit subpartitions block0, block1, block4, block5, block6, and block7.
■ Subpartitions block0 and block1 are used for plaintext and ciphertext data.
■ Subpartitions block4, block5, block6 and block7 are used for key information.
Unlike, for example, the BLOCK_MOV instruction, the AES and AES_INV instructions use predetermined/fixed subpartitions.

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The instructions are described in the following tables.

Table 12-24. AES Instruction

Instruction Format AES ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform an AES block cipher.
■ The 128-bit plaintext is in block0.
■ The resulting 128-bit ciphertext is in block1.
■ The input key is in block4 and block5. For a 128-bit key, the key is in
block4[127:0]. For a 192-bit key, the key is in {block5[63:0],
block4[127:0]}. For a 256-bit key, the key is in {block5[127:0],
block4[127:0]}.
AES 0x50 ■ The output key (round key of the final cipher round) is in block6 and
block7. For a 128-bit key, the key is in block6[127:0]. For a 192-bit key, the
key is in {block7[63:0], block6[127:0]}. For a 256-bit key, the key is in
{block7[127:0], block6[127:0]}. Note that the output key is the input key for
an AES inverse block cipher.
The instruction is non-destructive: block0, block4, and block5 are not changed
by the instruction.
Note that the AES instruction can be used to derive the AES_INV input key
from the symmetric key.

Table 12-25. AES_INV Instruction

Instruction Format AES_INV ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform an AES block cipher.
■ The 128-bit ciphertext is in block0.
■ The resulting 128-bit plaintext is in block1.
■ The input key is in block4 and block5. For a 128-bit key, the key is in
block4[127:0]. For a 192-bit key, the key is in {block5[63:0], block4[127:0]}.
For a 256-bit key, the key is in {block5[127:0], block4[127:0]}.
AES_INV 0x51
■ The output key (round key of the final inverse cipher round) is in block6
and block7. For a 128-bit key, the key is in block6[127:0]. For a 192-bit
key, the key is in {block7[63:0], block6[127:0]}. For a 256-bit key, the key is
in {block7[127:0], block6[127:0]}. Note that the output key is the input key
for an AES block cipher.
The instruction is non-destructive: block0, block4 and block5 are not changed
by the instruction.

The AES and AES_INV instructions are used with the FF_START, FF_CONTINUE, FF_STOP, BLOCK_MOV, BLOCK_XOR,
and BLOCK_SET instructions to implement different block cipher modes, such as EBC, CBC, OFB, CTR, and CMAC.

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12.7 CRC
The CRC functionality performs a cyclic redundancy check with a programmable polynomial of up to 32 bits.
The load FIFO 0 provides the data (and the size of the data) on which the CRC is performed. The data must be laid out in little
endian format (least significant byte of a multi-byte word should be located at the lowest memory address of the word).
CRC_DATA_CTL.DATA_XOR[7:0] specifies a byte pattern with which each data byte is XOR’d. This allows for inversion of
the data byte value.
CRC_CTL.DATA_REVERSE allows for bit reversal of the data byte (this provides support for serial interfaces that transfer
bytes in most-significant-bit first and least-significant bit first configurations).
CRC_POL_CTL.POLYNOMIAL[31:0] specifies the polynomial. The polynomial specification omits the high order bit and
should be left aligned. For example, popular 32-bit and 16-bit CRC polynomials are specified as follows:

CRC32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1

CRC_POL_CTL.POLYNOMIAL[31:0] = 0x04c11db7

CRC16-CCITT: x16 + x12 + x5 + 1

CRC_POL_CTL.POLYNOMIAL[31:0] = (0x1021 << 16)

CRC16: x16 + x15 + x2 + 1

CRC_POL_CTL.POLYNOMIAL[31:0] = (0x8005 << 16)
RESULT.DATA[31:0] holds the LFSR state of the CRC calculation. Before the CRC operation, this field should be initialized
with the CRC seed value.
CRC_REM_CTL.REM_XOR[31:0] specifies a 32-bit pattern with which the RESULT.DATA[31:0] LFSR state is XOR’d.
CRC_CTL.REM_REVERSE allows for bit reversal of the XOR’d state.
CRC_REM_RESULT.REM[31:0] holds the result of the CRC calculation, and is derived from the end state of the CRC
calculation (RESULT.DATA[31:0]).
The CRC instruction is described in Table 12-26.

Table 12-26. CRC Instruction

Instruction Format CRC ()
Encoding IW[31:24] = “operation code”
Mnemonic Operation Code Functionality
Perform the CRC function on all data in load FIFO 0. The result of the CRC
function is provided through CRC_REM_RESULT.REM[31:0].
If the data is scattered in memory, a single FF_START and multiple FF_CON-
CRC 0x58 TINUE instructions should be used to gather the data in a load FIFO 0 Byte
stream. Each FF_START and FF_CONTINUE instruction should be followed
by a CRC instruction, which processes all the bytes of the associated FIFO
instruction (the CRC instruction does not have a “size” operand).

Figure 12-2 illustrates the CRC functionality.

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 Cryptographic Function Block (Crypto)

Figure 12-2. CRC Functionality

Load FIFO 0

Single Byte

CRC_DATA_CTL.DATA_XOR[]

CRC_CTL.DATA_REVERSE

Data bit
reverse

CRC_POL_CTL.POLYNOMIAL[]

CRC
calculation
RESULT.DATA[]
(LFSR state)

CRC_REM_CTL.DATA_XOR[]

CRC_CTL.REM_REVERSE

Remainder bit
reverse

CRC_REM_RESULT.REM[]

The Linear Feedback Shift Register functionality operates on the LFSR state. It uses the programmed polynomial and
consumes a data bit for each iteration (eight iterations are performed per cycle to provide a throughput of one data byte per
cycle). Figure 12-3 illustrates the functionality for the CRC32 polynomial (x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7
+ x5 + x4 + x2 + x + 1).
Figure 12-3. CRC32 Functionality

CRC32 (x32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1) data bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LFSR0
Q D
bit

clk

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 Cryptographic Function Block (Crypto)

Different CRC algorithms require different seed values and have different requirements for XOR functionality and bit reversal.
Table 12-27 provides the proper settings for the CRC32, CRC16-CCITT, and CRC16 algorithms. The table also provides the
remainder after the algorithms are performed on a five-byte array {0x12, 0x34, 0x56, 0x78, 0x9a}.

Table 12-27. CRC32, CRC16-CCITT, and CRC16 Algorithm Settings

MMIO Register Field CRC32 CRC16-CCITT CRC16
CRC_POL_CTL.POLYNOMIAL 0x04c11db7 0x10210000 0x80050000
CRC_CTL.DATA_REVERSE 1 0 1
CRC_DATA_CTL.DATA_XOR 0x00 0x00 0x00
RESULT.DATA (seed) 0xffffffff 0xffff0000 0xffff0000
CRC_CTL.REM_REVERSE 1 0 1
CRC_REM_CTL.REM_XOR 0xffffffff 0x00000000 0x00000000
CRC_REM_RESULT.REM 0x3c4687af 0xf8a00000 0x000048d0

12.8 PRNG
The pseudo random number generation (PRNG) component generates pseudo random numbers in a fixed range [0,
PR_MAX_CTL.DATA[31:0]]. The generator is based on three Fibonacci-based Linear Feedback Shift Registers (LFSRs). The
following three irreducible polynomials (with minimum feedback) are used:
■ 32-bit polynomial: x32 + x30 + x26 + x25 + 1
■ 31-bit polynomial: x31 + x28 + 1
■ 29-bit polynomial: x29 + x27 + 1
Figure 12-4 illustrates the LFSR functionality.
Figure 12-4. Fixed Fibonacci-based LFSRs
32-bit irreducible polynomial: x 32 + x 30 + x 26 + x 25 + 1 (32 bit LFSR[31:0])

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D Q
LFSR32
output
clk

31-bit irreducible polynomial: x 31 + x 28 + 1 (31 bit LFSR[30:0])

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D Q
LFSR31
output
clk

29-bit irreducible polynomial: x 29 + x 27 + 1 (29 bit LFSR[28:0])

28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

D Q
LFSR29
output
clk

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 Cryptographic Function Block (Crypto)

Software initializes the LFSRs with non-zero seed values. The PR_LFSR_CTL0, PR_LFSR_CTL1 and PR_LFSR_CTL2
registers are provided for this purpose. At any time, the state of these registers can be read to retrieve the state of the LFSRs.
The 32-bit LFSR generates a repeating bit sequence of 232 – 1 bits, the 31-bit LFSR generates a repeating bit sequence of
231 – 1 and the 29-bit LFSR generates a repeating bit sequence of 229 – 1. As the
numbers 232-1, 231-1, and 229-1 are relatively prime, the XOR output is a repeating bit sequence of roughly 232+31+29.
The final pseudo random bit is the XOR of the three bits that are generated by the individual LFSRs.
Figure 12-5. XOR Reduction Logic

LFSR32 output
LFSR31 output pseudo random bit
LFSR29 output

The pseudo random number generator uses a total of 33 pseudo random bits to generate a result in the range [0,
PR_MAX_CTL.DATA[31:0]].
To generate a pseudo random number result, the following calculation is performed.
MAX[31:0] = PR_MAX_CTL.DATA[31:0]
MAX_PLUS1[32:0] = MAX[31:0] + 1;
product[63:0] = MAX_PLUS1[32:0] * pr[32:1] + MAX[31:0] * pr[0];
result = product[63:32];
PR_CMD.START is the PR command. The maximum value of the generated random number (in PR_RESULT.DATA) is
specified by PR_MAX_CTL.DATA. The PR command can be executed in parallel with the instruction FIFO instructions and
the TR command.

12.9 TRNG
The true random number generator component (TRNG) generates true random numbers. The bit size of these generated
numbers is programmable (TR_CTL.SIZE is in the range [0,32]).
The TRNG relies on up to six ring oscillators to provide physical noise sources. A ring oscillator consists of a series of
inverters connected in a feedback loop to form a ring. Due to (temperature) sensitivity of the inverter delays, jitter is
introduced on a ring's oscillating signal. The jittered oscillating signal is sampled to produce a “digitized analog signal” (DAS).
This is done for all multiple ring oscillators.
To increase entropy and to reduce bias in DAS bits, the DAS bits are further postprocessed. Post-processing involves two
steps:
■ An optional reduction step (over up to six ring oscillator DAS bits and over one or multiple DAS bit periods) to increase
entropy.
■ An optional “von Neumann correction” step to reduce a ‘0’ or ‘1’ bias.
This correction step processes pairs of reduction bits as produced by the previous step. Given two reduced bits r0 and r1
(with r0 being produced before r1), the correction step is defined as follows:
❐ {r0, r1} = {0, 0}: no bit is produced
❐ {r0, r1} = {0, 1}: a ‘0’ bit is produced (bit r0)
❐ {r0, r1} = {1, 0}: a ‘1’ bit is produced (bit r0)
❐ {r0, r1} = {1, 1}: no bit is produced
In other words the correction step only produces a bit on a ‘0’ to ‘1’ or ‘1’ to ‘0’ transition. Note that for a random input bit
sequence, the correction step produces an output bit sequence of roughly one-quarter the frequency of the input bit sequence
(the input reduction bits are processed in non-overlapping pairs and only half of the pair encodings result in an output bit).
Post-processing produces bit samples that are considered true random bit samples. The true random bit samples are shifted
into a register, to provide random values of up to 32 bits.

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 Cryptographic Function Block (Crypto)

As a result of high-switching activity, ring oscillators consume a significant amount of power. Therefore, when the TRNG
functionality is disabled, the ring is “broken” to prevent switching. When the TRNG functionality is enabled, a ring oscillator
initially has predictable behavior. However, over time, infinitesimal environmental (temperature) changes cause an increasing
deviation from this predictable behavior.
■ During the initial delay, the ring oscillator is not a reliable physical noise source.
■ After an initial delay, the same ring oscillator will show different oscillation behavior and provides a reliable physical noise
source.
Therefore, the DAS bits can be dropped during an initialization period (TR_CTL.INIT_DELAY[]).
Figure 12-6 gives an overview of the TRNG component.
Figure 12-6. TRNG Overview
SAMPLE_CLOCK_DIV[]
digitized Post-processing
oscillating signal analog
samples (DAS)
RO11_EN RO11 Sampler
INIT_DELAY[] RED_CLOCK_DIV[] TR_RESULT.DATA[31:0]

RO15_EN RO15 Sampler true

0 31
random
von bit
Neumann
GARO15_EN GARO15 Sampler corrector
shift register
GARO31_EN
GARO31 Sampler
POLYNOMIAL[30:0] VON_NEUMANN_CORR

FIRO15_EN FIRO15 Sampler

FIRO31_EN
FIRO31 Sampler
POLYNOMIAL[30:0]

INTR.TR_INITIALIZED INTR.TR_DATA_AVAILABLE

The “Sampler” logic digitizes an oscillating signal. Figure 12-7 illustrates the functionality (the complete logic is implemented
using standard platform toolkit components).
Figure 12-7. Sampler Logic

Sampler
clock_sample_en
(derived from SAMPLE_CLOCK_DIV[]) mxtk_clk_gate
clk_sys clk_sampler
test_icg_control

“oscillating signal” mxtk_2dff_sync “digitized analog sample”

START mxtk_rst_and
rst_sys_act_n rst_sampler_n
test_reset_control

Note that when a ring oscillator is disabled, the synchronization logic is reset. Therefore, the ring oscillator contributes a
constant ‘0’ to the reduction step of the post-processing. As mentioned, the TRNG relies on up to six ring oscillators:
■ RO11: A fixed ring oscillator consisting of 11 inverters.
■ RO15: A fixed ring oscillator consisting of 15 inverters.
■ GARO15: A fixed Galois based ring oscillator of 15 inverters.
■ GARO31: A flexible Galois based ring oscillator of up to 31 inverters. A programmable polynomial of up to order 31
provides the flexibility in the oscillator feedback.
■ FIRO15: A fixed Fibonacci based ring oscillator of 15 inverters.
■ FIRO31: A flexible Fibonacci based ring oscillator of up to 31 inverters. A programmable polynomial of up to order 31
provides the flexibility in the oscillator feedback.

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 Cryptographic Function Block (Crypto)

Each ring oscillator can be enabled or disabled. When disabled, the ring is “broken” to prevent switching. The following
Figures illustrate the schematics of the fixed ring oscillators.
Figure 12-8. Four Fixed Ring Oscillators: RO11, RO15, GARO15, FIRO15
RO11: oscillator with 11 inverters

10 9 8 7 6 5 4 3 2 1 0

RO11_EN output

RO15: oscillator with 15 inverters

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RO15_EN output

GARO15: fixed polynomial: x15 + x 14 + x 7 + x 6 + x 5 + x 4 + x 2 + 1

GARO15_EN

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

output

FIRO15: fixed polynomial: x15 + x 14 + x 7 + x 6 + x 5 + x 4 + x 2 + 1

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

FIRO15_EN output

The XXX_EN enable signals originate from a MMIO register field.

The flexible Galois- and Fibonacci-based ring oscillators rely on programmable polynomials to specify the oscillator feedback.
This allows for rings of 1, 3, 5, …, 31 inverters (an odd number is required to generate an oscillating signal). Figure 12-9 gives
an overview of the Galois-based ring oscillator.
Figure 12-9. Flexible Galois-based Ring Oscillators: GARO31
POLYNOMIAL[30]

POLYNOMIAL[29]

POLYNOMIAL[28]

POLYNOMIAL[27]

POLYNOMIAL[26]

POLYNOMIAL[25]

POLYNOMIAL[24]

POLYNOMIAL[23]

POLYNOMIAL[22]

POLYNOMIAL[10]

POLYNOMIAL[0]
POLYNOMIAL[9]

POLYNOMIAL[8]

POLYNOMIAL[7]

POLYNOMIAL[6]

POLYNOMIAL[5]

POLYNOMIAL[4]

POLYNOMIAL[3]

POLYNOMIAL[2]

POLYNOMIAL[1]

30 29 28 27 26 25 24 23 22 21 10 9 8 7 6 5 4 3 2 1 0

output

When the ring oscillator is disabled (GARO31_EN is ‘0’), the polynomial is forced to “0” and the ring is broken as illustrated by
Figure 12-10.

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 Cryptographic Function Block (Crypto)

Figure 12-10. GARO31 “stopped”

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’
30 29 28 27 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0

output

Constant ‘1’

30 29 28 27 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0
‘0’
output

The programmable polynomial specifies the oscillator feedback. Figure 12-11 illustrates two examples.
Figure 12-11. GARO31 – Two Examples
7-bit polynomial: x7 + x 6 + 1 (POLYNOMIAL = 0x0000:0041 << 24)

Constant ‘0’

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 4 2 1 0
‘0’
output

31 bit polynomial: x31 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 (POLYNOMIAL = 0x04c1:1db7)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

output

Figure 12-12 gives an overview of the Fibonacci-based ring oscillator.

Figure 12-12. Flexible Fibonacci-based Ring Oscillators: FIRO31

30 29 28 27 26 25 24 23 22 21 10 9 8 7 6 5 4 3 2 1 0

output
POLYNOMIAL[30]

POLYNOMIAL[29]

POLYNOMIAL[28]

POLYNOMIAL[27]

POLYNOMIAL[26]

POLYNOMIAL[25]

POLYNOMIAL[24]

POLYNOMIAL[23]

POLYNOMIAL[22]

POLYNOMIAL[21]

POLYNOMIAL[10]

POLYNOMIAL[9]

POLYNOMIAL[8]

POLYNOMIAL[7]

POLYNOMIAL[6]

POLYNOMIAL[5]

POLYNOMIAL[4]

POLYNOMIAL[3]

POLYNOMIAL[2]

POLYNOMIAL[1]

POLYNOMIAL[0]

When the ring oscillator is disabled (FIRO31_EN is ‘0’), the polynomial is forced to “0” and the ring is broken as illustrated by
Figure 12-13.

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 Cryptographic Function Block (Crypto)

Figure 12-13. FIRO31 “stopped”

30 29 28 27 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0
‘0’
output

Constant ‘1’

30 29 28 27 26 25 24 23 22 21 20 10 9 8 7 6 5 4 3 2 1 0

output
‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’

‘0’
The programmable polynomial specifies the oscillator feedback. Figure 12-14 illustrates two examples.
Figure 12-14. FIRO31 – Two Examples
7-bit polynomial: x7 + x 6 + 1 (POLYNOMIAL = 0x0000:0041 << 24)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

output

31 bit polynomial: x31 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x + 1 (POLYNOMIAL = 0x04c1:1db7)

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

output

There is one TR command, TR_CMD.START, which can be executed in parallel with the instruction FIFO instructions and the
PR command. The size of the generated random number (in TR_RESULT.DATA) is specified by TR_CTL.SIZE.
The TRNG has a built-in health monitor that performs tests on the digitized noise source to detect deviations from the
intended behavior. For example, the health monitor detects “stuck at” faults in the digitized analog samples. The health
monitor tests one out of three selected digitized bit streams:
■ DAS bitstream. This is XOR of the digitized analog samples.
■ RED bitstream. This is the bitstream of reduction bits. Note that each reduction bit may be calculated over multiple DAS
bits.
■ TR bitstream. This is the bitstream of true random bits (after the “von Neumann reduction” step).
The health monitor performs two different tests:
The repetition count test. This test checks for the repetition of the same bit value (‘0’ or ‘1’) in a bitstream. A detection
indicates that a specific active bit value (specified by a status field BIT) has repeated for a pre-programmed number of bits
(specified by a control field CUTOFF_COUNT[7:0]). The test uses a counter to maintain the number of repetitions of the
active bit value (specified by a status field REP_COUNT[7:0]).
If the test is started (specified by START_RC field) and a change in the bitstream value is observed, the active bit value BIT is
set to the new bit value and the repetition counter REP_COUNT[] is set to ‘1’. If the bitstream value is unchanged, the
repetition counter REP_COUNT[] is incremented by “1”.
A detection stops the repetition count test (the START_RC field is set to ‘0’), sets the associated interrupt status field to ‘1’ and
ensures that hardware does not modify the status fields. When the test is stopped, REP_COUNT[] equals
CUTOFF_COUNT[].
A detection stops the TRNG functionality (all TR_CTL.XXX_EN fields are set to ‘0’) if TR_CTL.STOP_ON_RC_DETECT is
set to ‘1’.
The adaptive proportion test. This test checks for a disproportionate occurrence of a specific bit value (‘0’ or ‘1’) in a bit
stream. A detection indicates that a specific active bit value (specified by a status field BIT) has occurred a pre-programmed
number of times (specified by a control field CUTOFF_COUNT[15:0]) in a bit sequence of a specific bit window size (specified
by a control field WINDOW_SIZE[15:0]). The test uses a counter to maintain an index in the current window (specified by

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 Cryptographic Function Block (Crypto)

WINDOW_INDEX[15:0]) and a counter to maintain the number of occurrences of the active bit value (specified by a status
field OCC_COUNT[15:0]).
If the test is started (specified by START_AP field), the bitstream is partitioned in bit sequences of a specific window size. At
the first bit of a bit sequence, the active bit value BIT is set to the first bit value, the counter WINDOW_INDEX is set to “0” and
the counter OCC_COUNT is set to “1”. For all other bits of a bit sequence, the counter WINDOW_INDEX is incremented by
“1”. If the new bit value equals the active bit value BIT, the counter OCC_COUNT[15:0] is incremented by “1”. Note that the
active bit value BIT is only set at the first bit of a bit sequence.
A detection stops adaptive proportion test (the START_AP field is set to ‘0’), sets the associated interrupt status field to ‘1’ and
ensures that hardware does not modify the status fields. When the test is stopped, OCC_COUNT[] equals
CUTOFF_COUNT[] and the WINDOW_INDEX identifies the bit sequence index on which the detection occurred.
A detection stops the TRNG functionality (all TR_CTL.XXX_EN fields are set to ‘0’) if TR_CTL.STOP_ON_AP_DETECT is set
to ‘1’.
Figure 12-15 illustrates the health monitor functionality.
Figure 12-15. Health Monitor Functionality
Post-processing
digitized
analog INIT_DELAY[] RED_CLOCK_DIV[]
samples (DAS)
true
random
von bit
Neumann
corrector

Health monitor
DAS_SEL RED_SEL TR_SEL
BITSTREAM_SEL[]

Adaptive proportion
START_RC Repetition count test START_AP
test

CUTOFF_COUNT[] CUTOFF_COUNT[]
WINDOW_SIZE[]
BIT BIT
REP_COUNT[] OCC_COUNT[]
INTR.TR_RC_DETECT WINDOW_INDEX[]
INTR.TR_AP_DETECT

Implementation note. The ring oscillators have special design requirements. They are not synthesized logic, but manually
constructed from selected cells from the standard cell library. Three types of standard cells are required:
■ An inverter cell. The selected cell should have similar rise and fall time requirements. Clock tree inverter cells tend to have
this property and are the preferred implementation of the inverter cell.
■ A two-input XOR cell.
■ A two-input AND cell.
The design uses three Verilog design modules to instantiate the selected cells. This allows easy porting from one standard
cell library to another standard cell library. The three Verilog design modules should not be changed by tools (similar to how
the platform toolkit components are treated in the design flow).
A ring oscillator should be placed and routed in a self-contained rectangular area. This area should preferably be as small as
possible.

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 Cryptographic Function Block (Crypto)

12.10 Vector Unit

The vector unit (VU) addresses the requirements of asymmetric key cryptography. Similar to other cryptography functionality,
the VU connects to the memory interface through the load and store FIFOs. The memory buffer or system memory contains
memory operand data for the vector unit instructions.
Figure 12-16. Vector Unit

Instruction FIFO Load FIFO 0 Load FIFO 1 Store FIFO

Vector unit

Register-file

16 registers; each register: 13-bit data field and 13-bit size field

The VU addresses asymmetric key cryptography. Asymmetric key cryptography includes RSA, Diffie-Hellman key exchange,
digital signature authentication, and elliptic curve cryptography (ECC). These algorithms share the requirement to efficiently
perform computations in a Galois field on large integers of up to 1000’s of bits.
The VU performs instructions on operand data.
■ The VU instructions are provided by the instruction FIFO.
■ The VU operand data is specified by any of the following (all encoded as part of the 32-bit instruction word):
❐ instruction operation code
❐ instruction register indices
❐ instruction immediate values
The VU uses the VU register file. A VU register is a (data, size) pair: a 13-bit data field (bits 28 down to 16) and a 13-bit size
field (bits 12 down to 0). The data field is either used as:
■ Instruction operand data: the complete 13-bit data is used.
■ An offset into memory: the 13-bit data value is a word offset wrt. a base address into memory.
The size field is only used when the data field is used as an offset into memory. In this case, the size field specifies the bit size
(minus 1) of the memory operand (the 13-bit field specifies a size in the range of [1, 8192] bits).
The VU is a “trimmed down” application domain specific CPU:
■ “Trimmed down”. It does not have a CPU instruction fetch unit that supports non-sequential program flow. This
functionality is typically not required for asymmetric key cryptography functions or needs to be provided by the external
AHB-Lite bus master (typically a CPU). This design decision simplifies the VU.
Note that the instruction FIFO provides the mechanism by which instructions are provided. This mechanism only supports
a sequential VU program flow.
■ Application domain specific. The VU instructions and operand data are tuned for asymmetric key cryptography. For
example, instructions are provided for arithmetic over binary extension fields (GF(2m)) or prime fields (GF(p)), and
memory operands allow for a large operand length of up to 8192 bits (although the VU internal data path is limited to 32
bit).
■ CPU. The VU has CPU-like design components, such as an instruction decoder, a register file, and data path with multiple
functional units.
The VU architecture is the result of a tradeoff between silicon area, design complexity, performance efficiency, and
algorithmic flexibility. Note that most asymmetric key algorithms can be performed by the regular CPU. However, this typically
comes at a lower performance level, possibly large code footprint (due to loop unrolling of code to improve performance when
operating on large operand data), and possibly large data footprint (due to lookup tables to improve performance).

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The improved performance of the VU (over a regular CPU) for asymmetric key algorithms also allows for more generic
algorithmic implementations, as opposed to implementations targeting, such as specific primes or irreducible polynomials.
Before describing the architecture, a short C example is illustrates the VU functionality.
#define SIZE 4096
void Example ()
{
int a = 0; int b = 1; int c = 2; // assign register indices
uint8_t c_data[SIZE/8];
ALLOC_MEM (a, SIZE); // allocate 4096 bits of data
ALLOC_MEM (b, SIZE); // allocate 4096 bits of data
ALLOC_MEM (c, SIZE); // allocate 4096 bits of data
Crypto_WriteMemNumber (a, “0x21542555:fed35532: … :ffea2345”);
Crypto_writeMemNumber (b, “0xef45ac2a:34a312bc: … :000003ab”);
ADD (c, a, b);
Crypto_ReadMemNumber (c, c_data);
}
The example adds two 4096-bit numbers and produces a 4096-bit number. The example is explained as follows:
■ Three local variables are assigned VU register indices:
❐ local variable a uses register 0
❐ local variable b uses register 1
❐ local variable c used register 2
■ Memory is allocated in the memory buffer for each variable: each variable needs 4096 bits.
■ A function “Crypto_WriteMemNumber” is called to initialize the memory operand data for source variables a and b.
■ A VU ADD instruction (long integer addition) is executed.
■ A function “Crypto_WriteMemNumber” is called to read the result of the instruction from the memory.
The example illustrates that the full expressive power of the C language is available when writing software for the VU.
The example illustrates that relatively complex functionality can be expressed in only a few lines of C code (consider
implementing the same functionality on a 32-bit Arm processor).
The “Crypto_” functions copy data to and from the memory. These functions are executed on the regular CPU and may take a
significant number of cycles. Asymmetric key algorithm typically requires little copy functions and a lot of VU instructions. As
a result, the cycle overhead of the copy functions is negligible. As an example, RSA requires exponentiation of a number by a
second number modulo a third number. This RSA functionality requires only four copy functions (three to initialize three
memory operands and one to read the result), but requires thousands of VU instructions.
The following sections provide an architectural overview of the VU.

12.10.1 VU Register File

The register file has sixteen registers (r0 through r15). Each register consists of a 13-bit data field and a 13-bit size field. The
data field is either used as:
■ Instruction operand data: the 13-bit data is used.
■ An offset into memory: the 13-bit data value is a word offset for a base address into memory. Typically, memory operand
data is located in the crypto memory buffer (this provides better latency/performance than memory operand data in
system memory).
The size field is used only when the data field is used as an offset into memory. In this case, the size field specifies the bit size
(minus 1) of the memory operand (the 13-bit field specifies a size in the range of [1, 8192] bits).
The CPU software decides what instructions use what registers. There is no compiler with specific conventions for register
usage or to perform register allocation. To ensure some consistency and interoperability of the functions in a software library,
the software programmer should introduce its own conventions. Some examples of conventions are:
■ Each non-leaf function saves all registers to the stack on function entry and restores all registers from the stack on
function exit. This makes all registers available for use within the function.

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■ Each non-leaf function restricts its register use to registers r4 through r14.
■ Each leaf function either restricts its register use to registers r0 through r3 or follows the same save/restore convention as
non-leaf functions.
The register-file register r15 serves a specific purpose. Similar to the Arm architecture, register r15 is used as a stack pointer.
Figure 12-17 illustrates the register file and how the data fields are used as offsets in a 16 KB memory region (either in the
crypto memory buffer or the system memory). The base address of the memory region is provided by VU_CTL.ADDR[31:8]
and the memory region size is specified by VU_CTL.MASK[].
Figure 12-17. Register File

16 KB
Register-file memory region

r15 size[12:0] data[12:0]

r14 size[12:0] data[12:0]

4096 entries
r13 size[12:0] data[12:0]
r12 size[12:0] data[12:0]
... ...
...
r1 size[12:0] data[12:0]
r0 size[12:0] data[12:0]

32-bit word

12.10.2 Stack
The VU stack resides in the memory region. Register r15 is used as a stack pointer. The stack has two purposes:
■ It is used to save/restore registers r0 through r14. Each register (data field and size field) uses a single 32-bit word.
The instruction PUSH_REG saves/pushes all registers r0 through r14 on the stack (and register r15 is decremented by
15).
The instruction POP_REG restores/pops all registers r0 through r14 from the stack (and register r15 is incremented by
15).
The use of the stack pointer (register r15) is implied by the PUSH_REG and POP_REG instructions.
■ It is used to allocate memory operands.
The instruction ALLOC_MEM (rx, size-1) allocates enough 32-bit words to hold a memory operand of “size” bits for regis-
ter rx. The stack pointer (register r15) is decremented by the number of allocated 32-bit words. The data field of register rx
is updated with the new stack pointer value.
The instruction FREE_MEM (“15 bit pattern”) frees the 32-bit words that hold memory operand data associated with the
registers identified by the bit pattern. Note that a register’s size field specifies the number 32-bit words that hold its asso-
ciated memory operand. The stack pointer is incremented by the number of freed 32-bit words.
The use of the stack pointer (register r15) is implied by the instruction. Note that to allocate multiple memory operands,
multiple ALLOC_MEM instructions are required. However, to free multiple memory buffer operands, only a single
FREE_MEM instruction is required.
Figure 12-18 illustrates the VU register-file state before and after the execution of instructions ALLOC_MEM (r0, 32-1) (32 bits
requiring one 32-bit stack element) and ALLOC_MEM (r1, 80-1) (80 bits requiring three 32-bit stack elements).

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Figure 12-18. Left: Register File State before ALLOC_MEM Instructions; Right: Register File after ALLOC_MEM Instructions

16 KB 16 KB
Register-file memory region Register-file memory region

r15 don’t care A A r15 don’t care A-4 A

r14 size[12:0] data[12:0] r14 size[12:0] data[12:0] A-1
r13 size[12:0] data[12:0] r13 size[12:0] data[12:0]
r12 size[12:0] data[12:0] r12 size[12:0] data[12:0] A-4
... ... ... ...
... ...
r1 size[12:0] data[12:0] r1 79 A-4
r0 size[12:0] data[12:0] r0 31 A-1

Figure 12-19 illustrates the VU component state after the execution of the instruction FREE_MEM ((1 << r1) | (1 << r0)).
Figure 12-19. Register File State after FREE_MEM Instruction

16 KB
Register-file memory region

r15 don’t care A A

r14 size[12:0] data[12:0]
r13 size[12:0] data[12:0]
r12 size[12:0] data[12:0]
... ...
...
r1 79 A-4
r0 31 A-1

Freeing of stack elements should be in the reverse order of allocation of stack elements. Also see the description of the
FREE_MEM instruction for the order in which registers are freed (lower registers are freed before higher registers).

12.10.3 Memory Operands

Asymmetric key cryptography requires computations on large integers of up to 1000’s of bits. These integers are
implemented using memory operands. The instruction registers’ data values provide offsets in a memory region. The base
address of the memory region is provided by VU_CTL.ADDR[31:8]. The memory region is located in either the IP memory
buffer or the system memory. The memory region is accessed through the load and store FIFOs.
Memory operands are typically located in the crypto memory buffer (better access latency). Memory operand require one or
multiple 32-bit words. The register size field specifies the bit size of a memory operand. This size is limited to the range [1,
8192] bits. Note that there is no size restriction within this range. A memory operand of n bits requires (n+31)/32 32-bit words.

12.10.4 Datapath
The VU instructions can operate on 13-bit register data values and/or large memory operands. The VU datapath is limited to
32 bits (the width of a single memory word).
To operate on large memory operands, multiple datapath iterations are required. Dependent on the instruction opcode, these
iterations may be independent of each other (for example, a OR instruction) or may be dependent of each other (for example,
an ADD instruction requires a carry). This complexity is completely hidden from software.
■ The instruction opcode specifies whether datapath iterations are dependent or independent.
■ The register size field provides the VU decoder and datapath with all the information it needs to determine the number of
datapath iterations.

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The VU datapath consists of three functional units:

■ An ALU that performs addition, subtraction, and logical instructions.
■ A barrel shifter that performs shift instructions.
■ A multiplier that performs multiplication and squaring instructions.
In addition, a state machine is present for instruction decoding and controlling multiple datapath iterations. The state machine
also performs administration instructions such as PUSH_REG, POP_REG, ALLOC_MEM, and FREE_MEM.
Note that the instruction execution time (in clock cycles) is typically independent of the instruction operand data values.
However, the execution time is dependent on the size of memory operands (as specified by the register size field). This is an
important characteristic, as the data value independence complicates differential power or execution time attacks.

12.10.5 Status Register

Similar to the Arm architecture, the VU has a STATUS register:
■ It is affected by instruction execution.
■ It controls instruction execution.
The STATUS register is a 4-bit field, with the following fields:
■ CARRY field (bit 0). This field is set to ‘1’ if the result of an addition exceeds the destination operand size, if the result of a
subtraction is positive or zero, or as the result of a shift instruction.
■ EVEN field (bit 1). This field is set to ‘1’ (and cleared to ‘0’ otherwise) if the result of an instruction is even (bit 0 of the
destination operand is ‘0’).
■ ZERO field (bit 2). This field is set to ‘1’ (and cleared to ‘0’ otherwise) if the result of an instruction is “0”.
■ ONE field (bit 3). This field is set to ‘1’ (and cleared to ‘0’ otherwise) if the result of an instruction is “1”.
The STATUS register fields are set and cleared as a result of instruction execution. Not all instructions affect all STATUS
register fields.
Conditional execution. As mentioned, the STATUS register controls instruction execution. It does so through conditional
instruction execution (again, similar to the Arm architecture). Almost all instructions (the SET_REG instruction is the
exception) support conditional execution. Conditional execution only executes an instruction when a specific condition, as
specified by a condition code in the instruction word, is met. The condition code is dependent on the STATUS register fields.
The following table lists the condition codes and the conditions under which the conditional instruction is executed.

Table 12-28. Condition Codes

Abbreviation Condition Code Value Description Condition
ALWAYS 0x0 Always ‘1’
EQ 0x1 Equal ZERO
NE 0x2 Not equal !ZERO
CS 0x3 Carry set/higher or same CARRY
CC 0x4 Carry clear/lower !CARRY
HI 0x5 Higher CARRY & !ZERO
LS 0x6 Lower or same !CARRY | ZERO
EVEN 0x7 Even EVEN
ODD 0x8 Odd !EVEN
ONE 0x9 One ONE
NOT_ONE 0xa Not one !ONE

If a conditional instruction has a condition code that evaluates to ‘0’/FALSE, it does not change the VU functional state. This
means that:
■ a destination operand is not updated
■ the STATUS register is not updated

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12.10.6 Instructions
The VU instructions operate on either register operand data or memory operand data.
Operand types. Typically, VU instruction operands all have the same type: either register or memory operands. However,
some exceptions do exist. For example, consider the following CTSAME (count trailing same) instruction.

CTSAME (r0, r1, r2)

This instruction counts the number of trailing bits (least significant bits), which are the same as the two memory operands that
are identified by register r1 and r2. The instruction result is stored in the data field of register r0. This instruction has two
source operands of the memory type and one destination operand of the register type.
Conditional execution. Conditional execution makes the execution of an instruction dependent on a condition. For example,
consider the COND_CTSAME (HI, r0, r1, r2) instruction. This instruction uses the “HI” condition code. The CTSAME
instruction is only executed when the “HI” condition code evaluates to ‘1’/TRUE. This is the case when the CARRY field of the
STATUS register is ‘1’/TRUE and the ZERO field of the STATUS register is ‘0’/FALSE.
Unconditional execution uses the “ALWAYS” condition code, which always evaluates to ‘1’/TRUE. For brevity, and
unconditional instruction XXX is not written as COND_XXX, but simply as XXX.
Note that a not executed conditional instruction does not update the STATUS register.
Memory operand data extension. Register operand data always has the same 13-bit size. Memory operand data has a size
that is specified by a register’s size field. Therefore, it is possible to have memory operands with different sizes. This is
intentional, but requires some rules in terms of how to deal with instructions that operate on memory operands with different
sizes. These rules are as follows:
■ If an instruction has a destination memory operand (for example, an ADD instruction), the size of this destination operand
specifies the size of the instruction execution.
■ If an instruction has no destination memory operand (for example, a CTSAME instruction), the maximum size of all source
memory operands specifies the size of the instruction.
■ If the instruction size (as determined by the previous two rules) is larger than a source memory operand, the memory
operand is extended with leading ‘0’ bits (most significant ‘0’ bits).
■ If the instruction size is smaller than a source memory operand, the memory operand’s leading bits (most significant bits)
are dropped/ignored (the LSR, LSR1, and LSR1_WITH_CARRY are an exception to this rule).
To illustrate memory operand extension, we give a few examples.
CTSAME (r0, r1, r2)
r1 specifies a 40-bit memory operand 0x11:12345678
r2 specifies a 64-bit memory operand 0x11111111:ffffff78
The instruction size is 64 bits (maximum size of the two source memory operands). The memory operand 0x11:12345678 is
extended to 0x00000011:12345678. The CTSAME instruction produces the result 8 in the register r0 data field.
ADD (r0, r1, r2)
r0 specifies a 48-bit memory operand
r1 specifies a 40-bit memory operand 0x11:12345678
r2 specifies a 64-bit memory operand 0xffffffff:ffffff78
The instruction size is 48 bits (size of the destination memory operand). The memory operand 0x11:12345678 is extended to
0x0011:12345678. The memory operand 0xffffffff:ffffff78 is reduced to 0xffff:ffffff78. The ADD instruction produces the 40-bit
result 0x0011:123455f0 in the destination memory operand. Note that this instruction generates a carry and will set the
CARRY field of the STATUS register to ‘1’/TRUE.

12.10.7 Instruction Set

This section describes all VU instructions. For each instruction, the following is described:
■ The instruction format
❐ Source operand types (register or memory operands)
❐ Support for conditional execution
❐ Encoding of the 32-bit instruction word (IW[31:0])

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■ Mnemonic
■ Operation code
■ Functionality
For instructions with memory operands, the source and destination memory operands may overlap, unless otherwise
mentioned (the USQUARE, XSQUARE, UMUL, and XMUL instructions do not allow memory operand overlap).

Table 12-29. ALLOC_MEM Instruction

Mnemonic (rdst, imm13[12:0])
Instruction Format rdst: register operand
imm13: 13-bit immediate date
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[19:16] = rdst
IW[12:0] = imm13
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
r15.data[12:0] = r15_data[12:0] – (imm13 >> 5) - 1;
ALLOC_MEM 0x12 rdst.data[12:0] = r15_data[12:0];
rdst.size[12:0] = imm13; // bit size minus ‘1’

Table 12-30. Instructions with Memory Operands, Category III

Mnemonic (imm16[15:0])
Instruction Format
imm16: 16-bit immediate date
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[15:0] = imm16
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
for (idx = 0; idx <= 15; idx++) {
if (imm16[idx]) {
imm13 = r[idx].size[12:0]
FREE_MEM 0x13
r15.data[12:0] = r15_data[12:0] + (imm13 >> 5) + 1;
}
}

Table 12-31. Instructions with Register Operand Only, Category I

Mnemonic (rdst, imm13_0[13:0], imm13_1[11:0])
rdst: register operand
Instruction Format
imm13_0: 13 bit immediate (for register data field)
imm13_1: 13-bit immediate (for register size field)
IW[31:30] = “operation code”
IW[29:26] = rdst
Encoding
IW[25:13] = imm13_1
IW[12:0] = imm13_0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
rdst.data[12:0] = imm13_1;
SET_REG 0x2
rdst.size[12:0] = imm13_0; // bit size minus ‘1’

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Table 12-32. MOV_REG Instruction

Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc)
rdst: register operand
Instruction Format
rsrc: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[15:12] = rdst
IW[3:0] = rsrc
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
MOV_REG 0x02 rdst.data = rsrc.data; rdst.size = rsrc.size;

Table 12-33. LD_REG Instruction

Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0)
rsrc1: register operand
Instruction Format
rsrc0: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[15:12] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
word = GetMemData (r15.data+rsrc0, 32-1); // r15: stack
pointer
LD_REG 0x00
rsrc1.data[12:0] = word >> 16;
rsrc1.size[12:0] = word;

Table 12-34. ST_REG Instruction

Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0)
rsrc1: register operand
Instruction Format
rsrc0: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[7:4] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
word = rsrc1.data[12:0] << 16 | rsrc1.size[12:0]
ST_REG 0x01
SetMemBuffData (r15.data+rsrc0, word, 32-1);

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Table 12-35. Instructions with Register Operand Only, Category III

Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0)
rsrc0: register operand
Instruction Format
rsrc1: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[7:4] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
data = rsrc1.data; size = rsrc1.size;
SWAP_REG 0x03 rsrc1.data = rsrc0.data; rsrc1.size = rsrc0.size;
rsrc0.data = data; rsrc0.size = size;

Table 12-36. Instructions with Register Operand Only, Category IV

Mnemonic () or COND_Mnemonic (cc)
Instruction Format
cc: condition code
IW[31:24] = “operation code”
Encoding
IW[23:20] = cc
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
r15.data -= 15; // r15: stack pointer
word = r0.data[12:0] << 16 | r0.size[12:0]; Mem-
Buff[r15.data+0] = word;
word = r1.data[12:0] << 16 | r1.size[12:0]; Mem-
PUSH_REG 0x10
Buff[r15.data+1] = word;
…
word = r14.data[12:0] << 16 | r14.size[12:0]; Mem-
Buff[r15.data+14] = word;
word = GetMemData (r15.data+0, 32-1);
r0.data = word >> 16; r0.size = word;
word = MemBuff[r15.data+1];
r1.data[12:0] = word >> 16; r1.size[12:0] = word;
POP_REG 0x11
…
word = MemBuff[r15.data+14];
r14.data[12:0] = word >> 16; r14.size[12:0] = word;
r15.data += 15;

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Table 12-37. Instructions with Register Operand Only, Category V

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: register operand
Instruction Format rsrc1: register operand
rsrc0: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding IW[15:12] = rdst
IW[7:4] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
ADD_REG 0x06 rdst.data[12:0] = rsrc1.data[12:0] + rsrc0.data[12:0];
SUB_REG 0x07 rdst.data[12:0] = rsrc1.data[12:0] – rsrc0.data[12:0];
OR_REG 0x08 rdst.data[12:0] = rsrc1.data[12:0] | rsrc0.data[12:0];
AND_REG 0x09 rdst.data[12:0] = rsrc1.data[12:0] & rsrc0.data[12:0];
XOR_REG 0x0a rdst.data[12:0] = rsrc1.data[12:0] ^ rsrc0.data[12:0];
NOR_REG 0x0b rdst.data[12:0] = ~(rsrc1.data[12:0] | rsrc0.data[12:0]);
NAND_REG 0x0c rdst.data[12:0] = ~(rsrc1.data[12:0] & rsrc0.data[12:0]);
MIN_REG 0x0d rdst.data[12:0] = Minimum (rsrc1.data[12:0], rsrc0.data[12:0]);
MAX_REG 0x0e rdst.data[12:0] = Maximum (rsrc1.data[12:0], rsrc0.data[12:0]);

Table 12-38. MOV_REG_TO_STATUS

Mnemonic (rsrc) or COND_Mnemonic (cc, rsrc)
Instruction Format rsrc: register operand
cc: condition code
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[3:0] = rsrc
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
STATUS.CARRY = rsrc.data[0];
STATUS.EVEN = rsrc.data[1];
MOV_REG_TO_STATUS 0x04
STATUS.ZERO = rsrc.data[2];
STATUS.ONE = rsrc.data[3];

Table 12-39. MOV_STATUS_TO_REG

Mnemonic (rdst) or COND_Mnemonic (cc, rdst)
Instruction Format rdst: register operand
cc: condition code
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[15:12] = rdst
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
rdst.data= 0;
rdst.data[0] = STATUS.CARRY;
MOV_STATUS_TO_REG 0x05 rdst.data[1] = STATUS.EVEN;
rdst.data[2] = STATUS.ZERO;
rdst.data[3] = STATUS.ONE;

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Table 12-40. MOV_IMM_TO_STATUS

Mnemonic (imm4) or COND_Mnemonic (cc, imm4)
Instruction Format imm4: immediate value
cc: condition code
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[3:0] = imm4
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
STATUS.CARRY = imm[0];
STATUS.EVEN = imm[1];
MOV_IMM_TO_STATUS 0x01
STATUS.ZERO = imm[2];
STATUS.ONE = imm[3];

Table 12-41. Instructions with Mixed Operands, Category I

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: memory buffer operand
Instruction Format rsrc1: memory buffer operand
rsrc0: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding IW[15:12] = rdst
IW[7:4] = rsrc1
IW[3:0] = rsrc0
STATUS.EVEN = (dst_data[0] == 0)
Shared Functionality STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, rdst.size);
dst_data = src1_data << rsrc0.data[12:0];
LSL 0x20 if (rsrc0.data[12:0] != 0) STATUS.CARRY = dst_-
data[rdst.size +1];
else STATUS.CARRY = 0
SetMemBuffData (rdst.data, dst_data, rdst.size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
dst_data = src1_data >> rsrc0.data[12:0];
LSR 0x23 if (rsrc0.data[12:0] != 0) STATUS.CARRY = dst_data[-1];
else STATUS.CARRY = 0;
SetMemBuffData (rdst.data, dst_data, rdst.size);

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Table 12-42. Instructions with Mixed Operands, Category II

Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc)
rdst: memory buffer operand
Instruction Format
rsrc: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[15:12] = rdst
IW[7:4] = rsrc
STATUS.EVEN = (dst_data[0] == 0)
Shared Functionality STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
src_data = GetMemData (rsrc.data, rsrc.size);
src_data = SizeAdjust (src_data, rdst.size);
LSL1 0x21 dst_data = (src_data << 1);
STATUS.CARRY = dst_data[rdst.size +1];
SetMemBuffData (rdst.data, dst_data, rdst.size);
src_data = GetMemData (rsrc.data, rsrc.size);
src_data = SizeAdjust (src_data, rdst.size);
LSL1_WITH_CARRY 0x22 dst_data = (src_data << 1) | STATUS.CARRY;
STATUS.CARRY = dst_data[rdst.size +1];
SetMemBuffData (rdst.data, dst_data, rdst.size);
src_data = GetMemData (rsrc.data, rsrc.size);
dst_data = src_data >> 1;
LSR1 0x24
STATUS.CARRY = dst_data[-1];
SetMemBuffData (rdst.data, dst_data, rdst.size);
src_data = GetMemData (rsrc.data, rsrc.size);
dst_data = src_data >> 1; dst_data[rdst.size] = STA-
LSR1_WITH_CARRY 0x25 TUS.CARRY;
STATUS.CARRY = dst_data[-1];
SetMemBuffData (rdst.data, dst_data, rdst.size);

Table 12-43. Instructions with Mixed Operands, Category III

Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc)
rdst: memory buffer operand
Instruction Format
rsrc: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[15:12] = rdst
IW[3:0] = rsrc
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
dst_data = GetMemData (rdst.data, rdst.size);
SET_BIT 0x28 dst_data[rsrc.data[12:0]] = 1;
SetMemBuffData (rdst.data, dst_data, rdst.size);
dst_data = GetMemData (rdst.data, rdst.size);
CLR_BIT 0x29 dst_data[rsrc.data[12:0]] = 0;
SetMemBuffData (rdst.data, dst_data, rdst.size);
dst_data = GetMemData (rdst.data, rdst.size);
INV_BIT 0x2a dst_data[rsrc.data[12:0]] = !dst_data[rsrc.data[12:0]];
SetMemBuffData (rdst.data, dst_data, rdst.size);

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 Cryptographic Function Block (Crypto)

Table 12-44. Instructions with Mixed Operands, Category IV

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: register operand
Instruction Format rsrc1: memory buffer operand
rsrc0: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding IW[15:12] = rdst
IW[7:4] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_bit = src1_data[rsrc0.data[12:0]];
GET_BIT 0x2b
rdst.data = src1_bit;
STATUS.CARRY = src1_bit;

Table 12-45. Instructions with Mixed Operands, Category V

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: register operand
Instruction Format rsrc1: memory buffer operand
rsrc0: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding IW[15:12] = rdst
IW[7:4] = rsrc1
IW[3:0] = rsrc0
STATUS.ZERO = (src0_data[instr_size:0] == src1_data[instr_size:0])
Shared Functionality Note that for 8192-bit operands, two equal operands result in rdst.data[12:0] = “0”. The ZERO cause field can
be used to identify this situation.
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = Maximum (rsrc1.size, rsrc0.size);
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
CLSAME 0x26
temp_data = src1_data ^ src0_data;
for (idx = instr_size-1; idx >= 0; idx--) {
if (temp_data[idx] == 1) break;
}
rdst.data[12:0] = instr_size - idx - 1;
instr_size = Maximum (rsrc1.size, rsrc0.size);
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
CTSAME 0x27
temp_data = src1_data ^ src0_data;
for (idx = 0; idx < instr_size; idx++) {
if (temp_data[idx] == 1) break;
}
rdst.data[12:0] = idx;

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 Cryptographic Function Block (Crypto)

Table 12-46. Instructions with Memory Operands, Category I

Mnemonic (rdst) or COND_Mnemonic (cc, rdst)
Instruction Format rdst: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[15:12] = rdst
STATUS.EVEN = (dst_data[0] == 0)
Shared Functionality STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = rdst.size;
SET_TO_ZERO 0x34 dst_data = 0;
SetMemBuffData (rdst.data, dst_data, instr_size);
instr_size = rdst.size;
SET_TO_ONE 0x35 dst_data = 1;
SetMemBuffData (rdst.data, dst_data, instr_size);

Table 12-47. Instructions with Memory Operands, Category II

Mnemonic (rdst, rsrc) or COND_Mnemonic (cc, rdst, rsrc)
rdst: memory buffer operand
Instruction Format
rsrc: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[15:12] = rdst
IW[3:0] = rsrc
STATUS.EVEN = (dst_data[0] == 0)
Shared Functionality STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = rdst.size;
src_data = GetMemData (rsrc.data, rsrc.size);
MOV 0x30 src_data = SizeAdjust (src_data, instr_size);
dst_data = src_data;
SetMemBuffData (rdst.data, dst_data, instr_size);
instr_size = rdst.size;
src_data = GetMemData (rsrc.data, rsrc.size);
src_data = SizeAdjust (src_data, instr_size);
XSQUARE 0x31
dst_data = PolynomialMultiplication (src_data, src_data);
SetMemBuffData (rdst.data, dst_data, instr_size);
Note: The source and destination memory operands must not overlap.
instr_size = rdst.size;
src_data = GetMemData (rsrc.data, rsrc.size);
src_data = SizeAdjust (src_data, instr_size);
USQUARE 0x2f
dst_data = src_data * src_data;
SetMemBuffData (rdst.data, dst_data, instr_size);
Note: The source and destination memory operands must not overlap.

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 Cryptographic Function Block (Crypto)

Table 12-48. Instructions with Memory Operands, Category III

Mnemonic (rsrc1, rsrc0) or COND_Mnemonic (cc, rsrc1, rsrc0)
rsrc1: memory buffer operand
Instruction Format
rsrc0: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[7:4] = rsrc1
IW[3:0] = rsrc0
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = Maximum (rsrc1.size, rsrc0.size);
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
CMP_SUB 0x3d
dst_data = src1_data – src0_data;
STATUS.CARRY = (src1_data >= src0_data);
STATUS.EVEN = (dst_data[0] == 0)
STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
instr_size = Maximum (rsrc1.size, rsrc0.size);
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
CMP_DEGREE 0x3e src1_data = SizeAdjust (src1_data, instr_size);
STATUS.CARRY = PolynomialDegree (src1_data) >= Polynomi-
alDegree (src0_data);
STATUS.ZERO = PolynomialDegree (src1_data) == Polynomial-
Degree (src0_data);

Table 12-49. Instructions with Memory Operands, Category IV

Mnemonic (rsrc) or COND_Mnemonic (cc, rsrc)
Instruction Format rsrc: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
Encoding IW[23:20] = cc
IW[3:0] = rsrc
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = rsrc.size;
src_data = GetMemData (rsrc.data, rsrc.size);
dst_data = src_data;
TST 0x3f STATUS.CARRY = 0; // always set to ‘0’!!!
STATUS.EVEN = (dst_data[0] == 0)
STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)

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 Cryptographic Function Block (Crypto)

Table 12-50. Instructions with Memory Operands, Category V

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: memory buffer operand
Instruction Format rsrc1: memory buffer operand
rsrc0: memory buffer operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding IW[15:12] = rdst
IW[7:4] = rsrc1
IW[3:0] = rsrc0
STATUS.EVEN = (dst_data[0] == 0)
Shared Functionality STATUS.ZERO = (dst_data[instr_size:0] == 0)
STATUS.ONE = (dst_data[instr_size:0] == 1)
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
XMUL 0x32 dst_data = PolynomialMultiplication (src1_data, src0_-
data);
SetMemBuffData (rdst.data, dst_data, instr_size);
Note: The source and destination memory operands must not overlap.
When one of the operands is 32 or less bits in size, performance is best when
rsrc0 is used for this operand.
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
UMUL 0x33
dst_data = src1_data * src0_data;
SetMemBuffData (rdst.data, dst_data, instr_size);
Note: The source and destination memory operands must not overlap.
When one of the operands is 32 or less bits in size, performance is best when
rsrc0 is used for this operand.
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
ADD 0x36
src1_data = SizeAdjust (src1_data, instr_size);
dst_data = src1_data + src0_data;
STATUS.CARRY = (dst_data >= (1 << instr_size));
SetMemBuffData (rdst.data, dst_data, instr_size);

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 Cryptographic Function Block (Crypto)

Table 12-50. Instructions with Memory Operands, Category V

Mnemonic (rdst, rsrc1, rsrc0) or COND_Mnemonic (cc, rdst, rsrc1, rsrc0)
rdst: memory buffer operand
Instruction Format rsrc1: memory buffer operand
rsrc0: memory buffer operand
cc: condition code
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
SUB 0x37
src1_data = SizeAdjust (src1_data, instr_size);
dst_data = src1_data - src0_data;
STATUS.CARRY = (src1_data >= src0_data);
SetMemBuffData (rdst.data, dst_data, instr_size);
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
ADD_WITH_CARRY 0x14
src1_data = SizeAdjust (src1_data, instr_size);
dst_data = src1_data + src0_data + STATUS.CARRY;
STATUS.CARRY = (dst_data >= (1 << instr_size));
SetMemBuffData (rdst.data, dst_data, instr_size);
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
SUB_WITH_CARRY 0x15
src1_data = SizeAdjust (src1_data, instr_size);
dst_data = src1_data - src0_data – !STATUS.CARRY;
STATUS.CARRY = (src1_data >= src0_data);
SetMemBuffData (rdst.data, dst_data, instr_size);
instr_size = rdst.size;
src0_data = GetMemData (rsrc0.data, rsrc0.size);
src0_data = SizeAdjust (src0_data, instr_size);
src1_data = GetMemData (rsrc1.data, rsrc1.size);
src1_data = SizeAdjust (src1_data, instr_size);
OR, AND, XOR, NOR, 0x38, 0x39, 0x3a, 0x3b,
OR: dst_data = src1_data | src0_data;
NAND 0x3c
AND: dst_data = src1_data & src0_data;
XOR: dst_data = src1_data ^ src0_data;
NOR: dst_data = ~(src1_data | src0_data);
NAND: dst_data = ~(src1_data & src0_data);
SetMemBuffData (rdst.data, dst_data, instr_size);

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 Cryptographic Function Block (Crypto)

Table 12-51. Instructions with Memory Operands, Category VI

Mnemonic (rdst, imm12) or COND_Mnemonic (cc, rdst, imm12)
rdst: memory buffer operand
Instruction Format
rsrc: register operand
cc: condition code
IW[31:24] = “operation code”
IW[23:20] = cc
Encoding
IW[19:16] = rdst
IW[12:0] = imm13
Mnemonic Operation Code Functionality (if “cc” evaluates to ‘1’/TRUE)
dst_data = GetMemData (rdst.data, rdst.size);
SET_BIT_IMM 0x2c dst_data[imm13] = 1;
SetMemBuffData (rdst.data, dst_data, rdst.size);
dst_data = GetMemData (rdst.data, rdst.size);
CLR_BIT_IMM 0x2d dst_data[imm13] = 0;
SetMemBuffData (rdst.data, dst_data, rdst.size);
dst_data = GetMemData (rdst.data, rdst.size);
INV_BIT_IMM 0x2e dst_data[imm13] = !dst_data[imm13];
SetMemBuffData (rdst.data, dst_data, rdst.size);

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 13. Program and Debug Interface

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU Program and Debug interface provides a communication gateway for an external device to perform
programming or debugging. The external device can be a Cypress-supplied programmer and debugger, or a third-party
device that supports programming and debugging. The serial wire debug (SWD) or the JTAG interface can be used as the
communication protocol between the external device and PSoC 6 MCUs.

13.1 Features
■ Supports programming and debugging through the JTAG or SWD interface.
■ CM4 supports 4-bit ETM tracing, serial wire viewer (SWV), and printf() style debugging through the single-wire output
(SWO) pin. CM0+ supports Micro Trace Buffer (MTB) with 4 KB dedicated RAM.
■ Supports Cross Triggering Interface (CTI) and Cross Triggering Matrix (CTM).
■ CM0+ supports four hardware breakpoints and two watchpoints. CM4 supports six hardware breakpoints and four
watchpoints.
■ Provides read and write access to all memory and registers in the system while debugging, including the Cortex-M4 and
Cortex-M0+ register banks when the core is running or halted

13.2 Architecture
Figure 13-1 shows the block diagram of the program and debug interface in the PSoC 6 MCU. The debug and access port
(DAP) acts as the program and debug interface. The external programmer or debugger, also known as the “host”,
communicates with the DAP of the PSoC 6 MCU “target” using either the SWD or JTAG interface. The debug physical port
pins communicate with the DAP through the high-speed I/O matrix (HSIOM). See the I/O System chapter on page 261 for
details on HSIOM.
The debug infrastructure is organized in the following four groups:
■ DAP (provides pin interfaces through which the debug host can connect to the chip)
■ Cortex-M0+ core debug components
■ Cortex-M4 core debug components
■ Other debug infrastructure (includes the CM4 tracing, the CTM, and the System ROM table)

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 Program and Debug Interface

Figure 13-1. Program and Debug Interface

PSoC 6

DAP Arm Cortex-M0+ subsystem

CM0+ AHB decoder

CM0 Access
SLV
Port
Cross Trigger CM0 external
Cortex-M0+
Interface (CTI) ROM table

AHB Micro Trace Buffer (MTB) SRAM

Arm Cortex-M4 subsystem

SWD/JTAG

DAP BUS

CM4 APB decoder

DAP
DAP
CM4 AP
Cross Trigger CM4
Interface (CTI) ROM table
Cortex-M4

AHB Embedded Trace Macro (ETM)

ITM

System System Cross Trigger Cross Trigger

Access Port ROM table Matrix (CTM) Interface (CTI)

Debug APB
Port Pins

Trace Port decoder

Interface Unit
(TPIU)

Debug
ROM table

The DAP communicates with the Cortex-M0+ CPU using the Arm-specified advanced high-performance bus (AHB) interface.
AHB is the systems interconnect protocol used inside the device, which facilitates memory and peripheral register access by
the AHB master. The PSoC 6 MCU has six AHB masters – Arm CM4 CPU core, Arm CM0 CPU core, Datawire0, Datawire1,
Crypto, and DAP. The external host can effectively take control of the entire device through the DAP to perform programming
and debugging operations.
The following are the various debug and trace components:
■ Debug components
❐ JTAG and SWD for debug control and access
■ Trace source components
❐ Micro trace buffer (MTB-M0+) for tracing Cortex-M0+ program execution
❐ Embedded trace macrocell (ETM-M4) for tracing Cortex-M4 program execution
■ Trace sink components
❐ Trace port interface unit (TPIU) to drive the trace information out of the chip to an external trace port analyzer
■ Cross-triggering components
❐ Cross-trigger interface (CTI)
❐ Cross-trigger matrix (CTM)
■ ROM tables

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 Program and Debug Interface

13.2.1 Debug Access Port (DAP) Note: The debug slave interfaces of both the CPUs bypass
the internal CPU MPU.
The DAP consists of a combined SWD/JTAG interface
(SWJ) that also includes the SWD listener. The SWD 13.2.1.2 DAP Power Domain
listener decides whether the JTAG interface (default) or
SWD interface is active. Note that JTAG and SWD are Almost all the debug components are part of the Active
mutually exclusive because they share pins. power domain. The only exception is the SWD/JTAG-DP,
which is part of the Deep Sleep power domain. This allows
The debug port (DP) connects to the DAP bus, which in turn the debug host to connect during Deep Sleep, while the
connects to one of three Access Ports (AP), namely: application is ‘running’ or powered down. This enables in-
■ The CM0-AP, which connects directly to the AHB debug field debugging for low-power applications in which the chip
slave port (SLV) of the CM0+ and gives access to the is mostly in Deep Sleep.
CM0+ internal debug components. This also allows
After the debugger is connected to the chip, it must bring the
access to the rest of the system through the CM0+ AHB
chip to the Active state before any operation. For this, the
master interface. This provides the debug host the same
SWD/JTAG-DP has a register (DP_CTL_STAT) with two
view as an application running on the CM0+. This
power request bits. The two bits are CDBGPWRUPREQ
includes access to the MMIO of other debug
and CSYSPWRUPREQ, which request for debug power
components of the Cortex M0+ subsystem. These
and system power, respectively. These bits must remain set
debug components can also be accessed by the CM0+
for the duration of the debug session.
CPU, but cannot be reached through the other APs or by
the CM4 core. Note that only the two SWD pins (SWCLKTCK and
■ The CM4-AP located inside the CM4 gives access to the SWDIOTMS) are operational during the Deep Sleep mode –
CM4 internal debug components. The CM4-AP also the JTAG pins are operational only in Active mode. The
allows access to the rest of the system through the CM4 JTAG debug and JTAG boundary scan are not available
AHB master interfaces. This provides the debug host the when the system is in Deep Sleep mode. JTAG functionality
same view as an application running on the CM4 core. is available only after a chip power-on-reset.
Additionally, the CM4-AP provides access to the debug
components in the CM4 core through the External 13.2.2 ROM Tables
Peripheral Bus (EPB). These debug components can
also be accessed by the CM4 CPU, but cannot be The ROM tables are organized in a tree hierarchy. Each AP
reached through the other APs or by the CM0+ core. has a register that contains a 32-bit address pointer to the
base of the root ROM table for that AP. For PSoC 6 MCUs,
■ The System-AP, which through an AHB mux gives
there are three such root ROM tables.
access to the rest of the system. This allows access to
the System ROM table, which cannot be reached any Each ROM table contains 32-bit entries with an address
other way. The System ROM table provides the chip ID pointer that either points to the base of the next level ROM
but is otherwise empty. table. Each ROM table also contains a set of ID registers
that hold JEDEC compliant identifiers to identify the
13.2.1.1 DAP Security manufacturer, part number, and major and minor revision
numbers. For all ROM tables in PSoC 6 MCUs, these IDs
For security reasons all three APs each can be are the same. Each ROM table and CoreSight compliant
independently disabled. Each AP disable is controlled by component also contains component identification registers.
two MMIO bits. One bit, CPUSS_AP_CTL.xxx_DISABLE
(where xxx can be CM0 or CM4 or SYS), can be set during
boot, before the debugger can connect, based on eFuse 13.2.3 Trace
settings. After this bit is set it cannot be cleared. The micro trace buffer (MTB-M0+) component captures the
The second bit, CPUSS_AP_CTL.xxx_ENABLE, is a regular program execution flow from Cortex-M0+ CPU and stores it
read/write bit. This bit also resets to zero and is set to ‘1’ by in a local SRAM memory. This information can be read by
either the ROM boot code or the flash boot code depending an external debug tool through JTAG/SWD interface to
on the life-cycle stage. This feature can be used to block construct the program execution flow.
debug access during normal operation, but re-enable some The embedded trace macro (ETM) component connected to
debug access after a successful authentication. Cortex-M4 captures the program execution flow from
In addition to the above, the System AP is also protected by Cortex-M4 CPU and generates trace output on its advanced
an MPU. This can be used to give the debugger limited trace bus (ATB) interface. The instrumentation trace
access to the rest of the system. Allow access to the System macrocell (ITM), which is inside Cortex-M4, also generates
ROM table for chip identification. If debug access is restored trace output on its ATB interface. These two ATB interfaces
after successful authentication, this MPU must be (from ETM-M4 and ITM) are connected a trace port interface
configured to allow authentication requests. unit (TPIU).

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 Program and Debug Interface

The TPIU drives the external pins of a trace port (through frequency clock domain. For more details, refer to the Arm
IOSS interface), so that the trace can be captured by an documentation.
external trace port analyzer (TPA). For more details, refer to
the Arm Debug Interface Architecture Specification ADIv5.0
to ADIv5.2. 13.3 Serial Wire Debug (SWD)
Interface
13.2.4 Embedded Cross Triggering
The PSoC 6 MCU supports programming and debugging
The Arm CoreSight includes Embedded Cross Triggering through the SWD interface. The SWD protocol is a packet-
(ECT) to communicate events between debug components. based serial transaction protocol. At the pin level, it uses a
These events are particularly useful with tracing and single bidirectional data signal (SWDIO) and a unidirectional
multicore platforms. For example trigger events can be used clock signal (SWDCK). The host programmer always drives
to: the clock line, whereas either the host or the target drives
■ Start or stop both CPUs at (almost) the same time the data line. A complete data transfer (one SWD packet)
■ Start or stop instruction tracing based on trace buffer requires 46 clocks and consists of three phases:
being full or not or based on other events ■ Host Packet Request Phase – The host issues a
request to the PSoC 6 MCU target.
CoreSight uses two components to support ECT, namely a
CTI and a CTM, both of which are used in PSoC 6 MCUs. ■ Target Acknowledge Response Phase – The PSoC 6
MCU target sends an acknowledgement to the host.
The CTI component interfaces with other debug ■ Data Transfer Phase – The host or target writes data to
components, sending triggers back and forth and the bus, depending on the direction of the transfer.
synchronizing them as needed. The CTM connects several
CTIs, thus allowing events to be communicated from one When control of the SWDIO line passes from the host to the
CTI to another. target, or vice versa, there is a turnaround period (Trn)
where neither device drives the line and it floats in a high-
The PSoC 6 MCU has three CTIs, one for each CPU and impedance (Hi-Z) state. This period is either one-half or one
one for the trace components in the debug structure. These and a half clock cycles, depending on the transition.
three CTIs are connected together through the CTM. The
CM4 CTI is located in the fast clock domain and the other Figure 13-2 shows the timing diagrams of read and write
two CTIs and the CTM are all located in the same slow- SWD packets.

Figure 13-2. SWD Write and Read Packet Timing Diagrams

SWD Write Packet

SWDCK ...

SWDIO ...
Trn (Hi-Z)

wdata[31]
Trn (Hi-Z)
RnW (0)
Start (1)

wdata[0]

wdata[1]
Stop (0)

Park (1)

1 0 0
APnDP

...
Parity

Parity
A[2:3]
ACK[0:2]

Host Packet Request Phase Target ACK Phase Host Data Transfer Phase

SWD Read Packet

SWDCK ...

SWDIO ...
Trn (Hi-Z)

Trn (Hi-Z)
RnW (1)

rdata[31]
Start (1)

Stop (0)

Park (1)

1 0 0
APnDP

rdata[0]

rdata[1]

...
Parity

Parity

A[2:3]
ACK[0:2]

Host Packet Request Phase Target ACK and Data Transfer Phases

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The sequence to transmit SWD read and write packets are drives the SWDIO line during the Host Packet Request
as follows: phase and, if the host is writing data to the target, during the
1. Host Packet Request Phase: SWDIO driven by the host Data Transfer phase as well. When the host is driving the
SWDIO line, each new bit is written by the host on falling
a. The start bit initiates a transfer; it is always logic 1.
SWDCK edges, and read by the target on rising SWDCK
b. The AP not DP (APnDP) bit determines whether the edges. The target drives the SWDIO line during the Target
transfer is an AP access – 1b or a DP access – 0b. Acknowledge Response phase and, if the target is reading
c. The Read not Write bit (RnW) controls which out data, during the Data Transfer phase as well. When the
direction the data transfer is in. 1b represents a ‘read target is driving the SWDIO line, each new bit is written by
from’ the target, or 0b for a ‘write to’ the target. the target on rising SWDCK edges, and read by the host on
d. The Address bits (A[3:2]) are register select bits for falling SWDCK edges.
AP or DP, depending on the APnDP bit value. Table 13-1 and Figure 13-2 illustrate the timing of SWDIO bit
Note: Address bits are transmitted with the LSb first. writes and reads.
e. The parity bit contains the parity of APnDP, RnW,
and ADDR bits. It is an even parity bit; this means, Table 13-1. SWDIO Bit Write and Read Timing
when XORed with the other bits, the result will be 0. SWDIO Edge
If the parity bit is not correct, the header is ignored by SWD Packet Phase
Falling Rising
the PSoC 6 MCU; there is no ACK response (ACK =
Host Packet Request
111b). The programming operation should be Host Write Target Read
aborted and retried again by following a device reset. Host Data Transfer
f. The stop bit is always logic 0. Target Ack Response
Host Read Target Write
g. The park bit is always logic 1. Target Data Transfer
2. Target Acknowledge Response Phase: SWDIO driven
by the target 13.3.2 ACK Details
a. The ACK[2:0] bits represent the target to host The acknowledge (ACK) bitfield is used to communicate the
response, indicating failure or success, among other status of the previous transfer. OK ACK means that previous
results. See Table 13-1 for definitions. Note: ACK packet was successful. A WAIT response requires a data
bits are transmitted with the LSb first. phase. For a FAULT status, the programming operation
3. Data Transfer Phase: SWDIO driven by either target or should be aborted immediately. Table 13-2 shows the ACK
host depending on direction bit-field decoding details.
a. The data for read or write is written to the bus, LSb
first. Table 13-2. SWD Transfer ACK Response Decoding
b. The data parity bit indicates the parity of the data Response ACK[2:0]
read or written. It is an even parity; this means when
OK 001b
XORed with the data bits, the result will be 0.
WAIT 010b
If the parity bit indicates a data error, corrective
action should be taken. For a read packet, if the host FAULT 100b
detects a parity error, it must abort the programming NO ACK 111b
operation and restart. For a write packet, if the target
detects a parity error, it generates a FAULT ACK Details on WAIT and FAULT response behaviors are as
response in the next packet. follows:
According to the SWD protocol, the host can generate any ■ For a WAIT response, if the transaction is a read, the
number of SWDCK clock cycles between two packets with host should ignore the data read in the data phase. The
SWDIO low. Three or more dummy clock cycles should be target does not drive the line and the host must not
generated between two SWD packets if the clock is not free- check the parity bit as well.
running or to make the clock free-running in IDLE mode. ■ For a WAIT response, if the transaction is a write, the
The SWD interface can be reset by clocking the SWDCK data phase is ignored by the PSoC 6 MCU. But, the host
line for 50 or more cycles with SWDIO high. To return to the must still send the data to be written to complete the
idle state, clock the SWDIO low once. packet. The parity bit corresponding to the data should
also be sent by the host.
13.3.1 SWD Timing Details ■ A WAIT response means that the PSoC 6 MCU is
processing the previous transaction. The host can try for
The SWDIO line is written to and read at different times a maximum of four continuous WAIT responses to see
depending on the direction of communication. The host whether an OK response is received. If it fails, then the

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programming operation should be aborted and retried 13.4 JTAG Interface

again.
■ For a FAULT response, the programming operation In response to higher pin densities on ICs, the Joint Test
should be aborted and retried again by doing a device Action Group (JTAG) proposed a method to test circuit
reset. boards by controlling the pins on the ICs (and reading their
values) via a separate test interface. The solution, later
formalized as IEEE Standard 1149.1-2001, is based on the
13.3.3 Turnaround (Trn) Period Details
concept of a serial shift register routed across all of the pins
There is a turnaround period between the packet request of the IC – hence the name “boundary scan.” The circuitry at
and the ACK phases, as well as between the ACK and the each pin is supplemented with a multipurpose element
data phases for host write transfers, as shown in called a boundary scan cell. In PSoC 6 MCUs, most GPIO
Figure 13-2. According to the SWD protocol, the Trn period port pins have a boundary scan cell associated with them
is used by both the host and target to change the drive (see the GPIO block diagrams in the I/O System chapter on
modes on their respective SWDIO lines. During the first Trn page 261). The interface used to control the values in the
period after the packet request, the target starts driving the boundary scan cells is called the Test Access Port (TAP)
ACK data on the SWDIO line on the rising edge of SWDCK. and is commonly known as the JTAG interface. It consists of
This action ensures that the host can read the ACK data on three signals: Test Data In (TDI), Test Data Out (TDO), and
the next falling edge. Thus, the first Trn period lasts only Test Mode Select (TMS). Also included is a clock signal
one-half cycle. The second Trn period of the SWD packet is (TCK) that clocks the other signals. TDI, TMS, and TCK are
one and a half cycles. Neither the host nor the PSoC 6 MCU all inputs to the device and TDO is the output from the
should drive the SWDIO line during the Trn period. device. This interface enables testing multiple ICs on a
circuit board, in a daisy-chain fashion, as shown in
Figure 13-3.
Figure 13-3. JTAG Interface to Multiple ICs on a Circuit Board

TMS

TCK

TMS Device 1 TMS Device 2 TMS Device 3

TCK TCK TCK
TDI
TDI TDO TDI TDO TDI TDO

TDO

The JTAG interface architecture within each device is shown in Figure 13-4. Data at TDI is shifted in, through one of several
available registers, and out to TDO.

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 Program and Debug Interface

Figure 13-4. JTAG Interface Architecture

Boundary Scan Path

Boundary
Scan Cells

IO Pads

Core
Logic

TDI Instruction Register

BYPASS Register

ID Register

Other Register

TCK
Test Access Port
TMS
Controller
TRST
TDO

The TMS signal controls a state machine in the TAP. The state machine controls which register (including the boundary scan
path) is in the TDI-to-TDO shift path, as shown in Figure 13-5. The following terms apply:
■ IR - the instruction register
■ DR - one of the other registers (including the boundary scan path), as determined by the contents of the instruction
register
■ capture - transfer the contents of a DR to a shift register, to be shifted out on TDO (read the DR)
■ update - transfer the contents of a shift register, shifted in from TDI, to a DR (write the DR)

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 Program and Debug Interface

Figure 13-5. TAP State Machine

TMS = 1
test logic reset
TMS = 0
TMS = 0
run test idle
TMS = 1

TMS = 1 TMS = 1
select dr scan select ir scan
TMS = 0 TMS = 0

TMS = 1 TMS = 1
capture dr capture ir
TMS = 0 TMS = 0 TMS = 0 TMS = 0

shift dr shift ir
TMS = 1 TMS = 1

TMS = 1
exit 1 dr exit 1 ir
TMS = 0 TMS = 0 TMS = 0 TMS = 0

pause dr pause ir
TMS = 1 TMS = 1

TMS = 0 TMS = 0
exit 2 dr exit 2 ir
TMS = 1 TMS = 1

update dr update ir
TMS = 1 TMS = 0 TMS = 1 TMS = 0

The registers in the TAP are:

■ Instruction – Typically two to four bits wide, holds the current instruction that defines which data register is placed in the
TDI-to-TDO shift path.
■ Bypass – one bit wide, directly connects TDI with TDO, causing the device to be bypassed for JTAG purposes.
■ ID – 32 bits wide, used to read the JTAG manufacturer/part number ID of the device.
■ Boundary Scan Path (BSR) – Width equals the number of I/O pins that have boundary scan cells, used to set or read the
states of those I/O pins.
Other registers may be included in accordance with the device manufacturer specifications. The standard set of instructions
(values that can be shifted into the instruction register), as specified in IEEE 1149, are:
■ EXTEST – Causes TDI and TDO to be connected to the BSR. The device is changed from its normal operating mode to a
test mode. Then, the device’s pin states can be sampled using the capture dr JTAG state, and new values can be applied
to the pins of the device using the update dr state.
■ SAMPLE – Causes TDI and TDO to be connected to the BSR, but the device remains in its normal operating mode.
During this instruction, the BSR can be read by the capture dr JTAG state to take a sample of the functional data entering
and leaving the device.
■ PRELOAD – Causes TDI and TDO to be connected to the BSR, but the device is left in its normal operating mode. The
instruction is used to preload test data into the BSR before loading an EXTEST instruction.
Optional, but commonly available, instructions are:
■ IDCODE – Causes TDI and TDO to be connected to an IDCODE register.
■ INTEST – Causes TDI and TDO to be connected to the BSR. While the EXTEST instruction allows access to the device
pins, INTEST enables similar access to the corelogic signals of a device
For more information, see the IEEE Standard, available at www.ieee.org.

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 Program and Debug Interface

13.5 Programming the PSoC 6 MCU

The PSoC 6 MCU is programmed using the following sequence. Refer to the PSoC 6 MCU Programming Specifications for
complete details on the programming algorithm, timing specifications, and hardware configuration required for programming.
1. Acquire the SWD port in the PSoC 6 MCU.
2. Enter the programming mode.
3. Execute the device programming routines such as Silicon ID Check, Flash Programming, Flash Verification, and
Checksum Verification.

13.5.1 SWD Port Acquisition

13.5.1.1 SWD Port Acquire Sequence
The first step in device programming is for the host to acquire the target’s SWD port. The host first performs a device reset by
asserting the external reset (XRES) pin. After removing the XRES signal, the host must send an SWD connect sequence for
the device within the acquire window to connect to the SWD interface in the DAP.
The debug access port must be reset using the standard Arm command. The DAP reset command consists of more than 49
SWDCK clock cycles with SWDIO asserted high. The transaction must be completed by sending at least one SWDCK clock
cycle with SWDIO asserted low. This sequence synchronizes the programmer and the chip. Read_DAP() refers to the read of
the IDCODE register in the debug port. The sequence of line reset and IDCODE read should be repeated until an OK ACK is
received for the IDCODE read or a timeout (2 ms) occurs. The SWD port is said to be in the acquired state if an OK ACK is
received within the time window and the IDCODE read matches with that of the Cortex-M0+ DAP.

13.5.2 SWD Programming Mode Entry

After the SWD port is acquired, the host must enter the device programming mode within a specific time window. This is done
by setting the TEST_MODE bit (bit 31) in the test mode control register (MODE register). The debug port should also be
configured before entering the device programming mode. Timing specifications and pseudo code for entering the
programming mode are detailed in the PSoC 6 MCU Programming Specifications document.

13.5.3 SWD Programming Routine Executions

When the device is in programming mode, the external programmer can start sending the SWD packet sequence for
performing programming operations such as flash erase, flash program, checksum verification, and so on. The programming
routines are explained in the Nonvolatile Memory chapter on page 164. The exact sequence of calling the programming
routines is given in the PSoC 6 MCU Programming Specifications document.

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 Program and Debug Interface

13.6 Registers
Table 13-3. List of Registers
Register Name Description
CM0P_DWT Cortex M0+ Data Watchpoint and Trace (DWT) registers
CM0P_BP Cortex M0+ BreakPoint (BP) registers
CM0P_ROM Cortex M0+ CPU Coresight ROM table
CM0P_CTI Cortex M0+ Cross-Trigger Interface (CTI) registers
CM0P_MTB Cortex M0+ Micro Trace Buffer (MTB) registers
CM4_ITM Cortex M4 Instrumentation Trace Macrocell (ITM) registers
CM4_DWT Cortex M4 Data Watchpoint and Trace (DWT) registers
CM4_FPB Cortex M4 Flash Patch and Breakpoint (FPB) registers
CM4_SCS Cortex M4 System Control Space (SCS) registers
CM4_ETM Cortex M4 Embedded Trace Macrocell (ETM) registers
CM4_CTI Cortex M4 Cross-Trigger Interface (CTI) registers
CM4_ROM Cortex M4 CPU Coresight ROM table
TRC_TPIU System Trace Coresight Trace Port Interface Unit (TPIU) registers

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 14. Nonvolatile Memory

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

Nonvolatile memory refers to the flash and SROM memory in the PSoC 6 MCU. This chapter explains the geometry and
capability of the flash memory. It also lists the SROM API functions that are used to program the flash memory.

14.1 Flash Memory

The PSoC 6 flash offers high bulk program performance and supports ultra-low-power operation. Flash is typically used to
store CPU instructions and data when the device power is off. Flash may be written, but the process is much slower and more
restrictive than for SRAM.

14.1.1 Features
This section lists the features of PSoC 6 flash.
■ 512-byte row size; minimum programmable unit
■ Supports the Read While Write (RWW) feature with a sector size of 256KB
■ 10-year retention
■ Endurance of 100 k program cycles

14.1.2 Configuration
14.1.2.1 Block Diagram
Flash is part of the CPU subsystem. The Cortex-M4 and Cortex M0+, as well as other bus masters, can access flash via the
AHB.

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 Nonvolatile Memory

Figure 14-1. Block Diagram

DataWire/
CM4 CM0+ Flash SRAM0-4 Crypto ROM
DMA

System Interconnect (AHB, IPC)

System
Resources Peripheral Interconnect (MMIO)

Interface (QSPI)
Serial Memory

2x SDHC
Peripherals

USBFS
I/O Subsystem

14.1.3 Flash Geometry

The flash is divided into three regions: the application region, and the supervisory flash (SFlash) region, and the auxiliary
flash (AUXFlash) region. The flash has an Erase Disturb mechanism in which writes to rows affect the endurance of other
rows in the same sector. It is recommended that the AUXFlash region is used for frequently-updated data. For data that
changes infrequently or code images, the application flash region can be used.
The SFlash region is used to store trim parameters, system configuration parameters, protection and security settings, boot
code, and other Cypress proprietary information. Read access to this region is permitted, but program/erase access is limited.
The application region is used to store code images or data. The AUXFlash is typically used for EEPROM emulation.
Each region divides into sectors and rows. The sector is the largest division of the region and consists of a number of 512
byte rows.

Table 14-1. Flash Geometry

Application Flash SFlash and AUXFlash
Read Rows/ Rows/
KB Sectors KB/Sector KB/Row KB Sectors KB/Sector KB/Row
Width Sector Sector
128 2048 8 256 512 0.5 64 2 32 64 0.5

Figure 14-2. Flash Geometry Organization

S0 R0

SFlash S1 R63
2 Sectors (32 kB) 64 Rows (0.5 kB)

AUXFlash S0
R0
S1
2 Sectors (32 kB) R63
64 Rows (0.5 kB)
Application
flash S0
R0

S7 R511
8 Sectors (256 kB) 512 Rows (0.5 kB)
Flash

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 Nonvolatile Memory

14.1.4 Flash Controller

Access to the flash memory is enabled through the flash controller. The flash controller interfaces with the AHB-Lite bus and
provides flash access for the CM0+, CM4, Crypto, DataWire, and debug. The flash controller generates a bus error if:
■ A flash read access to a sector that is currently being programmed/erased
■ A read access to a memory hole in the flash memory region. A memory hole is defined as a location that is not occupied
by the application flash, AUXFlash, or SFlash. Note that the AUXFlash space and SFlash space can be non-powers of 2
for some flash macros.
The flash controller also provides the registers which support configuration of flash accesses.

Table 14-2. Flash Controller Retention Registers

Register Name Description
FLASHC_FLASH_CTL Flash controller control register
FLASHC_FLASH_PWR_CTL Flash enable control
FLASHC_FLASH_CMD Flash commands for cache/buffer invalidation
FLASHC_CM0/CM4_STATUS CM0/4 interface status
FLASHC_CM0/CM4_CA_CTL CM0/4 cache control
Buffer control register where *peripheral* may be Crypto, DMA, DWx (DataWire x = 0, 1),
FLASHC_*Peripheral*_BUFF_CTL
or EXT_MSx (External master; x = 0, 1)

14.1.4.1 Wait State Count

FLASHC_FLASH_CTL supports configuration of flash wait cycles. If clk_hf is greater than the maximum operating frequency
of the flash memory, it is necessary to insert wait cycles when accessing the flash memory by setting the appropriate value in
the FLASHC_FLASH_CTL.MAIN_WS register. Set the wait cycles as follows.

HF Clock Frequency FLASH_CTL.MAIN_WS[3:0]

clk_hf  33 MHz 0
33 < clk_hf  66 MHz 1
66 < clk_hf  99 MHz 2
99 < clk_hf  133 MHz 3
133 < clk_hf  150 MHz 4

14.1.4.2 Power Modes

FLASHC_FLASH_PWR_CTL provides enable bits for the flash memory. Software can turn off all regions of the flash memory
by setting the ENABLE and ENABLE_HV fields to 0.
The wakeup time of flash memory is 10 µs. Software should wait at least 10 µs before reading from flash after it is re-enabled
through the FLASHC_FLASH_PWR_CTL register.
The flash controller provides functionality down to the Deep Sleep power mode. In the Deep Sleep power mode, the following
flash controller information is retained:
■ The retention MMIO registers (listed in Table 14-2)
■ The cache data structure
Note that buffer information (in the AHB-Lite buffer interfaces and in the synchronization logic) is not retained. Losing buffer
information after Deep Sleep transition has limited performance impact.

14.1.4.3 CPU Caches

The flash controller provides 8 kB caches for both the CM0+ and CM4 CPUs. Each cache is a four-way set associative with a
least recently used (LRU) replacement scheme. Four-way set associativity means that each cache has four ways per set, with

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 Nonvolatile Memory

each way containing a valid bit, tag, and data. The cache looks at all of the ways in a selected set, checking for validity and a
matching tag. These caches can be enabled/disabled through the FLASHC_CM0/4_CA_CTL.CA_EN registers.

Register Bit Field and Bit Name Description

Cache enable:
CM0_CA_CTL[32:0] CA_EN[31] 0: Disabled
1: Enabled
Cache enable:
CM4_CA_CTL[32:0] CA_EN[31] 0: Disabled
1: Enabled

The cache supports faster flash memory reads when enabled. On a read transfer “miss”, however, a normal flash controller
access will occur.

Cache Prefetch. The caches support pre-fetching through the CM0/4_CA_CTL.PREF_EN register.

Table 14-3. CM0/4 Cache Control Prefetch Enable Register Values and Bit Field
Register Bit Field and Bit Name Description
Prefetch enable:
CM0_CA_CTL[32:0] PREF_EN[30] 0: Disabled
1: Enabled
Prefetch enable:
CM4_CA_CTL[32:0] PREF_EN[30] 0: Disabled
1: Enabled

If prefetch is enabled, a cache miss results in a 16 B refill for 14.2 Flash Memory Programming
the missing data and a 16 B prefetch for the next sequential
data. The prefetch data is stored in a temporary buffer and is
only copied to the cache when a read transfer “misses” and 14.2.1 Features
requires that data. ■ SROM API library for flash management through system
calls such as Program Row, Erase Flash, and Blow
14.1.5 Read While Write (RWW) Support eFuse
The PSoC 6 MCU supports read operations on one area ■ System calls can be performed using CM0+, CM4, or
while programming/erasing in another area. This is DAP
implemented to support firmware upgrades and parallel
tasks in the dual-core system. The application flash contains 14.2.2 Architecture
eight sectors, each 256KB in size. The AUXFlash and
SFlash are additional sectors apart from the main flash. Flash programming operations are implemented as system
calls. System calls are executed out of SROM in Protection
The RWW feature is available between sectors – you can Context 0. System calls are executed inside CM0+ NMI. The
read/execute from one sector while there is an ongoing system call interface makes use of IPC to initiate an NMI to
write/erase operation in another sector. However, when the CM0+.
code execution/read is in the last 16 bytes of a given sector
(say sector 0) and the flash write/erase operation is in the System calls can be performed by CM0+, CM4, or DAP.
next sector (sector 1), an RWW violation may occur if Each of them have a reserved IPC structure (used as a
prefetch is enabled. This is because prefetch will fetch the mailbox) through which they can request CM0+ to perform a
next 16 bytes of data, which is part of sector 1 while a write system call. Each one acquires the specific mailbox, writes
operation is underway in the same sector. This will result in the opcode and argument to the data field of the mailbox,
a fault and should be considered during firmware design. and notifies a dedicated IPC interrupt structure. This results
Firmware can be designed to place dead code in the last 16 in an NMI interrupt in CM0+. The following diagram
bytes of every sector making sure the last 16 bytes of a illustrates the system call interface using IPC.
sector are never accessed or can disable prefetch during a
flash write/erase operation.

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 Nonvolatile Memory

Figure 14-3. System Call Interface Using IPC

IPC Structure 0
Control
Reserved for M0+ Access
Data (32 bytes)

IPC Structure 1
Control IPC Interrupt
Reserved for M4 Access M0+ NMI
Data (32 bytes) Structure 0

IPC Structure 2
Control
Reserved for DAP Access
Data (32 bytes)

Table 14-4. IPC Structure

Master IPC Structure Resource Used
M0+ IPC_STRUCT0
M4 IPC_STRUCT1
DAP IPC_STRUCT2
Access Point IPC Structure Resource Used
CM0+ NMI interrupt IPC_INTR_STRUCT0

The PSoC 6 MCU’s IPC component carries only a single 32- ■ The result is to be passed in SRAM: CM0+ writes the
bit argument. This argument is either a pointer to SRAM or a result in SRAM and releases the IPC structure. The
formatted opcode or argument value that cannot be a valid requester knows that the result is ready from the
SRAM address. The encoding used for DAP and the CM4 or RELEASE interrupt.
CM0+ is slightly different. ■ The result is scalar ( 32 bits) and there is no SRAM to
pass the result: in this case, the CM0+ writes the result
DAP. If (opcode + argument) is less than or equal to 31 to the data field of the IPC structure and releases it. The
bits, store them in the data field and set the LSb of the data requester can read the data when the IPC structure lock
field as ‘1’. Upon completion of the call, a return value is is released. The requester polls the IPC structure to
passed in the IPC data register. For calls that need more know when it is released.
argument data, the data field is a pointer to a structure in
SRAM (aligned on a word boundary) that has the opcode External programmers program the PSoC 6 MCU flash
and the argument. So it is a pointer if and only if the LSb is memory using the JTAG or SWD protocol by sending the
0. commands to the DAP. The programming sequence for
PSoC 6 MCUs with an external programmer is given in the
CM4 or CM0+. A pointer is always used to structure SRAM. PSoC 6 MCU Programming Specifications. Flash memory
Commands that are issued as a single word by DAP can still can also be programmed by the CM4/CM0+ CPU by
be issued by CM0+ or CM4, but use an SRAM structure accessing the IPC interface. This type of programming is
instead. typically used to update a portion of the flash memory as
part of a bootload operation, or other application
The NMI interrupt handler for system calls works as follows. requirement, such as updating a lookup table stored in the
■ If the ROM boot process code is not initialized in the flash memory. All write operations to flash memory, whether
protection state (PROTECTION is still at its default/reset from the DAP or from the CPU, are done through the CM0+.
value UNKOWN), the NMI calls have no effect and the
handler returns.
■ A jump table is used to point to the code in ROM or flash.
This jump table is located in ROM or flash (as configured
in SFlash).
The IPC mechanism is used to return the result of the
system call. Two factors must be considered.

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14.3 System Call Implementation

14.3.1 System Call via CM0+ or CM4
System calls can be made from the CM0+ or CM4 at any
point during code execution. CM0+ or CM4 should acquire
the IPC_STRUCT reserved for them and provide arguments
in either of the methods described above and notify IPC
interrupt 0 to trigger a system call.

14.3.2 System Call via DAP

If the device is acquired, then the boot ROM enters “busy-
wait loop” and waits for commands issued by the DAP. For a
detailed description on acquiring the device see the PSoC 6
MCU Programming Specifications.

14.3.3 Exiting from a System Call

When the API operation is complete, CM0+ will release the
IPC structure that initiated the system call. If an interrupt is
required upon release, the corresponding mask bit should
be set in IPC_INTR_STRUCT_INTR_MASK.RELEASE[i].
The exit code must also restore the CM0+ protection context
(PROT_MPU_MS_CTL.PC) to the one that was backed up
in PROT_MPU_MS_CTL.PC_SAVED.

14.3.4 SRAM Usage

2KB of SRAM [TOP_OF_SRAM – 2KB, TOP_OF_SRAM] is
reserved for system calls and 1KB of SRAM
[TOP_OF_SRAM – 3KB, TOP_OF_SRAM – 2KB] is used by
SROM boot and should not be part of noinit RAM.
TOP_OF_SRAM is the last address of SRAM.

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14.4 SROM API Library

SROM has two categories of APIs:
■ Flash management APIs – These APIs provide the ability to program, erase, and test the flash macro.
■ System management APIs – These APIs provide the ability to perform system tasks such as checksum and blowing
eFuse.
Table 14-5 shows a summary of the APIs.

Table 14-5. List of System Calls

API Access Allowed
System Call Opcode Description
Category Normala Secure Dead
Returns die ID, major/minor ID, and
Cypress ID 0x00 SYS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
protection state
Blow eFuse Bit 0x01 Blows the addressed eFuse bit SYS DAP None None
Read eFuse Byte 0x03 Reads addressed eFuse byte SYS CM0+, CM4, DAP CM0+, CM4, DAP None
Pre-program, erase, and program the
Write Row 0x05 FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
addressed flash row
Program Row 0x06 Programs the addressed flash row FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
Erase All 0x0A Erases all flash FLS CM0+, CM4, DAP None DAP
Reads either the whole flash or a row
Checksum 0x0B of flash, and returns the sum of each FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
byte read
Configures flash macro as per
FmTransitionToLpUlp 0x0C SYS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
desired low-power mode
Computes the hash value of the
Compute Hash 0x0D SYS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
mentioned flash region
Copies data from addressed source
ConfigureRegionBulk 0x0E SYS None None None
to addressed destination
Executes the code located at the
DirectExecute 0x0F
provided address
SYS DAPb None None

Erase Sector 0x14 Erases the addressed flash sector FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
Provides system reset to either or
Soft Reset 0x1B SYS CM0+, CM4, DAP DAPc CM0+, CM4
both cores
Erase Row 0x1C Erases the addressed flash row FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
Erases the addressed flash
Erase Subsector 0x1D FLS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
subsector
Generates the hash of the objects
GenerateHash 0x1E SYS CM0+, CM4, DAP None None
indicated by the table of contents
Returns the unique ID of the die from
ReadUniqueID 0x1F SYS CM0+, CM4, DAP CM0+, CM4, DAP CM0+, CM4, DAP
SFlash
CheckFactoryHash 0x27 Checks if FACTORY HASH is valid SYS CM0+, CM4, DAP None None
TransitionToRMA 0x28 Convert part to RMA life cycle SYS None CM0+, CM4, DAP None
ReadFuseByteMargin 0x2B Marginally reads eFuse SYS CM0+, CM4, DAP CM0+, CM4, DAPd None
Blows required eFuses to transition CM0+, CM4,
TransitionToSecure 0x2F to SECURE or SYS None None
SECURE_WITH_DEBUG DAPe

a. Refer to Device Security chapter on page 212.

b. Allowed only if SFLASH.DIRECT_EXECUTE_DISABLE = 0.
c. DAP has no access if secure eFuse is blown.
d. DAP has no access if secure eFuse is blown, but access is allowed in SECURE_WITH_DEBUG life cycle
e. Only allowed in the NORMAL_PROVISIONED life-cycle stage.

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14.5 System Calls

Table 14-5 lists all the system calls supported in PSoC 6 MCUs along with the function description and availability in device
protection modes. See the Device Security chapter on page 212 for more information on the device protection settings. Note
that some system calls cannot be called by the CM4, CM0+, or DAP as given in the table. The following sections provide
detailed information on each system call.

14.5.1 Cypress ID
This function returns a 12-bit family ID, 16-bit silicon ID, 8-bit revision ID, and the current device protection mode. These
values are returned to the IPC_STRUCT_DATA register if invoked with IPC_STRUCT_DATA[0] set to ‘1’. Parameters are
passed through the IPC_STRUCT_DATA register.
Note that only 32 bits are available to store the return value in the IPC structure. Therefore, the API takes a parameter ID type
based on which it will return family ID and revision ID if the ID type is set to ‘0’, and silicon ID and protection state if the ID type
is set to ‘1’.

Table 14-6. Cypress ID

Cypress IDs Memory Location Data
Family ID [7:0] 0xF0000FE0 Part Number [7:0]
Family ID [11:8] 0xF0000FE4 Part Number [3:0]
Major Revision 0xF0000FE8 Revision [7:4]
Minor Revision 0xF0000FEC Rev and Minor Revision Field [7:4]
Silicon ID SFlash Silicon ID [15:0]
Protection state MMIO Protection [3:0]

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x00 Silicon ID opcode.
0 - returns 0. Read family ID and revision ID from SFlash
Bits [15:8] ID type.
1 - returns 16-bit silicon ID and protection state
Bits [0] 0x1 Indicates that all the arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored.
Bits [31:0] SRAM_SCRATCH_ADDR
This must be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x00 Silicon ID opcode.
0 - returns 12-bit family ID and revision ID
Bits[15:8] ID type.
1 - returns 16-bit silicon ID and protection state
Bits[0] 0xXX Not used (don't care).

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Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
If ID type = 0, Family ID Lo
Bits [7:0]
If ID type = 1, Silicon ID Lo See the PSoC 61 datasheet/PSoC 62 datasheet for silicon ID
If ID type = 0, Family ID Hi values for different part numbers.
Bits [15:8]
If ID type = 1, Silicon ID Hi
If ID type = 0, Minor Revision ID
If ID type = 1, Protection state
0: UNKNOWN
Bits [19:16] 1: VIRGIN
2: NORMAL
3: SECURE
4: DEAD See the PSoC 61 datasheet/PSoC 62 datasheet for these
If ID Type = 0 Major Revision ID values.
If ID Type = 1 Life-cycle stage
0: VIRGIN
Bits [23:20] 1: NORMAL
2: SEC_W_DBG
3: SECURE
4: RMA
Bits [27:24] 0xXX Not used (don't care).
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
If ID type = 0, Family ID Lo
Bits [7:0]
If ID type = 1, Silicon ID Lo See the PSoC 61 datasheet/PSoC 62 datasheet for silicon ID values
If ID type = 0, Family ID Hi for different part numbers.
Bits [15:8]
If ID type = 1, Silicon ID Hi
If ID type = 0, Minor Revision ID
If ID type = 1, Protection state
0: UNKNOWN
Bits [19:16] 1: VIRGIN
2: NORMAL
3: SECURE
4: DEAD
If ID Type = 0 Major Revision ID
If ID Type = 1 Life-cycle stage
0: VIRGIN
Bits [23:20] 1: NORMAL
2: SEC_W_DBG
3: SECURE
4: RMA
Bits [27:24] 0xXX Not used (don't care).
Bits [31:28] 0xA Success status code.

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14.5.2 Blow eFuse Bit

This function blows the addressed eFuse bit. The read value of a blown eFuse bit is ‘1’ and that of an unblown eFuse bit is ‘0’.
These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA
register.
The Blow eFuse Bit function should be called with default boot clock configuration settings. This can be achieved by setting
SFLASH.TOC2_FLAGS.CLOCK_CONFIG as 0x3. For more information on the boot code configuration, see the Boot
Code chapter on page 193.
Other valid clock settings depend on the use of the FLL:
■ If you are not using the FLL, set CLK_HF[0] = 8 MHz.
■ If you are using the FLL and CLK_ROOT_SELECT.ROOT_DIV = DIV_BY_2, valid CLK_HF[0] frequencies are 25 MHz
and 50 MHz.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x01 Blow eFuse bit opcode.
Bits [23:16] Byte Address
Bits [15:12] Macro Address Refer to the Device Security chapter on page 212 for more details.
Bits [10:8] Bit Address
Bits [0] 0x1 Indicates that all the arguments are passed in DATA.

Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

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14.5.3 Read eFuse Byte

This function returns the eFuse contents of the addressed byte. The read value of a blown eFuse bit is ‘1’ and that of an
unblown eFuse bit is ‘0’. These values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the
IPC_STRUCT_DATA register.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x03 Read eFuse bit opcode.
Bits [23:8] eFuse Address Refer to the eFuse Memory chapter on page 210 for more details.
Bits [0] 0x1 Indicates all arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x03 Read eFuse bit opcode.
Bits [23:8] eFuse Address Refer to the eFuse Memory chapter on page 210 for more details.
Bits [7:0] 0xXX Not used (don't care).

Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [23:0] eFuse byte Byte read from eFuse if status is success; otherwise, error code.
Bits [27:24] 0xXX Not used (don't care).
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] eFuse byte Byte read from eFuse if status is success; otherwise, error code.
Bits [27:24] 0xXX Not used (don't care).
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

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14.5.4 Write Row

This function is used to program the flash. You must provide data to be loaded and the flash address to be programmed. The
WriteRow parameter performs pre-program and erase, and then programs the flash row with contents from the row latch.
The PSoC 6 MCU supports the Read While Write (RWW) feature, which allows flash to be read from a sector that is not
programmed/erased during a program/erase of another sector. Each row is of 512 bytes in size.
The API is implemented in three phases to make it non-blocking. The first phase sets up the flash for pre-program and erase
operations and returns to the user code by exiting from NMI without releasing the IPC structure that invoked the API. Now,
user code and interrupts can be handled but no NMI can be invoked.
Upon completion of the erase, an interrupt is generated by the flash macro, which will invoke the second phase of the
WriteRow API to complete the ongoing erase operation successfully and start the program operation. API returns from NMI to
user code after it sets up for program operation.
Upon completion of the program, an interrupt is generated by the flash macro, which will invoke the third phase of the
WriteRow API to complete the ongoing program operation successfully; this completes the WriteRow API. SROM API will
now return the pass or fail status and releases the IPC structure.
This API can also be called in blocking mode by setting the blocking parameter as ‘1’, in which case the API will return only
after all flash operation completes.
The API returns a fail status if you do not have write access to flash according to SMPU settings. See the CPU Subsystem
(CPUSS) chapter on page 32 for more details. After flash program operation is complete, the API will optionally compare the
flash row with the contents in row latch for data integrity check. The function returns 0xF0000022 if the data integrity check
fails.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operations.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.
Note that the device should not be reset or transitioned into Hibernate or Deep Sleep power modes until the flash write is
complete.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x05 Write Row opcode.
Bits[23:16] 0xXX Not used
Blocking: 0x01 – API blocks CM0+
Bits[15:8]
Other values - Non-blocking
0 - Read operation is allowed on the
sector that is not being erased/
Bit [2] programmed
1 - Read operation is stalled until the
erase/program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled

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Address Value to be Written Description

SRAM_SCRATCH Register + 0x04
Verify row:
Bits [23:16] 0 - Data integrity check is not performed
1 - Data integrity check is performed
Bits [31:24], Bits [15:0] 0xXX Not used (don't care).
SRAM_SCRATCH Register + 0x08
Flash address to be programmed. This should be provided in 32-bit
Bits [31:0] system address format. For example, to program the second half-
word, provide either of the byte address 0x1000003 or 0x1000004.
SRAM_SCRATCH Register + 0x0C
Data word 0 (data provided should be
Bits [31:0] proportional to the data size provided,
data to be programmed into LSbs)
SRAM_SCRATCH Register + 0x0C + n*0x04
Bits [31:0] Data word n (data to be programmed)

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS/Program command
Bits [31:28] ongoing in background Status code (see System Call Status for details).
0xF = ERROR

14.5.5 Program Row

This function programs the addressed flash row. You must provide the data to be loaded and flash address to be
programmed. The flash row should be in the erased state before calling this function.
The function is implemented in two phases to make it non-blocking. The first phase sets up the flash for program operation
and returns to user code by exiting from NMI without releasing the IPC structure that invoked the API. Now user code and
interrupts can be handled but no NMI can be invoked.
Upon completion of the program operation, an interrupt is generated by the flash macro, which will invoke the second phase
of the ProgramRow API to complete the ongoing program operation successfully. The SROM API will return the pass or fail
status and releases the IPC structure.
After flash program operation is complete, the API will optionally compare the flash row with the contents in the row latch for
data integrity check. It returns STATUS_PL_ROW_COMP_FA if data integrity check fails. The values are returned to the
IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operations.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.
Note that the device should not be reset or transitioned into Hibernate or Deep Sleep power modes until the flash write is
complete.

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Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits[31:24] 0x06 Program Row opcode.
Skip blank check:
Bits[23:16] 0x01 – Skips the blank check step
Other – Perform blank check
Blocking: 0x01 – API blocks CM0+
Bits[15:8]
Other values - Non-blocking
0 - Read operation is allowed on the
sector that is not being erased/
Bit [2] programmed
1 - Read operation is stalled until the
erase/program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled
SRAM_SCRATCH Register + 0x04
Verify row:
Bits [23:16] 0 - Data integrity check is not performed
1 - Data integrity check is performed
Data location:
Bits [15:8] 0 - row latch
1 - SRAM
Bits[7:0] 0xXX Not used (don't care).
SRAM_SCRATCH Register + 0x08
Flash address to be programmed. This should be provided in 32-bit
Bits [31:0] system address format. For example, to program the second half-
word, provide either of the byte address 0x1000003 or 0x1000004.
SRAM_SCRATCH Register + 0x0C
Data word 0 (data provided should be
Bits [31:0] proportional to data size provided, data
to be programmed into LSbs)
SRAM_SCRATCH Register + 0x0C + n*0x04
Bits [31:0] Data word n (data to be programmed)

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS/Program command
Bits [31:28] ongoing in background Status code (see System Call Status for details).
0xF = ERROR

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14.5.6 Erase All

This function erases the entire flash macro specified. This API will erase only the main flash array. The API will check whether
all data is ‘0’ to confirm whether the erase is successful. It will return CHECKSUM_NON_ZERO error status if a non-zero
word is encountered in the available flash.
The values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA
register.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operation.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x0A Erase All opcode.
0 - Read operation is allowed on the
sector that is not being erased/
Bit [2] programmed
1 - Read operation is stalled until the
erase/program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled
Bits [0] 1 Indicates that all the arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x0A Erase All opcode.
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled

Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [23:20] 0x00
Bits [27:24] 0xXX Not used (don't care).
Bits [31:28] 0xA Success status code

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Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:20] 0x00
Bits [27:24] 0xXX Not used (don't care).
Bits [31:28] 0xA Success status code

14.5.7 Checksum
This function reads either the entire flash or a row of flash, and returns the sum of each byte read. Bytes 1 and 2 of the
parameters select whether the checksum is performed on the entire flash or on a row of flash. This function will inherit the
identity of the master that called the function. Hence if a non-secure master requests for either the whole or row checksum of
a secured flash, then the fault exception will be raised by the hardware.
The values are returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA
register.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x0B Checksum opcode.
0 - application
Bits [23:22] 1 - AUXFlash Flash region.
other - supervisory
0 - row
Bits [21] Whole flash.
1 - whole flash
Bits [20:8] Row ID.
Bits [0] 1 Indicates that all the arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x0B Checksum opcode.
0 - application
Bits [23:22] 1 - AUXFlash Flash region.
2 - supervisory
0 - row
Bits [21] Whole flash.
1 - whole flash
Bits [20:8] Row ID.
Bits [0] 0

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Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [23:0] Checksum Checksum if status is SUCCESS
Bits [27:24] 0xXX Not used (don’t care)
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] Checksum Checksum if status is SUCCESS
Bits [27:24] 0xXX Not used (don’t care)
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.8 FmTransitionToLpUlp
This system call configures the required flash macro from trim bits when transitioning from LP to ULP mode or vice-versa.
This function takes approximately 20 µs; reads from flash are stalled during this time.

Parameters if DAP/CM0+/CM4 is Master and SRAM is used

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x0C Opcode for FmTransitionToLpUlp.
Bits [23:2] 0xXX Not used (don’t care)
0 - Transition to LP
Bit [1] Transition mode
1 - Transition to ULP
Bits [0] 0xXX Not used (don’t care)

Parameters if DAP/CM0+/CM4 is Master and SRAM is not used

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x0C Opcode for FmTransitionToLpUlp.
Bits [23:2] 0xXX Not used (don’t care)
0 - Transition to LP
Bit [1] Transition mode
1 - Transition to ULP
0 - Parameters are in address pointed to
Bit [0] by IPC_DATA Parameter location
1 - Parameters are in IPC_DATA

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Return if DAP/CM0+/CM4 Invoked the System Call and SRAM is used

Address Return Value Description

SRAM_SCRATCH Register
0xA = SUCCESS
Bits [31:28] Status code
0xF = ERROR
Bits [23:0] Error code (if any) Error code

Return if DAP/CM0+/CM4 Invoked the System Call and SRAM is not used

Address Return Value Description

IPC_STRUCT_DATA Register
0xA = SUCCESS
Bits [31:28] Status code
0xF = ERROR
Bits [23:0] Error code (if any) Error code

14.5.9 Compute Hash

This function generates the hash of the flash region provided using the formula:
H(n+1) = {H(n)*2+Byte}% 127; where H(0) = 0
This function returns an invalid address status if called on an out-of-bound flash region. Note that CM0+ will inherit the
protection context of the master, which invoked it before performing hash. The values are returned to the
IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x0D Compute hash opcode.
Bits[23:16] 0xXX Not used (don't care).
0x01 - CRC8 SAE
Bits[15:8] Type
others - Basic hash
Bits[7:0] 0xXX Not used (don't care)
SRAM_SCRATCH Register + 0x04
Bits [31:0] Start address (32-bit system address of the first byte of the data).
SRAM_SCRATCH Register + 0x08
0 – 1 byte
Bits [31:0] Number of bytes.
1 – 2 bytes, and so on

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Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] Hash of the data Hash of data if status is SUCCESS.
Bits [27:24] 0xXX Not used (don't care).
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.10 ConfigureRegionBulk
This API writes a 32-bit data value to a set of contiguous addresses. It cannot be used to configure protected registers or
flash. The Start and End addresses of the region are configurable but must be within a writable area. The region must also be
32-bit aligned. The data will be written to the region starting at the start address up to and including the memory at the end
address. The start address must be lower than the end address or the API will return an error status.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits [31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x0E Configure region bulk opcode.
Bits [23:0] 0xXX Not used (don't care).
SRAM_SCRATCH Register + 0x04
Bits [31:0] Start address 32-bit system address of the first byte of the data
SRAM_SCRATCH Register + 0x08
Bits [31:0] End address 32-bit system address of the first byte of the data
SRAM_SCRATCH Register + 0x0C
Bits [31:0] Data Data to be written to each 32-bit address from start to end

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] Error Code (if any) Error Code
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

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14.5.11 DirectExecute
This function directly executes code located at a configurable address. This function is only available in normal life-cycle state
if the DIRECT_EXECUTE_DISABLE bit is 0.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x0F Direct Execute Opcode
Bits [23:2] Address [21:0] Address of function to execute
0 - SRAM
Bit [1] Location of function to execute
1 - Flash
Bit [0] 1 Indicates that all arguments are passed through DATA

Return if DAP Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] Error Code (if any) Error Code
Bits [31:28] 0xF = ERROR Does not return any status on success.

14.5.12 Erase Sector

This function erases the specified sector. Each sector consists of 512 rows. The values are returned to the
IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operations.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.
Note that the device should not be reset or transitioned into Hibernate or Deep Sleep power modes until the erase is
complete.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x14 Erase Sector opcode.
0x01 - Set FM interrupt mask
Bits[23:16] Interrupt mask
Other - Do not set FM interrupt mask
Blocking: 0x01 – API blocks CM0+
Bits[15:8]
Other values – Non-blocking

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Address Value to be Written Description

0 - Read operation is allowed on the
sector that is not being erased/
Bit [2] programmed
1 - Read operation is stalled until the
erase/program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled
SRAM_SCRATCH Register + 0x04
Flash address to be erased. Should be provided in 32-bit system
address format. For example, to erase the second sector you need to
Bits [31:0]
provide the 32-bit system address of any of the bytes in the second
sector.

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.13 Soft Reset

This function resets the system by setting CM0+ AIRCR system reset bit. This will result in a system-wide reset, except debug
logic. This API can also be used for selective reset of only the CM4 core based on the ‘Type’ parameter. The values are
returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x1B Soft Reset opcode.
0 - System reset
Bits [7:1] Type of reset
1 - Only CM4 resets
Bits[0] 0x1 Indicates all arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x1B Soft Reset opcode.
0 - System reset
Bits [7:1] Type of reset
1 - Only CM4 resets
Bits [0] 0xXX Not used (don't care).

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Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.14 Erase Row

This function erases the specified row. You must provide the address of the row that needs to be erased. The values are
returned to the IPC_STRUCT_DATA register. Parameters are passed through the IPC_STRUCT_DATA register.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operations.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description
IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be
Bits [31:0] SRAM_SCRATCH_ADDR
a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x1C Erase row opcode.
Bits[23:16] 0xXX
0x01 - API blocks CM0+
Bits[15:8]
Other - Non-blocking
0 - Read operation is allowed on the sector
that is not being erased/programmed
Bit [2]
1 - Read operation is stalled until the erase/
program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled
SRAM_SCRATCH Register + 0x04
Flash address to be erased. This should be provided in the 32-bit
system address format. For example, to erase the second row you
Bits [31:0] Address
need to provide the 32-bit system address of any of the bytes in the
second row.

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Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.15 Erase Subsector

This function erases the specified subsector, which consists of 8 rows. The values are returned to the IPC_STRUCT_DATA
register. Parameters are passed through the IPC_STRUCT_DATA register.
Note that to be able to perform flash writes, the VCCD should be more than 0.99 V. If the device operating voltage is less than
0.99 V (the 0.9-V mode of operation), follow this sequence to perform any flash write operations.
1. Write the appropriate registers to increase voltage from 0.9 V to 1.1 V. Refer to Power Supply on page 220 for details on
how to switch voltages.
2. Write VCC_SEL = 1.
3. Perform the flash write operations.
4. Write the appropriate registers to drop the regulated voltage from 1.1 V to 0.9 V.
5. Write VCC_SEL = 0.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must be a
Bits [31:0] SRAM_SCRATCH_ADDR
32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x1D Erase subsector opcode.
Bits [23:16] 0xXX Not used (don't care).
0x01- API blocks CM0+
Bits [15:8]
Other - Non-blocking
0 - Read operation is allowed on the
sector that is not being erased/
Bit [2] programmed
1 - Read operation is stalled until the
erase/program operation is complete
0 - HV cycles are firmware controlled
Bit [1]
1 - HV cycles are hardware controlled
SRAM_SCRATCH Register + 0x04
Flash address to be erased. This should be provided in 32-bit system
address format. For example, to erase the second subsector you
Bits [31:0] Address
need to provide the 32-bit system address of any of the bytes in the
second subsector.

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Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [23:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.16 GenerateHash
This function returns the truncated SHA-256 of the Flash boot programmed in SFlash. This function gets the Flash Boot size
from the TOC. This function is typically called to confirm that the hash value to be blown into eFuse matches what the ROM
Boot expects.
This function returns the number of zeros of the SECURE_HASH

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits[31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits[31:24] 0x1E Opcode for GenerateHash
0x1 - Return the factory hash
Bits[15:8] Other - Return hash of all objects per
TOC1 and TOC2

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits[23:0] Error code (if any) See System Call Status for details
0xA = SUCCESS
Bits[31:28] Status code (See System Call Status for details)
0xF = ERROR
SRAM_SCRATCH Register + 0x04
Bits[31:0] HASH_WORD0
SRAM_SCRATCH Register + 0x08
Bits[31:0] HASH_WORD1
SRAM_SCRATCH Register + 0x0C
Bits[31:0] HASH_WORD2
SRAM_SCRATCH Register + 0x10
Bits[31:0] HASH_WORD3
SRAM_SCRATCH Register + 0x14
Bits[31:0] HASH_ZEROS

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 Nonvolatile Memory

14.5.17 ReadUniqueID
This function returns the unique ID of the die from SFlash.

Parameters if DAP/ CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits[31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits[31:24] 0x1F Opcode for ReadUniqueID
Bits[15:0] Not Used (Don't care)

Return if DAP/ CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits[23:0] DIE_LOT if SUCCESS See System Call Status for details
0xA = SUCCESS
Bits[31:28] Status code (see System Call Status for details)
0xF = ERROR
SRAM_SCRATCH Register + 0x04
Bits[31:0] DIE_ID0
SRAM_SCRATCH Register + 0x08
Bits[31:0] DIE_ID1

14.5.18 CheckFactoryHash
This function generates the FACTORY_HASH according to the TOC1 and compares the value with the FACTORY1_HASH
eFuse value.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x27 CheckFactoryHash Opcode
Bit [0] 1 Indicates all arguments are passed in DATA.

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits [31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x27 CheckFactoryHash Opcode

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Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.19 TransitionToRMA
This function converts the part from SECURE, SECURE_WITH_DEBUG, or NORMAL to the RMA life-cycle stage. This API
performs eFuse programming, VDD should be set to 2.5 V for successful programming.
This function uses Flash Boot functions. The stack consumed by these functions is around 700 bytes. This function returns
STATUS_EMB_ACTIVE failure code if any active embedded flash operations are going on.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits [31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:0] 0x28 Transition to RMA opcode
SRAM_SCRATCH + 0x04
Bits [31:0] Object Size in Bytes (including itself)
SRAM_SCRATCH + 0x08
Bits [31:0] Command ID (0x120028F0)
SRAM_SCRATCH + 0x0C
Bits [31:0] Unique ID word 0
SRAM_SCRATCH + 0x10
Bits [31:0] Unique ID word 1
SRAM_SCRATCH + 0x14
Bits [31:0] Unique ID word 2
SRAM_SCRATCH + 0x18
Bits [31:0] Signature of RMA certificate

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 Nonvolatile Memory

Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

14.5.20 ReadFuseByteMargin
This API returns the eFuse contents of the addressed byte read marginally. The read value of a blown bit is ‘1’ and of a not
blown bit is ‘0’.

Parameters if DAP is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
Bits [31:24] 0x2B Opcode for ReadFuseByteMargin
0 - Low resistance, –50% from nominal
1 - Nominal resistance
Bits [23:20] (default read condition) Margin control
2 - High resistance (+50% from nominal)
Other - 100% from nominal
Bits [19:8] eFuse address (0, 1… 511)
1 - Indicates all arguments are passed
Bit [0]
from DATA

Parameters if CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits [31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x2B Opcode for ReadFuseByteMargin
0 - Low resistance, –50% from nominal
1 - Nominal resistance
Bits [23:20] (default read condition) Margin control
2 - High resistance (+50% from nominal)
Other - 100% from nominal
Bits [19:8] eFuse address (0, 1… 511)
1 - Indicates all arguments are passed
Bit [0]
from DATA

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Return if DAP Invoked the System Call

Address Return Value Description

IPC_STRUCT_DATA Register
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR
Bits [23:0] Byte read from eFuse See System Call Status for details.

Return if CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR
Bits [23:0] Byte read from eFuse See System Call Status for details.

14.5.21 TransitionToSecure
This API validates the FACTORY_HASH value and programs the SECURE_HASH, secure access restrictions, and dead
access restrictions into eFuse. This function programs the SECURE or SECURE_WITH_DEBUG eFuse to transition to the
SECURE or SECURE_WITH_DEBUG life-cycle stage. If the FACTORY_HASH or the TOC1 magic number is invalid, then
the API fails and returns status code 0xF00000b5. Note that if the Factory_HASH in eFuse is invalid, then the
TransitionToSecure API fails and the error code is written to the IPC[2].DATA register.

Parameters if DAP/CM0+/CM4 is Master

Address Value to be Written Description

IPC_STRUCT_DATA Register
SRAM address where the API parameters are stored. This must
Bits [31:0] SRAM_SCRATCH_ADDR
be a 32-bit aligned address.
SRAM_SCRATCH Register
Bits [31:24] 0x2F Transition to Secure opcode
1 - Blow Debug Fuse
Bits [15:8] Select SECURE_WITH_DEBUG or SECURE life-cycle Stage
Other - Blow Secure Fuse
SRAM_SCRATCH + 0x04
Bits [31:0] SECURE_ACCESS_RESTRICT
SRAM_SCRATCH + 0x08
Bits [31:0] DEAD_ACCESS_RESTRICT

Return if DAP/CM0+/CM4 Invoked the System Call

Address Return Value Description

SRAM_SCRATCH Register
Bits [27:0] Error code (if any) See System Call Status for details.
0xA = SUCCESS
Bits [31:28] Status code (see System Call Status for details).
0xF = ERROR

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 Nonvolatile Memory

14.6 System Call Status

At the end of every system call, a status code is written over the arguments in the IPC_DATA register or the SRAM address
pointed by IPC_DATA. A success status is 0xAXXXXXXX, where X indicates don’t care values or return data for system calls
that return a value. A failure status is indicated by 0xF00000XX, where XX is the failure code.
Note that for system calls that require access to restricted memory regions, if the client does not have access to the restricted
region, the system call may return 0xF000_0013 rather than the expected 0xF000_0008. Because of this, it is important to
ensure that arguments are passed correctly and that the memory region to access is available for read or write access.

Table 14-7. System Call Status

Status Code Description
0xAXXXXXXX Success – The X denotes a don't care value, which has a value of '0' returned by the SROM.
0xF0000001 Invalid protection state – This API is not available in current protection state.
0xF0000002 Invalid eFuse address.
0xF0000003 Invalid flash row latch address.
0xF0000004 Wrong or out-of-bound flash address.
0xF0000005 Row is write protected.
0xF0000006 Client did not use its reserved IPC structure for invoking the system call.
0xF0000008 Client does not have access to the addressed memory location.
0xF0000009 Command in progress.
0xF000000A Checksum of flash resulted in non-zero.
0xF000000B The opcode is not valid.
0xF0000013 An argument to the system call is not in a valid location.
0xF0000021 Sector erase requested on SFlash region.
0xF0000041 Bulk erase failed.
0xF0000042 Sector erase failed.
0xF0000043 Subsector erase failed.
0xF0000044 Verification of Bulk, Sector, or Subsector fails after program/erase.
0xF000000F Returned when invalid arguments are passed to the API. For example, calling Silicon ID API with ID type of 0x5.
0xF000000b5 Invalid FACTORY_HASH

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 15. Boot Code

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

System boot is defined as the process of validating and starting the product firmware. PSoC 6-2M has 64KB of embedded
SROM, which stores the firmware to begin the boot process. This firmware is called ROM boot. The second stage of the boot
process takes place in SFlash and is called Flash boot. The main function of the boot process is to configure the system
(apply trims, configure access, and set protection settings according to the product life-cycle stage), authenticate the
application, and transfer control to the application.

15.1 Features
The PSoC 6 boot code supports the following features:
■ After reset, the boot code starts execution from ROM on the CM0+.
■ The boot process consists of two parts – ROM boot process and Flash boot process.
■ The ROM boot code applies life-cycle stage and protection state.
■ The ROM boot code validates the integrity of the Flash boot process before starting it.
■ The Flash boot code validates the integrity of the user application before starting it when the device in the SECURE life-
cycle stage. User application validation may optionally be enabled in the NORMAL life-cycle stage.

15.2 ROM Boot

The boot code starts execution from ROM. The ROM boot code applies trims and configurations, and validates the integrity of
the flash boot process before starting it.

15.2.1 Data Integrity Checks

ROM boot uses a Table of Contents (TOC) data structure to locate various objects that are stored in both application flash and
SFlash. The location of some of these objects is fixed in the factory while other object locations are fixed at the original
equipment manufacturer (OEM). The TOC is split into two parts – TOC1 and TOC2 – that correspond to objects fixed in the
factory and objects fixed at OEM, respectively. TOC1 and TOC2 are stored in SFlash.
The data integrity of selected objects listed at the beginning of TOC1 must be verified at the OEM before transitioning the part
to the SECURE life-cycle stage. The FACTORY_HASH is generated using SHA-256, which is the concatenation of the
objects to be verified in TOC1. The FACTORY_HASH is stored in eFuse before the device leaves Cypress. The device
validates the FACTORY_HASH as part of the TransitionToSecure system call.
The data integrity of selected objects in both TOC1 and TOC2 must be verified as part of authentication of Flash boot by ROM
boot in the SECURE life-cycle stage. A 128-bit truncated SHA-256 value known as the SECURE_HASH is used to check the

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 Boot Code

integrity of these objects. If the TOC structures fail integrity checks, then the RTOC structures are checked for validity. If the
RTOC structures are valid, then the boot process uses the RTOC structures in place of the TOC structures. The
SECURE_HASH is programmed automatically during the TransitionToSecure system call. If the TransitionToSecure system
call fails, it will exit before programming the SECURE_HASH in eFuse. See System Call Status on page 192 for more
information.
A summary of the objects used in the data integrity checks is shown in Figure 15-1. The TOC structure formats are outlined in
Table 15-1 to Table 15-3.
Figure 15-1. Objects, Memory Regions, and Stages of Boot Process for Data Integrity Checks
Secure_HASH
Factory_HASH
DAP Configs
LifeCycle State
eFuse (OTP)

eFuse cells can be programmed

from 0 to 1, but not back to 0.
Public Key

TOC 2 User Application Code

TOC 1 Public Key Digital Signature

ROM Factory_HASH (Normal Mode)
User Application Block
Code Secure_HASH (Secure Mode) Flash Boot
Code
(Fixed)
Trim Values
& Misc

Factory_Hash is only used to SFlash

validate that the device has not
been modified before the
transition to Secure mode.
In Secure mode, Flash Boot,
Trim values, TOC1, TOC2, and
Public key are validated with
Secure_HASH in eFuse.

Table 15-1. TOC1 Format

Offset from
Purpose Comments
Beginning of Row
0x00 Object size in bytes for CRC calculation starting from offset 0x00
0x04 Magic number (0x01211219)
0x08 Number of objects starting from offset 0xC to be verified for FACTORY_HASH
0x0C Unused TOC1 filled in
VIRGIN pro-
0x10 Address of Unique ID (fixed size of 12 bytes) stored in SFlash
tection state
0x14 Address of Flash boot object that includes Flash Patch object stored in SFlash by Cypress
0x18 Unused
0x1C-0x1F8 Unused
0x1FC CRC16-CCITT (the upper two bytes contain the CRC little endian value and the lower two bytes are 0)

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 Boot Code

Table 15-2. TOC2 Format

Offset from
Absolute
Beginning of SFlash Register Purpose
Address
Row
0x00 0x16007C00 TOC2_OBJECT_SIZE Object size in bytes for CRC calculation starting from offset 0x00
0x04 0x16007C04 TOC2_MAGIC_NUMBER Magic Number (0x01211220)
Address of Key Storage Flash Blocks. Note that this also marks
0x08 0x16007C08 TOC2_KEY_BLOCK_ADDR
the top of flash available.
TOC2_SMIF_CFG_- Null terminated table of pointers representing the SMIF
0x0C 0x16007C0C
STRUCT_ADDR configuration structure
0x10 0x16007C10 TOC2_FIRST_USER_APP_ADDR Address of First User Application Object
First Application Object Format (4 bytes). 0 means Basic
TOC2_FIRST_USER_APP_FOR-
0x14 0x16007C14 Application Format, 1 means Cypress Secure Application
MAT
Format, and 2 means Simplified Secure Application Format
TOC2_SECOND_USER_AP-
0x18 0x16007C18 Address of Second User Application Object (0's if none)
P_ADDR
TOC2_SECOND_USER_APP_-
0x1C 0x16007C1C Second Application Object Format (4 bytes).
FORMAT
Number of additional objects (In addition to the object included
in the FACTORY_HASH) starting from offset 0x24 to be verified
0x20 0x16007C20 TOC2_SHASH_OBJECT
for SECURE_HASH. The maximum number of additional
objects is 15.
Address of signature verification key (0 if none). The object is
0x24 0x16007C24 TOC2_SIGNATURE_VERIF_KEY
signature scheme specific. It is the public key in case of RSA.
0x1F8 0x16007DF8 TOC2_FLAGS Flash boot parameters. These fields are listed in Table 15-3.
CRC16-CCITT (the upper 2 bytes contain the CRC little endian
0x1FC 0x16007DFC TOC2_CRC_ADDR
value and the lower 2 bytes are 0)

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 Boot Code

Table 15-3. TOC2_FLAGS Bits, Default Settings, and Descriptions

TOC2_FLAGS Default
Name Description
Bits Value
CM0+ clock during boot. This clock will remain at this setting after Flash boot
execution until the OEM firmware changes it.
0 = 8 MHz IMO, no FLL
1:0 IMO/FLL clock frequency 2
1 = 25 MHz IMO + FLL
2 = 50 MHz IMO + FLL
3 = Use ROM boot clocks configuration (100 MHz)
Determines the wait window to allow sufficient time to acquire the debug port.
0 = 20 ms
1 = 10 ms
4:2 Wait window time 0 2 = 1 ms
3 = 0 ms (No wait window)
4 = 100 ms
5-7 = Reserved
Determines whether SWJ pins are configured in SWJ mode by Flash boot in
SECURE LCS.
Note: SWJ pins may be enabled later in the user code.
6:5 SWJ (debug) pin state 2 0 = Do not enable SWJ pins
1 = Do not enable SWJ pins
2 = Enable SWJ pins
3 = Do not enable SWJ pins
Determines whether the application image digital signature verification
(authentication) is performed.
0 = Authentication is enabled
8:7 App authenticate disable 0
1 = Authentication is disabled
2 = Authentication is enabled
3 = Authentication is enabled

The wait window time is configurable; however, the CRC value used to validate the TOC2 must be updated after changing the
value. New entries that need HASH can grow from the top starting at offset 0x28; entries that do not need HASH can grow
from the bottom starting at offset 0x1F8. When the device is in the SECURE life-cycle state, the TOC2 can no longer be
modified.

15.2.2 Life-cycle Stages and Protection States

SECURE and SECURE_WITH_DEBUG life-cycle stages are governed by eFuse. All life-cycle stages are irreversible once
set. Table 15-4 shows the eFuse locations that store information, access restriction settings, and life-cycle stage settings.

Table 15-4. Object Location in eFuse

Offset # of Bytes Name Description
0x00 20 Reserved Reserved for PSoC 6 MCU system usage
0x14 16 SECURE_HASH Secure objects 128-bit hash
0x24 2 Reserved Reserved
0x26 1 SECURE_HASH_ZEROS Number of zeros in SECURE_HASH
0x27 2 DEAD_ACCESS_RESTRICT Access restrictions in Dead life-cycle stage
0x29 2 SECURE_ACCESS_RESTRICT Access restrictions in Secure life-cycle stage

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 Boot Code

Table 15-4. Object Location in eFuse

Offset # of Bytes Name Description
0x2B 1 LIFECYCLE_STAGE Normal, Secure, and Secure with Debug fuse bits
0x2C 16 FACTORY_HASH FACTORY_HASH value
0x40 16 CY_ASSET_HASH CY_ASSET_HASH value
0x51 47 CUSTOMER_DATA Customer data

Normal mode access restrictions to be applied on DAP are stored in SFlash.

Table 15-5. Normal Life-cycle Stage DAP Restriction Register in SFlash

Offset # of Bytes Name Description
Access restrictions applied to DAP in NORMAL
0x1A00 2 NORMAL_ACCESS_RESTRICTIONS
life-cycle state.

The LIFECYCLE_STAGE object in eFuse is used to set the life-cycle state of the device. Table 15-6 shows the bits and the
associated settings of the LIFECYCLE_STAGE location.

Table 15-6. eFuse Bits and Life-Cycle States

Bits Field Name Description
A ‘1’ indicates that all factory trimming and testing is complete. The device is in NORMAL
0 NORMAL
mode.
A ‘1’ indicates that the device is in SECURE_WITH_DEBUG mode. Before the device is tran-
1 SECURE_WITH_DEBUG sitioned to this stage, the SECURE_HASH must have been programmed in eFuse and valid
application code must have been programmed in the main flash.
A ‘1’ indicates that the device is in SECURE mode. The SECURE_HASH must have been pro-
2 SECURE
grammed in eFuse and valid application code has been programmed in the main flash.
This life-cycle stage allows Failure Analysis (FA). The part is transitioned to the RMA life-cycle
3 RMA stage when the customer wants Cypress to perform failure analysis. The customer erases all
sensitive data before invoking the system call that transitions the part to RMA.

DAP settings for Secure and Dead protection states are set in the SECURE_ACCESS_RESTRICT0 and
DEAD_ACCESS_RESTRICT0 registers. DAP settings for the Normal protection state is set in
NORMAL_ACCESS_RESTRICTIONS in SFlash. Table 15-7 shows the format used to set the DAP settings for these states.
For more information about the protection states, see the Device Security chapter on page 212.

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 Boot Code

Table 15-7. DAP Access Restriction Registers for Normal, Secure, and Dead Protection States (all default to 0)
Bits Name Description
0 CM0_AP_DISABLE A ‘1’ indicates that this device does not allow access to the M0+ debug access port.
1 CM4_AP_DISABLE A ‘1’ indicates that this device does not allow access to the M4 debug access port.
2 SYS_AP_DISABLE A ‘1’ indicates that this device does not allow access to the system debug access port.
A ‘1’ indicates that the MPU on the system debug access port must be programmed and
locked according to the settings in the next four fields. The SYS_DISABLE bit must be left at
3 SYS_AP_MPU_ENABLE
‘0’ for this setting to matter. If the SYS_DISABLE bit is set to ‘1’, then the next four fields are
invalid. This affects only the SYS_AP. It does not affect the CM0/4 AP.
This field indicates what portion of Supervisory Flash is accessible through the system debug
access port. Only a portion of Supervisory Flash starting at the bottom of the area is exposed.
Encoding is as follows:
0: entire region
5:4 SFLASH_ALLOWED 1: one-half
2: one-quarter
3: nothing
For example, for an encoding of “2: one-quarter”, the valid code region starts at address
0x16000000 and will go up to one-quarter of the SFlash memory region.
This field indicates what portion of the MMIO region is accessible through the system debug
access port. Encoding is as follows:
7:6 MMIO_ALLOWED 0: All MMIO registers
1: Only IPC MMIO registers accessible (system calls)
2, 3: No MMIO access

The SECURE_ACCESS_RESTRICT1, DEAD_ACCESS_RESTRICT1, and NORMAL_ACCESS_RESTRICTIONS [15:8]

(SFlash) registers control debug access restriction to specific memory regions. Table 15-8 shows the format used to set these
restrictions.

Table 15-8. SECURE_ACCESS_RESTRICT1, DEAD_ACCESS_RESTRICT1, and NORMAL_ACCESS_RESTRICTIONS

[15:8] Registers (All default to 0)
Bits Name Description
This field indicates what portion of the main flash is accessible through the system
debug access port. Only the portion starting at the bottom of flash (0x1000_0000) is
exposed to the system DAP. The encoding is as follows:
0: entire region
1: seven-eighth
2: three-fourth
2:0 FLASH_ALLOWED 3: one-half
4: one-quarter
5: one-eighth
6: one-sixteenth
7: nothing
See Figure 15-2 for an example of the encoding for FLASH_ALLOWED.
This field indicates what portion of SRAM 0 is accessible through the system debug
5:3 SRAM_ALLOWED access port. Only the portion starting at the bottom of the area is exposed. Encoding is
the same as FLASH_ALLOWED.
6 UNUSED UNUSED
Disables DirectExecute system call functionality (implemented in software). See the
7 DIRECT_EXECUTE_DISABLE
Nonvolatile Memory chapter on page 164 for more information.

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 Boot Code

As an example, if you want to limit the lower one-quarter of flash of a device with 2MB of flash, a “4” is written into the
FLASH_ALLOWED field. Only the flash area between 0x1000_0000 and 0x1007_FFFF will be accessible via the SYS_DAP.
The remaining areal between 0x1008_0000 to 0x101F_FFFF is not accessible. This means that only the lower quarter of
flash can be reprogrammed, erased, or read by the debug port.
Figure 15-2. FLASH_ALLOWED with encoding “4”
0x10200000
Main Flash

Address 
0x10080000

DAP Accessable

0x10000000

As shown in Figure 15-2, if you want to limit the lower fourth of flash of a device with 2MB of flash, write a ‘4’ into the
FLASH_ALLOWED field. Only the flash area between 0x10000000 and 0x1007FFFF will be accessible via the SYS_DAP.
The remaining area between 0x10080000 to 0x101FFFFF would not be accessible. This means that only the lower fourth of
flash can be reprogrammed, erased, or read by the debug port.

15.2.3 Secure Boot in ROM Boot

At the end of the ROM boot process, the SECURE eFuse bit is checked. If the life-cycle is SECURE, then ROM boot reads
the SECURE access restrictions in eFuse and deploys the settings using the SYS_AP MPU. If the APP_AUTH_DISABLE
field of the TOC2 is not disabled, then ROM boot calculates the SECURE_HASH value from the contents of Flash boot, the
TOC1 and TOC2 structures, and the public key and compares it to the stored hash value (SECURE_HASH) in eFuse. If they
match, the Flash boot code and data are authentic. If the Flash boot code is authentic, then ROM boot will hand over the boot
process to Flash boot, which resides in SFlash. If the Flash boot is not authentic, then the boot code sets the device into the
DEAD protection state.

15.2.4 Protection Setting

ROM boot sets some of the protections units (SMPU, PPU, and MPU) during the boot process. It is recommended that these
settings are not modified.
SYS_AP DAP access restrictions are deployed by MPU15 based on access restrictions encoding stored in SFlash or eFuse.
Eight MPU structures implement the SYS_AP DAP access restrictions. If the SYS_AP MPU is disabled, the following regions
are available for access through the system debug access port.

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 Boot Code

Table 15-9. Protection Setting

Protection Structure Attribute Settings Protected Region Region Base Region Size (Bytes)
ADDR: 0x00000000
PROT_MPU15_MPU_STRUCT0 ALL 0x00000000 2G
ATT: 0x9E000000
ADDR: 0x402200F8
PROT_MPU15_MPU_STRUCT1 IPC 0x40220000 96
ATT: 0x8700007F
Work flash region protection
PROT_MPU15_MPU_STRUCT2 – – –
option is not present in PSoC 6
ADDR: 0x16000000
PROT_MPU15_MPU_STRUCT3 SFlash 0x16000000 32K (SFlash size)
ATT: 0x8E00007F
ADDR: 0x10000000
PROT_MPU15_MPU_STRUCT4 Flash 0x10000000 2M (Flash Size)
ATT: 0x9400007F
ADDR: 0x8000000
PROT_MPU15_MPU_STRUCT6 RAM0 0x08000000 512K (SRAM0 size)
ATT: 0x9200007F

Other protection units are set up during ROM boot to restrict access to various regions to ensure device security. The
following tables list those structures, the regions they protect, and the protection settings applied to those regions. The
protection settings are applied in all life-cycle stages except VIRGIN.

Table 15-10. Region Access

Region Description
Contains CM0+ protection context 0-3, debug port control, protection status, RAM, and ROM trim control
CPUSS_BOOT
registers.
EFUSE_CTL EFUSE_CTL register. Specifies retention for eFuse registers.
EFUSE_DATA Contains registers that support life-cycle setting, key storage, and other one-time-programmable data.
Specifies flash hardware block control settings including direct memory cell access addressing, write enable,
FM_CTL
and interface selection.
Bottom 2KB of SRAM Contains the system call stack.
SROM Contains system firmware that supports ROM boot and system calls.
Contains registers that support error correction, random number generation, device key locations, and other
CRYPTO MMIO
general cryptography information.
IPC MMIO Contains registers that support inter-processor communication

Table 15-11. Protection Structures

Protection Region Size
Protection Structure Attribute Settings Protected Region Region Base
(Bytes)
(Read/Write)
Write only in PC0 ATT0: 0x1515151F
PERI_MS_PPU_FX18 CPUSS_BOOT 0x40202000 512
Read Always ATT1: 0x15151515
Write only in PC0 ATT0: 0x1515151F MPU15_MAIN DAP
PERI_MS_PPU_FX59 0x40237C00 1K
Read Always ATT1: 0x15151515 MPU
PERI_MS_PPU_FX70 R/W only in PC0 ATT0: 0x0000001F FM_CTL 0x4024F000 4K

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 Boot Code

Table 15-11. Protection Structures

Protection Region Size
Protection Structure Attribute Settings Protected Region Region Base
(Bytes)
(Read/Write)
ATT0: 0x8AFFFE00 0x080FF800
PROT_SMPU_SMPU_STRUCT15 Read only in PC0 Last 2KB of SRAM 2K
ATT1: 0x80FFFE40
SROM area
containing boot
ATT0: 0x8E00FF00
PROT_SMPU_SMPU_STRUCT14 Read only in PC0 code, Crypto, and 0x00000000 24K
ATT1: 0x8700FF49
Flash macro
controls.
Disable access during
Entire Crypto MMIO
system calls with Crypto ATT0: 1F1F1F1F
PERI_MS_PPU_PR0 region during any 0x40100000 64K
enabled (all access ATT1: 1F1F1F1F crypto operation
allowed otherwise)
Disable access during
ATT0: 1F1F1F1F IPC MMIO (during
PERI_MS_PPU_PR1 system calls (all access 0x40220000 32
ATT1: 1F1F1F1F system calls)
allowed otherwise)

15.2.5 SWD/JTAG Repurposing

The TOC2 flag option SWJ_PIN_CTL provides an option that allows users to set the default state of the debug ports when in
the SECURE life cycle stage. User firmware can, at any time, change the configuration of the SWD/JTAG pins to another
mode, peripheral, configuration, or purpose. To allow debugging of such applications, a configurable ‘listen window’ is
provided in the TOC2 at offset 0x1F8 bits [4:2]. The boot process will connect and enables the JTAG/SWD interface if the
SWJ_PIN_CTL is set to 0x10 and wait for a specified time before starting application firmware. It is expected that application
firmware checks the CPUSS DP_STATUS.SWJ_CONNECTED bit and repurposes the pins only when no SWD/JTAG
connection is available.

15.2.6 Waking up from Hibernate

Waking up from Hibernate mode will result in system boot. The integrity checks on the SFlash trim values and SWD/JTAG
connection delay (listen window in Flash boot) are skipped when waking from hibernate.

15.2.7 Disable Watchdog Timer

The ROM boot code will disable the watchdog timer (WDT) if the eFuse.WDT_DISABLE bit is set.

15.2.8 ROM Boot Flow Chart

Figure 15-3 shows the ROM boot flow chart.

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 Boot Code

Figure 15-3. ROM Boot Flow Chart

RESET

Get M4 Reset Vector

I am M0+? No CM4_VECTOR_TABLE_BASE (CPUSS MMIO)
(CPUSS MMIO) Set RST SP
Goto RST PC
Yes

Get M0+ Reset Vector

PROTECTION==UNKOWN ? No CM0_VECTOR_TABLE_BASE (CPUSS MMIO)
(CPUSS MMIO) (Warm Boot Set RST SP
due to CPU Goto RST PC
Yes Reset)

Enable SRAMs

Apply initial trim settings

(eFuse)

Hash on trim No
area OK ? (SFlash)

Yes

Apply general trim

settings (SFlash)

Test Mode ? Yes

(SRSS MMIO)

No

No Secure Boot ?
(eFuse)

Yes
Deploy NORMAL
Access Restrictions Corrupt
(SFlash) Authenticate Flash Boot

PROTECTION=NORMAL
PROTECTION=SECURE

Deploy SECURE Access

Restrictions (eFuse) Deploy DEAD Access
Restrictions (eFuse)
Get Flashboot Location

PROTECTION=DEAD

Get Flashboot Location

Flash boot
Setup SysCall IPC
(NORMAL) Configure SWD/JTAG pins

Flash boot IDLE

(DEAD)
(SECURE)

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 Boot Code

15.3 Flash Boot

15.3.1 Overview
The second stage of boot, Flash boot, is entered after ROM boot has authenticated the Flash boot image if the device is in the
SECURE or SECURE_WITH_DEBUG life-cycle stage, or if the APP_AUTH_DISABLE field is not set in TOC2. In the
SECURE or SECURE_WITH_DEBUG life-cycle states, flash boot prevents an application that does not pass integrity checks
from running. The integrity checks can optionally be enabled in the NORMAL mode by setting the APP_AUTH_DISABLE field
in TOC2 to any 2-bit value other than 1. This ensures that the application originates from a valid source and has not been
altered.
The Flash boot firmware:
■ Runs on the security processor (Cortex-M0+)
■ Validates the contents of the TOC2
■ Validates the user application in the Secure life-cycle state or optionally in the Normal life-cycle state
■ Sets up the debug access port (DAP)
■ Enables system calls
■ Hands control to the user application

15.3.2 Features of Flash Boot

■ RSASSA PKCS1 V1.5 with SHA-256 User Application Signature Verification
■ 2048-bit RSA public key with pre-calculated key coefficients for RSA calculation speed increase
■ Support for all device life-cycle stages
■ Configurable debug listen window

15.3.3 Using Flash Boot

Flash boot can be used to allow only authenticated firmware to run on a given platform.
Flash boot determines the life-cycle stage, validates the TOC2, and optionally validates the firmware before transferring
execution to the user's CM0+ application code. The user's CM0+ application enables the CM4 core.
The user firmware will not execute if it is modified by third-party malicious software. The user firmware in flash is validated
using the RSA algorithm. The 2048-bit public key in SFlash and the digital signature stored with the user application are
located using the table of contents, which is located at the end of SFlash. The public key is hashed by SECURE_HASH and
is validated during boot time. If the code is defined as insecure, the device will go to dead mode with limited debug capabilities
determined by the eFuse settings.

15.3.4 Flash Boot Layout

Flash boot consists of a Header field and a Code Segment field. For hash calculation, the object size must be a multiple of
16B so zero padding is applied in the Code Segment.

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 Boot Code

Figure 15-4. Flash Boot Layout

CM0 Core[0] code and data
Code (Flash boot, Flash Patch)
Segment
Core[0] Vector Table
Flash Boot Alignment Padding
Size Core0 CPU ID/Index
Header
Core0 VT offset
Number of cores (N)
Attributes
Application ID/Version
Object Size

15.3.4.1 Header
The Flash boot header consists of:
■ The Flash boot object size
■ The Flash boot application version
■ The number of cores (set to ‘1’ for Flash boot)
■ CM0+ vector table offset
■ Cypress ID and CPU Core Index

15.3.4.2 Code Segment

The CM0 code segment consists of:
■ CM0+ vector table
■ CM0+ Flash boot code and data
■ Zero padding to make the Flash boot object a multiple of 16B

15.3.5 Flash Boot Flow Chart

The Flash boot program flow is shown in Figure 15-5. The entry point is a fixed offset in SFlash. Each section of the flow chart
is labeled with an index number. In the sections following the flow chart, explanations of each step are provided with the
associated index number.

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 Boot Code

Figure 15-5. Flash Boot Flow Chart

(0) From ROM
Boot

* Set up SP
Interrupt and
(1) * Enable IRQ (50)
System Calls
* Initialization

Dead State Handler

No
(2) Is TOC2 valid?

Yes

(4)
(30) Set Error Code
Is Hard Fault Yes
(3) Trigger a Hardfault
triggered?

No
Protection = Yes
(31) Set up SP (17)
Get App #0 Virgin?
(5)
Reset Handler
No

Idle Loop (18)

Is Reset No
(6)
Handler valid?
Lifecycle = Yes
(32)
Yes SECURE?

(7)
No (33) Protection = DEAD
No Authenticate
App?

Yes Deploy SECURE_DEAD

(34)
Access Restrictions

Is Public Key No
(8)
valid?
Enable System Calls (10) Enable System Calls

Yes

Set up DAP from AR (35) Set up DAP for AR

Is Digital No
(9)
Signature valid?

Yes Apply System Apply System

(36)
Protection Protection

No
(11) Is DAP enabled?
(10) Enable System
Calls
Yes
No
(11) Is DAP enabled?
Configure SWD/JTAG
(12)
pins
Yes

(12) Configure SWJ Pins

Wake-up from Yes
(13)
Hibernate?

No

(17) Setup-SP
Wait window
(14)
(default = 20 ms)

(18) Idle Loop

(15)
Yes Test
Mode?

No

(17) Set up SP

Launch CM0+
(16)
Idle Loop Application
(18)
( In SROM )

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 Boot Code

15.3.5.1 Entry from ROM Boot (0) 15.3.5.6 Get App #0 Reset Handler (5)
ROM boot transfers control to Flash boot after it validates Flash boot reads the application start address from the
the SFlash block and TOC1 in the user flash. TOC2 entry:
■ SFLASH_TOC2_FIRST_USER_APP_ADDR for App#0.
15.3.5.2 Basic Initialization (1)
The application format is stored in the TOC2 entry:
This stage sets the value of the stack pointer during runtime.
■ SFLASH_TOC2_FIRST_USER_APP_FORMAT for App
To support recovery from Hard-Fault exceptions during
#0.
Flash boot, this stage also enables interrupts.
The address of reset handler inside the application depends
15.3.5.3 Is TOC2 Valid? (2) on the application format.

The TOC2 may be in three states: 15.3.5.7 Is Reset Handler Valid? (6)
■ VALID: The TOC2 structure and CRC are valid. This is
the default state of the TOC2. Flash boot checks if the address of the reset handler for the
user application is in RAM, SFlash, application flash, or
■ CORRUPTED: Either the TOC2 structure or CRC value
AUXFlash.
are incorrect.
■ ERASED: The first two 32-bit words at the start of TOC2 15.3.5.8 Authenticate App? (7)
are equal to the SFlash erase value. The erased value is
0x0000_0000. Flash boot optionally authenticates a digital signature for the
application image if the TOC2_FLAGS bit
If the PROTECTION is SECURE then ERASED state is a APP_AUTH_DISABLE = 0.
part of CORRUPTED state.
If this field is set then the authentication step is skipped.
If the PROTECTION is not SECURE then ERASED state is
a special case of VALID state. In this case, Flash boot treats 15.3.5.9 Is Public Key Valid (8)
all the TOC2 entries as having a default value:
■ SFLASH_TOC2_FIRST_USER_APP_ADDR is The public key structure is filled by the user. Thus, it must be
0x1000_0000 (the start of Flash). validated to ensure the correctness of the its entries before
being used.
■ SFLASH_TOC2_FIRST_USER_APP_FORMAT is 0
(Basic Application Format). 15.3.5.10 Is Digital Signature Valid? (9)
■ SFLASH_TOC2_FLAGS = 0x0000_0000
The user application located in main flash is validated using
The other TOC2 entries will not be used when TOC2 is in the standard RSA 2048-bit algorithm (RSASSA-PKCS1-
ERASED or corrupted states. v1_5-2048). The public key used for this operation is stored
in the user public key area of SFlash.
15.3.5.4 Is Hard Fault Triggered? (3)
The application can be in one of three formats, only two of
The Flash boot test system requires a way to trigger a hard which are validated using a public key.
fault in the Flash boot code. The condition to trigger a hard-
fault is as follows: The Crypto block is used for validation and is only enabled
during the application validation process to conserve power.
1. SFLASH_FLAGS bit FB_HARDFAULT is set.
2. A 32-bit word in TOC2 at offset + 500 contains an The following figure shows the application validation flow.
address to a 32-bit word named HardFaultTrigger.
3. HardFaultTrigger value is 0x0000_0001.

15.3.5.5 Trigger a Hard Fault (4)

Flash boot can be used to trigger a hard fault for a testing
purposes.
This can be done, for example, by a 32-bit word read or
write to an unaligned address, or to an invalid memory
region.
The hard fault handler recovers the MCU into the DEAD
state branch. In this branch, an error code is set and the
DAP is enabled.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 206
 Boot Code

Figure 15-6. Application Validation

Binary Firmware
Binary (Not Encrypted)
Code Binary
Image Code
(Firmware) Application
Image Bundle

Digital
Signature
Hash
Digital
Function Signature

SHA-256
Decrypt
Public Key
( 2048-bit)
( RSA N-bit )
Calculated
Digital
Digest Decrypted
Digital
Digest

Compare Stored Digest

With Calculated Digest

Do No Invalid
Signatures
Application
Match?

Yes

Valid
Application

15.3.5.11 Enable System Calls (10) 15.3.5.15 Wait Window (14)

At this point the system calls are enabled. A table of the The CPU delays execution to allow the debug hardware to
system calls is found in SROM API Library on page 170. acquire the CM0+. The default delay time is 20 ms, but the
The function calls are access via IPC that communicate to user can set other delay options. For a SECURE mode
the CM0+ with interrupts. The SROM function device, it is recommended to set the delay to 0 as debug will
EnableSystemCall() is called to enable these system calls. not be enabled.
This delay allows the debug hardware to acquire the debug
15.3.5.12 Is DAP Enabled (11)
interface and set the operation to test mode.
Determines if the Debug Access Port (DAP) is enabled by
reading the CPUSS_AP_CTL register, that was set during 15.3.5.16 Test Mode Enable? (15)
ROM BOOT. The DAP consist of three sections: CM4 AP,
After the listen window delay, the firmware checks if the
CM0+ AP, and System AP. If any of these APs are enabled,
SRSS_TST_MODE register has either TEST_MODE or
then the DAP is considered to be enabled.
TEST_KEY_DFT_EN bit set. If either bit is set, execution is
transferred to an endless loop in SROM. This is done by
15.3.5.13 Configure SWD/JTAG Pins (12)
calling the BusyWaitLoop() ROM boot function.
The SWD and JTAG pins are configured based on the
values set in the TOC2_FLAGS bit SWJ_PIN_CTL. The 15.3.5.17 Launch CM0+ Application (16)
CPUSS_AP_CTL register will be used to set DAP.
If the TOC2 is erased and the life-cycle stage is NORMAL,
Flash boot assumes that an application is in the “Basic
15.3.5.14 Wake from Hibernate? (13)
Application Format” and the application start address is the
If the reason for the reset was wake from hibernate, skip the start of the user flash.
wait window and test mode check.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 207
 Boot Code

If the TOC2 is valid and the life-cycle stage is NORMAL, 15.3.5.18 Set Up SP (17)
then the application can be in either the Basic or Cypress
Standard Secure application formats. The SP register value for Flash boot is at the top of user
RAM.
Otherwise, the application is stored in the Cypress Secure
application format. 15.3.5.19 Idle Loop (18)
The procedure to launch a user application is: Before going to an idle loop the Flash boot sets the
1. Set CPUSS_CM0_VECTOR_TABLE_BASE to the start CPUSS_CM0_VECTOR_TABLE_BASE MMIO register to
of the user application interrupt vector table. 0xFFFF_0000.
2. Set CPUSS_CM4_VECTOR_TABLE_BASE to In this state, a NMI interrupt can wake up the device. To
0xFFFF_0000. prevent unwanted firmware access, device access
3. Perform a core reset. restrictions must be set up correctly for the appropriate life
4. After a core reset is performed ROM boot is launched cycle stage. The protection settings for each life-cycle stage
(on CM0+). are listed in Life-cycle Stages and Protection States on
page 196.
5. ROM boot checks if CPUSS_PROTECTION ! = 0, which
means ROM boot is launched on CM0+ after a core
15.3.5.20 Set Error Code (30)
reset.
6. If (5) is true, ROM boot sets SP and PC register values If the user application flash or the TOC2 was determined to
from the user interrupt vector table. The address of a be invalid, an error code will be written to IPC.DATA
user application interrupt vector table is stored at step (structure 2); this will enable to detect the cause during
(1) to CPUSS_CM0_VECTOR_TABLE_BASE. debug.
7. When ROM boot sets PC register value with the user
reset handler address, user code starts executing.

Table 15-12. Error Code

Error Name Value Description
CY_FB_STATUS_SUCCESS 0xA100_0100 Success status value
Debugger probe acquired the device in Test Mode. The Flash
CY_FB_STATUS_BUSY_WAIT_LOOP 0xA100_0101
boot entered a busy wait loop.
Application signature validation failed for the device families
where flash boot launches only one application from TOC2.
CY_FB_ERROR_INVALID_APP_SIGN 0xF100_0100 Either the application structure or a digital signature is invalid
for the device families in which Flash boot may launch either of
two applications in TOC2.
CY_FB_ERROR_INVALID_TOC 0xF100_0101 Empty or invalid TOC
CY_FB_ERROR_INVALID_KEY 0xF100_0102 Invalid public key
CY_FB_ERROR_UNREACHABLE 0xF100_0103 Unreachable code
CY_FB_ERROR_TOC_DATA_CLOCK 0xF100_0104 TOC contains invalid CM0+ clock attribute
CY_FB_ERROR_TOC_DATA_DELAY 0xF100_0105 TOC contains invalid listen window delay
CY_FB_ERROR_FLL_CONFIG 0xF100_0106 FLL configuration failed
Application structure is invalid for the device families in which
CY_FB_ERROR_INVALID_APP0_DATA 0xF100_0107
Flash boot may launch only one application from TOC2
CY_FB_ERROR_CRYPTO 0xF100_0108 Error in Crypto operation
CY_FB_ERROR_INVALID_PARAM 0xF100_0109 Invalid parameter value
CY_FB_ERROR_BOOT_HARD_FAULT 0xF100_010a A hard fault exception had happened in the Flash boot
CY_FB_ERROR_UNEXPECTED_INTERRUPT 0xF100_010B Any unexpected interrupt had happened in the Flash boot
CY_FB_ERROR_BOOTLOADER 0xF100_0140 Any bootloader error
CY_FB_ERROR_BOOT_LIN_INIT 0xF100_0141 Bootloader error, LIN initialization failed
CY_FB_ERROR_BOOT_LIN_SET_CMD 0xF100_0142 Bootloader error, LinSetCmd() failed

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 208
 Boot Code

15.3.5.21 Protection = Virgin? (31) 15.3.5.24 Deploy Access Restrictions (34)

The CPUSS_PROTECTION MMIO register value is SECURE_DEAD access restrictions are applied for entering
compared to the desired protection mode. DEAD branch from the SECURE life-cycle stage.
Assess restrictions are applied by calling the
15.3.5.22 Life Cycle = SECURE (32)
RestrictAccess() ROM boot function.
The life-cycle stage value is stored in eFuse. To determine
this value, Flash boot reads the corresponding eFuse bits. If 15.3.5.25 Set Up DAP from AR (35)
the SECURE life-cycle bit is set in eFuse, then the device is
ROM boot function GetAccessRestrictStruct() is called to
in the SECURE life-cycle stage. Otherwise, the device is in
determine which APs (access points, one of CM0+ AP, CM4,
another life-cycle stage.
and TC) are enabled. Based on this information the proper
Note: Life-cycle stage is not the same as protection mode. values are written to the CPUSS_AP_CTL register.
In this case, SECURE_WITH_DEBUG is not equal to
SECURE life-cycle stage; however, the protection state 15.3.5.26 Apply System Protection (36)
equals to SECURE for both these stages.
System protection settings are usually applied by ROM boot
15.3.5.23 Protection = DEAD (33) code before entering Flash boot. If the device enters the
DEAD branch, the system protection settings are changed.
In DEAD protection state, the system will not attempt to start Thus, Flash boot calls the ROM boot function
any flash firmware and will restrict access to system ApplyProtectionSettings() to reconfigure them.
resources to shield secure/sensitive information. The
intention is to allow a controlled set of failure analysis
capabilities only. By default, DEAD mode is open to all
debug functions and users should change to the level of
security required.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 209
 16. eFuse Memory

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The eFuse memory consists of a set of eFuse bits. When an eFuse bit is programmed, or “blown”, its value can never be
changed. Some of the eFuse bits are used to store various unchanging device parameters, including critical device factory
trim settings, device life cycle stages (see the Device Security chapter on page 212), DAP security settings, and encryption
keys. Other eFuse bits are available for custom use.

16.1 Features
The PSoC 6 MCU eFuses have the following features:
■ A total of 1024 eFuse bits. 512 of them are available for custom purposes.
■ The eFuse bits are programmed one at a time, in a manufacturing environment. The eFuse bits cannot be programmed in
the field.
■ Multiple eFuses can be read at the bit or byte level through a PDL API function call or an SROM call. An unblown eFuse
reads as logic 0 and a blown eFuse reads as logic 1. There are no hardware connections from eFuse bits to elsewhere in
the device.
■ SROM system calls are available to program and read eFuses. See the Nonvolatile Memory chapter on page 164. For
detailed information on programming eFuses, see the PSoC 6 MCU Programming Specifications.

16.2 Architecture
The PSoC 6 MCU eFuses can be programmed only in a manufacturing environment. VDDIO0 must be set to 2.5 V, and the
device must be in a specific test mode, entered through an XRES key. For more information, see the PSoC 6 MCU
Programming Specifications.
Table 16-1 shows the usage of the PSoC 6 MCU eFuse bytes.

Table 16-1. PSoC 6 MCU eFuse Byte Assignments

No. of
Offset Name Description
Bytes
0 20 Reserved Reserved for PSoC 6 MCU system usage
20 16 SECURE_HASH Secure objects 128-bit hash
36 2 Reserved Reserved for PSoC 6 MCU system usage
38 1 SECURE_HASH_ZEROS Number of zeros in SECURE_HASH
39 2 DEAD_ACCESS_RESTRICT Access restrictions in DEAD life cycle stage

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 eFuse Memory

Table 16-1. PSoC 6 MCU eFuse Byte Assignments (continued)

No. of
Offset Name Description
Bytes
41 2 SECURE_ACCESS_RESTRICT Access restrictions in SECURE life cycle stage
43 1 LIFECYCLE_STAGE Life cycle state
44 17 FACTORY_HASH, FACTORY_HASH_ZEROS Secure objects 128-bit hash plus number of zeros in the hash
61 2 Reserved Reserved for PSoC 6 MCU system usage
63 1 Unused Not used
Similar to the factory hash, but it does not include trim values
so it will be the same for all parts with the same silicon and
64 17 CY_ASSET_HASH, CY_ASSET_HASH_ZEROS
firmware version. (This is generated and written to eFuse
automatically).
81 47 CUSTOMER_DATA Custom data

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 211
 17. Device Security

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU offers several features to protect user designs from unauthorized access or copying. Selecting a secure life
cycle stage, enabling flash protection, and using hardware-based encryption can provide a high level of security.

17.1 Features
The PSoC 6 MCU provides the following device security features:
■ Nonvolatile and irreversible life cycle stages that can limit program and debug access.
■ Shared memory protection unit (SMPU) that provides programmable flash, SRAM, and register protection.
■ Cryptographic function block that provides hardware-based encryption and decryption of data and code.

17.2 Architecture
17.2.1 Life Cycle Stages and Protection States
PSoC 6 MCUs have configurable, nonvolatile life cycle stages. Life cycle stages follow a strict, irreversible progression
governed by writing to eFuse – a 1024-bit nonvolatile memory with each bit being one time programmable (OTP). The eFuse
can hold unalterable keys and trim information. See the eFuse Memory chapter on page 210 for more details of the eFuse;
see the Nonvolatile Memory chapter on page 164 for eFuse access system calls.
This chapter discusses hardware blocks used to implement device security. For system-level implementation of device
security, see AN221111 - PSoC™ 6 MCU designing a custom secured system.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 212
 Device Security

Figure 17-1. PSoC 6 MCU Life Cycle Stage Transitions

Virgin

Write
Nomal
eFuse

Normal
Write Write
Secure Secure /w
eFuse Debug
eFuse

Secure Secure w/ Debug

Write RMA
eFuse

RMA

The EFUSE_DATA_LIFECYCLE_STAGE eFuse governs the life-cycle stages.

The PSoC 6 MCU supports the following life cycle stages: EFUSE_DATA_SECURE_ACCESS_RESTRICT1
■ VIRGIN – This stage is used by Cypress during registers.
assembly and testing. During this stage, trim values and ❐ The TOC2 should optionally be programmed with the
flash boot are written into SFlash. Devices that are in correct address of the user key storage blocks in
this stage never leave the factory. In this stage, the boot flash.
ROM assumes that no other eFuse data or flash data is ❐ The TOC2 should be programmed with the user
valid. Devices are transitioned to the Normal stage application format, the starting addresses of the user
before they leave the factory. application, and the address of the public key in
■ NORMAL – This is the life cycle stage of a device after SFlash.
trimming and testing is complete in the factory. All ❐ Protection units should be set up to protect sensitive
configuration and trimming information is complete. Valid code regions.
flash boot code is programmed in the SFlash. To allow
❐ Public and private keys must be generated.
the OEM to check data integrity of trims, flash boot, and
other objects from the factory, a hash (SHA-256 In this stage, the protection state is set to Secure, and
truncated to 128 bits) of these objects is stored in eFuse. Secure DAP access restrictions are deployed. A secure
This hash is referred to as Factory_HASH. In Normal device will boot only after successful authentication of its
mode, by default, there is full debug access to the CPUs flash boot and application code.
and system. The device may be erased and After an MCU is in the Secure life cycle stage, it cannot
programmed as needed. go back to the Normal stage. SFlash cannot be pro-
■ SECURE – This is the stage of a secure device. Before grammed in this stage. The debug ports may be dis-
transitioning to this stage, ensure that the following steps abled depending on user preferences, so it is not
are complete: possible to reprogram or erase the device with a hard-
ware programmer/debugger. At this point, the firmware
❐ Secure access restrictions are programmed into the
can only be updated by invoking a bootloader, which
EFUSE_DATA_SECURE_ACCESS_RESTRICT0
must be provided as part of device firmware.
and
Access restrictions in the SECURE state can be con-
trolled by writing to the following eFuses:

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 213
 Device Security

EFUSE_DATA_SECURE_ACCESS_RESTRICT0 and cycle stage, but it cannot be transitioned to Virgin or any

EFUSE_DATA_SECURE_ACCESS_RESTRICT1. other stage. The life cycle stage stored in eFuse cannot
Code should be tested in Normal and Secure with be changed from RMA. Every time the device is reset, it
Debug stages before advancing to this stage. This is to must execute the “Open for RMA” command success-
prevent a configuration error that can cause the device fully before the device can be used
to be inaccessible for programming and therefore, A powered PSoC 6 MCU also has a volatile protection state
become unusable. that reflects its life cycle stage. The protection state is
■ SECURE_WITH_DEBUG – This is similar to the Secure determined on boot by reading the eFuse values.
stage, except that Normal access restrictions are applied Figure 17-2 illustrates the protection state transitions.
to enable debugging. Devices that are in the Secure with
Debug stage cannot be changed back to either Secure
or Normal stage.
Secure applications may also be developed in the
Normal life-cycle stage with code validation enabled.
This requires the TOC2_FLAGS.APP_AUTH_DISABLE
bits at offset 0x1F8 to be set. See the Boot Code chapter
on page 193 for more information. This method has the
advantage of being able to transition to the SECURE
life-cycle stage after testing is complete.
■ RMA – Customers can transition the device to the RMA
stage (from Secure) when they want Cypress to perform
failure analysis on the device. The customer should
erase all sensitive data (including firmware) before
invoking the system call that transitions the device to
RMA. Flash erase should be performed by calling
EraseRow/EraseSubSector/EraseSector/EraseAll.
SROM APIs five times repeatedly on the secure FLASH
region before converting the device to RMA. Erasing the
device five times eliminates any possibility of
determining the previous state of any flash cell. See the
Nonvolatile Memory chapter on page 164 for more
details on these SROM APIs.
When invoking the system call to transition to RMA, the
customer must provide a certificate that authorizes
Cypress to transition the device with a specific Unique ID
to the RMA life cycle stage. The certificate will be signed
by the customer using the same private key that is used
to sign the user application image. The verification of the
signature uses the same algorithm used by flash boot to
authenticate the user application. The same public key
(injected by the OEM) stored in SFlash is used for the
verification. Note that the signature is unique to a spe-
cific device. A signature will only work with the specific
device for which it was generated because it uses the
unique device ID.
When a device is reset in the RMA life cycle stage, the
boot will set access restrictions such that the DAP has
access only to System AP and IPC MMIO registers for
making system calls, and adequate RAM for communi-
cation. It will then wait for the “Open for RMA” system
call from the DAP along with the certificate of authoriza-
tion. This is the same certificate used in transitioning the
device to RMA. The boot process will not initiate any
firmware until it successfully executes the “Open for
RMA” command. After the command is successful, the
device will behave as though it were in the Virgin life

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 214
 Device Security

Figure 17-2. Protection State Transitions

UNKNOWN
(After Reset)

No
eFuse Lifecycle Bits Set? VIRGIN

Yes

NORMAL Lifecycle in Yes

eFuse NORMAL

No

SECURE Lifecycle in Yes

eFuse SECURE

Corruption or error
detected during the boot
process

DEAD

Protection state is defined by the STATE field of the CPUSS_PROTECTION register.

■ STATE is 0: UNKNOWN state.
■ STATE is 1: VIRGIN state.
■ STATE is 2: NORMAL state.
■ STATE is 3: SECURE state.
■ STATE is 4: DEAD state.
The CPUSS_PROTECTION register can be written only to affect the transitions defined in Figure 17-2. Any value written to
this register that does not represent a transition in Figure 17-2 is rejected in hardware. A life cycle stage change (by writing to
eFuse) does not immediately affect a protection state change. After writing the NORMAL, SECURE_WITH_DEBUG, or
SECURE state in the eFuse, a reboot is required for the change of life cycle stage to take effect on the protection state.
There are more protection states than there are life-cycle stages. The additional protection states are:
■ UNKNOWN – A device comes out of reset in this state. The ROM boot code needs to run through its courses (reading
eFuses and checking integrity) to determine the life cycle stage of the device and select the proper protection state.
■ DEAD – A device will enter the DEAD protection state when a corruption/error is detected in the boot process. In DEAD
protection state, the system will not attempt to start any flash firmware and may restrict access to system resources to
shield secure/sensitive information. Access restrictions in DEAD mode are controlled by
EFUSE_DATA_DEAD_ACCESS_RESTRICT0 and EFUSE_DATA_DEAD_ACCESS_RESTRICT1 eFuses.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 215
 Device Security

17.2.2 Flash Security

PSoC 6 MCUs include a flexible flash-protection system that controls access to flash memory. This feature is designed to
secure proprietary code, but it can also be used to protect against inadvertent writes to the bootloader portion of flash.
Flash memory is organized in sectors. Flash protection is provided by a shared memory protection unit (SMPU). The SMPU is
intended to distinguish between different protection contexts and to distinguish secure from non-secure accesses. The
system function that performs flash programming first looks at the SMPU settings and will not allow to program or erase flash
blocks protected by the SMPUs.
For more details, see the Protection Units chapter on page 73.

17.2.3 Hardware-Based Encryption

The PSoC 6 MCU has a cryptographic block (Crypto) that provides hardware implementation and acceleration of
cryptographic functions. It implements symmetric key encryption and decryption, hashing, message authentication, random
number generation (pseudo and true), and cyclic redundancy checking. It can work with internal as well as external memory.
See the Cryptographic Function Block (Crypto) chapter on page 111 and Serial Memory Interface (SMIF) chapter on
page 375 for more details.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 216
 Section C: System Resources Subsystem (SRSS)

This section encompasses the following chapters:

■ Power Supply and Monitoring chapter on page 218
■ Device Power Modes chapter on page 225
■ Backup System chapter on page 235
■ Clocking System chapter on page 242
■ Reset System chapter on page 257
■ I/O System chapter on page 261
■ Watchdog Timer chapter on page 283
■ Trigger Multiplexer Block chapter on page 294
■ Profiler chapter on page 299

Top Level Architecture

Figure C-1. System-Wide Resources Block Diagram

Color Key:
System Resources
Power Modes and
Power Clocks
Domains
OVP LVD IMO ECO
System LP/ULP Mode
CPUs Active/Sleep POR BOD FLL 2x PLL
System Buck Regulator 2x MCWDT
DeepSleep Mode
ILO WDT
System XRES Reset
Hibernate Mode
RTC WCO

Backup Backup Regs PMIC Control

Domain

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 217
 18. Power Supply and Monitoring

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU family supports an operating voltage range of 1.7 V to 3.6 V. It integrates multiple regulators including an
on-chip buck converter to power the blocks within the device in various power modes. The device supports multiple power
supply rails – VDDD, VDDA, VDDIO, and VBACKUP – enabling the application to use a dedicated supply for different blocks within
the device. For instance, VDDA is used to power analog peripherals such as ADC and opamps.
The PSoC 6 MCU family supports power-on-reset (POR), brownout detection (BOD), over-voltage protection (OVP), and low-
voltage-detection (LVD) circuit for power supply monitoring and failure protection purposes.

18.1 Features
The power supply subsystem of the PSoC 6 MCU supports the following features:
■ Operating voltage range of 1.7 V to 3.6 V
■ User-selectable core logic operation at either 1.1 V (LP) or 0.9 V (ULP)
■ Three independent supply rails (VDDD, VDDA, and VDDIO) for PSoC core peripherals and one independent supply rail
(VBACKUP) for backup domain
■ Multiple on-chip regulators
❐ One low-dropout (LDO) regulator to power peripherals in Active power mode
❐ One buck converter
❐ Multiple low-power regulators to power peripherals operating in different low-power modes
■ Two BOD circuit (VDDD and VCCD) in all power modes except Hibernate mode
■ LVD circuit to monitor VDDD, VAMUXA, VAMUXB, VBACKUP, or VDDIO
■ One OVP block monitoring VCCD

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 218
 Power Supply and Monitoring

18.2 Architecture
Figure 18-1. Power System Block Diagram

10 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF 1 µF 0.1 µF

VSS_NS VDD_NS VDDD VBACKUP VDDIO VDDA

VSSD VSSD VSSIO VSSA
VIND
PSoC 6
On-chip Low-dropout regulator
buck converter (Active regulator) Flash IO Cells
Legend:
2.2 uH

Regulators (LDO or Buck)

VCCD Deep Sleep power supply/logic

Active domain and Deep Sleep domain Active mode power supply/logic
Dee-Sleep and SRAM (Active)
High frequency logic/ peripherals / SRAM Analog peripherals
Retention regulators
4.7 µF peripherals On-chip buck connections

Retention power supply/logic

VSSD VCCDPSLP
Backup power supply/logic

External power pad

VCCRET External IO pad

Internal power rails

High voltage (V DDD)
and hibernate Domain
peripherals
VDDBAK

Backup Supply Backup logic, WCO,

Selection RTC

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 219
 Power Supply and Monitoring

See the PSoC 61 datasheet/PSoC 62 datasheet for the operation of the peripherals from VDDD. The regulator is
values to be used for the capacitors and inductor shown in capable of providing 0.9 V and 1.1 V for core operation. See
Figure 18-1. Core Operating Voltage on page 221. The regulator is
The regulators and supply pins/rails shown in Figure 18-1 available in Active and Sleep power modes. This regulator
power various blocks inside the device. The availability of implements two sub-modes – high-current and low-current
various supply rails/pins for an application will depend on modes. LINREG_LPMODE bit [24] of the PWR_CTL
the device package selected. Refer to the PSoC 61 register selects between the two modes of operation. The
datasheet/PSoC 62 datasheet for details. high-current mode is the normal operating mode, that is, the
device operates to its full capacity in Active or Sleep power
All the core regulators draw their input power from the VDDD modes. In the low-current mode or the minimum regulator
supply pin. The on-chip buck uses the VDD_NS supply pin as current mode, the current output from the regulator is
its input. VCCD supply is used to power all active domain and limited. This mode implements the Low-Power Active and
high frequency peripherals. The output of the buck is Sleep power modes. The low-current mode sets a limitation
connected to the VCCD pin and in firmware the VCCD supply on the capabilities and availability of resources in the Low-
can be switched to the buck output. A dedicated Deep Sleep Power Active and Sleep modes. For details, see the Device
regulator powers all the Deep Sleep peripherals. The Deep Power Modes chapter on page 225.
Sleep regulator switches its output to VCCD when available
and to its regulated output when VCCD is not present By default, the linear regulator is powered on reset. The
(System Deep Sleep power mode). Hibernate domain does regulator can be disabled by setting the LINREG_DIS bit
not implement any regulators and the peripherals available [23] of the PWR_CTL register. Note that the linear regulator
in that domain such as Low-Power comparator and ILO should be turned OFF only when the following conditions
operate directly from VDDD. are satisfied:
■ Switching buck regulator is ON.
When the VDDA pin is not present, analog peripherals run
directly from the VDDD. ■ The load current requirement of the device from the
VCCD supply does not exceed 20 mA. This should be
The I/O cells operate from various VDDx (VDDA, VDDD, or ensured by the firmware by disabling power consuming
VDDIO) pins depending on the port where they are located. high-frequency peripherals and reducing the system
VCCD supply is used to drive logic inside the I/O cells from clock frequency.
core peripherals. VDDA powers the analog logic such as
analog mux switches inside the I/O cell. To know which I/Os If the linear regulator is turned OFF without the above
operate from which supply, refer to the PSoC 61 datasheet/ conditions satisfied, it will result in VCCD brownout and the
PSoC 62 datasheet. device will reset.

The device includes a VBACKUP supply pin to power a small Switching (Buck) Core Regulator
set of peripherals such as RTC and WCO, which run
independent from other supply rails available in the device. The device includes a switching (buck) core regulator. The
When the VBACKUP supply is not present, the device uses buck requires an inductor and a capacitor to generate the
VDDD to power these peripherals. output. Note that the buck output is also available in the
Deep Sleep device power mode.
In addition to the power rails and regulators, the device
provides options to monitor supply rails and protection The buck regulator can be enabled by setting the BUCK_EN
against potential supply failures. These include a POR bit [30] of the PWR_BUCK_CTL register. The buck output
circuit, a BOD circuit, an OVP circuit, and a LVD circuit. can be enabled/disabled using the BUCK_OUT1_EN bit [31]
of the PWR_BUCK_CTL registers. The buck output
supports voltages from 0.85 V to 1.20 V. Use either 0.9 V or
18.3 Power Supply 1.1 V for VCCD operation.
The output selection can be made using BUCK_OUT_SEL
18.3.1 Regulators Summary bits in the PWR_BUCK_CTL registers.

18.3.1.1 Core Regulators When used to power the core peripherals, the buck
regulator provides better power efficiency than the linear
The device includes the following core regulators to power regulator, especially at higher VDDD. However, the buck
peripherals and blocks in various power modes. regulator has less load current capability (20 mA individually
or 30 mA combined) than the linear regulator. Therefore,
Linear Core Regulator when using the buck regulator, take care not to overload the
The device includes a linear LDO regulator to power the regulator by running only the necessary peripherals at a
Active and Sleep mode peripherals. This regulator lower frequency in firmware. Overload conditions can cause
generates the core voltage (VCCD) required for Active mode the buck output to drop and result in a brownout reset.

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 Power Supply and Monitoring

Follow these steps in firmware when switching to the buck Core Operating Voltage
regulator for core (VCCD) operation without causing a
PSoC 6 MCUs can operate at either 0.9 V LP mode
brownout.
(nominal) or 1.1 V ULP mode (nominal) core voltage. On
1. Make sure the necessary inductor and capacitor reset, the core is configured to operate at 1.1 V by default.
connection for the buck as explained in Figure 18-1 is At 0.9 V, power consumption is less, but there are some
present in the hardware. limitations. The maximum operating frequency for all HFCLK
2. Change the core supply voltage to 50 mV more than the paths should not exceed 50 MHz, whereas the peripheral
final buck voltage. For instance, if the final buck voltage and slow clock should not exceed 25 MHz.
is 0.9 V, then set the LDO output to 0.95 V and 1.15 V for
Follow these steps to change the PSoC 6 MCU core
1.1 V buck operation. Set the ACT_REG_TRIM bits[4:0]
voltage:
of the PWR_TRIM_PWRSYS_CTL register to ‘0x0B’ to
switch to 0.9 V and '0x1B' to switch to 1.1 V buck 1. While transitioning to 0.9 V (ULP mode), reduce the
operation. This is discussed in Core Operating Voltage. operating frequency to be within the HFCLK and peri
clock limits defined in the PSoC 61 datasheet/PSoC 62
3. Reduce the device current consumption by reducing
datasheet for ULP mode. Turn off blocks, if required, to
clock frequency and switching off blocks to meet the
be within the maximum current consumption limit of the
buck regulator’s load capacity.
linear regulator at 0.9 V.
4. Disable System Deep Sleep mode regulators. Because
2. Set the ACT_REG_TRIM bits[4:0] of the
the buck regulator is available in the System Deep Sleep
PWR_TRIM_PWRSYS_CTL register to ‘0x07’ for 0.9 V
power mode, other deep-sleep regulators can be
or ‘0x17’ for 1.1 V. For the buck regulator, set the
powered down. This is done by setting the following bits
BUCK_OUT1_SEL bits[2:0] of the PWR_BUCK_CTL
in the PWR_CTL register:
register to ‘0x02’ for 0.9 V and ‘0x05’ for 1.1 V.
a. DPSLP_REG_DIS bit [20] – Disables the deep-sleep
3. In the case of 1.1 V to 0.9 V transition, the time it takes
core regulator.
to discharge or settle to the new voltage may depend on
b. RET_REG_DIS bit [21] – Disables the logic retention the load. So the system can continue to operate while
regulator. the voltage discharges.
c. NWELL_REG_DIS bit [22] – Disables the nwell 4. In the case of 0.9 V to 1.1 V transition, wait 9 µs for the
regulator. regulator to stabilize to the new voltage. The clock
5. Set the buck output to the desired value by writing ‘2’ (for frequency can be increased after the settling delay.
0.9 V) or ‘5’ (for 1.1 V) to the BUCK_OUT1_SEL bits[2:0]
Notes:
of the PWR_BUCK_CTL register.
■ When changing clock frequencies, make sure to update
6. Enable the buck regulator and output by setting the
wait states of RAM/ROM/FLASH. Refer to the CPU
BUCK_EN bit[30] and BUCK_OUT1_EN bit[31] of the
Subsystem (CPUSS) chapter on page 32 for details on
PWR_BUCK_CTL register.
the wait states.
7. Wait 200 µs for the buck regulator to start up and settle.
■ Flash write is not allowed in 0.9 V (ULP mode) core
8. Disable the linear regulator by setting the LINREG_DIS operation.
bit[23] of the PWR_CTL register.
After transitioning to the buck regulator, do not switch back Other Low-power Regulators
to the linear regulator mode to ensure proper device In addition to the core active regulators, the device includes
operation. This should happen once during powerup. multiple low-power regulators for powering Deep Sleep
peripherals/logic (VCCDPSLP), digital retention logic/SRAM
(VCCRET), and N-wells (VNWELL) in the device. Note that
VNWELL is not shown in Figure 18-1 because this rail is used
across the device for powering all the N-wells in the chip.
These rails are shorted to VCCD in Active and Sleep power
modes. VCCRET powers all the Active mode logic that needs
to be in retention in Deep Sleep mode.
Note that none of these power rails are available in
Hibernate mode. In Hibernate mode, all the hibernate logic
and peripherals operate from VDDD directly and a Hibernate
wakeup resets the device. For details, refer to the Device
Power Modes chapter on page 225.

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 Power Supply and Monitoring

18.3.2 Power Pins and Rails

Table 18-1 lists all the power supply pins available in the device. The supply rails running inside the device (VCCDPSLP,
VCCRET, VDDBAK, and VNWELL) are derived from these external supply pins/rails.

Table 18-1. Supply Pins

Supply Pin Ground Pin Voltage Range Supporteda Description

VDD is a single supply input for multiple supplies and VDDD is a
VDD or VDDD VSS or VSSD 1.7 V to 3.6 V digital supply input. Either of the pins will be present in a given
package.
VDD_NS VSS_NS 1.7 V to 3.6 V Supply input to the buck regulator on-chip.
Core supply or bypass capacitor for the internal core regulator
VCCD VSS or VSSD Capacitor (0.9 V or 1.1 V)
(LDO).
VDDA VSS or VSSA (if available) 1.7 V to 3.6 V Analog supply voltage.
VDDIO VSS or VSSIO (if available) 1.7 V to 3.6 V Additional I/O supply voltage.
VBACKUP VSS or VSSD (if available) 1.4 V to 3.6 V Backup domain supply voltage.
VIND – Inductor Inductor connection for the internal buck regulator.
a. Refer to the PSoC 61 datasheet/PSoC 62 datasheet for exact range and recommended connections.

18.3.3 Power Sequencing Requirements Other supply rails and pins such as VDDA, VDDIO, and
VBACKUP exist independent of VDDD and VCCD.
VDDD, VBACKUP, VDDIO, and VDDA do not have any
sequencing limitation and can establish in any order. The
presence of VDDA without VDD or VDDD can cause some 18.4 Voltage Monitoring
leakage from VDDA. However, it will not drive any analog or
The PSoC 6 MCU offers multiple voltage monitoring and
digital output. All the VDDA pins in packages that offer
supply failure protection options. This includes POR, BOD,
multiple VDDA supply pins, must be shorted externally (on
LVD, and OVP.
the PCB). Note that the system will not exit reset until both
VDDD and VDDA are established. However, it will not wait for
18.4.1 Power-On-Reset (POR)
other supplies to establish.
POR circuits provide a reset pulse during the initial power
18.3.4 Backup Domain ramp. POR circuits monitor VDDD voltage. Typically, the
POR circuits are not very accurate about the trip-point.
The PSoC 6 MCU offers an independent backup supply
option (VBACKUP). This rail powers a small set of peripherals POR circuits are used during initial chip power-up and then
that includes an RTC, WCO, and a small number of disabled. Refer to the PSoC 61 datasheet/PSoC 62
retention registers. This rail is independent of all other rails datasheet for details on the POR trip-point levels.
and can exist even when other rails are absent. As
Figure 18-1 shows, this pin sources the VDDBAK rail in the 18.4.2 Brownout-Detect (BOD)
device. The VDDBAK rail is connected to VDDD when no
The BOD circuit protects the operating or retaining logic
VBACKUP supply exists. For details on the backup domain, from possibly unsafe supply conditions by applying reset to
refer to the Backup System chapter on page 235. the device. The PSoC 6 MCU offers two BOD circuits –
high-voltage BOD (HVBOD) and low-voltage BOD (LVBOD).
18.3.5 Power Supply Sources The HVBOD monitors the VDDD voltage and LVBOD
monitors the VCCD voltage. Both BOD circuits generate a
The PSoC 6 MCU offers power supply options that support
reset if a voltage excursion dips below the minimum VDDD/
a wide range of application voltages and requirements.
VDDD input supports a voltage range of 1.7 V to 3.6 V. If the VCCD voltage required for safe operation (see the PSoC 61
application voltage is in this range, then the PSoC 6 MCU datasheet/PSoC 62 datasheet for details). The system will
(VDDD) can be interfaced directly to the application voltage. not come out of RESET until the supply is detected to be
valid again.
In applications that have voltage beyond this range, a
suitable PMIC (Buck or Boost or Buck-Boost) should be The HVBOD circuit guarantees a reset in System LP, ULP,
used to bring the voltage to this range. and Deep Sleep power modes before the system crashes,

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 Power Supply and Monitoring

provided the VDDD supply ramp satisfies the datasheet bits[1:0] of SRSS_INTR_CFG register. By default, the
maximum supply ramp limits in that mode. There is no BOD configuration disables the interrupt. Note: LVD logic may
support in Hibernate mode. Applications that require BOD falsely detect a falling edge during Deep Sleep entry.
support should not use Hibernate mode and should disable This applies only when HVLVD1_EDGE_SEL is set to
it. Refer to the Device Power Modes chapter on page 225 FALLING(2) or BOTH(3). Firmware can workaround this
for details. condition by disabling falling edge detection before
entering Deep Sleep, and re-enabling it after exiting
The LVBOD, operating on VCCD, is not as robust as the Deep Sleep.
HVBOD. The limitation is because of the small voltage
4. Enable the LVD by setting the HVLVD1_EN bit in the
detection range available for LVBOD on the minimum
PWR_LVD_CTL register. This may cause a false LVD
allowed VCCD.
event.
For details on the BOD trip-points, supported supply ramp 5. Wait at least 8 µs for the circuit to stabilize.
rate, and BOD detector response time, refer to the PSoC 61 6. Clear any false event by setting the HVLVD1 bit in the
datasheet/PSoC 62 datasheet. SRSS_INTR register. The bit will not clear if the LVD
condition is truly present.
18.4.3 Low-Voltage-Detect (LVD) 7. Unmask the interrupt by setting the HVLVD1 bit in
An LVD circuit monitors external supply voltage and SRSS_INTR_MASK.
accurately detects depletion of the energy source. The LVD LVD is used to detect potential brownouts. When the supply
generates an interrupt to cause the system to take being monitored drops below the threshold, the interrupt
preventive measures. generated can be used to save necessary data to flash,
The LVD can be configured to monitor VDDD, VAMUXA, dump logs, trigger external circuits, and so on.
VAMUXB, or VDDIO. The HVLVD1_SRCSEL bits [6:4] of the For details on supported LVD thresholds, refer to the PSoC
PWR_LVD_CTL register selects the source of the LVD. The 61 datasheet/PSoC 62 datasheet and the PWR_LVD_CTL
LVD support up to 15 voltage levels (thresholds) to monitor register definition in the registers TRM.
between 1.2 V to 3.1 V. The HVLVD1_TRIPSEL bits [3:0] of
the PWR_LVD_CTL register select the threshold levels of
the LVD. LVD should be disabled before selecting the
threshold. The HVLVD1_EN bit [7] of the PWR_LVD_CTL
register can be used to enable or disable the LVD.
Whenever the voltage level of the supply being monitored
drops below the threshold, the LVD generates an interrupt.
This interrupt status is available in the SRSS_INTR register.
HVLVD1 bit [1] of the SRSS_INTR register indicates a
pending LVD interrupt. The SRSS_INTR_MASK register
decides whether LVD interrupts are forwarded to the CPU or
not.
Note that the LVD circuit is available only in Active,
LPACTIVE, Sleep, and LPSLEEP power modes. If an LVD is
required in Deep Sleep mode, then the device should be
configured to periodically wake up from Deep Sleep mode
using a Deep Sleep wakeup source. This makes sure an
LVD check is performed during Active/LPACTIVE mode.
When enabling the LVD circuit, it is possible to receive a
false interrupt during the initial settling time. Firmware can
mask this by waiting for 8 µs after setting the HVLVD1_EN
bit in the PWR_LVD_CTL register. The recommended
firmware procedure to enable the LVD function is:
1. Ensure that the HVLVD1 bit in the SRSS_INTR_MASK
register is 0 to prevent propagating a false interrupt.
2. Set the required trip-point in the HVLVD1_TRIPSEL field
of the PWR_LVD_CTL register.
3. Configure the LVD edge (falling/rising/both) that triggers
the interrupt by configuring HVLVD1_EDGE_SEL

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 Power Supply and Monitoring

Figure 18-2. PSoC 6 MCU LVD Block

PSoC 6 LVD block

HVLVD1_EN
HVLVD1_SRCSEL [2:0]

VDDD
VAMUXA -
VAMUXB

HVLVD1 SRSS_INTR[HVLVD1]
To CPU as SRSS
1.2 V . SRSS_INTR_MASK[HVLVD1]
. interrupt
.
.
+
.
3.1 V
4

HVLVD1_TRIPSEL [3:0]

18.4.4 Over-Voltage Protection (OVP)

The PSoC 6 MCU offers an over-voltage protection circuit that monitors the VCCD supply. Similar to the BOD circuit, the OVP
circuit protects the device from unsafe supply conditions by applying a reset. As the name suggests, the OVP circuit applies a
device reset, when the VCCD supply goes above the maximum allowed voltage. The OVP circuit can generate a reset in all
device power modes except the Hibernate mode.

18.5 Register List

Name Description
Power Mode Control register - controls the device power mode options and allows observation of current
PWR_CTL
state
PWR_BUCK_CTL Buck Control register - controls the buck output and master buck enable
PWR_LVD_CTL LVD Configuration register
SRSS_INTR SRSS Interrupt register - shows interrupt requests from the SRSS peripheral
SRSS_INTR_MASK SRSS Interrupt Mask register - controls forwarding of the interrupt to CPU
SRSS_INTR_SET SRSS Interrupt Set register - sets interrupts; this register is used for firmware testing
SRSS Interrupt Masked register - logical AND of corresponding SRSS interrupt request (SRSS Interrupt
SRSS_INTR_MASKED
register) and mask bits (SRSS Interrupt Mask register)

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 19. Device Power Modes

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU can operate in four system and three CPU power modes. These modes are intended to minimize the
average power consumption in an application. The power modes supported by PSoC 6 MCUs, in the order of decreasing
power consumption, are:
■ System Low Power (LP) – All peripherals and CPU power modes are available at maximum speed and current
■ System Ultra Low Power (ULP) – All peripherals and CPU power modes are available, but with limited speed and current
■ CPU Active – CPU is executing code in system LP or ULP mode
■ CPU Sleep – CPU code execution is halted in system LP or ULP mode
■ CPU Deep Sleep – CPU code execution is halted and system deep sleep is requested while in system LP or ULP mode
■ System Deep Sleep – Entered only after both CPUs enter CPU Deep Sleep mode. Only low-frequency peripherals are
available
■ System Hibernate – Device and I/O states are frozen and the device resets on wakeup
CPU Active, Sleep, and Deep Sleep are standard Arm-defined power modes supported by the Arm CPU instruction set
architecture (ISA). System LP, ULP, Deep Sleep and Hibernate modes are additional low-power modes supported by PSoC 6.
Hibernate mode is the lowest power mode in the PSoC 6 MCU and on wakeup, the CPU and all peripherals go through a
reset.

19.1 Features
The PSoC 6 MCU power modes have the following features:
■ Four system and three CPU power modes aimed at optimizing power consumption in an application
■ System ULP mode with reduced operating current and clock frequency while supporting full device functionality
■ System Deep Sleep mode with support for multiple wakeup sources and configurable amount of SRAM retention
■ System Hibernate mode with wakeup from I/O, comparator, WDT, RTC, and timer alarms
The power consumption in different power modes is further controlled by using the following methods:
■ Enabling and disabling clocks to peripherals
■ Powering on/off clock sources
■ Powering on/off peripherals and resources inside the PSoC 6 device

19.2 Architecture
The PSoC 6 device supports multiple power modes. Some modes only affect the CPUs (CPU power modes) and others affect
the whole system (system power modes). The system and CPU power modes are used in combination to control the total
system performance and power. CPU power modes are entered separately for each CPU on the device.

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 Device Power Modes

The SysPm Peripheral Driver Library (PDL) driver supports all device power mode transitions and is the recommended
method of transition and configuration of PSoC 6 MCU power resources.
Table 19-1 summarizes the power modes available in PSoC 6 MCUs, their description, and details on their entry and exit
conditions.
Table 19-1. PSoC 6 MCU Power Modes
System MCU
Wakeup Wakeup
Power Power Description Entry Conditions
Sources Action
Mode Mode
Reset from external reset, brownout,
System – Primary mode of operation. 1.1 power on reset system and Hibernate
V core voltage. All peripherals are avail- mode. Manual register write from sys-
Active able (programmable). Maximum clock fre- tem ULP mode. Wakeup from CPU Not applicable N/A
quencies Sleep or CPU Deep Sleep while in sys-
CPU – Active mode tem LP mode. Wakeup from system
Deep Sleep after entered from LP mode.
1.1 V core voltage. One or more CPUs in
LP In system LP mode, CPU executes WFI/
Sleep mode (execution halted). All periph- Any interrupt to
Sleep WFE instruction with Deep Sleep dis- Interrupt
erals are available (programmable). Maxi- CPU
abled
mum clock frequencies
1.1 V core voltage. One CPU in Deep
Sleep mode (execution halted). Other In system LP mode, CPU executes WFI/
Deep Any interrupt to
CPU in Active or Sleep mode. All periph- WFE instruction with Deep Sleep Interrupt
Sleep CPU
erals are available (programmable). Maxi- enabled
mum clock frequencies
Manual register write from system LP
0.9 V core voltage. All peripherals are mode. Wakeup from CPU Sleep or CPU
Active available (programmable). Limited clock Deep Sleep while in system ULP mode. Not applicable N/A
frequencies. No Flash write. Wakeup from system Deep Sleep after
entered from ULP mode.
0.9 V core voltage. One or more CPUs in
In system ULP mode, CPU executes
Sleep mode (execution halted). All periph- Any interrupt to
ULP Sleep WFI/WFE instruction with Deep Sleep Interrupt
erals are available (programmable). Lim- CPU
disabled
ited clock frequencies. No Flash write.
0.9 V core voltage. One CPU in Deep
Sleep mode (execution halted). Other In system ULP mode, CPU executes
Deep Any interrupt to
CPU in Active or Sleep mode. All periph- WFI/WFE instruction with Deep Sleep Interrupt
Sleep CPU
erals are available (programmable). Lim- enabled
ited clock frequencies. No Flash write.
All high-frequency clocks and peripherals GPIO interrupt,
are turned off. Low-frequency clock (32 Low-Power
Deep Deep kHz) and low-power analog and digital Both CPUs simultaneously in CPU Deep comparator,
Interrupt
Sleep Sleep peripherals are available for operation Sleep mode. SCB, watchdog
and as wakeup sources. SRAM is timer, and RTC
retained (programmable). alarms
GPIO states are frozen. All peripherals
and clocks in the device are completely WAKEUP pin,
turned off except optional low-power com- low- power com-
parators and backup domain. Wakeup is Manual register write from LP or ULP parator, watch- Reset
Hibernate N/A
possible through WAKEUP pins, XRES, modes.
dog timera, and
low-power comparator (programmable),
WDT, and RTC alarms (programmable). RTCb alarms
Device resets on wakeup.
a. Watchdog timer is capable of generating a hibernate wakeup. See the Watchdog Timer chapter on page 283 for details.
b. RTC (along with WCO) is part of the backup domain and is available irrespective of the device power mode. RTC alarms are capable of waking up the device
from any power mode.

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 Device Power Modes

19.2.1 CPU Power Modes voltage, which then requires reduced operating clock
frequency and limited high-frequency clock sources. Flash
The CPU Active, Sleep, and Deep Sleep modes are the write operations are not available in ULP mode. Table 19-5
standard Arm-defined power modes supported by both provides the list of resources available in ULP mode along
Cortex-M4 and Cortex-M0+ CPUs. All Arm CPU power with limitations.
modes are available in both system LP and ULP power
modes. CPU power modes affect each CPU independently. While in system ULP mode, the CPUs may operate in any of
the standard Arm-defined CPU modes detailed in 19.2.1
19.2.1.1 CPU Active Mode CPU Power Modes.

In CPU Active mode, the CPU executes code and all logic Transitioning between LP and ULP modes is performed by
and memory is powered. The firmware may decide to reducing the core regulator voltage from the LP mode
enable or disable specific peripherals and power domains voltage to the ULP mode voltage. The lower voltage reduces
depending on the application and power requirements. All system operating current and slows down signal speeds
the peripherals are available for use in Active mode. The requiring a lower maximum operating frequency. Refer to
device enters CPU Active mode upon any device reset or Core Operating Voltage section in Power Supply and
wakeup. Monitoring chapter on page 218 for details on how to switch
between LP and ULP modes.
19.2.1.2 CPU Sleep Mode
19.2.3 System Deep Sleep Mode
In CPU Sleep mode, the CPU clock is turned off and the
CPU halts code execution. Note that in the PSoC 6 MCU, In system Deep Sleep mode, all the high-speed clock
Cortex-M4 and Cortex-M0+ both support their own CPU sources are off. This in turn makes high-speed peripherals
Sleep modes and each CPU can be in sleep independent of unusable in system Deep Sleep mode. However, low-speed
the other CPU state. All peripherals available in Active mode clock sources and peripherals may continue to operate, if
are also available in Sleep mode. Any peripheral interrupt, configured and enabled by the firmware. In addition, the
masked to the CPU, will wake the CPU to Active mode. Only peripherals that do not need a clock or receive a clock from
the CPU(s) with the interrupt masked will wake. their external interface (I2C or SPI slave) may continue to
operate, if configured for system Deep Sleep operation. The
19.2.1.3 CPU Deep Sleep Mode PSoC 6 MCU provides an option to configure the amount of
SRAM, in blocks of 32 KB, that are retained during Deep
In CPU Deep Sleep mode, the CPU requests the device to Sleep mode.
go into system Deep Sleep mode. When the device is ready,
it enters Deep Sleep mode as detailed in 19.2.3 System Both Cortex-M0+ and Cortex-M4 can enter CPU Deep
Deep Sleep Mode. Sleep mode independently. However, the entire device
enters system Deep Sleep mode only when both the CPUs
Because PSoC 6 has more than one CPU, both CPUs must are in CPU Deep Sleep. On wakeup, the CPU that woke up
independently enter CPU Deep Sleep before the system will enters CPU Active mode and the other CPU remains in CPU
transition to system Deep Sleep. Deep Sleep mode. On wakeup, the system will return to LP
or ULP mode based on what mode was Active before
19.2.2 System Power Modes entering system Deep Sleep. Both CPUs may wake up to
CPU Active simultaneously from the same wakeup source if
System power modes affect the whole device and may be so configured.
combined with CPU power modes.
The device enters system Deep Sleep mode after the
19.2.2.1 System Low Power Mode following conditions are met.
■ The LPM_READY bit of the PWR_CTL register should
System Low Power (LP) mode is the default operating mode
read ‘1’. This ensures the system is ready to enter Deep
of the device after reset and provides maximum system
Sleep. If the bit reads ‘0’, then the device will wait in
performance. In LP mode all resources are available for
system LP or ULP mode instead of system Deep Sleep
operation at their maximum power level and speed.
until the bit is set, at which instant the device
While in system LP mode the CPUs may operate in any of automatically enters Deep Sleep mode, if requested.
the standard Arm defined CPU modes detailed in 19.2.1 ■ Both Cortex-M0+ and Cortex-M4 must be in CPU Deep
CPU Power Modes. Sleep. This is achieved by setting the SLEEPDEEP bit
[2] of the SCR register of both Cortex-M0+ and Cortex-
19.2.2.2 System Ultra Low Power Mode M4 and then executing WFI or WFE instruction.
System Ultra Low Power (ULP) mode is identical to LP ■ The HIBERNATE bit [31] of the PWR_HIBERNATE
mode with a performance tradeoff made to achieve lower register should be cleared; otherwise, the device will
system current. This tradeoff lowers the core operating enter system Hibernate mode.

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 Device Power Modes

In system Deep Sleep mode, the LP and ULP mode stable. In addition, make sure the supply is stable for at least
regulator is turned off and a lower power, Deep Sleep 250 µs before the device enters Hibernate mode. To prevent
regulator sources all the peripherals enabled in system accidental entry into Hibernate mode in applications that
Deep Sleep mode. Alternatively, the buck regulator can be cannot meet these requirements, an option to disable the
used to power the Deep Sleep peripherals. See the Power Hibernate mode is provided. Set the HIBERNATE_DISABLE
Supply and Monitoring chapter on page 218 for details. bit [30] of the PWR_HIBERNATE register to disable
Table 19-5 provides the list of resources available in system Hibernate mode in the device. Note that this bit is a write-
Deep Sleep mode. once bit during execution and is cleared only on reset.
Debug functionality will be lost and the debugger will
Interrupts from low-speed, asynchronous, or low-power
disconnect on entering Hibernate mode.
analog peripherals can cause a CPU wakeup from system
Deep Sleep mode. Note that when a debugger is running on 19.2.5 Other Operation Modes
either core, the device stays in system LP or ULP mode and
In addition to the power modes discussed in the previous
the CPUs enter CPU Sleep mode instead of CPU Deep
sections, there are three other states the device can be in –
Sleep mode. PSoC 6 uses buffered writes. Therefore, writes
Reset, Off, and Backup states. These states are determined
to an MMIO register or memory can take few a cycles from
by the external power supply and XRES connections. No
the write instruction execution. The only way to ensure that
firmware action is required to enter these modes nor an
the write operation is complete is by reading the same
interrupt or wakeup event to exit them.
location after the write. It is required to follow a write by a
read to the same location before executing a WFI/WFE 19.2.5.1 Backup Domain
instruction to enter CPU Deep Sleep mode.
PSoC 6 offers an independent backup supply option that
19.2.4 System Hibernate Mode can be supplied through a separate Vbackup pin. For details
on the backup domain and the powering options, refer to the
System Hibernate mode is the lowest power mode of the
Backup System chapter on page 235. This domain powers a
device when external supplies are still present and XRES is
real-time clock (RTC) block, WCO, and a small set of
deasserted. It is intended for applications in a dormant state.
backup registers. Because the power supply to these blocks
In this mode, both the Active LP/ULP mode regulator and
come from a dedicated Vbackup pin, these blocks continue
Deep Sleep regulator are turned off and GPIO states are
to operate in all CPU and system power modes, and even
automatically frozen. Wakeup is facilitated through
when the device power is disconnected or held in reset as
dedicated wakeup pins and a Low-Power comparator
long as a Vbackup supply is provided. The RTC present in
output. Low-Power comparator operation in Hibernate mode
the backup domain provides an option to wake up the
requires externally generated voltages for wakeup
device from any CPU or system power mode. The RTC can
comparison. Internal references are not available in
be clocked by an external crystal (WCO) or the internal low-
Hibernate mode. Optionally, an RTC alarm from the backup
speed oscillator (ILO). However, the ILO is available only if
domain or a watchdog timer (16-bit free-running WDT)
the device is powered – the device should not be in the off or
interrupt can generate a Hibernate wakeup signal. Set the
reset state. Using ILO is not recommended for timekeeping
MASK_HIBALARM bit [18] of the PWR_HIBERNATE
purpose; however, it can be used for wakeup from Hibernate
register to enable the RTC alarm wakeup from Hibernate
power mode.
mode.
The device goes through a reset on wakeup from Hibernate. 19.2.5.2 Reset State
I/O pins remain in the configuration they were frozen before Reset is the device state when an external reset (XRES pin
entering Hibernate mode. To differentiate between other pulled low) is applied or when POR/BOD is asserted. Reset
system resets and a Hibernate mode wakeup, the TOKEN is not a power mode. During the reset state, all the
bits [7:0] of the PWR_HIBERNATE register can be used as components in the device are powered down and I/Os are
described in the Power Mode Transitions on page 230. The tristated, keeping the power consumption to a minimum.
PWR_HIBERNATE (except the HIBERNATE bit [31])
register along with the PWR_HIB_DATA register are 19.2.5.3 Off State
retained through the Hibernate wakeup sequence and can The off state simply represents the device state with no
be used by the application for retaining some content. Note power applied. Even in the device off state, the backup
that these registers are reset by other reset events. On a domain can continue to receive power (Vbackup pin) and
Hibernate wakeup event, the HIBERNATE bit [31] of the run the peripherals present in that domain. The reset and off
PWR_HIBERNATE register is cleared. states are discussed for completeness of all possible modes
and states the device can be in. These states can be used in
The brownout detect (BOD) block is not available in
a system to further optimize power consumption. For
Hibernate mode. As a result, the device does not recover
instance, the system can control the supply of the PSoC 6
from a brownout event in Hibernate mode. Do not enter
MCU by enabling or disabling the regulator output powering
Hibernate mode in applications that require brownout
the device using the PMIC interface.
detection, that is, applications where the supply is not

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 228
 Device Power Modes

19.3 Power Mode Transitions

Figure 19-1 shows various states the device can be in along with possible power mode transition paths.
Figure 19-1. Power Mode Transitions in PSoC 6 MCU

O ff

XRES/
X R E S /P O R /B O D
d e a s s e rt XRES P O R /B O D
a s s e rt

S y s te m L P S y s te m U L P
(1 .1 V C o re ) (0 .9 V C o re )

F irm w a re
C P U A c tiv e a c tio n C P U A c tiv e F irm w a re
a c tio n

F irm w a re P e rip h e ra l F irm w a re P e rip h e ra l

a c tio n in te rru p t a c tio n in te rru p t

C P U S le e p / C P U S le e p /
D e e p s le e p D e e p s le e p

B o th
C P U s in
D e e p s le e p D e e p s le e p D e e p s le e p D e e p s le e p D e e p s le e p
in te rru p t fo r in te rru p t fo r in te rru p t fo r in te rru p t fo r
th is C P U o th e r C P U o th e r C P U th is C P U

S y s te m
D e e p s le e p

W akeup S y s te m
a s s e rt
H ib e rn a te

LEGEND:

Pow er M ode A c tio n

R eset event

F irm w a re a c tio n

H ib e rn a te w a k e u p e v e n ts
P e rip h e ra l in te rru p ts /
H a rd w a re e v e n ts

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 Device Power Modes

19.3.1 Power-up Transitions

Table 19-2 summarizes various power-up transitions, their type, triggers, and actions.

Table 19-2. Power Mode Transitions

Initial State Final State Type Trigger Actions
Power rail (VDDD) ramps up
Off XRES External above POR voltage level with 1. All high-voltage logic is reset
XRES pin asserted.
1. All high-voltage logic is reset
2. Low-voltage (internal core and Deep Sleep mode)
Power rail (VDDD) ramps up
regulators and references are ramped up
Off Reset External above POR voltage level with
3. All low-voltage logic (logic operating from internal
XRES pin de-asserted.
regulators) is reset
4. IMO clock is started
1. Low-voltage regulators and references are ramped up
XRES is de-asserted with VDDD
XRES Reset External 2. All low-voltage logic is reset
present and above POR level.
3. IMO clock is started
Reset sequence completes. This 1. Clock is released to the system
Reset Active Internal transition can also be caused by 2. System reset is de-asserted
internal resets. 3. CPU starts execution

19.3.2 Power Mode Transitions

Table 19-3. Power Mode Transitions
Initial State Final State Type Trigger Actions
Firmware action 1. Device is put into ULP
1. Ensure the Clk_HF paths, peripheral, and slow clocks are less than the mode with all peripherals
System ULP clock speed limitations. available with limited
System LP Internal
ULP 2. Flash/SRAM/ROM wait states values are increased to ULP values as speed. Flash write
detailed in the Nonvolatile Memory chapter on page 164. operation are not
3. Configure the core regulator to 0.9 V. supported.
Firmware action
1. Configure the core regulator to 1.1 V. 1. Device is put into LP
2. Wait 9 µs to allow the core voltage to stabilize at the new value. mode with all peripherals
System
System LP Internal 3. Flash/SRAM/ROM wait states values are decreased to LP values as available with maximum
ULP
detailed in the Nonvolatile Memory chapter on page 164. speed. Flash write
operations are supported.
4. Increase the Clk_HF paths, peripheral, and slow clocks as desired up to
the maximum LP clock speed specifications.

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 Device Power Modes

Table 19-3. Power Mode Transitions

Initial State Final State Type Trigger Actions
Firmware action
1. Clear the SLEEPDEEP bit [2] of the SCR register for both Cortex-M0+
and Cortex-M4.
2. Optionally, set the SLEEPONEXIT bit [1] of the SCR register, if the CPU
runs only on interrupts. When this bit is set, the CPU does not return to 1. CPU clocks are gated
System LP/ System LP/ application code after the WFI/WFE instruction is executed. The CPU wakes off
ULP and ULP and Internal up on any enabled (masked to CPU) interrupt or event and enters CPU 2. CPU waits for an inter-
CPU Active CPU Sleep Sleep mode as soon as it exits the interrupt or services the event. rupt or event to wake it
3. Optionally, set the SEVONPEND bit [4] of the SCR register if the applica- up.
tion must wake up the CPU from any pending interrupt. If this bit is set, any
interrupt that enters a pending state wakes up the CPU. This includes all the
disabled (unmasked) interrupts to CPU.
4. Execute WFI/WFE instruction on both CPUs.
Firmware action
Perform these steps to enter Deep Sleep mode (LPM_READY bit [5] of the
PWR_CTL register should read '1' before performing these steps):
1. Clear the HIBERNATE bit [31] of the PWR_HIBERNATE register.
2. Set the SLEEPDEEP bit [2] of the SCR register for one or both Cortex-
M0+ and Cortex-M4.
3. Optionally, set the SLEEPONEXIT bit [1] of the SCR register if the CPU
runs only on interrupts. When this bit is set, the CPU does not return to
application code after the WFI/WFE instruction is executed. The CPU wakes
up on any enabled (masked to CPU) interrupt or event and enters CPU
Deep Sleep mode as soon as it exits the interrupt or services the event.
4. Optionally, set the SEVONPEND bit [4] of the SCR register if the applica- 1. CPU clocks are gated
System LP/ tion needs to wake up the CPU from any pending interrupt. If this bit is set,
System LP/ off
UP and any interrupt that enters a pending state wakes up the CPU. This includes all
ULP and Internal 2. CPU waits for a Deep
CPU Deep the disabled (unmasked) interrupts to CPU.
CPU Active Sleep interrupt to wake it
Sleep
5. Read the SCR register before executing a WFI/WFE instruction to ensure up.
the write operation is complete. PSoC 6 uses buffered writes and any write
transfer just before executing WFI/WFE instruction should be followed by a
read to the same memory location. This ensures that the write operation has
taken effect before entering Deep Sleep mode. Execute WFI/WFE instruc-
tion on both CPUs.
6. CPU in Deep Sleep mode generates a hardware request for the whole
device to enter system Deep Sleep. A CPU waiting in CPU Deep Sleep state
is functionally identical to CPU Sleep mode with the exception of the
hardware request.
7. If only one CPU is in Deep Sleep mode the system will remain in system
LP or ULP mode until the other CPU also enters CPU Deep Sleep. While
waiting, a masked interrupt can wake the CPU to Active mode.
1. High-frequency clocks
are shut down.
System LP/ Hardware action 2. Retention is enabled
ULP and System 1. When both CPUs enter CPU Deep Sleep mode and the LPM_READY bit and non-retention logic is
Internal
CPU Deep Deep Sleep [5] of the PWR_CTL register reads '1', the device will automatically transition reset.
Sleep to system Deep Sleep power mode. 3. Active regulator is dis-
abled and Deep Sleep
regulator takes over.

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 Device Power Modes

Table 19-3. Power Mode Transitions

Initial State Final State Type Trigger Actions
Firmware action
Perform these steps to enter Hibernate mode (LPM_READY bit [5] of the
PWR_CTL register should read '1' before performing these steps):
1. Set the TOKEN bits [7:0] of the PWR_HIBERNATE register (optional) and
PWR_HIB_DATA register to some application-specific branching data that 1. CPU enters low-power
can be used on a wakeup event from Hibernate mode. mode.
2. Set the UNLOCK bits [8:15] of the PWR_HIBERNATE register to 0x3A, 2. Both high-frequency
this ungates writes to FREEZE and HIBERNATE bits of the PWR_HIBER- and low-frequency clocks
NATE register. are shut down.
3. Configure wakeup pins polarity (POLARITY_HIBPIN bits [23:20]), wakeup 3. Retention is enabled
System LP/ pins mask (MASK_HIBPIN bits [27:24]) and wakeup alarm mask (MASK_HI- and non-retention logic is
System
ULP and Internal BALARM bit [18]) in the PWR_HIBERNATE register based on the applica- reset.
Hibernate
CPU Active tion requirement. 4. Both Active and Deep
4. Optionally, set the FREEZE bit [17] of the PWR_HIBERNATE register to Sleep regulators are
freeze the I/O pins. powered down. The
5. Set the HIBERNATE bit [31] of the PWR_HIBERNATE register to enter peripherals that are
Hibernate mode. active in the Hibernate
domain operate directly
6. Ensure that the write operation to the PWR_HIBERNATE register is
out of VDDD.
complete by reading the PWR_HIBERNATE register. Otherwise, instead of
entering Hibernate mode, the CPU may start executing instructions after the
write instruction. When the write is followed by a WFI/WFE instruction, the
WFI/WFE can prevent the write from taking effect. On completion of the
write operation, the device automatically enters Hibernate mode.

19.3.3 Wakeup Transitions

Table 19-4. Wakeup Transitions
Initial State Final State Type Trigger Actions

Any peripheral 1. Clock to CPU is ungated.

CPU Sleep CPU Active Internal/External interrupt masked to 2. Peripheral interrupt is serviced by CPU.
CPU 3. Device remains in current system LP or ULP power mode.
1. Active regulator and references are enabled.
2. Retention is disabled and non-retention reset is de-asserted.
3. High-frequency clocks are turned on.
4. CPU exits low-power mode and services the interrupt.
System LP/ 5. Returns to previous system LP or ULP power mode.
System Deep ULP Active Any Deep Sleep
Internal/External Note: If only one CPU wakes up from the system Deep Sleep
Sleep and CPU interrupt
interrupt, then the other CPU remains in the CPU Deep Sleep
Active
state until its Deep Sleep interrupt wakes it up. However, the
system will wake up to LP or ULP mode. Note that a Deep Sleep
interrupt can wake up either one or both CPUs depending on the
WIC configuration for the CPU. See the Interrupts chapter on
page 56.
1. Device is reset and goes through a reset to active power-up
transition.
Wakeup pin, RTC 2. Optionally, read the TOKEN bits [7:0] of the
System LP alarm, WDT interrupt, PWR_HIBERNATE and PWR_HIB_DATA registers for
Hibernate and CPU External or Low-Power application-specific branching from hibernate wakeup.
Active comparator output 3. Optionally, set the I/O drive modes by reading the I/O frozen
asserts output and setting the I/O output to the read value.
4. Unfreeze the I/O cells by clearing the FREEZE bit [17] of the
PWR_HIBERNATE register.

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 Device Power Modes

19.4 Summary
Table 19-5. Resources Available in Different Power Modes
Power Modes
LP ULP
Component Power Off
CPU Sleep/ CPU Sleep/ Deep Sleep Hibernate XRES
CPU Active CPU Active with Backup
Deep Sleep Deep Sleep

Core functions
CPU On Sleep On Sleep Retention Off Off Off
SRAM On On On On Retention Off Off Off
Flash Read/Write Read/Write Read Only Read Only Off Off Off Off
High-Speed Clock
On On On On Off Off Off Off
(IMO, ECO, PLL, FLL)
LVD On On On On Off Off Off Off
ILO On On On On On On Off Off
Peripherals
SMIF/SHDC On On On On Retention Off Off Off
SAR ADC On On On On On Off Off Off
LPCMP On On On On a a Off Off
On On
TCPWM On On On On Off Off Off Off
CSD On On On On Retention Off Off Off
LCD On On On On On Off Off Off
Retention (I2C/SPI
SCB On On On On Off Off Off
wakeup available)b
GPIO On On On On On Freeze Off Off
Watchdog timer On On On On On On Off Off
Multi-Counter WDT On On On On On Off Off Off
Resets
XRES On On On On On On On Off
POR On On On On On On Off Off
BOD On On On On On Off Off Off
Watchdog reset On On On On On Onc Off Off
Backup domain
WCO, RTC, alarms On On On On On On On On
a. Low-Power comparator may be optionally enabled in the Hibernate mode to generate wakeup.
b. Only the SCB with system Deep Sleep support is available in the Deep Sleep power mode; other SCBs are not available in the Deep Sleep power mode.
c. Watchdog interrupt can generate a Hibernate wakeup. See the Watchdog Timer chapter on page 283 for details.

19.5 Register List

Name Description
PWR_CTL Power Mode Control register – controls the device power mode options and allows observation of current state
PWR_HIBERNATE Hibernate Mode register – controls various Hibernate mode entry/exit related options
PWR_HIB_DATA Hibernate Mode Data register – data register that is retained through a hibernate wakeup sequence
Cortex-M4 System Control register – controls the CM4 CPU sleep and deep sleep decisions on the WFI/WFE
CM4_SCS_SCR instruction execution. This register is detailed in the ARMv7-M Architecture Reference Manual available from
Arm

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 Device Power Modes

Name Description
Cortex-M0+ System Control register – controls the CM0+ CPU sleep and deep sleep decisions on the WFI/
CM0P_SCS_SCR WFE instruction execution. This register is detailed in the ARMv7-M Architecture Reference Manual available
from Arm
Controls the CM0+ power state. Note that this register may only be modified by the CM4 while the CM0+ is in
CPUSS_CM0_CTL
CPU Deep Sleep mode
CPUSS_CM0_STATUS Specifies if the CM0+ is in CPU Active, Sleep, or Deep Sleep power mode
Controls the CM4 power state. Note that this register may only be modified by the CM0+ while the CM4 is in
CPUSS_CM4_PWR_CTL
CPU Deep Sleep mode.
CPUSS_CM4_STATUS Specifies if the CM4 is in CPU Active, Sleep, or Deep Sleep power mode

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 234
 20. Backup System

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Backup domain adds an “always on” functionality to PSoC 6 MCUs using a separate power domain supplied by a backup
supply (VBACKUP) such as a battery or supercapacitor. It contains a real-time clock (RTC) with alarm feature, supported by a
32768-Hz watch crystal oscillator (WCO), and power-management IC (PMIC) control.
Backup is not a power mode; it is a power domain with its own power supply, which can be active during any of the device
power modes. For more details, see the Power Supply and Monitoring chapter on page 218 and Device Power
Modes chapter on page 225.

20.1 Features
■ Fully-featured RTC
❐ Year/Month/Date, Day-of-Week, Hour : Minute : Second fields
❐ All fields binary coded decimal (BCD)
❐ Supports both 12-hour and 24-hour formats
❐ Automatic leap year correction
■ Configurable alarm function
❐ Alarm on Month/Date, Day-of-Week, Hour : Minute : Second fields
❐ Two independent alarms
■ 32768-Hz WCO with calibration
■ Automatic backup power switching
■ Built-in supercapacitor charger
■ External PMIC control
■ 32-byte backup registers

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 Backup System

20.2 Architecture
Figure 20-1. Block Diagram

AHB-Lite Bus

User RTC (Power Supply Pins)

AHB
Registers Registers
Interface V DDBAK Backup V DDD
Power
RTC RTC Switch V BACKUP
MMIO
Interface Alarm Alarm

Config Config
PMIC_W akeup_In

W atch
Backup PMIC_W akeup_Out
Crystal
Registers
Oscillator
(32 bytes)
(W CO) (Controls an External
Power Management IC)
LFCLK
(from System Resources)

WCO_IN W CO_OUT
(Crystal and Capacitor Connections /
External Clock Input)

The Backup system includes an accurate WCO that can The VDDBAK_CTL bitfield in the BACKUP_CTL register
generate the clock required for the RTC with the help of an controls the behavior of the power selector switch. See the
external crystal or external clock inputs. The RTC has a registers TRM for details of this register. Possible options
programmable alarm feature, which can generate interrupts are:
to the CPU. An AHB-Lite interface provides firmware access ■ VDDBAK_CTL = 0 (Default mode): Selects VDDD when
to MMIO registers in the Backup domain.
the brownout detector in the system resources is
An automatic backup power switch selects the VDDBAK enabled and no brownout situation is detected (see the
supply required to run the blocks in the Backup domain – Power Supply and Monitoring chapter on page 218 for
either VDDD (main power) or VBACKUP (backup battery/ more details). Otherwise, it selects the highest supply
supercapacitor power). among VDDD and VBACKUP.
■ VDDBAK_CTL = 1, 2, or 3: Always selects VBACKUP for
The domain also has backup registers that can store 32
bytes of data and retain its contents even when the main debug purposes.
supply (VDDD) is OFF as long as the backup supply If a supercapacitor is connected to VBACKUP, the PSoC 6
(VBACKUP) is present. The Backup system can also control MCU can charge the supercapacitor while VDDD is available.
an external PMIC that supplies VDDD. Supercapacitor charging can be enabled by writing “3C” to
the EN_CHARGE_KEY bitfield in the BACKUP_CTL
register. Note that this feature is for charging
20.3 Power Supply supercapacitors only and cannot safely charge a battery. Do
not write this key when VBACKUP is connected to a battery.
Power to the backup system (VDDBAK) is automatically
Battery charging must be handled at the board level using
switched between VDDD (main supply) and VBACKUP
external circuitry.
(Backup domain supply). VBACKUP is typically connected to
an independent supply derived from a battery or Note: If VDDD and VBACKUP are connected on the PCB, the
supercapacitor (see the Power Supply and Backup domain may require an explicit reset triggered by
Monitoring chapter on page 218 for more details). firmware using the RESET bitfield in the BACKUP_RESET
register. This firmware reset is required if the VBACKUP
There are no VBACKUP versus VDDD sequencing restrictions
supply was invalid during a previous power supply ramp-up
for the power selector switch. Either VBACKUP or VDDD may or brownout event. It is not necessary to reset the Backup
be removed during normal operation, and the Backup domain if the RES_CAUSE register indicates a non-power-
system will remain powered. related reset as the reset cause, or if the PSoC 6 MCU just

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 Backup System

woke from the Hibernate power mode and the supply is 20.4.1 WCO with External Clock/Sine
assumed to have been valid the entire time.
Wave Input
It is possible to monitor the VBACKUP supply using an ADC
The WCO can also operate from external clock/sine wave
attached to AMUXBUS-A by setting the VBACKUP_MEAS inputs. In these modes, WCO must be bypassed by setting
bit in the BACKUP_CTL register. Note that the VBACKUP the WCO_BYPASS bit in the BACKUP_CTL register before
signal is scaled by 10 percent so it is within the supply range enabling the WCO. Also, GPIOs must be configured for
of the ADC. See the SAR ADC chapter on page 506 for WCO_OUT and WCO_IN signals (in Analog mode). The
more details on how to connect the ADC to AMUXBUS-A. external clock/sine wave input modes, prescaler settings,
and electrical connections are as follows:
20.4 Clocking ■ 32768-Hz external clock mode: In this mode, WCO_IN is
floating and WCO_OUT is externally driven by a 32768-
The RTC primarily runs from a 32768-Hz clock, after it is Hz square wave clock toggling between ground and
scaled down to one-second ticks. This clock signal can VDDD supply levels. In this configuration, the WCO_OUT
come from either of these internal sources: pin functions as a digital input pin for the external clock.
■ Watch-crystal oscillator (WCO). This is a high-accuracy The PRESCALER bitfield in BACKUP_CTL must be
clock generator that is suitable for RTC applications and configured for a prescaler value of 32768.
requires a 32768-Hz external crystal populated on the ■ 60-Hz external clock mode: This mode can be used for
application board. WCO can also operate without deriving a clock from the 60-Hz AC mains supply. In this
crystal, using external clock/sine wave inputs. These mode, WCO_OUT is floating and WCO_IN is driven with
additional operating modes are explained later in this an external sine wave with zero DC offset, derived from
section. WCO is supplied by the Backup domain and can the 60-Hz/120-V mains through a 100:1 capacitive
therefore run without VDDD present. divider. For example, a suitable capacitive divider can be
■ Alternate Backup Clock (ALTBAK): This option allows formed by connecting a 220-pF/6-V capacitor between
the use of LFCLK generated by the System Resources WCO_IN and ground, and a 2.2-pF/ 200-V capacitor
Subsystem (SRSS) as the Backup domain clock. Note between WCO_IN and the 60-Hz/120-V mains input.
that LFCLK is not available in all device power modes or The PRESCALER bitfield in BACKUP_CTL must be
when the VDDD is removed. (See the Device Power configured for a prescaler value of 60.
Modes chapter on page 225 for more detail.) ■ 50-Hz external clock mode: This mode is similar to the
60-Hz mode, and can be used for 50-Hz/220-V mains
Clock glitches can propagate into the Backup system
standard. The capacitive divider explained previously
when LFCLK is enabled or disabled by the SRSS. In
can be modified to fit this type of supply by having a 1-pF
addition, LFCLK may not be as accurate as WCO
/250-V capacitor between WCO_IN and the mains input.
depending on the actual source of LFCLK. Because of
The PRESCALER bitfield in BACKUP_CTL must be
these reasons, LFCLK is not recommend for RTC
configured for a prescaler value of 50.
applications. Also, if the WCO is intended as the clock
source then choose it directly instead of routing through
LFCLK. 20.4.2 Calibration
For more details on these clocks and calibration, see the The absolute frequency of the clock input can be calibrated
Clocking System chapter on page 242. using the BACKUP_CAL_CTL register. Calibration only
works when the PRESCALER bitfield in BACKUP_CTL is
The RTC clock source can be selected using the CLK_SEL set to 32768.
bitfield in the BACKUP_CTL register. The WCO_EN bit in
the BACKUP_CTL register can be used to enable or disable CALIB_VAL is a 6-bit field in the BACKUP_CAL_CTL
the WCO. If the WCO operates with an external crystal, register that holds the calibration value for absolute
make sure the WCO_BYPASS bit in the BACKUP_CTL frequency (at a fixed temperature). One bit of this field
register is cleared before enabling the WCO. In addition, the translates into 128 ticks to be added or removed from the
PRESCALER bitfield in BACKUP_CTL must be configured clock count. Therefore, each bit translates to a change of
for a prescaler value of 32768. 1.085 ppm (= 128/(60*60*32768)).

Note: External crystal and bypass capacitors of proper The CALIB_SIGN field in the BACKUP_CAL_CTL register
values must be connected to WCO_IN and WCO_OUT and controls whether the ticks are added (it takes fewer clock
pins. See the PSoC 61 datasheet/PSoC 62 datasheet for ticks to count one second) or subtracted (it takes more clock
details of component values and electrical connections. In ticks to count one second).
addition, GPIOs must be configured for WCO_OUT and
For more information, see the BACKUP_CAL_CTL register
WCO_IN signals. See the I/O System chapter on page 261
in the registers TRM.
to know how to configure the GPIOs.

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 Backup System

20.5 Reset
The PSoC 6 MCU reset sources that monitor device power supply such as power-on reset (POR) and brownout reset (BOD)
cannot reset the backup system as long as the backup supply (VDDBAK) is present. Moreover, internal and external resets
such as watchdog timer (WDT) reset and XRES cannot reset the backup system. The backup system is reset only when:
■ all the power supplies are removed from the Backup domain, also known as a “cold-start”.
■ the firmware triggers a Backup domain reset using the RESET bitfield in the BACKUP_RESET register.

20.6 Real-Time Clock

The RTC consists of seven binary coded decimal (BCD) fields and one control bit as follows:
Table 20-1. RTC Fields
Number
Bitfield Name Description
of Bits
RTC_SEC 7 Calendar seconds in BCD, 0-59
RTC_MIN 7 Calendar minutes in BCD, 0-59
Calendar hours in BCD; value depends on 12-hour or 24-hour format set in the BACKUP_RTC_TIME register.
In 24-hour mode, bits RTC_HOUR[5:0] = 0–23
RTC_HOUR 6
In 12-hour mode, bit RTC_HOUR[5] = 0 for AM and 1 for PM
Bits RTC_HOUR[4:0] = 1–12
CTRL_12HR 1 Select the 12-hour or 24-hour mode: 1=12HR, 0=24HR
Calendar day of the week in BCD, 1-7
RTC_DAY 3
You should define the meaning of the values
Calendar day of the month in BCD, 1-31
RTC_DATE 6
Automatic leap year correction
RTC_MON 4 Calendar month in BCD, 1-12
RTC_YEAR 8 Calendar year in BCD, 0-99 (Can be used to represent years 2000 -2099)

BCD encoding indicates that each four-bit nibble represents registers require special care. These processes are
one decimal digit. Constant bits are omitted in the RTC explained in the following section.
implementation. For example, the maximum RTC_SEC is
59, which can be represented as two binary nibbles 0101b 20.6.1 Reading RTC User Registers
1001b. However, the most significant bit is always zero and
is therefore omitted, making the RTC_SEC a 7-bit field. To start a read transaction, the firmware should set the
READ bit in the BACKUP_RTC_RW register. When this bit
The RTC supports both 12-hour format with AM/PM flag, is set, the RTC registers will be copied to user registers and
and 24-hour format for “hours” field. The RTC also includes frozen so that a coherent RTC value can safely be read by
a “day of the week” field, which counts from 1 to 7. You the firmware. The read transaction is completed by clearing
should define which weekday is represented by a value of the READ bit.
‘1’.
The READ bit cannot be set if:
The RTC implements automatic leap year correction for the
Date field (day of the month). If the Year is divisible by 4, the ■ RTC is still busy with a previous operation (that is, the
month of February (Month=2) will have 29 days instead of RTC_BUSY bit in the BACKUP_STATUS register is set)
28. When the year reaches 2100 - the Year field rolls over ■ WRITE bit in the BACKUP_RTC_RW register is set
from 99 to 00 - the leap year correction will be wrong (2100
The firmware should verify that the above bits are not set
is flagged as a leap year which it is not); therefore, an
before setting the READ bit.
interrupt is raised to allow the firmware to take appropriate
actions. This interrupt is called the century interrupt.
20.6.2 Writing to RTC User Registers
User registers containing these bitfields are
BACKUP_RTC_TIME and BACKUP_RTC_DATE. See the When the WRITE bit in the BACKUP_RTC_RW register is
corresponding register descriptions in the registers TRM for set, data can be written into the RTC user registers;
details. As the user registers are in the high-frequency bus- otherwise, writes to the RTC user registers are ignored.
clock domain and the actual RTC registers run from the low- When all the RTC writes are done, the firmware must clear
frequency 32768-Hz clock, reading and writing RTC the WRITE bit for the RTC update to take effect. After the

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 Backup System

WRITE bit is cleared, the hardware will copy all the new data cleared by a WRITE transaction. If the write operation is in
on one single WCO clock edge to ensure coherency to the progress (RTC_BUSY), data corruption can occur if the
actual RTC registers. system is reset or enters Deep Sleep or Hibernate mode.
The WRITE bit cannot be set if:
■ RTC is still busy with a previous operation (that is, the 20.7 Alarm Feature
RTC_BUSY bit in the BACKUP_STATUS register is set)
The Alarm feature allows the RTC to be used to generate an
■ READ bit in the BACKUP_RTC_RW register is set
interrupt, which may be used to wake up the system from
The firmware should make sure that the values written to the Sleep, Deep Sleep, and Hibernate power modes.
RTC fields form a coherent legal set. The hardware does not
The Alarm feature consists of six fields corresponding to the
check the validity of the written values. Writing illegal values
fields of the RTC: Month/Date, Day-of-Week, and
results in undefined behavior of the RTC.
Hour : Minute : Second. Each Alarm field has an enable bit
When in the middle of an RTC update with the WRITE bit that needs to be set to enable matching; if the bit is cleared,
set, and a brownout, reset, or entry to Deep Sleep or then the field will be ignored for matching.
Hibernate mode occurs, the write operation will not be
The Alarm bitfields are as follows:
complete. This is because the WRITE bit will be cleared by
a reset, and the RTC update is triggered only when this bit is

Table 20-2. Alarm Bitfields

Number
Bitfield Name Description
of Bits
ALARM_SEC 7 Alarm seconds in BCD, 0-59
ALARM_SEC_EN 1 Alarm second enable: 0=disable, 1=enable
ALARM _MIN 7 Alarm minutes in BCD, 0-59
ALARM _MIN_EN 1 Alarm minutes enable: 0=disable, 1=enable
Alarm hours in BCD, value depending on the 12-hour or 24-hour mode
In 12-hour mode, bit ALARM _HOUR[5] = 0 for AM and 1 for PM,
ALARM _HOUR 6
bits ALARM_HOUR[4:0] = 1–12
In 24-hour mode, bits ALARM_HOUR[5:0] = 0–23
ALARM _HOUR_EN 1 Alarm hour enable: 0=disable, 1=enable
Calendar day of the week in BCD, 1-7
ALARM_DAY 3
You should define the meaning of the values
ALARM_DAY_EN 1 Alarm day of the week enable: 0=disable, 1=enable
Alarm day of the month in BCD, 1-31
ALARM _DATE 6
Leap year corrected
ALARM _DATE_EN 1 Alarm day of the month enable: 0=disable, 1=enable
ALARM _MON 4 Alarm month in BCD, 1-12
ALARM _MON_EN 1 Alarm month enable: 0=disable, 1=enable
Master enable for alarm.
0: Alarm is disabled. Fields for date and time are ignored.
ALM_EN 1
1: Alarm is enabled. If none of the date and time fields are enabled, then this alarm triggers once
every second.

If the master enable (ALM_EN) is set, but all alarm fields for date and time are disabled, an alarm interrupt will be generated
once every second. Note that there is no alarm field for Year because the life expectancy of a chip is about 20 years and thus
setting an alarm for a certain year means that the alarm matches either once or never in the lifetime of the chip.
The PSoC 6 MCU has two independent alarms. See the BACKUP_ALM1_TIME, BACKUP_ALM1_DATE,
BACKUP_ALM2_TIME, and BACKUP_ALM2_DATE registers in the registers TRM for details.
Note that the alarm user registers, similar to RTC user registers, require certain special steps before read/write operations, as
explained in sections Reading RTC User Registers on page 238 and Writing to RTC User Registers on page 238.
Interrupts must be properly configured for the RTC to generate interrupts/wake up events. Also, to enable RTC interrupts to
wake up the device from Hibernate mode, the MASK_HIBALARM bit in the PWR_HIBERNATE register must be set. See the
Device Power Modes chapter on page 225 and Interrupts chapter on page 56 for details.

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 Backup System

The BACKUP_INTR_MASK register can be used to disable certain interrupts from the backup system.

Table 20-3. Interrupt Mask Bits

Bit Name Description
ALARM1 Mask bit for interrupt generated by ALARM1
ALARM2 Mask bit for interrupt generated by ALARM2
CENTURY Mask bit for century interrupt (interrupt generated when the Year field rolls over from 99 to 00)

The RTC alarm can also control an external PMIC as explained in the following section.

20.8 PMIC Control

The backup system can control an external PMIC that supplies VDDD. PMIC enable is an active-high output that is available at
a certain pin PMIC_Wakeup_Out. See the PSoC 61 datasheet/PSoC 62 datasheet for the location of this pin. This pin can be
connected to the “enable” input of a PMIC. PMIC_Wakeup_Out will retain its state until the backup domain is powered. If
there is a brownout and backup domain looses power, the pin is reset to its default high value.
Table 20-4 shows the bitfields in BACKUP_PMIC_CTL.

Table 20-4. PMIC Control Bits

Number
Bitfield Name Description
of Bits
This byte must be set to 0x3A for PMIC to be disabled. Any other value in this field will
UNLOCK 8 cause writes to PMIC_EN to be ignored. Do not change PMIC_EN in the same write cycle
as setting/clearing the UNLOCK code; do these in separate write cycles.
POLARITY 1 Reserved for future use. Keep this bit at ‘1’.
Output enable of the PMIC_EN pin.
0: PMIC_EN pin output is HI-Z. This allows the PMIC_EN pin to be used as a GPIO. The
PMIC_EN_OUTEN 1
HI-Z condition is kept only if the UNLOCK key (0x3A) is present.
1: PMIC_EN pin output is enabled.
Override normal PMIC controls to prevent errant firmware from accidentally turning off the
PMIC.
0: Normal operation; PMIC_EN and PMIC_OUTEN work as explained in their bitfield
PMIC_ALWAYSEN 1 descriptions.
1: PMIC_EN is forced set; PMIC_EN and PMIC_OUTEN are ignored.
This bit is a write-once bit that cannot be cleared until the next Backup domain reset.
Enable external PMIC (hardware output available at pin PMIC_Wakeup_Out). This bit is
enabled by default.
PMIC_EN 1
This bit will only clear if the UNLOCK field was written correctly in a previous write operation
and PMIC_ALWAYSEN = 0.

Note that two writes to the BACKUP_PMIC_CTL register removed. The time between firmware disabling the
are required to change the PMIC_EN setting. The first write PMIC_EN bit and the actual removal of VDDD depends on
should update the desired settings (including the UNLOCK the external PMIC and supply-capacitor characteristics.
code) but should not change PMIC_EN or
Additionally, PMIC can be turned on by one of these events:
PMIC_EN_OUTEN. The second write must use the same bit
values as the first one except desired PMIC_EN/ ■ An RTC Alarm/Century Interrupt
PMIC_EN_OUTEN settings. ■ A logic high input at the PMIC_Wakeup_In pin. See the
PSoC 61 datasheet/PSoC 62 datasheet for the location
When the PMIC_EN bit is cleared by firmware, the external
of this pin. This allows a mechanical button or an
PMIC is disabled and the system functions normally until
external input from another device to wake up the
VDDD is no longer present (OFF with Backup mode). The
system and enable the PMIC. The POLARITY bit in the
firmware can set this bit if it does so before VDDD is actually

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 Backup System

BACKUP_PMIC_CTL register must be set to ‘1’ to use 20.9 Backup Registers

this feature. The same wakeup pin PMIC_Wakeup_In
can wake up the device from Hibernate mode. See the The Backup domain has sixteen registers
Device Power Modes chapter on page 225 for details. (BACKUP_BREG0 to BACKUP_BREG15), which can be
used to store 32 bytes of important information/flags. These
Make sure that one or more of these events are configured
registers retain their contents even when the main supply
properly, and a battery or supercapacitor is connected to
(VDDD) is off as long as backup supply (VBACKUP) is present.
VBACKUP with sufficient charge to power the backup system
These registers can also be used to store information that
until one of these events occur. Otherwise, the PMIC may
must be retained when the device enters Hibernate mode.
continue to be in the disabled state with the PSoC 6 MCU
unable to enable it again.

20.10 Register List

Table 20-5. Backup Registers
Register Name Description
BACKUP_CTL Main control register (including power and clock)
BACKUP_RTC_RW RTC read/write control register
BACKUP_STATUS Status register
BACKUP_RTC_TIME Calendar seconds, minutes, hours, and day of week
BACKUP_RTC_DATE Calendar day of month, month, and year
BACKUP_ALM1_TIME Alarm 1 seconds, minute, hours, and day of week
BACKUP_ALM1_DATE Alarm 1 day of month, and month
BACKUP_ALM2_TIME Alarm 2 seconds, minute, hours, and day of week
BACKUP_ALM2_DATE Alarm 2 day of month, and month
BACKUP_INTR Interrupt request register
BACKUP_INTR_MASK Interrupt mask register
BACKUP_INTR_MASKED Interrupt masked request register
BACKUP_PMIC_CTL PMIC control register
BACKUP_BREG0 to BACK-
Backup registers
UP_BREG15
BACKUP_RESET Reset register for the backup domain

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 241
 21. Clocking System

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

PSoC 6 MCU provides flexible clocking options with on-chip crystal oscillators, phase lock loop, frequency lock loop, and
supports multiple external clock sources.

21.1 Features
The PSoC 6 MCU clock system includes these resources:
■ Two internal clock sources:
❐ 8-MHz internal main oscillator (IMO)
❐ 32-kHz internal low-speed oscillator (ILO)
■ Three external clock sources
❐ External clock (EXTCLK) generated using a signal from an I/O pin
❐ External 16–35 MHz crystal oscillator (ECO)
❐ External 32-kHz watch crystal oscillator (WCO)
■ One frequency lock loop (FLL) with 24–100 MHz output range
■ Two phase-locked loop (PLL) with 10.625–150 MHz output range

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 Clocking System

21.2 Architecture
Figure 21-1 gives a generic view of the clocking system in PSoC 6 MCUs.
Figure 21-1. Clocking System Block Diagram

Path Mux (FLL/PLLs) Root Clock mux (Clks_HF[i] are Root Clocks)
CM4
Clock
Predivider CLK_HF[0]
FLL (1/2/4/8) CM0+
IMO clk_peri
Clock

EXTCLK Predivider CLK_HF[1] Peripheral

(1/2/4/8) Audio Clock
PLL1
Dividers
ECO

PLL2 Predivider CLK_HF[2] QSPI,

(1/2/4/8) SDHC[1]

CLK_PATH3 Predivider CLK_HF[3]

USB
(1/2/4/8)
CLK_PATH4

Predivider CLK_HF[4] SDHC[0]

(1/2/4/8)
CLK_PATH5

Predivider CLK_HF[5] clk_ext

(1/2/4/8)
ILO
CLK_LF
WCO

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 243
 Clocking System

21.3 Clock Sources sets the crystal drive level when automatic gain control
(AGC) is enabled (CLK_ECO_CONFIG.AGC_EN = 1). AGC
must be enabled all the time.
21.3.1 Internal Main Oscillator (IMO)
ATRIM and WDTRIM values are set at 15 and 7,
The IMO is an accurate, high-speed internal (crystal-less) respectively.
oscillator that produces a fixed frequency of 8 MHz. The
IMO output can be used by the PLL or FLL to generate a The GTRIM sets up the trim for amplifier gain based on the
wide range of higher frequency clocks, or it can be used calculated gm, as shown in Table 21-1.
directly by the high-frequency root clocks.
Table 21-1. GTRIM Settings
When USB is present the USB Start-of-Frame (SOF) signal
gm GTRIM
is used to trim the IMO to ensure that the IMO matches the
accuracy of the USB SOF. The ENABLE_LOCK bitfield in gm < 9 mA/V 0x01
the USBFS0_USBDEV_CR register of the USB block needs 9 mA/V < gm < 18 mA/V 0x00
to be set for this feature to work. The driver for the USB
block in the PDL does this automatically. gm > 18 mA/V INT (gm / 9 mA/V)

The IMO is available only in the system LP and ULP power

RTRIM and FTRIM are set to 0 and 3, respectively.
modes.
First, set up the trim values based on Table 21-1 and other
21.3.2 External Crystal Oscillator (ECO) listed values; then enable the ECO. After the ECO is
enabled, the CLK_ECO_STATUS register can be checked
The PSoC 6 MCU contains an oscillator to drive an external to ensure it is ready.
16-MHz to 35-MHz crystal. This clock source is built using
an oscillator circuit in PSoC. The circuit employs an external 21.3.3 External Clock (EXTCLK)
crystal that needs to be populated on the external crystal
pins of the PSoC 6 MCU. See AN218241 - PSoC 6 MCU The external clock is a 0- to 100-MHz range clock that can
Hardware Design Considerations for more details. be sourced from a signal on a designated I/O pin. This clock
can be used as the source clock for either the PLL or FLL, or
The ECO can be enabled by using the CLK_ECO_CONFIG can be used directly by the high-frequency clocks.
ECO_EN register bitfields.
When manually configuring a pin as an input to EXTCLK,
21.3.2.1 ECO Trimming the drive mode of the pin must be set to high-impedance
digital to enable the digital input buffer. See the I/O
The ECO supports a wide variety of crystals and ceramic System chapter on page 261 for more details. Consult the
resonators with the nominal frequency range specification of PSoC 61 datasheet/PSoC 62 datasheet to determine the
f = 16 MHz – 35 MHz. The crystal manufacturer typically specific pin used for EXTCLK. See KBA224493 for more
provides numerical values for parameters, namely the details.
maximum drive level (DL), the maximum equivalent series
resistance (ESR), shunt capacitance of the crystal (C0), and
21.3.4 Internal Low-speed Oscillator (ILO)
the parallel load capacitance (CL). These parameters can be
used to calculate the transconductance (gm) and the The ILO operates with no external components and outputs
maximum peak to peak (VPP). a stable clock at 32.768 kHz nominal. The ILO is relatively
low power and low accuracy. It is available in all power
Max peak to peak value: modes. If the ILO is to remain active in Hibernate mode, and
across power-on-reset (POR) or brownout detect (BOD), the
V PP = 2  V P
ILO_BACKUP bit must be set in the CLK_ILO_CONFIG
register.
 DL-
2----------------
ESR The ILO can be used as the clock source for CLK_LF, which
V P = 2  ---------------------------------------------- in turn can be used as a source for the backup domain
4  f   C L + C 0 
(CLK_BAK). CLK_BAK runs the real-time clock (RTC). This
Transconductance: can be useful if you do not wish to populate a WCO.
2 Although the ILO is not suitable as an RTC due to its poor
g m = 4  5   2  f   C L + C 0    ESR
accuracy, it can be used as a HIBERNATE wakeup source
ECO does not support VPP less than 1.3 V. using the wakeup alarm facility in the RTC. In this case, the
VDDD rail must be supplied during HIBERNATE for the ILO
The following fields are found in the CLK_TRIM_ECO_CTL
register. The Amplitude trim (ATRIM) and WDTRIM settings to run, and the ILO_BACKUP bit must be set in the
control the trim for amplitude of the oscillator output. ATRIM CLK_ILO_CONFIG register. CLK_LF is also the source of

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 Clocking System

the MCWDT timers; see the Watchdog Timer chapter on 21.3.5 Watch Crystal Oscillator (WCO)
page 283 for details.
The WCO is a highly accurate 32.768-kHz clock source. It is
The ILO is always the source of the watchdog timer (WDT). the primary clock source for the RTC. The WCO can also be
The ILO is enabled and disabled with the ENABLE bit of the used as a source for CLK_LF.
CLK_ILO_CONFIG register. Always leave the ILO enabled The WCO can be enabled and disabled by setting the
as it is the source of the WDT. WCO_EN bit in the CTL register for the backup domain. The
If the WDT is enabled, the only way to disable the ILO is to WCO can also be bypassed and an external 32.768-kHz
first clear the WDT_LOCK bit in the WDT_CTL register and clock can be routed on a WCO output pin. This is done by
then clear the ENABLE bit in the CLK_ILO_CONFIG setting the WCO_BYPASS bit in the CTL register for the
register. If the WDT_LOCK bit is set, any register write to backup domain. See WCO with External Clock/Sine Wave
disable the ILO will be ignored. Enabling the WDT will Input on page 237 for more details.
automatically enable the ILO.
The calibration counters described in Clock Calibration 21.4 Clock Generation
Counters on page 256 can be used to measure the ILO
against a high-accuracy clock such as the ECO. This result
21.4.1 Phase-Locked Loop (PLL)
can then be used to determine how the ILO must be
adjusted. The ILO can be trimmed using the The PSoC 6 MCU contains two PLLs, which reside on
CLK_TRIM_ILO_CTL register. CLK_PATH1 and CLK_PATH2. They are capable of
generating a clock output in the range 10.625–150 MHz; the
input frequency must be between 4 and 64 MHz. This
makes it possible to use the IMO to generate much higher
clock frequencies for the rest of the system.
Figure 21-2. PLL Block Diagram

Lock
Detect Bypass
Reference Logic
Clock
Reference
Divider (Q) Voltage
Phase Charge control Output PLL OUT
Detector pump Oscillator Divider
Feedback (VCO)
Divider (P)

The PLL is configured following these steps: granularity; therefore, consider the frequency error of
the two closest choices.
Note: fref is the input frequency of the PLL, that is, the
d. Choose the best combination of divider parameters
frequency of input clock, such as 8 MHz for the IMO.
depending on the application. Some possible
1. Determine the desired output frequency (fout). Calculate decision-making factors are: minimum output
the reference (REFERENCE_DIV), feedback frequency error, lowest power consumption (lowest
(FEEDBACK_DIV), and output (OUTPUT_DIV) dividers fvco), or lowest jitter (highest fvco).
subject to the following constraints:
2. Program the divider settings in the appropriate
a. PFD frequency (phase detector frequency). fpfd = fref CLK_PLL_CONFIG register. Do not enable the PLL on
/ REFERENCE_DIV. It must be in the range 4 MHz the same cycle as configuring the dividers. Do not
to 8 MHz. There may be multiple reference divider change the divider settings while the PLL is enabled.
values that meet this constraint.
3. Enable the PLL (CLK_PLL_CONFIG.ENABLE = 1). Wait
b. VCO frequency. fvco = fpfd * FEEDBACK_DIV. It must at least 1 µs for PLL circuits to start.
be in the range 170 MHz to 400 MHz. There may be 4. Wait until the PLL is locked before using the output. By
multiple feedback divider values that meet this default, the PLL output is bypassed to its reference clock
constraint with different REFERENCE_DIV choices. and will automatically switch to the PLL output when it is
c. Output frequency. fout = fvco / OUTPUT_DIV. It must locked. This behavior can be changed using
be in the range 10.625 MHz to 150 MHz. Note that PLL_CONFIG.BYPASS_SEL. The status of the PLL can
your device may not be capable of operating at this be checked by reading CLK_PLL_STATUS. This register
frequency; check the device datasheet. It may not be contains a bit indicating the PLL has locked. It also
possible to get the desired frequency due to contains a bit indicating if the PLL lost the lock status.

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 Clocking System

To disable the PLL, first set the PLL_CONFIG.BYPASS_SEL is set by the FLL_REF_DIV field in the CLK_FLL_CONFIG2
to PLL_REF. Then wait at least six PLL output clock cycles register.
before disabling the PLL by setting PLL_CONFIG.ENABLE
After the CCO clocks are counted, they are compared
to ‘0’.
against an ideal value and an error is calculated. The ideal
value is programmed into the FLL_MULT field of the
21.4.2 Frequency Lock Loop (FLL) CLK_FLL_CONFIG register.
The PSoC 6 MCU contains one frequency lock loop (FLL), As an example, the reference clock is the IMO (8 MHz), the
which resides on Clock Path 0. The FLL is capable of desired CCO frequency is 100 MHz, the value for
generating a clock output in the range 24 MHz to 100 MHz; FLL_REF_DIV is set to 146. This means that the FLL will
the input frequency must be between 0.001 and 100 MHz, count the number of CCO clocks within 146 clock periods of
and must be at least 2.5 times less than the CCO frequency. the reference clock. In one clock cycle of the reference clock
This makes it possible to use the IMO to generate much (IMO), there should be 100 / 8 = 12.5 clock cycles of the
higher clock frequencies for the rest of the system. CCO. Multiply this number by 146 and the value of
The FLL is similar in purpose to a PLL but is not equivalent: FLL_MULT should be 1825.
■ FLL can start up (lock) much faster than the PLL. If the FLL counts a value different from 1825, it attempts to
■ It consumes less current than the PLL. adjust the CCO such that it achieves 1825 the next time it
counts. This is done by scaling the error term with
■ FLL does not lock the phase. At the heart of the FLL is a FLL_LF_IGAIN and FLL_LF_PGAIN found in
current-controlled oscillator (CCO). The output CLK_FLL_CONFIG3. Figure 21-3 shows how the error (err)
frequency of this CCO is controlled by adjusting the trim term is multiplied by FLL_LF_IGAIN and FLL_LF_PGAIN
of the CCO; this is done in hardware and is explained in and then summed with the current trim to produce a new
detail later in this section. trim value for the CCO. The CCO_LIMIT field in the
■ FLL can produce up to 100-MHz clock with good duty CLK_FLL_CONFIG4 can be used to put an upper limit on
cycle through its divided clock output. the trim adjustment; this is not needed for most situations.
■ FLL reference clock can be the WCO (32 kHz), IMO
(8 MHz), or any other periodic clock source.
Note: The CCO frequency must be at least 2.5 times
greater than the reference frequency.
The CCO can output a stable frequency in the 48 MHz to
200 MHz range. This range is divided into five sub-ranges
as shown by Table 21-2.

Table 21-2. CCO Frequency Ranges

CCO
0 1 2 3 4
Range
fmin 48 MHz 64 MHz 85 MHz 113 MHz 150 MHz
fmax 64 MHz 85 MHz 113 MHz 150 MHz 200 MHz

Note: The output of the CCO has an option to enable a

divide by two or not. For this device, the divide by two must
always be enabled.
Within each range, the CCO output is controlled via a 9-bit
trim field. This trim field is updated via hardware based on
the control algorithm described below.
A reference clock must be provided to the FLL. This
reference clock is typically the IMO, but could be many
different clock sources. The FLL compares the reference
clock against the CCO clock to determine how to adjust the
CCO trim. Specifically, the FLL will count the number of
CCO clock cycles inside a specified window of reference
clock cycles. The number of reference clock cycles to count

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 Clocking System

Figure 21-3. FLL Error Correction Diagram

limit

PGAIN

X max

err + new_trim

X 0

IGAIN

current_trim

The FLL determines whether it is “locked” by comparing the error term with the LOCK_TOL field in the CLK_FLL_CONFIG2
register. When the error is less than LOCK_TOL the FLL is considered locked.
After each adjustment to the trim the FLL can be programmed to wait a certain number of reference clocks before doing a
new measurement. The number of reference clocks to wait is set in the SETTLING_COUNT field of CLK_FLL_CONFIG3. Set
this such that the FLL waits ~1 µs before a new count. Therefore, if the 8-MHz IMO is used as the reference this field should
be programmed to ‘8’.
When configuring the FLL there are two important factors that must be considered: lock time and accuracy. Accuracy is the
closeness to the intended output frequency. These two numbers are inversely related to each other via the value of REF_DIV.
Higher REF_DIV values lead to higher accuracy, whereas lower REF_DIV values lead to faster lock times.
In the example used previously the 8-MHz IMO was used as the reference, and the desired FLL output was 100 MHz. For
that example, there are 12.5 CCO clocks in one reference clock. If the value for REF_DIV is set to ‘1’ then FLL_MULT must
be set to either ‘13’ or ‘12’. This will result in a CCO output of either 96 MHz or 104 MHz, and an error of 4 percent from the
desired 100 MHz. Therefore, the best way to improve this is to increase REF_DIV. However, the larger REF_DIV is, the
longer each measurement cycle takes, thus increasing the lock time. In this example, REF_DIV was set to 146. This means
each measurement cycle takes 146 * (1/8 MHz) = 18.25 µs, whereas when REF_DIV is set to 1, each measurement cycle
takes 1 * (1/ 8 MHz) 0.125 µs.
Another issue with lower REF_DIV values is that the minimum LOCK_TOL is 1, so the output of the CCO can have an error of
±1. In the example where REF_DIV = 1 and FLL_MULT = 13, the MULT value can really be 12, 13, or 14 and still be locked.
This means the output of the FLL may vary between 96 and 112 MHz, which may not be desirable.
Thus, a choice must be made between faster lock times and more accurate FLL outputs. The biggest change to make for this
is the value of REF_DIV. The following section describes how to configure all of the FLL registers and gives some example
equations to set REF_DIV N for best accuracy.

21.4.2.1 Configuring the FLL

This section provides a guide to calculate FLL parameters. ModusToolbox and the PDL provide drivers and calculators that
automatically populate the FLL registers based on FLL input and output frequency requirements.
The following equations are tailored to achieve the best accuracy.
In these equations:
N = REF_DIV
M = FLL _MULT
1. Set CCO_RANGE in the CLK_FLL_CONFIG4 register.
a. Determine the output frequency of the FLL.
b. Calculate the CCO frequency. The CCO frequency = 2 * FLL output frequency.

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 Clocking System

c. Use Table 21-3 to determine the CCO range.

d. Write CCO range into CCO_RANGE in the CLK_FLL_CONFIG4 register.

Table 21-3. CCO Frequency Ranges

CCO
0 1 2 3 4
Range
fmin 48 MHz 64 MHz 85 MHz 113 MHz 150 MHz
fmax 64 MHz 85 MHz 113 MHz 150 MHz 200 MHz

2. Set the FLL_OUTPUT_DIV in CLK_FLL_CONFIG. Set the output divider to ‘1’.

3. Set FLL_REF_DIV in CLK_FLL_CONFIG2.
FLL_REF_DIV divides the FLL input clock. The FLL counts the number of CCO clocks within one period of the divided
reference clock. A general equation to calculate the reference divider is as follows:

 2  f ref 
N = ROUNDUP  -----------------------------------------------------------
 CCO Trim Step  f CCO T arg et
Equation 21-1
The CCOTrimStep is found in Table 21-4.

Table 21-4. CCO Trim Steps

CCO Range 0 1 2 3 4
CCO_Trim_Steps 0.0011 0.0011 0.0011 0.0011 0.00117

A larger N results in better precision on the FLL output, but longer lock times; a smaller N will result in faster lock times,
but less precision.
Note: When the WCO is used as the reference clock, N must be set to 19.
4. Set FLL_MULT in CLK_FLL_CONFIG.
FLL_MULT is the ratio between the desired CCO frequency and the divided input frequency. This is the ideal value for the
counter that counts the number of CCO clocks in one period of the divided input frequency.
N
M = f CCO  --------
T arg et f ref
Equation 21-2
5. Set the FLL_LF_IGAIN and FLL_LF_PGAIN in CLK_FLL_CONFIG3.
Within each range of the CCO there are 512 steps of adjustment for the CCO frequency. These steps are controlled by
CCO_FREQ in the CLK_FLL_CONFIG4 register. The FLL automatically adjusts CCO_FREQ based on the output of the
FLL counter.
The output of the counter gives the number of CCO clocks, over one period of the divided reference clock, by which the
FLL is off. This value is then multiplied by the sum of FLL_LF_IGAIN and FLL_LF_PGAIN. The result of this multiplication
is then summed with the value currently in the CCO_FREQ register.
To determine the values for IGAIN and PGAIN use the following equation:

 
 0.85 
I GAIN   -----------------------------
K N
 --------
 CCO f ref
Equation 21-3
Find the value of IGAIN closest but not over the values in the gain row in Table 21-5.

Table 21-5. IGAIN and PGAIN Register Values

Register Value 0 1 2 3 4 5 6 7 8 9 10 11
Gain Value 1/256 1/128 1/64 1/32 1/16 1/8 1/4 1/2 1 2 4 8

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 Clocking System

Program FLL_LF_IGAIN with the register value that corresponds to the chosen gain value.
Take the IGAIN value from the register and use it in the following equation:

0.85
P GAIN  I GAIN reg – -----------------------------
N
K CCO  --------
f ref
Equation 21-4
Find the value of PGAIN closest but not over the values in the gain row in Table 21-5. Program FLL_PF_IGAIN with the
register value that corresponds to the chosen gain value.
For best performance Pgain_reg + Igain_reg should be as close as possible to calculated IGAIN without exceeding it.
kCCO is the gain of the CCO; Table 21-6 lists the kCCO for each CCO range.

Table 21-6. kCCO Values

CCO Range 0 1 2 3 4
kCCO 48109.38 64025.65 84920 113300 154521.85

6. Set SETTLING_COUNT in CLK_FLL_CONFIG3.

SETTLING_COUNT is the number of reference clocks to wait for the CCO to settle after it has changed. It is best to set
this such that the settling time is around 1 µs.
SETTLING_COUNT =1 µs * fref

Do not set the settling time to anything less than 1 µs, greater will lead to longer lock times.
1. Set LOCK_TOL in CLK_FLL_CONFIG2.
LOCK_TOL determines how much error the FLL can tolerate at the output of the counter that counts the number of CCO
clocks in one period of the divided reference clock. A higher tolerance can be used to lock more quickly or track a less
accurate source. The tolerance should be set such that the FLL does not unlock under normal conditions. A lower
tolerance means a more accurate output, but if the input reference is unstable then the FLL may unlock.
The following equation can be used to help determine the value:

1 + CCO accuracy
LOCK_TOL = M   ----------------------------------------- – 1
1 – F refaccuracy
Equation 21-5
CCO (accuracy) = 0.25% or 0.0025
ref (accuracy) is the accuracy of the reference clock
2. Set CCO_FREQ in CLK_FLL_CONFIG4.
This field determines the frequency at which the FLL starts before any measurement. The nearer the FLL is to the desired
frequency, the faster it will lock.

  f CCO T arg et 

 LOG  --------------------- - 
  f CCOBase  
CCO FREQ = ROUPNDUP  ----------------------------------------------------------
 LOG  1 + CCO Trim Step 
  Equation 21-6
 
fCCOBase can be found in Table 21-7.

Table 21-7. CCO Base Frequency

CCO Range 0 1 2 3 4
CCO_Base 43600 58100 77200 103000 132000

Table 21-8. CCO Trim Steps

CCO Range 0 1 2 3 4
CCO_Trim_Steps 0.0011 0.0011 0.0011 0.0011 0.00117

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 Clocking System

9. Calculating Precision, Accuracy, and Lock Time of FLL

To calculate the precision and accuracy of the FLL, the accuracy of the input source must be considered.
The precision is the larger of:

 1 + f ref  accuracy 
Precision FLL = f ref   ----------------------------------------------
 N  f CCO T arg et 
Equation 21-7
Or (CCO_Trim_Steps / 2)
Example: The desired FLL output is 100 MHz, thus CCO target is 200 MHz. The 2 percent accurate 8 MHz IMO is used as
the reference input. N is calculated to be 69.
PrecisionFLL = ((8 MHz * 1.02)/(69 * 200 MHz)) = 0.059%, which is greater than the (CCO_Trim_Steps / 2)
The accuracy of the FLL output is the precision multiplied by the lock tolerance. If the CCO goes beyond this range, then
the FLL will unlock.
AccuracyFLL = PrecisionFLL * LOCK_TOL
The value for the reference divider N should be tuned such that it achieves the best precision/accuracy versus lock time.
The lock time depends on the time for each adjustment step in the locking process;
Step_Time = (N / fref) + (SETTLING_COUNT / fref)
Multiply this number by the number of steps it takes to lock, to determine lock time. Typically, the FLL locks within the first
~10 steps.

21.4.2.2 Enabling and Disabling the FLL

The FLL requires firmware sequencing when enabling, disabling, and entering/exiting DEEPSLEEP.
To enable the FLL, follow these steps:
1. Enable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE = 1 and wait until CLK_FLL_STATUS.CCO_READY==1.
2. Ensure the reference clock has stabilized and CLK_FLL_CONFIG3.BYPASS_SEL = FLL_REF.
3. Write FLL_ENABLE = 1 and wait until CLK_FLL_STATUS.LOCKED==1.
4. Write CLK_FLL_CONFIG3.BYPASS_SEL = FLL_OUT to switch to the FLL output.
To disable the FLL, follow these steps:
1. Ensure the processor is operating from a different clock than clk_path0. If the muxes are changed, wait four FLL output
clock cycles for it to complete.
2. Write CLK_FLL_CONFIG3.BYPASS_SEL = FLL_REF and read the same register to ensure the write completes.
3. Wait at least six FLL reference clock cycles and disable it with FLL_ENABLE = 0.
4. Disable the CCO by writing CLK_FLL_CONFIG4.CCO_ENABLE = 0.
Before entering DEEPSLEEP, either disable the FLL using the above sequence or use the following procedure to deselect/
select it before/after DEEPSLEEP. Before entering DEEPSLEEP, write CLK_FLL_CONFIG3.BYPASS_SEL = FLL_REF to
change the FLL to use its reference clock. After DEEPSLEEP wakeup, wait until CLK_FLL_STATUS.LOCKED==1 and then
write CLK_FLL_CONFIG3.BYPASS_SEL = FLL_OUT to switch to the FLL output.
Note: It is not recommended to use the FLL_AUTO option in the BYPASS_SEL field.

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 Clocking System

21.5 Clock Trees 21.5.2 High-Frequency Root Clocks

The PSoC 6 MCU clocks are distributed throughout the The PSoC 6 MCU has six high-frequency root clocks
device, as shown in Figure 21-1. The clock trees are (CLK_HF[i]). Each CLK_HF has a particular destination on
described in this section: the device, as shown in Table 21-11.
■ Path Clocks Table 21-11. CLK_HF Destinations
■ High-Frequency Root Clocks (CLK_HF[i])
Name Description
■ Low-Frequency Clock (CLK_LF)
Root clock for both CPUs, PERI, and
■ Timer Clock (CLK_TIMER) CLK_HF[0]
AHB infrastructure
■ Analog Pump Clock (CLK_PUMP) Root clock for the PDM/PCM and I2S
CLK_HF[1]
audio subsystem
21.5.1 Path Clocks Root clock for the Serial Memory
CLK_HF[2] Interface subsystem and SDHC[1]
The PSoC 6 MCU has six clock paths: CLK_PATH0 contains block
the FLL, CLK_PATH1 and CLK_PATH2 contain the PLLs,
CLK_HF[3] Root clock for USB communications
and CLK_PATH3, CLK_PATH4, and CLK_PATH5 are a
direct connection to the high-frequency root clocks. Note CLK_HF[4] Root clock for SDHC[0] block
that the FLL and PLL(s) can be bypassed if they are not Clock output on clk_ext pin (when used
CLK_HF[5]
needed. These paths are the input sources for the high- as an output)
frequency clock roots.
Each clock path has a mux to determine which source clock Each high-frequency root clock has a mux to determine its
will clock that path. This configuration is done in source. This configuration is done in the
CLK_PATH_SELECT[i] register. CLK_ROOT_SELECT[i] register.

Table 21-9. Clock Path Source Selections Table 21-12. HFCLK Input Selection Bits
Name Description
Name Description
HFCLK input clock selection
Selects the source for clk_path[i]
0: Select CLK_PATH0
0: IMO
1: Select CLK_PATH1
1: EXTCLK
PATH_MUX[2:0] ROOT_MUX[3:0] 2: Select CLK_PATH2
2: ECO
3: Select CLK_PATH3
4: DSI_MUX
4: Select CLK_PATH4
3: Reserved
5: Select CLK_PATH5
The DSI mux is configured through the
CLK_DSI_SELECT[i] register. Each CLK_HF has a pre-divider, which is set in the
CLK_ROOT_SELECT register.
Table 21-10. DSI Mux Source Selection
Table 21-13. HFCLK Divider Selection
Name Description
Name Description
Selects the source for the DSI_MUX[i]
0-15: Reserved Selects predivider value for the clock
root
16: ILO
0: No Divider
DSI_MUX[4:0] 17: WCO ROOT_DVI[5:4]
1: Divide clock by 2
18: Reserved
2: Divide clock by 4
19: Reserved
3: Divide clock by 8
20-31: Invalid

CLK_HF[1-5] can be enabled and disabled. CLK_HF[0] is

always enabled as it is the source of the CPU. To enable
and disable CLK_HF[1-5] set the ENABLE bit in the
CLK_ROOT_SELECT register.

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 Clocking System

21.5.3 Low-Frequency Clock

The low-frequency clock (CLK_LF) in the PSoC 6 MCU has
two input options: ILO and WCO.
CLK_LF is the source for the multi-counter watchdog timers
(MCWDT) and the RTC.
The source of CLK_LF is set in the LFCLK_SEL bits of the
CLK_SELECT register.

Table 21-14. LFCLK Input Selection Bits LFCLK_SEL

Name Description
LFCLK input clock selection
0: ILO. Uses the internal local oscillator
as the source of the LFCLK
LFCLK_SEL[1:0] 1: WCO. Uses the watch crystal
oscillator as the source of the LFCLK
2: Reserved
3: Reserved

21.5.4 Timer Clock

The timer clock (CLK_TIMER) can be used as a clock
source for the profiler or the CPU SYSTICK timer. The
source for CLK_TIMER can either be the IMO or
CLK_HF[0]. This selection is made in the TIMER_SEL
bitfield of the CLK_TIMER_CTL register. Several dividers
can be applied to this clock, which are found in the
CLK_TIMER_CTL register.

21.5.5 Group Clocks (clk_sys)

On the PSoC 6 platform, peripherals are grouped. Each
group has a dedicated group clock (also referred to as
clk_sys). The group clock sets the clock rate for the AHB
interface on the peripheral; it also sets the clock rate for the
trigger outputs and trigger input synchronization. Each
group clock has an eight-bit divider located in the
CLOCK_CTL register in the PERI_GROUP_STRUCT in the
PERI register set. For a majority of applications these
dividers should be left at default (divide by 1).

21.5.6 Backup Clock (clk_bak)

The backup clock is used to clock the backup domain,
specifically the RTC. For more information see WCO with
External Clock/Sine Wave Input on page 237.

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 Clocking System

21.6 CLK_HF[0] Distribution

clk_hf[0] is the root clock for the CPU subsystem and for the peripheral clock dividers.
Figure 21-4. CLK_HF[0] Distribution

Predivider
CLK_HF[0] CLK_FAST CM4
1-256

Predivider Predivider
CLK_PERI CLK_SLOW CM0+
1-256 1-256

To peripheral
clock dividers

21.6.1 CLK_FAST 21.7.1 Fractional Clock Dividers

CLK_FAST clocks the Cortex-M4 processor. This clock is a Fractional clock dividers allow the clock divisor to include a
divided version of CLK_HF[0]. The divider for this clock is fraction of 0..31/32. For example, a 16.5-bit divider with an
set in the CM4_CLOCK_CTL register of the CPU integer divide value of 3 generates a 16-MHz clock from a
subsystem. 48-MHz CLK_PERI. A 16.5-bit divider with an integer divide
value of 4 generates a 12-MHz clock from a 48-MHz
21.6.2 CLK_PERI CLK_PERI. A 16.5-bit divider with an integer divide value of
3 and a fractional divider of 16 generates a 48 / (3 + 16/32) =
CLK_PERI is the source clock for all programmable 48 / 3.5 = 13.7-MHz clock from a 48-MHz CLK_PERI. Not all
peripheral clock dividers and for the Cortex-M0+ processor. 13.7-MHz clock periods are equal in size; some will have a
It is a divided version of CLK_HF[0]. The divider for this 16-MHz period and others will have a 12-MHz period, such
clock is set in the PERI_INT_DIV bitfields of the that the average is 13.7 MHz.
CM0_CLOCK_CTL register.
Fractional dividers are useful when a high-precision clock is
required (for example, for a UART/SPI serial interface).
21.6.3 CLK_SLOW Fractional dividers are not used when a low jitter clock is
CLK_SLOW is the source clock for the Cortex-M0+. This required, because the clock periods have a jitter of one
clock is a divided version of CLK_PERI. The divider for this CLK_PERI cycle.
clock is set in the SLOW_INT_DIV bitfields of the
CM0_CLOCK_CTL register. 21.7.2 Peripheral Clock Divider
Configuration
21.7 Peripheral Clock Dividers The peripheral clock dividers are configured using registers
from the peripheral block; specifically DIV_CMD,
The PSoC 6 MCU peripherals such as SCBs and TCPWMs DIV_8_CTL, DIV_16_CTL, DIV_16_5_CTL,
require a clock. These peripherals can be clocked only by a DIV_24_5_CTL, and CLOCK_CTL registers.
peripheral clock divider.
First the clock divider needs to be configured. This is done
The PSoC 6 MCU has 29 peripheral clock dividers (PCLK). via the DIV_8_CTL, DIV_16_CTL, DIV_16_5_CTL, and
It has eight 8-bit dividers, sixteen 16-bit dividers, four DIV_24_5_CTL registers. There is one register for each
fractional 16.5-bit dividers (16 integer bits, five fractional divider; for example, there are eight DIV_8_CTL registers as
bits), and one 24.5-bit divider (24 integer bits, five fractional there are eight 8-bit dividers. In these registers, set the
bits). The output of any of these dividers can be routed to value of the integer divider; if it is a fractional divider then set
any peripheral. the fraction portion as well.

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 Clocking System

After the divider is configured use the DIV_CMD register to 21.7.2.1 Phase Aligning Dividers
enable the divider. This is done by setting the DIV_SEL to
the divider number you want to enable, and setting the For specific use cases, you must generate clocks that are
TYPE_SEL to the divider type. For example, if you wanted phase-aligned. For example, consider the generation of two
to enable the 0th 16.5-bit divider, write ‘0’ to DIV_SEL and gated clocks at 24 and 12 MHz, both of which are derived
‘2’ to TYPE_SEL. If you wanted to enable the tenth 16-bit from a 48-MHz CLK_PERI. If phase alignment is not
divider, write ‘10’ to DIV_SEL and ‘1’ to TYPE_SEL. See the considered, the generated gated clocks appear as follows.
registers TRM for more details.
Figure 21-5. Non Phase-Aligned Clock Dividers
No phase alignment

CLK_PERI (48 MHz)

24 MHz gated clock

12 MHz gated clock

These clock signals may or may not be acceptable, depending on the logic functionality implemented on these two clocks. If
the two clock domains communicate with each other, and the slower clock domain (12 MHz) assumes that each high/‘1’ pulse
on its clock coincides with a high/‘1’ phase pulse in the higher clock domain (24 MHz), the phase misalignment is not
acceptable. To address this, it is possible to have dividers produce clock signals that are phase-aligned with any of the other
(enabled) clock dividers. Therefore, if (enabled) divider x is used to generate the 24-MHz clock, divider y can be phase-
aligned to divider x and used to generate the 12-MHz clock. The aligned clocks appear as follows.
Figure 21-6. Phase-Aligned Clock Dividers
Phase alignment

CLK_PERI (48 MHz)

24 MHz gated clock

12 MHz gated clock

Phase alignment also works for fractional divider values. If (enabled) divider x is used to generate the 38.4-MHz clock (divide
by 1 8/32), divider y can be phase-aligned to divider x and used to generate the 19.2-MHz clock (divide by 2 16/32). The
generated gated clocks appear as follows.
Figure 21-7. Phase-Aligned Fractional Dividers
Phase alignment

CLK_PERI (48 MHz)

38.4 MHz gated clock

19.2 MHz gated clock

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 Clocking System

Divider phase alignment requires that the divider to which it Table 21-15. Clock Dividers to Peripherals
is phase-aligned is already enabled. This requires the
Clock Number Destination
dividers to be enabled in a specific order.
18 tcpwm[0].clocks[3]
Phase alignment is implemented by controlling the start
19 tcpwm[0].clocks[4]
moment of the divider counters in hardware. When a divider
is enabled, the divider counters are set to ‘0’. The divider 20 tcpwm[0].clocks[5]
counters will only start incrementing from ‘0’ to the 21 tcpwm[0].clocks[6]
programmed integer and fractional divider values when the 22 tcpwm[0].clocks[7]
divider to which it is phase-aligned has an integer counter
23 tcpwm[1].clocks[0]
value of ‘0’.
24 tcpwm[1].clocks[1]
Note that the divider and clock multiplexer control register
25 tcpwm[1].clocks[2]
fields are all retained during the Deep Sleep power mode.
However, the divider counters that are used to implement 26 tcpwm[1].clocks[3]
the integer and fractional clock dividers are not. These 27 tcpwm[1].clocks[4]
counters are set to ‘0’ during the Deep Sleep mode. 28 tcpwm[1].clocks[5]
Therefore, when transitioning from Deep Sleep to Active
mode, all dividers (and clock signals) are enabled and 29 tcpwm[1].clocks[6]
phase-aligned by design. 30 tcpwm[1].clocks[7]

Phase alignment is accomplished by setting the 31 tcpwm[1].clocks[8]

PA_DIV_SEL and PA_DIV_TYPE bits in the DIV_CMD 32 tcpwm[1].clocks[9]
register before enabling the clock. For example, to align the 33 tcpwm[1].clocks[10]
fourth 8-bit divider to the third 16-bit divider, set DIV_SEL to
34 tcpwm[1].clocks[11]
‘4’, TYPE_SEL to ‘0’, PA_DIV_SEL to ‘3’, and
PA_TYPE_SEL to ‘1’. 35 tcpwm[1].clocks[12]
36 tcpwm[1].clocks[13]
21.7.2.2 Connecting Dividers to Peripheral 37 tcpwm[1].clocks[14]
The PSoC 6 MCU has 54 peripherals, which can connect to 38 tcpwm[1].clocks[15]
one of the programmable dividers. Table 21-15 lists those 39 tcpwm[1].clocks[16]
peripherals.
40 tcpwm[1].clocks[17]
Table 21-15. Clock Dividers to Peripherals 41 tcpwm[1].clocks[18]

Clock Number Destination 42 tcpwm[1].clocks[19]

43 tcpwm[1].clocks[20]
0 scb[0].clock
44 tcpwm[1].clocks[21]
1 scb[1].clock
2 scb[2].clock 45 tcpwm[1].clocks[22]
46 tcpwm[1].clocks[23]
3 scb[3].clock
47 csd.clock
4 scb[4].clock
5 scb[5].clock 48 lcd.clock
49 profile.clock_profile
6 scb[6].clock
50 cpuss.clock_trace_in
7 scb[7].clock
8 scb[8].clock 51 pass.clock_pump_peri
52 pass.clock_sar
9 scb[9].clock
10 scb[10].clock 53 usb.clock_dev_brs

11 scb[11].clock To connect a peripheral to a specific divider, the

12 scb[12].clock PERI_CLOCK_CTL register is used. There is one
13 smartio[8].clock PERI_CLOCK_CTL register for each entry in Table 21-15.
For example, to select the twelfth 16-bit divider for
14 smartio[9].clock
tcpwm[0].clocks[2] write to the twenty-fifth CLOCK_CTL
15 tcpwm[0].clocks[0] register, set the DIV_SEL to ‘12’, and the TYPE_SEL to ‘1’.
16 tcpwm[0].clocks[1]
17 tcpwm[0].clocks[2]

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 Clocking System

21.8 Clock Calibration Counters

A feature of the clocking system in PSoC 6 MCUs is built-in hardware calibration counters. These counters can be used to
compare the frequency of two clock sources against one another. The primary use case is to take a higher accuracy clock
such as the ECO and use it to measure a lower accuracy clock such as the ILO. The result of this measurement can then be
used to trim the ILO.
There are two counters: Calibration Counter 1 is clocked off of Calibration Clock 1 (generally the high-accuracy clock) and it
counts down; Calibration Counter 2 is clocked off of Calibration Clock 2 and it counts up. When Calibration Counter 1 reaches
0, Calibration Counter 2 stops counting up and its value can be read. From that value the frequency of Calibration Clock 2 can
be determined with the following equation.
Counter 2 Final Value
Calibration Clock 2 Frequency = ----------------------------------------------------------  Calibration Clock 1 Frequency
Counter 1 Initial Value

For example, if Calibration Clock 1 = 8 MHz, Counter 1 = 1000, and Counter 2 = 5

Calibration Clock 1 Frequency = (5/1000) * 8 MHz = 40 kHz.
Calibration Clock 1 and Calibration Clock 2 are selected with the CLK_OUTPUT_FAST register. All clock sources are
available as a source for these two clocks. CLK_OUTPUT_SLOW is also used to select the clock source.
Calibration Counter 1 is programmed in CLK_CAL_CNT1. Calibration Counter 2 can be read in CLK_CAL_CNT2.
When Calibration Counter 1 reaches 0, the CAL_COUNTER_DONE bit is set in the CLK_CAL_CNT1 register.

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 22. Reset System

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU family supports several types of resets that guarantee error-free operation during power up and allow the
device to reset based on user-supplied external hardware or internal software reset signals. The PSoC 6 MCU also contains
hardware to enable the detection of certain resets.

22.1 Features
The PSoC 6 MCU has these reset sources:
■ Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to
function properly
■ Brownout reset (BOD) to reset the device if the power supply falls below the device specifications during normal operation
■ External reset (XRES) to reset the device using an external input
■ Watchdog timer (WDT) reset to reset the device if the firmware execution fails to periodically service the watchdog timer
■ Software initiated reset to reset the device on demand using firmware
■ Logic-protection fault resets to reset the device if unauthorized operating conditions occur
■ Clock-supervision logic resets to reset the device when clock-related errors occur
■ Hibernate wakeup reset to bring the device out of the Hibernate low-power mode

22.2 Architecture
The following sections provide a description of the reset sources available in the PSoC 6 MCU family.
Note: None of these sources can reset the Backup system. The Backup domain is reset only when all the power supplies are
removed from it, also known as a “cold start” or if the firmware triggers a reset using the BACKUP_RESET register. Firmware
reset is required if the VBACKUP supply was invalid during a previous power supply ramp-up or brownout event. For more
details, see the Backup System chapter on page 235.

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 Reset System

Table 22-1 lists all the reset sources in the PSoC 6 MCU.

Table 22-1. PSoC 6 MCU Reset Sources

Availability in
Reset Source Reset Condition System Power Cause Detection
Modes
This reset condition occurs during device
power-up. POR holds the device under
Power-on Reset reset until the VDDD reaches the threshold All Not inferable using the reset cause registers.
voltage as specified in the PSoC 61
datasheet/PSoC 62 datasheet.
VDDD falls below the minimum logic
Brownout Reset operating voltage specified in the PSoC 61 All Not inferable using the reset cause registers.
datasheet/PSoC 62 datasheet.
RESET_HWWDT bit or RESET_SWWDT0 to
RESET_SWWDT3 status bits of the
RES_CAUSE register is set when a watchdog
WDT is not reset by firmware within the
Watchdog Timer Reset All reset occurs. This bit remains set until cleared
configured reset time period of the WDT.
by the firmware or until a POR, XRES, or BOD
reset occurs. All other resets leave this bit
unaltered.
Value written to the TOKEN bit field of the
System wakes up from Hibernate power
Hibernate Wakeup Hibernate PWR_HIBERNATE register is retained after
mode.
reset.
SYSRESETREQ bit is set by the firmware RESET_SOFT bit of the RES_CAUSE register
Software Reset Active
in the CM0_AIRCR/CM4_AIRCR register. is set
External Reset Logic LOW input to XRES pin All Not inferable using the reset cause registers.
RESET_ACT_FAULT or
Logic Protection Fault Active, Deep Sleep
Unauthorized protection violation RESET_DPSLP_FAULT bits of the
Reset modes
RES_CAUSE register is set.
RESET_CSV_WCO_LOSS bit of the
RES_CAUSE register is set when WCO clock
is lost. The RESET_CSV_HF_LOSS of
Loss of a high-frequency clock or watch-
Clock-Supervision Active, Deep Sleep RES_CAUSE2 register can be used to identify
crystal clock, or due to a high-frequency
Logic Reset modes resets caused by the loss of a high-frequency
clock error.
clock. RESET_CSV_HF_FREQ field can be
used to identify resets caused by the
frequency error of a high-frequency clock.

22.2.1 Power-on Reset PSoC 62 datasheet. See the Power Supply and
Monitoring chapter on page 218 for more details.
Power-on reset is provided to keep the system in a reset
state during power-up. POR holds the device in reset until BOD events do not set a reset cause status bit, but in some
the supply voltage, VDDD reaches the datasheet cases they can be detected. In some BOD events, VDDD will
specification. The POR activates automatically at power-up. fall below the minimum logic operating voltage specified by
Refer to thePSoC 61 datasheet/PSoC 62 datasheet for the datasheet, but remain above the minimum logic
details on the POR trip-point levels. retention voltage.

POR events do not set a reset cause status bit, but can be
partially inferred by the absence of any other reset source. If
22.2.3 Watchdog Timer Reset
no other reset event is detected, then the reset is caused by Watchdog timer reset causes a reset if the WDT is not
POR, BOD, or XRES. serviced by the firmware within a specified time limit. See
the Watchdog Timer chapter on page 283 for more details.
22.2.2 Brownout Reset The RESET_WDT bit or RESET_MCWDT0 to
Brownout reset monitors the chip digital voltage supply RESET_MCWDT3 status bits of the RES_CAUSE register
VDDD and generates a reset if VDDD falls below the minimum is set when a watchdog reset occurs. This bit remains set
logic operating voltage specified in the PSoC 61 datasheet/

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 Reset System

until cleared by the firmware or until a POR, XRES, or BOD 22.2.6 Logic Protection Fault Reset
reset occurs. All other resets leave this bit unaltered.
Logic protection fault reset detects any unauthorized
For more details, see the Watchdog Timer chapter on protection violations and causes the device to reset if they
page 283. occur. One example of a protection fault is reaching a debug
breakpoint while executing privileged code.
22.2.4 Software Initiated Reset The RESET_ACT_FAULT or RESET_DPSLP_FAULT bits of
Software initiated reset is a mechanism that allows the CPU the RES_CAUSE register is set when a protection fault
to request a reset. The Cortex-M0+ and Cortex-M4 occurs in Active or Deep Sleep modes, respectively. These
Application Interrupt and Reset Control registers bits remain set until cleared or until a POR, XRES, or BOD
(CM0_AIRCR and CM4_AIRCR, respectively) can request a reset. All other resets leave this bit unaltered.
reset by writing a ‘1’ to the SYSRESETREQ bit of the
respective registers. 22.2.7 Clock-Supervision Logic Reset
Note that a value of 0x5FA should be written to the Clock-supervision logic initiates a reset due to the loss of a
VECTKEY field of the AIRCR register before setting the high-frequency clock or watch-crystal clock, or due to a
SYSRESETREQ bit; otherwise, the processor ignores the high-frequency clock error.
write. See the CPU Subsystem (CPUSS) chapter on
page 32 and Arm documentation on AIRCR for more details. The RESET_CSV_WCO_LOSS bit of the RES_CAUSE
register is set when the clock supervision logic requests a
The RESET_SOFT status bit of the RES_CAUSE register is reset due to the loss of a watch-crystal clock (if enabled).
set when a software reset occurs. This bit remains set until
cleared by firmware or until a POR, XRES, or BOD reset The RESET_CSV_HF_LOSS is a 16-bit field in the
occurs. All other resets leave this bit unaltered. RES_CAUSE2 register that can be used to identify resets
caused by the loss of a high-frequency clock. Similarly, the
RESET_CSV_HF_FREQ field can be used to identify resets
22.2.5 External Reset caused by the frequency error of a high-frequency clock.
External reset (XRES) is a reset triggered by an external
For more information on clocks, see the Clocking
signal that causes immediate system reset when asserted.
System chapter on page 242.
The XRES pin is active low – a logic ‘1’ on the pin has no
effect and a logic ‘0’ causes reset. The pin is pulled to logic
‘1’ inside the device. XRES is available as a dedicated pin. 22.2.8 Hibernate Wakeup Reset
For detailed pinout, refer to the pinout section of the PSoC Hibernate wakeup reset occurs when one of the Hibernate
61 datasheet/PSoC 62 datasheet. wakeup sources performs a device reset to return to the
The XRES pin holds the device in reset as long as the pin Active power mode. See the Device Power Modes chapter
input is ‘0’. When the pin is released (changed to logic ‘1’), on page 225 for details on Hibernate mode and available
the device goes through a normal boot sequence. The wakeup sources.
logical thresholds for XRES and other electrical TOKEN is an 8-bit field in the PWR_HIBERNATE register
characteristics are listed in the Electrical Specifications that is retained through a Hibernate wakeup sequence. The
section of the PSoC 61 datasheet/PSoC 62 datasheet. firmware can use this bitfield to differentiate hibernate
XRES is available in all power modes, but cannot reset the wakeup from a general reset event. Similarly, the
Backup system. PWR_HIB_DATA register can retain its contents through a
An XRES event does not set a reset cause status bit, but Hibernate wakeup reset, but is cleared when XRES is
can be partially inferred by the absence of any other reset asserted.
source. If no other reset event is detected, then the reset is
caused by POR, BOD, or XRES.
22.3 Identifying Reset Sources
When the device comes out of reset, it is often useful to
know the cause of the most recent or even older resets. This
is achieved through the RES_CAUSE and RES_CAUSE2
registers. These registers have specific status bits allocated
for some of the reset sources. These registers record the
occurrences of WDT reset, software reset, logic-protection
fault, and clock-supervision resets. However, these registers
do not record the occurrences of POR, BOD, XRES, or
Hibernate wakeup resets. The bits in these registers are set
on the occurrence of the corresponding reset and remain

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 Reset System

set after the reset, until cleared by the firmware or a loss of an XRES cannot be detected. The other reset sources can
retention, such as a POR, XRES, or BOD. be inferred to some extent by the status of the RES_CAUSE
and RES_CAUSE2 registers, as shown in Table 22-2.
Hibernate wakeup resets can be detected by examining the
TOKEN field in the PWR_HIBERNATE register as described
previously. Hibernate wakeup resets that occur as a result of

Table 22-2. Reset Cause Bits to Detect Reset Source

Number of
Register Bitfield Description
Bits
RES_CAUSE RESET_WDT 1 A hardware WDT reset has occurred since the last power cycle.
RES_CAUSE RESET_ACT_FAULT 1 Fault logging system requested a reset from its Active logic.
RES_CAUSE RESET_DPSLP_FAULT 1 Fault logging system requested a reset from its Deep Sleep logic.
Clock supervision logic requested a reset due to loss of a watch-crystal
RES_CAUSE RESET_CSV_WCO_LOSS 1
clock.
A CPU requested a system reset through its SYSRESETREQ. This can
RES_CAUSE RESET_SOFT 1
be done via a debugger probe or in firmware.
RES_CAUSE RESET_MCWDT0 1 Multi-counter WDT reset #0 has occurred since the last power cycle.
RES_CAUSE RESET_MCWDT1 1 Multi-counter WDT reset #1 has occurred since the last power cycle.
RES_CAUSE RESET_MCWDT2 1 Multi-counter WDT reset #2 has occurred since the last power cycle.
RES_CAUSE RESET_MCWDT3 1 Multi-counter WDT reset #3 has occurred since the last power cycle.
Clock supervision logic requested a reset due to loss of a high-frequency
RES_CAUSE2 RESET_CSV_HF_LOSS 16 clock. Each bit index K corresponds to a clk_hf<K>. Unimplemented
clock bits return zero.
Clock supervision logic requested a reset due to frequency error of a
RES_CAUSE2 RESET_CSV_HF_FREQ 16 high-frequency clock. Each bit index K corresponds to a clk_hf<K>.
Unimplemented clock bits return zero.

For more information, see the RES_CAUSE and RES_CAUSE2 registers in the registers TRM.
If these methods cannot detect the cause of the reset, then it can be one of the non-recorded and non-retention resets: BOD,
POR, or XRES. These resets cannot be distinguished using on-chip resources.

22.4 Register List

Table 22-3. Reset System Register List
Register Description
RES_CAUSE Reset cause observation register
RES_CAUSE2 Reset cause observation register 2
Hibernate power mode control register. Contains a TOKEN field that can be used to detect the Hibernate
PWR_HIBERNATE
wakeup reset
PWR_HIB_DATA Retains its contents through Hibernate wakeup reset
CM4_AIRCR Application interrupt and reset control register of Cortex-M4
CM0_AIRCR Application interrupt and reset control register of Cortex-M0+

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 260
 23. I/O System

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

This chapter explains the PSoC 6 MCU I/O system, its features, architecture, operating modes, and interrupts. The I/O
system provides the interface between the CPU core and peripheral components to the outside world. The flexibility of
PSoC 6 MCUs and the capability of its I/O to route most signals to most pins greatly simplifies circuit design and board layout.
The GPIO pins in the PSoC 6 MCU family are grouped into ports; a port can have a maximum of eight GPIO pins.

23.1 Features
The PSoC 6 MCU GPIOs have these features:
■ Analog and digital input and output capabilities
■ Eight drive strength modes
■ Separate port read and write registers
■ Overvoltage tolerant (OVT-GPIO) pins
■ Separate I/O supplies and voltages for up to six groups of I/O
■ Edge-triggered interrupts on rising edge, falling edge, or on both edges, on all GPIO
■ Slew rate control
■ Frozen mode for latching previous state (used to retain the I/O state in System Hibernate Power mode)
■ Selectable CMOS and low-voltage LVTTL input buffer mode
■ CapSense support
■ Smart I/O provides the ability to perform Boolean functions in the I/O signal path
■ Segment LCD drive support

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 I/O System

23.2 Architecture
The PSoC 6 MCU is equipped with analog and digital peripherals. Figure 23-1 shows an overview of the routing between the
peripherals and pins.
Figure 23-1. GPIO Interface Overview

GPIO & Port

Control Fixed

Configuration
CapSense Segment Function

Interface
Interrupt
Controller LCD Digital
Peripherals

High Speed IO Matrix

I/O Cell

Pin
CapSense Analog
Sensing Peripherals

AMUXBUS-A
AMUXBUS-B

GPIO pins are connected to I/O cells. These cells are equipped with an input buffer for the digital input, providing high input
impedance and a driver for the digital output signals. The digital peripherals connect to the I/O cells via the high-speed I/O
matrix (HSIOM). The HSIOM for each pin contains multiplexers to connect between the selected peripheral and the pin.
Analog peripherals such as SAR ADC, Low-Power comparator (LPCOMP), and CapSense are either connected to the GPIO
pins directly or through the AMUXBUS.

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 I/O System

23.2.1 I/O Cell Architecture

Figure 23-2 shows the I/O cell architecture present in every GPIO cell. It comprises an input buffer and an output driver that
connect to the HSIOM multiplexers for digital input and output signals. Analog peripherals connect directly to the pin for point
to point connections or use the AMUXBUS.
Figure 23-2. GPIO and GPIO_OVT Cell Architecture

GPIO_PRTx_CFG_IN[VTRIP_SELy_0]
GPIO_PRTx_CFG[IN_ENy]

GPIO_PRTx_INTR[EDGEy]
GPIO_PRTx_INTR[IN_INy]
GPIO_PRTx_MASK[EDGEy]
GPIO
GPIO_PRTx_INTR_MASKED[EDGEy] Edge
x = Port Number
y = Pin Number
GPIO_PRTx_INTR_SET[EDGEy]
Detect
GPIO_PRTx_INTR_CFG[EDGEy_SEL]
Pin Interrupt Signal

GPIO_PRTx_IN[INy]
ACTIVE_[15:0]

DEEP_SLEEP_[7:0]

Input Buffer
GPIO_PRTx_CFG_OUT[SLOWy] Output Driver

GPIO_PRTx_CFG_OUT[DRIVE_SELy] 2

HSIOM_PRTx_PORT_SEL[1:0][IOy_SEL] 5

GPIO_PRTx_OUT[OUTy]
ACTIVE_0(TCPWM)
ACTIVE_1(SCB)
ACTIVE_2(CAN) VDD

ACTIVE_[15:3] OUT
OUT_EN
DEEP_SLEEP_0(LCD-COM) 13

DEEP_SLEEP_1(LCD-SEG) Pin
Digital Slew
DEEP_SLEEP_2(SCB) Logic Rate
Control

DEEP_SLEEP_[7:3] 5
Note: HSIOM selection connects OUT and OUT_EN.
ACTIVE_[2:0] and DEEP_SLEEP_[2:0] connections are examples.
See Device Datasheet for specific connections to HSIOM ACTIVE
and DEEP_SLEEP selections.
VSS

GPIO_PRTx_CFG[DRIVE_MODEy] 3 Drive
Mode

Dedicated Analog Resources (SAR ADC, LPCOMP)

Switches

AMUXBUS-A (CapSense Source, SAR ADC)

AMUXBUS-B (CapSense Shield, SAR ADC)

23.2.2 Digital Input Buffer The input buffer is connected to the HSIOM for routing to the
CPU port registers and selected peripherals. Writing to the
The digital input buffer provides a high-impedance buffer for HSIOM port select register (HSIOM_PORT_SELx) selects
the external digital input. The buffer is enabled or disabled the pin connection. See the PSoC 61 datasheet/PSoC 62
by the IN_EN[7:0] bit of the Port Configuration Register datasheet for the specific connections available for each pin.
(GPIO_PRTx_CFG, where x is the port number).
If a pin is connected only to an analog signal, the input
buffer should be disabled to avoid crowbar currents.

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 I/O System

Each pin’s input buffer trip point and hysteresis are Each GPIO pin has ESD diodes to clamp the pin voltage to
configurable for the following modes: the I/O supply source. Ensure that the voltage at the pin
does not exceed the I/O supply voltage VDDIO/VDDD/VDDA or
■ CMOS + I2C
drop below VSSIO/VSSD/VSSA. For the absolute maximum
■ TTL and minimum GPIO voltage, see the PSoC 61 datasheet/
These buffer modes are selected by the VTRIP_SEL[7:0]_0 PSoC 62 datasheet.
bit of the Port Input Buffer Configuration register.
(GPIO_PRTx_CFG_IN). 23.2.3.1 Drive Modes
Each I/O is individually configurable to one of eight drive
23.2.3 Digital Output Driver modes by the DRIVE_MODE[7:0] field of the Port
Configuration register, GPIO_PRTx_CFG. Table 23-1 lists
Pins are driven by the digital output driver. It consists of
the drive modes. Drive mode ‘1’ is reserved and should not
circuitry to implement different drive modes and slew rate
be used in most designs. CPU register and AMUXBUS
control for the digital output signals. The HSIOM selects the
connections support seven discrete drive modes to
control source for the output driver. The two primary types of
maximize design flexibility. Fixed-function digital peripherals,
control sources are CPU registers and fixed-function digital
such as SCB and TCPWM blocks, support modified
peripherals. A particular HSIOM connection is selected by
functionality for the same seven drive modes compatible
writing to the HSIOM port select register
with fixed peripheral signaling. Figure 23-3 shows simplified
(HSIOM_PORT_SELx).
output driver diagrams of the pin view for CPU register
I/O ports are powered by different sources. The specific control on each of the eight drive modes. Figure 23-4 is a
allocation of ports to supply sources can be found in the simplified output driver diagram that shows the pin view for
Pinout section of the PSoC 61 datasheet/PSoC 62 fixed-function-based peripherals for each of the eight drive
datasheet. modes.

Table 23-1. Drive Mode Settings

CPU Register, AMUXBUS Fixed-Function Digital Peripheral
Drive Mode Value OUT_EN = 1 OUT_EN = 0 OUT_EN = 1 OUT_EN = 0
OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0 OUT = 1 OUT = 0
High Impedance 0 HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
Weak 1 & Weak 1 &
Reserved 1 Strong 1 Strong 0 HI-Z HI-Z Strong 1 Strong 0
0 0
Resistive Pull Up 2 Weak 1 Strong 0 HI-Z HI-Z Strong 1 Strong 0 Weak 1 Weak 1
Resistive Pull Down 3 Strong 1 Weak 0 HI-Z HI-Z Strong 1 Strong 0 Weak 0 Weak 0
Open Drain, Drives Low 4 HI-Z Strong 0 HI-Z HI-Z Strong 1 Strong 0 HI-Z HI-Z
Open Drain, Drives High 5 Strong 1 HI-Z HI-Z HI-Z Strong 1 Strong 0 HI-Z HI-Z
Strong 6 Strong 1 Strong 0 HI-Z HI-Z Strong 1 Strong 0 HI-Z HI-Z
Resistive Pull Up and Down 7 Weak 1 Weak 0 HI-Z HI-Z Strong 1 Strong 0 Weak 1 Weak 0

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 I/O System

Figure 23-3. CPU I/O Drive Mode Block Diagram

VDDIO VDDIO VDDIO

OUT_EN OUT_EN OUT_EN OUT_EN

OUT OUT OUT OUT

Pin Pin Pin Pin
IN IN IN IN

0. High Impedance 1. Reserved 2. Resistive 3. Resistive

Pull up Pull down
VDDIO VDDIO VDDIO

OUT_EN OUT_EN OUT_EN OUT_EN

OUT OUT OUT OUT

Pin Pin Pin Pin
IN IN IN IN

4. Open Drain 5. Open Drain 6. Strong 7. Resistive Pull

Drives Low Drives High Up and Down

Figure 23-4. Peripheral I/O Drive Mode Block Diagrams

VDDIO VDDIO VDDIO

OUT_EN OUT_EN OUT_EN OUT_EN

OUT OUT OUT OUT

Pin Pin Pin Pin
IN IN IN IN

0. High Impedance 1. Reserved 2. Resistive 3. Resistive

Pull up Pull down
VDDIO VDDIO VDDIO VDDIO

OUT_EN OUT_EN OUT_EN OUT_EN

OUT OUT OUT OUT

Pin Pin Pin Pin
IN IN IN IN

4. Open Drain, 5. Open Drain, 6. Strong 7. Resistive Pull

Drives Low Drives High Up and Down

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 I/O System

■ High-Impedance are recommended for low-frequency signals or signals

without strict timing constraints.
This is the standard high-impedance (HI-Z) state
recommended for analog and digital inputs. For digital When configured for fast slew rate, the drive strength can be
signals, the input buffer is enabled; for analog signals, the set to one of four levels using the DRIVE_SEL field of the
input buffer is typically disabled to reduce crowbar current port output configuration register (GPIO_PRTx_CFG_OUT).
and leakage in low-power designs. To achieve the lowest The drive strength field determines the active portion of the
device current, unused GPIOs must be configured to the output drivers used and can affect the slew rate of output
high-impedance drive mode with input buffer disabled. High- signals. Drive strength options are full drive strength
impedance drive mode with input buffer disabled is also the (default), one-half strength, one-quarter strength, and one-
default pin reset state. eighth strength. Drive strength must be set to full drive
■ Resistive Pull-Up or Resistive Pull-Down strength when the slow slew rate bit (SLOW) is set.

Resistive modes provide a series resistance in one of the Note: For some devices in the PSoC 6 MCU family,
data states and strong drive in the other. Pins can be used simultaneous GPIO switching with unrestricted drive
for either digital input or digital output in these modes. If strengths and frequency can induce noise in on-chip
resistive pull-up is required, a ‘1’ must be written to that pin’s subsystems affecting CapSense and ADC results. Refer to
Data Register bit. If resistive pull-down is required, a ‘0’ the Errata section in the respective device datasheet for
must be written to that pin’s Data Register. Interfacing details.
mechanical switches is a common application of these drive
modes. The resistive modes are also used to interface 23.2.3.3 GPIO-OVT Pins
PSoC with open drain drive lines. Resistive pull-up is used Select device pins are overvoltage tolerant (OVT) and are
when the input is open drain low and resistive pull-down is useful for interfacing to busses or other signals that may
used when the input is open drain high. exceed the pin’s VDDIO supply, or where the whole device
■ Open Drain Drives High and Open Drain Drives Low supply or pin VDDIO may not be always present. They are
identical to regular GPIOs with the additional feature of
Open drain modes provide high impedance in one of the
being overvoltage tolerant. GPIO-OVT pins have hardware
data states and strong drive in the other. Pins are useful as
to compare VDDIO to the pin voltage. If the pin voltage
digital inputs or outputs in these modes. Therefore, these
exceeds VDDIO, the output driver is disabled and the pin
modes are widely used in bidirectional digital
driver is tristated. This results in negligible current sink at the
communication. Open drain drive high mode is used when
pin.
the signal is externally pulled down and open drain drive low
is used when the signal is externally pulled high. A common Note that in overvoltage conditions, the input buffer data will
application for the open drain drives low mode is driving I2C not be valid if the external source’s specification of VOH and
bus signal lines. VOL do not match the trip points of the input buffer defined
■ Strong Drive by the current VDDIO voltage.
The strong drive mode is the standard digital output mode
for pins; it provides a strong CMOS output drive in both high
and low states. Strong drive mode pins should not be used
as inputs under normal circumstances. This mode is often
used for digital output signals or to drive external devices.
■ Resistive Pull-Up and Resistive Pull-Down
In the resistive pull-up and pull-down mode, the GPIO will
have a series resistance in both logic 1 and logic 0 output
states. The high data state is pulled up while the low data
state is pulled down. This mode is useful when the pin is
driven by other signals that may cause shorts.

23.2.3.2 Slew Rate Control

GPIO pins have fast and slow output slew rate options for
the strong drivers configured using the SLOW bit of the port
output configuration register (GPIO_PRTx_CFG_OUT). By
default, this bit is cleared and the port works in fast slew
mode. This bit can be set if a slow slew rate is required.
Slower slew rate results in reduced EMI and crosstalk and

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 I/O System

23.3 High-Speed I/O Matrix

The high-speed I/O matrix (HSIOM) is a set of high-speed multiplexers that route internal CPU and peripheral signals to and
from GPIOs. HSIOM allows GPIOs to be shared with multiple functions and multiplexes the pin connection to a user-selected
peripheral. The HSIOM_PRTx_PORT_SEL[1:0] registers allow a single selection from up to 32 different connections to each
pin as listed in Table 23-2.

Table 23-2. HSIOM Connections

Digital Driver Signal Source Digital Input Analog Switches
SELy_SEL Name Signal Description
OUT OUT_EN Destination AMUXA AMUXB

GPIO_PRTx_OUT register controls

0 GPIO OUT Register 1 IN Register 0 0
OUT
1 Reserved – – – – – –
2 Reserved – – – – – –
3 Reserved – – – – – –
4 AMUXA OUT Register 1 IN Register 1 0 Analog mux bus A connected to pin
5 AMUXB OUT Register 1 IN Register 0 1 Analog mux bus B connected to pin
6 Reserved – – – – – –
7 Reserved – – – – – –
Active Source Active Source Active functionality 0 - See the
8 ACT_0 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 1 - See the
9 ACT_1 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 2 - See the
10 ACT_2 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 3 - See the
11 ACT_3 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Deep Sleep
Deep Sleep Deep Sleep functionality 0 - See the
12 DS_0 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 1 - See the
13 DS_1 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 2 - See the
14 DS_2 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 3 - See the
15 DS_3 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Active Source Active Source Active functionality 4 - See the
16 ACT_4 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 5 - See the
17 ACT_5 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 6 - See the
18 ACT_6 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 7 - See the
19 ACT_7 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 8 - See the
20 ACT_8 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 9 - See the
21 ACT_9 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity

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Table 23-2. HSIOM Connections

Digital Driver Signal Source Digital Input Analog Switches
SELy_SEL Name Signal Description
OUT OUT_EN Destination AMUXA AMUXB

Active Source Active Source Active functionality 10 - See the

22 ACT_10 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 11 - See the
23 ACT_11 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 12 - See the
24 ACT_12 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 13 - See the
25 ACT_13 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 14 - See the
26 ACT_14 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Active Source Active Source Active functionality 15 - See the
27 ACT_15 Active Source IN 0 0
OUT OUT_EN datasheet for specific pin connectivity
Deep Sleep
Deep Sleep Deep Sleep functionality 4 - See the
28 DS_4 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 5 - See the
29 DS_5 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 6 - See the
30 DS_6 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN
Deep Sleep
Deep Sleep Deep Sleep functionality 7 - See the
31 DS_7 Source OUT- Deep Sleep IN 0 0
Source OUT datasheet for specific pin connectivity
_EN

Note: The Active and Deep Sleep sources are pin dependent. See the “Pinouts” section of the PSoC 61 datasheet/PSoC 62
datasheet for more details on the features supported by each pin.

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 I/O System

23.4 I/O State on Power Up

During power up, all the GPIOs are in high-impedance analog state and the input buffers are disabled. During runtime, GPIOs
can be configured by writing to the associated registers. Note that the pins supporting debug access port (DAP) connections
(SWD lines) are always enabled as SWD lines during power up. The DAP connection does not provide pull-up or pull-down
resistors; therefore, if left floating some crowbar current is possible. The DAP connection can be disabled or reconfigured for
general-purpose use through the HSIOM only after the device boots and starts executing code.

23.5 Behavior in Low-Power Modes

Table 23-3 shows the status of GPIOs in low-power modes.

Table 23-3. GPIO in Low-Power Modes

Low-Power Mode Status
■ Standard GPIO, GPIO-OVT, and SIO pins are active and can be driven by most peripherals such as CapSense,
CPU Sleep TCPWMs, and SCBs, which can operate in CPU Sleep mode.
■ Inputs buffers are active; thus an interrupt on any I/O can be used to wake the CPU.
■ GPIO, GPIO-OVT, and SIO pins, connected to System Deep Sleep domain peripherals, are functional. All other
System Deep Sleep pins maintain the last output driver state and configuration.
■ Pin interrupts are functional on all I/Os and can be used to wake the device.
■ Pin output states and configuration are latched and remain in the frozen state.
System Hibernate ■ Pin interrupts are functional only on select IOs and can be used to wake the device. See the PSoC 61
datasheet/PSoC 62 datasheet for specific hibernate pin connectivity.

23.6 Interrupt
All port pins have the capability to generate interrupts. Figure 23-5 shows the routing of pin signals to generate interrupts.
Figure 23-5. Interrupt Signal Routing

Pin Dedicated IRQ Route

GPIO Edge Interrupt
HSIOM
Detect Controller

■ Pin signal through the “GPIO Edge Detect” block with direct connection to the CPU interrupt controller
Figure 23-6 shows the GPIO Edge Detect block architecture.
Figure 23-6. GPIO Edge Detect Block Architecture
50 ns Glitch Filter Edge Detector

Pin 0 Edge Detector

Pin 1 Edge Detector
Pin 2 Edge Detector
Pin 3 Edge Detector Interrupt
Signal
Pin 4 Edge Detector
Pin 5 Edge Detector
Pin 6 Edge Detector
Pin 7 Edge Detector

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An edge detector is present at each pin. It is capable of The GPIO_PRTx_INTR_MASK register enables forwarding
detecting rising edge, falling edge, and both edges without of the GPIO_PRTx_INTR edge detect signal to the interrupt
any reconfiguration. The edge detector is configured by controller when a ‘1’ is written to a pin’s corresponding
writing into the EDGEv_SEL bits of the Port Interrupt bitfield. The GPIO_PRTx_INTR_MASKED register can then
Configuration register, GPIO_PRTx_INTR_CFG, as shown be read to determine the specific pin that generated the
in Table 23-4. interrupt signal forwarded to the interrupt controller. The
masked edge detector outputs of a port are then ORed
Table 23-4. Edge Detector Configuration together and routed to the interrupt controller (NVIC in the
EDGE_SEL Configuration CPU subsystem). Thus, there is only one interrupt vector
per port.
00 Interrupt is disabled
01 Interrupt on Rising Edge The masked and ORed edge detector block output is routed
10 Interrupt on Falling Edge to the Interrupt Source Multiplexer shown in Figure 8-3 on
page 59, which gives an option of Level and Rising Edge
11 Interrupt on Both Edges
detection. If the Level option is selected, an interrupt is
triggered repeatedly as long as the Port Interrupt Status
Writing ‘1’ to the corresponding status bit clears the pin edge register bit is set. If the Rising Edge detect option is
state. Clearing the edge state status bit is important; selected, an interrupt is triggered only once if the Port
otherwise, an interrupt can occur repeatedly for a single Interrupt Status register is not cleared. Thus, the interrupt
trigger or respond only once for multiple triggers, which is status bit must be cleared if the Edge Detect block is used.
explained later in this section. When the Port Interrupt
Control Status register is read at the same time an edge is All of the port interrupt vectors are also ORed together into a
occurring on the corresponding port, it can result in the edge single interrupt vector for use on devices with more ports
not being properly detected. Therefore, when using GPIO than there are interrupt vectors available. To determine the
interrupts, read the status register only inside the port that triggered the interrupt, the GPIO_INTR_CAUSEx
corresponding interrupt service routine and not in any other registers can be read. A ‘1’ present in a bit location indicates
part of the code. that the corresponding port has a pending interrupt. The
indicated GPIO_PRTx_INTR register can then be read to
Firmware and the debug interface are able to trigger a determine the pin source.
hardware interrupt from any pin by setting the corresponding
bit in the GPIO_PRTx_INTR_SET register.
In addition to the pins, each port provides a glitch filter
23.7 Peripheral Connections
connected to its own edge detector. This filter can be driven
by one of the pins of a port. The selection of the driving pin 23.7.1 Firmware-Controlled GPIO
is done by writing to the FLT_SEL field of the
GPIO_PRTx_INTR_CFG register as shown in Table 23-5. For standard firmware-controlled GPIO using registers, the
GPIO mode must be selected in the HSIOM_PORT_SELx
Table 23-5. Glitch Filter Input Selection register.
FLT_SEL Selected Pin The GPIO_PRTx_OUT register is used to read and write the
000 Pin 0 is selected output buffer state for GPIOs. A write operation to this
001 Pin 1 is selected
register changes the GPIO’s output driver state to the
written value. A read operation reflects the output data
010 Pin 2 is selected
written to this register and the resulting output driver state. It
011 Pin 3 is selected does not return the current logic level present on GPIO pins,
100 Pin 4 is selected which may be different. Using the GPIO_PRTx_OUT
101 Pin 5 is selected register, read-modify-write sequences can be safely
110 Pin 6 is selected performed on a port that has both input and output GPIOs.
111 Pin 7 is selected In addition to the data register, three other registers –
GPIO_PRTx_SET, GPIO_PRTx_CLR, and
When a port pin edge occurs, you can read the Port GPIO_PRTx_INV – are provided to set, clear, and invert the
Interrupt Status register, GPIO_PRTx_INTR, to know which output data respectively on specific pins in a port without
pin caused the edge. This register includes both the latched affecting other pins. This avoids the need for read-modify-
information on which pin detected an edge and the current write operations in most use cases. Writing ‘1’ to these
pin status. This allows the CPU to read both information in a register bitfields will set, clear, or invert the respective pin;
single read operation. This register has an additional use – writing ‘0’ will have no affect on the pin state.
to clear the latched edge state.

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GPIO_PRTx_IN is the port I/O pad register, which provides 23.8 Smart I/O
the actual logic level present on the GPIO pin when read.
Writes to this register have no effect. The Smart I/O block adds programmable logic to an I/O port.
This programmable logic integrates board-level Boolean
23.7.2 Analog I/O logic functionality such as AND, OR, and XOR into the port.
A graphical interface is provided with the ModusToolbox
Analog resources, such as LPCOMP and SAR ADC, which install for configuring the Smart I/O block. For more informa-
require low-impedance routing paths have dedicated pins. tion about the configurator tool, see the ModusToolbox
Dedicated analog pins provide direct connections to specific Smart I/O Configurator Guide.
analog blocks. They help improve performance and should
be given priority over other pins when using these analog The Smart I/O block has these features:
resources. See the PSoC 61 datasheet/PSoC 62 datasheet ■ Integrate board-level Boolean logic functionality into a
for details on these dedicated pins of the PSoC 6 MCU. port
To configure a GPIO as a dedicated analog I/O, it should be ■ Ability to preprocess HSIOM input signals from the GPIO
configured in high-impedance analog mode (see Table 23-1) port pins
with input buffer disabled. The respective connection should ■ Ability to post-process HSIOM output signals to the
be enabled via registers in the specific analog resource. GPIO port pins
To configure a GPIO as an analog pin connecting to ■ Support in all device power modes except Hibernate
AMUXBUS, it should be configured in high-impedance ■ Integrate closely to the I/O pads, providing shortest
analog mode with the input buffer disabled and then routed signal paths with programmability
to the correct AMUXBUS using the HSIOM_PORT_SELx
register. 23.8.1 Overview
While it is preferred for analog pins to disable the input The Smart I/O block is positioned in the signal path between
buffer, it is acceptable to enable the input buffer if the HSIOM and the I/O port. The HSIOM multiplexes the
simultaneous analog and digital input features are required. output signals from fixed-function peripherals and CPU to a
specific port pin and vice-versa. The Smart I/O block is
23.7.2.1 AMUXBUS Connection placed on this signal path, acting as a bridge that can
Static connection of AMUXBUS A or B is made by selecting process signals between port pins and HSIOM, as shown in
AMUXA or AMUXB in the HSIOM_PORT_SELx register. Figure 23-7.

To properly configure a pin as AMUXBUS input, follow these

steps:
1. Configure the GPIO_PRTx_CFG register to set the pin
in high-Impedance mode with input buffer disabled,
enabling analog connectivity on the pin.
2. Configure the HSIOM_PRT_SELx register to connect
the pin to AMUXBUS A or B.

23.7.3 LCD Drive

GPIOs have the capability of driving an LCD common or
segment line. HSIOM_PORT_SELx registers are used to
select pins for the LCD drive. See the LCD Direct
Drive chapter on page 483 for details.

23.7.4 CapSense
The pins that support CapSense can be configured as
CapSense widgets such as buttons, slider elements,
touchpad elements, or proximity sensors. CapSense also
requires external capacitors and optional shield lines. See
the PSoC 4 and PSoC 6 MCU CapSense Design Guide for
more details.

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Figure 23-7. Smart I/O Interface

HSIOM GPIO Output

Output Signals Signals
3

HSIOM 2 Smart I/O 1 I/O Port

4
HSIOM GPIO Input
Input Signals Signals

The signal paths supported through the Smart I/O block as clock. Therefore, communication between Smart I/O and
shown in Figure 23-7 are as follows: other synchronous logic should be treated as asynchronous.
1. Implement self-contained logic functions that directly The following clock sources are available for selection:
operate on port I/O signals
■ GPIO input signals “io_data_in[7:0]”. These clock
2. Implement self-contained logic functions that operate on sources have no associated reset.
HSIOM signals
■ HSIOM output signals “chip_data[7:0]”. These clock
3. Operate on and modify HSIOM output signals and route sources have no associated reset.
the modified signals to port I/O signals
■ Smart I/O clock (clk_smartio). This is derived from the
4. Operate on and modify port I/O signals and route the system clock (clk_sys) using a peripheral clock divider.
modified signals to HSIOM input signals See the Clocking System chapter on page 242 for
The following sections discuss the Smart I/O block details on peripheral clock dividers. This clock is
components, routing, and configuration in detail. In these available only in System LP and ULP power modes. The
sections, GPIO signals (io_data) refer to the input/output clock can have one out of two associated resets:
signals from the I/O port; device or chip (chip_data) signals rst_sys_act_n and rst_sys_dpslp_n. These resets
refer to the input/output signals from HSIOM. determine in which system power modes the block
synchronous state is reset; for example, rst_sys_act_n is
intended for Smart I/O synchronous functionality in the
23.8.2 Block Components System LP and ULP power modes and reset is activated
The internal logic of the Smart I/O includes these in the System Deep Sleep power mode.
components: ■ Low-frequency system clock (clk_lf). This clock is
■ Clock/reset available in System Deep Sleep power mode. This clock
has an associated reset, rst_lf_dpslp_n. Reset is
■ Synchronizers
activated if the system enters Hibernate, or is at POR.
■ Three-input lookup table (LUT)
When the block is enabled, the selected clock (clk_block)
■ Data unit
and associated reset (rst_block_n) are provided to the fabric
components. When the fabric is disabled, no clock is
23.8.2.1 Clock and Reset
released to the fabric components and the reset is activated
The clock and reset component selects the Smart I/O (the LUT and data unit components are set to the reset
block’s clock (clk_block) and reset signal (rst_block_n). A value of ‘0’).
single clock and reset signal is used for all components in
The I/O input synchronizers introduce a delay of two
the block. The clock and reset sources are determined by
clk_block cycles (when synchronizers are enabled). As a
the CLOCK_SRC[4:0] bitfield of the SMARTIO_PRTx_CTL
result, in the first two cycles, the block may be exposed to
register. The selected clock is used for the synchronous
stale data from the synchronizer output. Hence, during the
logic in the block components, which includes the I/O input
first two clock cycles, the reset is activated and the block is
synchronizers, LUT, and data unit components. The
in bypass mode.
selected reset is used to asynchronously reset the
synchronous logic in the LUT and data unit components.
Note that the selected clock (clk_block) for the block’s
synchronous logic is not phase-aligned with other
synchronous logic in the device, operating on the same

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Table 23-6. Clock and Reset Register Control

Register[BIT_POS] Bit Name Description
Clock (clk_block)/reset (rst_block_n) source selection:
0: io_data_in[0]/1
...
7: io_data_in[7]/1
8: chip_data[0]/1
...
15: chip_data[7]/1
16: clk_smartio/rst_sys_act_n; asserts reset in any power mode other than System LP
or ULP; that is, Smart I/O is active only in LP or ULP power modes with clock from the
SMARTIO_PRTn_CTL[12:8] CLOCK_SRC[4:0] peripheral divider.
17: clk_smartio/rst_sys_dpslp_n. Smart I/O is active in all power modes with a clock
from the peripheral divider. However, the clock will not be active in System deep sleep
power mode.
19: clk_lf/rst_lf_dpslp_n. Smart I/O is active in all power modes with a clock from ILO.
20-30: Clock source is a constant '0'. Any of these clock sources should be selected
when Smart I/O is disabled to ensure low power consumption.
31: clk_sys/1. This selection is not intended for clk_sys operation. However, for
asynchronous operation, three clk_sys cycles after enabling, the Smart I/O is fully
functional (reset is de-activated). To be used for asynchronous (clockless) block
functionality.

23.8.2.2 Synchronizer
Each GPIO input signal and device input signal (HSIOM input) can be used either asynchronously or synchronously. To use
the signals synchronously, a double flip-flop synchronizer, as shown in Figure 23-8, is placed on both these signal paths to
synchronize the signal to the Smart I/O clock (clk_block). The synchronization for each pin/input is enabled or disabled by
setting or clearing the IO_SYNC_EN[i] bitfield for GPIO input signal and CHIP_SYNC_EN[i] for HSIOM signal in the
SMARTIO_PRTx_SYNC_CTL register, where ‘i’ is the pin number.
Figure 23-8. Smart I/O Clock Synchronizer
Clock Synchronizer

0
To SMARTIO
block io_data_in[i]
1 Q D Q D
Or
chip_data_in[i]

clk clk

clk_block

SYNC_CTL.IO_SYNC_EN[i]
Or
SYNC_CTL.CHIP_SYNC_EN[i]

23.8.2.3 Lookup Table (LUT)

Each Smart I/O block contains eight lookup table (LUT) components. The LUT component consists of a three-input LUT and
a flip-flop. Each LUT block takes three input signals and generates an output based on the configuration set in the
SMARTIO_PRTx_LUT_CTLy register (y denotes the LUT number). For each LUT, the configuration is determined by an 8-bit
lookup vector LUT[7:0] and a 2-bit opcode OPC[1:0] in the SMARTIO_PRTx_LUT_CTLy register. The 8-bit vector is used as
a lookup table for the three input signals. The 2-bit opcode determines the usage of the flip-flop. The LUT configuration for
different opcodes is shown in Figure 23-9.

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The SMARTIO_PRTx_LUT_SELy registers select the three input signals (tr0_in, tr1_in, and tr2_in) going into each LUT. The
input can come from the following sources:
■ Data unit output
■ Other LUT output signals (tr_out)
■ HSIOM output signals (chip_data[7:0])
■ GPIO input signals (io_data[7:0])

LUT_TR0_SEL[3:0] bits of the SMARTIO_PRTx_LUT_SELy register selects the tr0_in signal for the yth LUT. Similarly,
LUT_TR1_SEL[3:0] bits and LUT_TR2_SEL[3:0] bits select the tr1_in and tr2_in signals, respectively. See Table 23-7 for
details.

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Table 23-7. LUT Register Control

Register[BIT_POS] Bit Name Description
LUT configuration. Depending on the LUT opcode (LUT_OPC), the internal
state, and the LUT input signals tr0_in, tr1_in, and tr2_in, the LUT
SMARTIO_PRTx_LUT_CTLy[7:0] LUT[7:0]
configuration is used to determine the LUT output signal and the next
sequential state.
SMARTIO_PRTx_LUT_CTLy[9:8] LUT_OPC[1:0] LUT opcode specifies the LUT operation as illustrated in Figure 23-9.
LUT input signal “tr0_in” source selection:
0: Data unit output
1: LUT 1 output
2: LUT 2 output
3: LUT 3 output
4: LUT 4 output
5: LUT 5 output
6: LUT 6 output
SMARTIO_PRTx_LUT_SELy[3:0] LUT_TR0_SEL[3:0] 7: LUT 7 output
8: chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7)
9: chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7)
10: chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7)
11: chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7)
12: io_data_in[0] (for LUTs 0, 1, 2, 3); io_data[4] (for LUTs 4, 5, 6, 7)
13: io_data_in[1] (for LUTs 0, 1, 2, 3); io_data[5] (for LUTs 4, 5, 6, 7)
14: io_data_in[2] (for LUTs 0, 1, 2, 3); io_data[6] (for LUTs 4, 5, 6, 7)
15: io_data_in[3] (for LUTs 0, 1, 2, 3); io_data[7] (for LUTs 4, 5, 6, 7)
LUT input signal “tr1_in” source selection:
0: LUT 0 output
1: LUT 1 output
2: LUT 2 output
3: LUT 3 output
4: LUT 4 output
5: LUT 5 output
6: LUT 6 output
SMARTIO_PRTx_LUT_SELy[11:8] LUT_TR1_SEL[3:0] 7: LUT 7 output
8: chip_data[0] (for LUTs 0, 1, 2, 3); chip_data[4] (for LUTs 4, 5, 6, 7)
9: chip_data[1] (for LUTs 0, 1, 2, 3); chip_data[5] (for LUTs 4, 5, 6, 7)
10: chip_data[2] (for LUTs 0, 1, 2, 3); chip_data[6] (for LUTs 4, 5, 6, 7)
11: chip_data[3] (for LUTs 0, 1, 2, 3); chip_data[7] (for LUTs 4, 5, 6, 7)
12: io_data_in[0] (for LUTs 0, 1, 2, 3); io_data[4] (for LUTs 4, 5, 6, 7)
13: io_data_in[1] (for LUTs 0, 1, 2, 3); io_data[5] (for LUTs 4, 5, 6, 7)
14: io_data_in[2] (for LUTs 0, 1, 2, 3); io_data[6] (for LUTs 4, 5, 6, 7)
15: io_data_in[3] (for LUTs 0, 1, 2, 3); io_data[7] (for LUTs 4, 5, 6, 7)
LUT input signal “tr2_in” source selection. Encoding is the same as for
SMARTIO_PRTx_LUT_SELy[19:16] LUT_TR2_SEL[3:0]
LUT_TR1_SEL.

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 I/O System

Figure 23-9. Smart I/O LUT Configuration

OPC[1:0] = 0

tr0_in

tr1_in LUT tr_out

tr2_in

LUT[7:0]

OPC[1:0] = 1

tr0_in

tr1_in LUT tr_out

tr2_in

clk_block 8

LUT[7:0]

OPC[1:0] = 2

tr0_in

tr1_in LUT tr_out

tr2_in

8 clk_block
LUT[7:0]

LUT[5] OPC[1:0] = 3
Enable
LUT[4]
tr2_in
LUT[3]
LUT[2] Set
tr1_in tr_out
Clr
LUT[1] Clk
LUT[0]
tr0_in
clk_block

23.8.2.4 Data Unit (DU)

Each Smart I/O block includes a data unit (DU) component. The DU consists of a simple 8-bit datapath. It is capable of
performing simple increment, decrement, increment/decrement, shift, and AND/OR operations. The operation performed by
the DU is selected using a 4-bit opcode DU_OPC[3:0] bitfield in the SMARTIO_PRTx_DU_CTL register.
The DU component supports up to three input trigger signals (tr0_in, tr1_in, tr2_in) similar to the LUT component. These
signals are used to initiate an operation defined by the DU opcode. In addition, the DU also includes two 8-bit data inputs
(data0_in[7:0] and data1_in[7:0]) that are used to initialize the 8-bit internal state (data[7:0]) or to provide a reference. The 8-
bit data input source is configured as:
■ Constant ‘0x00’
■ io_data_in[7:0]
■ chip_data_in[7:0]
■ DATA[7:0] bitfield of SMARTIO_PRTx_DATA register

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 I/O System

The trigger signals are selected using the DU_TRx_SEL[3:0] bitfield of the SMARTIO_PRTx_DU_SEL register. The DUT_-
DATAx_SEL[1:0] bits of the SMARTIO_PRTx_DU_SEL register select the 8-bit input data source. The size of the DU (number
of bits used by the datapath) is defined by the DU_SIZE[2:0] bits of the SMARTIO_PRTx_DU_CTL register. See Table 23-8
for register control details.

Table 23-8. Data Unit Register Control

Register[BIT_POS] Bit Name Description
Size/width of the data unit (in bits) is DU_SIZE+1. For example, if DU_SIZE is
SMARTIO_PRTx_DU_CTL[2:0] DU_SIZE[2:0]
7, the width is 8 bits.
Data unit opcode specifies the data unit operation:
1: INCR
2: DECR
3: INCR_WRAP
4: DECR_WRAP
5: INCR_DECR
SMARTIO_PRTx_DU_CTL[11:8] DU_OPC[3:0] 6: INCR_DECR_WRAP
7: ROR
8: SHR
9: AND_OR
10: SHR_MAJ3
11: SHR_EQL
Otherwise: Undefined.
Data unit input signal “tr0_in” source selection:
0: Constant '0'.
1: Constant '1'.
SMARTIO_PRTx_DU_SEL[3:0] DU_TR0_SEl[3:0]
2: Data unit output.
10–3: LUT 7–0 outputs.
Otherwise: Undefined.
Data unit input signal “tr1_in” source selection. Encoding same as DU_TR0_-
SMARTIO_PRTx_DU_SEL[11:8] DU_TR1_SEl[3:0]
SEL
Data unit input signal “tr2_in” source selection. Encoding same as DU_TR0_-
SMARTIO_PRTx_DU_SEL[19:16] DU_TR2_SEl[3:0]
SEL
Data unit input data “data0_in” source selection:
0: 0x00
SMARTIO_PRTx_DU_SEL[25:24] DU_DATA0_SEL[1:0] 1: chip_data[7:0].
2: io_data[7:0].
3: SMARTIO_PRTx_DATA.DATA[7:0] register field.
Data unit input data “data1_in” source selection. Encoding same as DU_DA-
SMARTIO_PRTx_DU_SEL[29:28] DU_DATA1_SEL[1:0]
TA0_SEL.
SMARTIO_PRTx_DATA[7:0] DATA[7:0] Data unit input data source.

The DU generates a single output trigger signal (tr_out). The internal state (du_data[7:0]) is captured in flip-flops and requires
clk_block.
The following pseudo code describes the various datapath operations supported by the DU opcode. Note that “Comb”
describes the combinatorial functionality – that is, functions that operate independent of previous output states. “Reg”
describes the registered functionality – that is, functions that operate on inputs and previous output states (registered using
flip-flops).
// The following is shared by all operations.
mask = (2 ^ (DU_SIZE+1) – 1)
data_eql_data1_in = (data & mask) == (data1_in & mask));
data_eql_0 = (data & mask) == 0);
data_incr = (data + 1) & mask;
data_decr = (data - 1) & mask;

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 I/O System

data0_masked = data_in0 & mask;

// INCR operation: increments data by 1 from an initial value (data0) until it reaches a
// final value (data1).
Comb:tr_out = data_eql_data1_in;
Reg: data <= data;
if (tr0_in) data <= data0_masked; //tr0_in is reload signal - loads masked data0
// into data
else if (tr1_in) data <= data_eql_data1_in ? data : data_incr; //increment data until
// it equals data1

// INCR_WRAP operation: operates similar to INCR but instead of stopping at data1, it wraps
// around to data0.
Comb:tr_out = data_eql_data1_in;
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) data <= data_eql_data1_in ? data0_masked : data_incr;

// DECR operation: decrements data from an initial value (data0) until it reaches 0.
Comb:tr_out = data_eql_0;
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) data <= data_eql_0 ? data : data_decr;

// DECR_WRAP operation: works similar to DECR. Instead of stopping at 0, it wraps around to

// data0.
Comb:tr_out = data_eql_0;
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) data <= data_eql_0 ? data0_masked: data_decr;

// INCR_DECR operation: combination of INCR and DECR. Depending on trigger signals it either
// starts incrementing or decrementing. Increment stops at data1 and decrement stops at 0.
Comb:tr_out = data_eql_data1_in | data_eql_0;
Reg: data <= data;
if (tr0_in) data <= data0_masked; // Increment operation takes precedence over
// decrement when both signal are available
else if (tr1_in) data <= data_eql_data1_in ? data : data_incr;
else if (tr2_in) data <= data_eql_0 ? data : data_decr;

// INCR_DECR_WRAP operation: same functionality as INCR_DECR with wrap around to data0 on

// reaching the limits.
Comb:tr_out = data_eql_data1_in | data_eql_0;
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) data <= data_eql_data1_in ? data0_masked : data_incr;
else if (tr2_in) data <= data_eql_0 ? data0_masked : data_decr;

// ROR operation: rotates data right and LSb is sent out. The data for rotation is taken from
// data0.
Comb:tr_out = data[0];
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) {
data <= {0, data[7:1]} & mask; //Shift right operation
data[du_size] <= data[0]; //Move the data[0] (LSb) to MSb
}

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 I/O System

// SHR operation: performs shift register operation. Initial data (data0) is shifted out and
// data on tr2_in is shifted in.
Comb:tr_out = data[0];
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) {
data <= {0, data[7:1]} & mask; //Shift right operation
data[du_size] <= tr2_in; //tr2_in Shift in operation
}

// SHR_MAJ3 operation: performs the same functionality as SHR. Instead of sending out the
// shifted out value, it sends out a '1' if in the last three samples/shifted-out values
// (data[0]), the signal high in at least two samples. otherwise, sends a '0'. This function
// sends out the majority of the last three samples.
Comb:tr_out = (data == 0x03)
| (data == 0x05)
| (data == 0x06)
| (data == 0x07);
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) {
data <= {0, data[7:1]} & mask;
data[du_size] <= tr2_in;
}

// SHR_EQL operation: performs the same operation as SHR. Instead of shift-out, the output is
// a comparison result (data0 == data1).
Comb:tr_out = data_eql_data1_in;
Reg: data <= data;
if (tr0_in) data <= data0_masked;
else if (tr1_in) {
data <= {0, data[7:1]} & mask;
data[du_size] <= tr2_in;
}

// AND_OR operation: ANDs data1 and data0 along with mask; then, ORs all the bits of the
// ANDed output.
Comb:tr_out = | (data & data1_in & mask);
Reg: data <= data;
if (tr0_in) data <= data0_masked;

23.8.3 Routing
The Smart I/O block includes many switches that are used to route the signals in and out of the block and also between
various components present inside the block. The routing switches are handled through the PRTGIO_PRTx_LUT_SELy and
SMARTIO_PRTx_DU_SEL registers. Refer to the registers TRM for details. The Smart I/O internal routing is shown in
Figure 23-10. In the figure, note that LUT7 to LUT4 operate on io_data/chip_data[7] to io_data/chip_data[4] whereas LUT3 to
LUT0 operate on io_data/chip_data[3] to io_data/chip_data[0].

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 I/O System

Figure 23-10. Smart I/O Routing

8 rst_block_n
0x00 Clock and
8 Reset
SMARTIO_PRTx_DATA.DATA[7:0] clk_block
8
chip_data[7:0]
8

io_data[7:0]

data_in0

data_in1
clk_smartio
Data Unit clk_sys

tr_out
tr0_in
tr1_in
tr2_in
clk_lf

Sync io_data[7]
smartio_data[7] smartio_data[7]
chip_data[7] Sync chip_data[7]

Sync io_data[6]
smartio_data[6] smartio_data[6]
chip_data[6] Sync chip_data[6]

Sync io_data[5]
smartio_data[5] smartio_data[5]
chip_data[5] Sync chip_data[5]

Sync io_data[4]
smartio_data[4] smartio_data[4]
chip_data[4] Sync chip_data[4]

Sync io_data[3]
smartio_data[3] smartio_data[3]
chip_data[3] Sync chip_data[3]

Sync io_data[2]
smartio_data[2] smartio_data[2]
chip_data[2] Sync chip_data[2]

Sync io_data[1]
smartio_data[1] smartio_data[1]
chip_data[1] Sync chip_data[1]

Sync io_data[0]
smartio_data[0] smartio_data[0]
chip_data[0] Sync chip_data[0]

1'b0
tr1_in
tr2_in

tr0_in
tr1_in

tr0_in
tr1_in
tr2_in
tr1_in
tr_out

tr_out

tr_out

tr_out
tr_out

tr_out

tr_out

tr_out
tr0_in

tr2_in

tr0_in
tr1_in
tr2_in
tr0_in
tr1_in
tr2_in

tr0_in

tr2_in

tr0_in
tr1_in
tr2_in

tr0_in
tr1_in
tr2_in
1'b1

clk_block
LUT0 LUT1 LUT2 LUT3 LUT4 LUT5 LUT6 LUT7 Various signals
8-bit wide data bus
Programmable Switch (ONLY ONE of the switches along a
vertical line can be closed at a time)
Closed switch connecting a bit of the 8-bit data bus

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 I/O System

23.8.4 Operation
The Smart I/O block should be configured and operated as follows:
1. Before enabling the block, all the components and routing should be configured as explained in “Block Components” on
page 272.
2. In addition to configuring the components and routing, some block level settings must be configured correctly for desired
operation.
a. Bypass control: The Smart I/O path can be bypassed for a particular GPIO signal by setting the BYPASS[i] bitfield in
the SMARTIO_PRTx_CTL register. When bit ‘i’ is set in the BYPASS[7:0] bitfield, the ith GPIO signal is bypassed to
the HSIOM signal path directly – Smart I/O logic will not be present in that signal path. This is useful when the Smart I/
O function is required only on select I/Os.
b. Pipelined trigger mode: The LUT input multiplexers and the LUT component itself do not include any combinatorial
loops. Similarly, the data unit also does not include any combinatorial loops. However, when one LUT interacts with
the other or to the data unit, inadvertent combinatorial loops are possible. To overcome this limitation, the
PIPELINE_EN bitfield of the SMARTIO_PRTx_CTL register is used. When set, all the outputs (LUT and DU) are
registered before branching out to other components.
3. After the Smart I/O block is configured for the desired functionality, the block can be enabled by setting the ENABLED
bitfield of the SMARTIO_PRTx_CTL register. If disabled, the Smart I/O block is put in bypass mode, where the GPIO
signals are directly controlled by the HSIOM signals and vice-versa. The Smart I/O block must be configured; that is, all
register settings must be updated before enabling the block to prevent glitches during register updates.

Table 23-9. Smart I/O Block Controls

Register [BIT_POS] Bit Name Description
Enable for pipeline register:
SMARTIO_PRTx_CTL[25] PIPELINE_EN 0: Disabled (register is bypassed).
1: Enabled
Enable Smart I/O. Should only be set to '1' when the Smart I/O is completely configured:
0: Disabled (signals are bypassed; behavior as if BYPASS[7:0] is 0xFF). When disabled,
the block (data unit and LUTs) reset is activated.
If the block is disabled:
SMARTIO_PRTx_CTL[31] ENABLED - The PIPELINE_EN register field should be set to '1', to ensure low power consumption.
- The CLOCK_SRC register field should be set to 20 to 30 (clock is constant '0'), to ensure
low power consumption.
1: Enabled. When enabled, it takes three clk_block clock cycles until the block reset is de-
activated and the block becomes fully functional. This action ensures that the I/O pins'
input synchronizer states are flushed when the block is fully functional.
Bypass of the Smart I/O, one bit for each I/O pin: BYPASS[i] is for I/O pin i. When
ENABLED is '1', this field is used. When ENABLED is '0', this field is not used and Smart I/
SMARTIO_PRTx_CTL[7:0] BYPASS[7:0] O is always bypassed.
0: No bypass (Smart I/O is present in the signal path)
1: Bypass (Smart I/O is absent in the signal path)

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 I/O System

23.9 Registers
Table 23-10. I/O Registers
Name Description
GPIO_PRTx_OUT Port output data register reads and writes the output driver data for I/O pins in the port.
GPIO_PRTx_OUT_CLR Port output data clear register clears output data of specific I/O pins in the port.
GPIO_PRTx_OUT_SET Port output data set register sets output data of specific I/O pins in the port.
GPIO_PRTx_OUT_INV Port output data invert register inverts output data of specific I/O pins in the port.
GPIO_PRTx_IN Port input state register reads the current pin state present on I/O pin inputs.
GPIO_PRTx_INTR Port interrupt status register reads the current pin interrupt state.
Port interrupt mask register configures the mask that forwards pin interrupts to the CPU’s
GPIO_PRTx_INTR_MASK
interrupt controller.
Port interrupt masked status register reads the masked interrupt status forwarded to the CPU
GPIO_PRTx_INTR_MASKED
interrupt controller.
GPIO_PRTx_INTR_SET Port interrupt set register allows firmware to set pin interrupts.
GPIO_PRTx_INTR_CFG Port interrupt configuration register selects the edge detection type for each pin interrupt.
GPIO_PRTx_CFG Port configuration register selects the drive mode and input buffer enable for each pin.
GPIO_PRTx_CFG_IN Port input buffer configuration register configures the input buffer mode for each pin.
GPIO_PRTx_CFG_OUT Port output buffer configuration register selects the output driver slew rate for each pin.
High-speed I/O Mux (HSIOM) port selection register selects the hardware peripheral connection
HSIOM_PORT_SELx
to I/O pins.

Note The ‘x’ in the GPIO register name denotes the port number. For example, GPIO_PTR1_OUT is the Port 1 output data
register.

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 24. Watchdog Timer

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The watchdog timer (WDT) is a hardware timer that automatically resets the device in the event of an unexpected firmware
execution path. The WDT, if enabled, must be serviced periodically in firmware to avoid a reset. Otherwise, the timer elapses
and generates a device reset. In addition, the WDT can be used as an interrupt source or a wakeup source in low-power
modes.
The PSoC 6 MCU family includes one free-running WDT and two multi-counter WDTs (MCWDT). The WDT has a 16-bit
counter. Each MCWDT has two 16-bit counters and one 32-bit counter. Thus, the watchdog system has a total of seven
counters – five 16-bit and two 32-bit. All 16-bit counters can generate a watchdog device reset. All seven counters can
generate an interrupt on a match event.

24.1 Features
The PSoC 6 MCU WDT supports these features:
■ One 16-bit free-running WDT with:
❐ ILO as the input clock source
❐ Device reset generation if not serviced within a configurable interval
❐ Periodic Interrupt/wakeup generation in LP/ULP Active, LP/ULP Sleep, Deep Sleep, and Hibernate power modes
■ Two MCWDTs, each supporting:
❐ Device reset generation if not serviced within a configurable interval
❐ LFCLK (ILO or WCO) as the input clock source
❐ Periodic interrupt/wake up generation in LP/ULP Active, LP/ULP Sleep, and Deep Sleep power modes (Hibernate
mode is not supported)
❐ Two 16-bit and one 32-bit independent counters, which can be configured as a single 64-bit or 48-bit (with one 16-bit
independent counter), or two 32-bit cascaded counters

24.2 Architecture
The PSoC 6 MCU supports 174 system interrupts. The interrupts are routed to both the CPU cores. In the case of CM4 only
the first 39 interrupts are routed to WIC while all 174 interrupts are routed to NVIC. The CM0 has access to only eight
interrupts of the maximum supported 32 interrupts. The 174 interrupt sources are multiplexed and at a time eight interrupt
sources can be connected to the CM0. The CPUSS_CM0_SYSTEM_INT_CTLx register decides which interrupts are
connected to the CM0. See the Interrupts chapter on page 56 for details on how to configure the interrupt for the free-running

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 Watchdog Timer

WDT/MCWDT to the required CPU. The free-running WDT/MCWDT resource must be used by one CPU only; it is not
intended for simultaneous use by both CPUs because of the complexity involved in coordination.
Figure 24-1. Watchdog Timer Block Diagram
Device Interrupt
CFG/STATUS
Registers WIC
Free running watchdog
timer
ILO Clock
Reset

2
CFG/STATUS Interrupt

Low
Multi counter watchdog
frequency
Clock
timers (x2) Device
clock 2 Reset
Reset
(LFCLK)

24.3 Free-running WDT

24.3.1 Overview
Figure 24-2 shows the functional overview of the free-running WDT. The WDT has a free-running wraparound up-counter with
a maximum of 16-bit resolution. The counter is clocked by the ILO. The timer can generate an interrupt on match and a reset
event on the third unhandled interrupt. The number of bits used for a match comparison is configurable as depicted in
Figure 24-2.
Figure 24-2. Free-running WDT Functional Diagram

ILO WDT (16-bit Counter)

2(16-WDT_MATCH.IGNORE_BITS*) -1
WDT_CNT
WDT_EN EN

Bitwise AND

== WDT_MATCH.MATCH **

Yes
INTERRUPT

++Count

Count == 3 RESET
***
SRSS_INTR.WDT_MATCH Count = 0
(Write 1 from Firmware)
Reset Generation
logic

Free-running WDT
* WDT_MATCH.IGNORE_BITS refer to value held by the bits[19:16] of the WDT_MATCH register.
** WDT_MATCH.MATCH refer to the value held by the bits[15:0] of the WDT_MATCH register.
*** SRSS_INTR.WDT_MATCH refers to the WDT_MATCH bit of the SRSS_INTR register.

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 Watchdog Timer

When enabled, the WDT counts up on each rising edge of bits are ignored while performing the match and the WDT
the ILO. When the counter value (WDT_CNT register) counter behaves similar to a 13-bit counter. Note that these
equals the match value stored in MATCH bits [15:0] of the bits do not reduce the counter size – the WDT_CNT register
WDT_MATCH register, an interrupt is generated. The match still counts from 0 to 65535 (16-bit).
event does not reset the WDT counter and the WDT keeps
The WDT can be enabled or disabled using the WDT_EN bit
counting until it reaches the 16-bit boundary (65535) at
[0] of the WDT_CTL register. The WDT_CTL register
which point, it wraps around to 0 and counts up. The match
provides a mechanism to lock the WDT configuration
interrupt is generated every time the counter value equals
registers. The WDT_LOCK bits [31:30] control the lock
the match value.
status of the WDT registers. These bits are special bits,
The WDT_MATCH bit of the SRSS_INTR register is set which can enable the lock in a single write; to release the
whenever a WDT match interrupt occurs. This interrupt must lock, two different writes are required. The WDT_LOCK bits
be cleared by writing a ‘1’ to the same bit. Clearing the protect the WDT_EN bit, WDT_MATCH register,
interrupt resets the watchdog. If the firmware does not clear CLK_ILO_CONFIG register, and LFCLK_SEL bits [1:0] of
the interrupt for two consecutive occasions, the third the CLK_SELECT register. Note that the WDT_LOCK bits
interrupt generates a device reset. are not retained in Deep Sleep mode and reset to their
default (LOCK) state after a deep sleep wakeup. As a result,
In addition, the WDT provides an option to set the number of
to update any register protected by the WDT_LOCK bits
bits to be used for comparison. The IGNORE_BITS (bits
after a deep sleep wakeup, a WDT UNLOCK sequence
[19:16] of the WDT_MATCH register) is used for this
should be issued before the register update.
purpose. These bits configure the number of MSbs to ignore
from the 16-bit count value while performing the match. For Table 24-1 explains various registers and bitfields used to
instance, when the value of these bits equals 3, the MSb 3 configure and use the WDT.
Table 24-1. Free-running WDT Configuration Options
Register [Bit_Pos] Bit_Name Description
Enable or disable the watchdog reset
WDT_CTL[0] WDT_EN 0: WDT reset disabled
1: WDT reset enabled
Lock or unlock write access to the watchdog configuration and clock related registers. When
the bits are set, the lock is enabled.
0: No effect
1: Clear bit 0
WDT_CTL[31:30] WDT_LOCK
2: Clear bit 1
3: Set both bit 0 and 1 (lock enabled)
WDT will lock on a reset. This field is not retained in Deep Sleep or Hibernate mode, so the
WDT will be locked after wakeup from these modes.
WDT_CNT[15:0] COUNTER Current value of WDT counter
WDT_MATCH[15:0] MATCH Match value to a generate watchdog match event
Number of MSbs of the WDT_CNT register to ignore for comparison with the MATCH value.
WDT_MATCH[19:16] IGNORE_BITS
Up to 12 MSbs can be ignored; settings above 12 act same as a setting of 12.
WDT interrupt request
SRSS_INTR[0] WDT_MATCH This bit is set whenever a watchdog match event happens. The WDT interrupt is cleared by
writing a ‘1’ to this bit
Mask for the WDT interrupt
SRSS_INTR_MASK[0] WDT_MATCH 0: WDT interrupt is blocked
1: WDT interrupt is forwarded to CPU

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 Watchdog Timer

24.3.2 Watchdog Reset

A watchdog is typically used to protect the device against firmware/system crashes or faults. When the WDT is used to
protect against system crashes, the WDT interrupt bit should be cleared by a portion of the code that is not directly associated
with the WDT interrupt. Otherwise, even if the main function of the firmware crashes or is in an endless loop, the WDT
interrupt vector can still be intact and feed the WDT periodically. Note that when the debug probe is connected, the device
reset is blocked and an interrupt is generated instead.
The safest way to use the WDT against system crashes is to:
■ Configure the watchdog reset period such that firmware is able to reset the watchdog at least once during the period, even
along the longest firmware delay path. If both CM4 and CM0 are being used then, use the free-running WDT for one of the
CPU and one MCWDT for the other CPU to prevent firmware crashes on either core.
■ Reset (feed) the watchdog by clearing the interrupt bit regularly in the main body of the firmware code by writing a ‘1’ to
the WDT_MATCH bit in the SRSS_INTR register. Note that this does not reset the watchdog counter, it feeds only the
watchdog so that it does not cause a reset for the next two match events.
Do not reset the watchdog (clear interrupt) in the WDT interrupt service routine (ISR) if WDT is being used as a reset source
to protect the system against crashes. Therefore, do not use the WDT reset feature and ISR together.
The recommended steps to use WDT as a reset source are as follows:
1. Make sure the WDT configuration is unlocked by clearing the WDT_LOCK bits[31:30] of the WDT_CTL register. Note that
clearing the bits requires two writes to the register with each write clearing one bit as explained in Table 24-1.
2. Write the desired IGNORE_BITS in the WDT_MATCH register to set the counter resolution to be used for the match.
3. Write any match value to the WDT_MATCH register. The match value does not control the period of watchdog reset as
the counter is not reset on a match event. This value provides an option to control only the first interrupt interval, after that
the successive interrupts’ period is defined by the IGNORE_BITS. Approximate watchdog period (in seconds) is given by
the following equation:

16 – IGNORE_BITS
Watchdog reset period = ILO period   2  2 + WDT_MATCH 
Equation 24-1
4. Set the WDT_MATCH bit in the SRSS_INTR register to clear any pending WDT interrupt.
5. Enable ILO by setting the ENABLE bit [31] of the CLK_ILO_CONFIG register.
6. Enable the WDT by setting the WDT_EN bit in WDT_CTL register.
7. Lock the WDT and ILO configuration by writing ‘3’ to the WDT_LOCK bits. This also locks the LFCLK_SEL bits of the
CLK_SELECT register.
8. In the firmware, write ‘1’ to the WDT_MATCH bit in the SRSS_INT register to feed (clear interrupt) the watchdog.

24.3.3 Watchdog Interrupt

In addition to generating a device reset, the WDT can be used to generate interrupts. Note that interrupt servicing and
watchdog reset cannot be used simultaneously using the free-running WDT.
The watchdog counter can send interrupt requests to the CPU in CPU Active power modes and to the wakeup interrupt
controller (WIC) in CPU Sleep and Deep Sleep power modes. In addition, the watchdog is capable of waking up the device
from Hibernate power mode. It works as follows:
■ CPU Active Mode: In Active power mode, the WDT can send the interrupt to the CPU. The CPU acknowledges the
interrupt request and executes the ISR. Clear the interrupt in the ISR.
■ CPU Sleep or Deep Sleep Mode: In this mode, the CPU is powered down. Therefore, the interrupt request from the WDT
is directly sent to the WIC, which then wakes up the CPU. The CPU acknowledges the interrupt request and executes the
ISR. Clear the interrupt in the ISR.
■ Hibernate Mode: In this mode, the entire device except a few peripherals (such as WDT and LPCOMP) are powered
down. Any interrupt to wake up the device in this mode results in a device reset. Hence, there is no interrupt service
routine or mechanism associated with this mode.
For more details on device power modes, see the Device Power Modes chapter on page 225.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 286
 Watchdog Timer

Because of its free-running nature, the WDT should not be used for periodic interrupt generation. Use the MCWDT instead;
see 24.4 Multi-Counter WDTs. The MCWDT counters can be used to generate periodic interrupts. If absolutely required,
follow these steps to use the WDT as a periodic interrupt generator:
1. Unlock the WDT if this is the first update to the WDT registers after a deep sleep or hibernate wakeup, or a device reset.
2. Write the desired IGNORE_BITS in the WDT_MATCH register to set the counter resolution to be used for the match.
3. Write the desired match value to the WDT_MATCH register.
4. Set the WDT_MATCH bit in the SRSS_INTR register to clear any pending WDT interrupt.
5. Enable the WDT interrupt to CPU by setting the WDT_MATCH bit in SRSS_INTR_MASK.
6. Enable SRSS interrupt to the CPU by configuring the appropriate ISER register (See the Interrupts chapter on page 56 for
details).
7. In the ISR, unlock the WDT; clear the WDT interrupt and add the desired match value to the existing match value. By
doing so, another interrupt is generated when the counter reaches the new match value (period).

24.4 Multi-Counter WDTs

24.4.1 Overview
Figure 24-3 shows the functional overview of a single multi-counter WDT block. The PSoC 6 MCU has two MCWDT blocks.
Each MCWDT block includes two 16-bit counters (MCWDTx_WDT0 and MCWDTx_WDT1) and one 32-bit counter
(MCWDTx_WDT2). These counters can be configured to work independently or in cascade (up to 64-bit). The 16-bit counters
can generate an interrupt or reset the device. The 32-bit counter can only generate an interrupt. All the counters are clocked
by LFCLK.
Note: Because the PSoC 6 MCU includes two CPUs (Cortex-M0+ and Cortex-M4), associate one MCWDT block to only one
CPU during runtime. Although both the MCWDT blocks are available for both CPUs, a single MCWDT is not intended to be
used by multiple CPUs simultaneously; however, a CPU can be associated with 0 or more MCWDTs.
Figure 24-3. Multi-Counter WDT Functional Diagram
LFCLK
MCWDT_CASCADE0_1 MCWDT_CASCADE1_2

MCWDTx_WDT0 (16-bit MCWDTx_WDT1 (16-bit MCWDTx_WDT2 (32-bit

Counter) Counter) Counter)
MCWDT_CTR0 MCWDT_CTR1 MCWDT_CTRHIGH

16 16 32

MCWDT_CTR0 == MCWDT_CTR1 ==
MCWDT_BITS2
MCWDT_MATCH0 MCWDT_MATCH1
5

MCWDT MCWDT MCWDT

MCWDT_MODE0 Mode MCWDT_MODE1 Mode MCWDT_MODE2 Mode
2 Configuration 2 Configuration 1 Configuration
RESET MCWDT_INT0 RESET MCWDT_INT1 MCWDT_INT2

INTERRUPT

Multi counter
RESET WDT

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 287
 Watchdog Timer

24.4.1.1 MCWDTx_WDT0 and MCWDTx_WDT1 Counters Operation

MCWDTx_WDT0 and MCWDTx_WDT1 are 16-bit up counters, which can be configured to be a 16-bit free-running counter
or a counter with any 16-bit period. These counters can be used to generate an interrupt or reset.
The WDT_CTR0 bits [15:0] and WDT_CTR1 bits [16:31] of the MCWDTx_CNTLOW register hold the current counter values
of MCWDTx_WDT0 and MCWDTx_WDT1 respectively. The WDT_MATCH0 bits [15:0] and WDT_MATCH1 bits [16:31] of the
MCWDTx_MATCH register store the match value for MCWDTx_WDT0 and MCWDTx_WDT1 respectively. The
WDT_MODEx bits of the MCWDTx_CONFIG register configure the action the watchdog counter takes on a match event
(WDT_MATCHx == WDT_CTRx). The MCWDTx_WDT0/WDT1 counters perform the following actions:
■ Assert interrupt (WDT_INTx) on match
■ Assert a device reset on match
■ Assert an interrupt on match and a device reset on the third unhandled interrupt
In addition to generating reset and interrupt, the match event can be configured to clear the corresponding counter. This is
done by setting the WDT_CLEARx bit of the MCWDTx_CONFIG register. MCWDTx_WDT0/WDT1 counter operation is
shown in Figure 24-4.
Figure 24-4. MCWDTx_WDT0/WDT1 Operation
Counts value
MCWDTx_WDT0/WDT1 operation with WDT_CLEARx bit = 0

0xFFFF

MCWDTx_WDT0/
WDT1 Match value

MCWDTx_WDT0/WDT1 MCWDTx_WDT0/WDT1 MCWDTx_WDT0/WDT1 Time

interrupt 1 interrupt 2 interrupt 3

MCWDTx_WDT0/WDT1 MCWDTx_WDT0/WDT1
counters overflow counters overflow

Counts value
MCWDTx_WDT0/WDT1 operation with WDT_CLEARx bit = 1

0xFFFF

MCWDTx_WDT0/
WDT1 Match value

Time

MCWDTx_WDT0/WDT1
interrupt and WDT0
reset

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 288
 Watchdog Timer

Table 24-2. MCWDTx_WDT0 and MCWDTx_WDT1 Configuration Options

Register [Bit_Pos] Bit_Name Description
WDT action on a match event (WDT_CTRx == WDT_MATCHx)
0: Do nothing
MCWDTx_CONFIG[1:0] WDT_MODE0
1: Assert interrupt (WDT_INTx)
MCWDTx_CONFIG[9:8] WDT_MODE1
2: Assert device reset
3: Assert interrupt on match and a device reset on the third unhandled interrupt
Clear the MCWDTx_WDT0/WDT1 counter on match. In other words, (WDT_-
MCWDTx_CONFIG[2] WDT_CLEAR0 MATCHx + 1) acts similar to a period for the MCWDTx_WDT0/WDT1 counter.
MCWDTx_CONFIG[10] WDT_CLEAR1 0: Free-running counter
1: Clear WDT_CTRx bits on match
MCWDTx_CNTLOW[15:0] WDT_CTR0 Current counter values. Bits[15:0] contain the current value of the MCWDTx_WDT0
MCWDTx_CNTLOW[16:31] WDT_CTR1 counter and bits[31:16] contain the current value of MCWDTx_WDT1 counter.
Match values
MCWDTx_MATCH[15:0] WDT_MATCH0 Changing WDT_MATCHx requires 1.5 LFCLK cycles to come into effect. After
MCWDTx_MATCH[16:31] WDT_MATCH1 changing WDT_MATCHx, do not enter the Deep Sleep mode for at least one LFCLK
cycle to ensure the WDT updates to the new setting.

24.4.1.2 MCWDTx_WDT2 Counter Operation

The MCWDTx_WDT2 is a 32-bit free-running counter, which can be configured to generate an interrupt. The
MCWDTx_CNTHIGH register holds the current value of the MCWDTx_WDT2 counter. MCWDTx_WDT2 does not support a
match feature. However, it can be configured to generate an interrupt when one of the counter bits toggle. The WDT_BITS2
bits [28:24] of the MCWDTx_CONFIG register selects the bit on which the MCWDTx_WDT2 interrupt is asserted.
WDT_MODE2 bit [16] of the MCWDTx_CONFIG register decides whether to assert an interrupt on bit toggle or not.
Figure 24-5 shows the MCWDTx_WDT2 counter operation.
Figure 24-5. MCWDTx_WDT2 Operation
MCWDTx_WDT2 operation
Counts value

0xFFFFFFFF

0x0000 0010
0x0000 000F
0x0000 000E
0x0000 000D
0x0000 000C
0x0000 000B
0x0000 000A
0x0000 0009
0x0000 0008
0x0000 0007
0x0000 0006
0x0000 0005
0x0000 0004
0x0000 0003
0x0000 0002
0x0000 0001
0x0000 0000

Time

MCWDTx_WDT2 Interrupt
WDT_BITS2 = 1 MCWDTx_WDT2
MCWDTx_WDT2 Interrupt counter period
WDT_BITS2 = 2
MCWDTx_WDT2 Interrupt
WDT_BITS2 = 3

MCWDTx_WDT2 Interrupt
WDT_BITS2 = 4

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 Watchdog Timer

Table 24-3. MCWDTx_WDT2 Configuration Options

Register [Bit_Pos] Bit_Name Description
MCWDTx_WDT2 mode
0: Free-running counter
MCWDTx_CONFIG[16] WDT_MODE2 1: Free-running counter with interrupt (WDT_INTx) request generation. The interrupts are
generated when the bit position specified in WDT_BITS2 toggles in the counter value held
by MCWDTx_CNTHIGH register.
Bit to monitor for MCWDTx_WDT2 interrupt assertion
0: Asserts when bit [0] of MCWDTx_CNTHIGH register toggles (interrupt every tick)
MCWDTx_CONFIG[28:24] WDT_BITS2
……
31: Asserts when bit [31] of MCWDTx_CNTHIGH register toggles (interrupt every 231 ticks)
MCWDTx_CNTHIGH[31:0] WDT_CTR2 Current counter value of MCWDTx_WDT2

24.4.2 Enabling and Disabling WDT

The MCWDT counters are enabled by setting the WDT_ENABLEx bit in the MCWDTx_CTL register and are disabled by
clearing it. Enabling or disabling a MCWDT requires 1.5 LFCLK cycles to come into effect. Therefore, the WDT_ENABLEx bit
value must not be changed more than once in that period and the WDT_ENABLEDx bit of the MCWDTx_CTL register can be
used to monitor enabled/disabled state of the counter.
The WDT_RESETx bit of the MCWDTx_CTL register clears the corresponding MCWDTx counter when set in firmware. The
hardware clears the bit after the counter resets. This option is useful when the MCWDTx_WDT0 or MCWDTx_WDT1 is
configured to generate a device reset on a match event. In such cases, the device resets when the counter reaches the
match value. Thus, setting the WDT_RESET0 or WDT_RESET1 bit resets MCWDTx_WDT0 or MCWDTx_WDT1
respectively, preventing device reset.
After the MCWDT is enabled, do not write to the MCWDT configuration (MCWDTx_CONFIG) and control (MCWDTx_CTL)
registers. Accidental corruption of these registers can be prevented by setting the WDT_LOCK bits [31:30] of the
MCWDTx_CTL register. If the application requires updating the match value (WDT_MATCH) when the MCWDT is running,
the WDT_LOCK bits must be cleared. The WDT_LOCK bits require two different writes to clear both the bits. Writing a ‘1’ to
the bits clears bit 0. Writing a ‘2’ clears bit 1. Writing a ‘3’ sets both the bits and writing ‘0’ does not have any effect. Note that
the WDT_LOCK bits protects only MCWDTx_CTL (except the WDT_LOCK bits), MCWDTx_CONFIG, and MCWDTx_MATCH
registers. The LFCLK select registers are protected by the free-running WDT lock bits.

Table 24-4. Watchdog Configuration Options

Register [Bit_Pos] Bit_Name Description
MCWDTx_CTL[0] WDT_ENABLE0 Enable MCWDT counter x
MCWDTx_CTL[8] WDT_ENABLE1 0: Counter is disabled
MCWDTx_CTL[16] WDT_ENABLE2 1: Counter is enabled
MCWDTx_CTL[1] WDT_ENABLED0
Indicates the actual enabled/disabled state of counter x. This bit should be monitored after
MCWDTx_CTL[9] WDT_ENABLED1
changing the WDT_ENABLEx bit, to receive an acknowledgment of the change
MCWDTx_CTL[17] WDT_ENABLED2
MCWDTx_CTL[3] WDT_RESET0 Reset MCWDT counter x to 0. Hardware clears the bit when the reset is complete
MCWDTx_CTL[11] WDT_RESET1 0: Software - No action
MCWDTx_CTL[19] WDT_RESET2 1: Software - Resets the counter
Locks or unlocks write access to the MCWDTx_CTL (except the WDT_LOCK bits), MCWDTx-
_CONFIG, and MCWDTx_MATCH registers. When the bits are set, the lock is enabled.
0: No effect
MCWDTx_CTL[31:30] WDT_LOCK
1: Clears bit 0
2: Clears bit 1
3: Sets both bit 0 and 1 (lock enabled)

Note: When the watchdog counters are configured to generate an interrupt every LFCLK cycle, make sure you read the
MCWDTx_INTR register after clearing the watchdog interrupt (setting the WDT_INTx bit in the MCWDTx_INTR register).
Failure to do this may result in missing the next interrupt. Hence, the interrupt period becomes LFCLK/2.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 290
 Watchdog Timer

24.4.3 Watchdog Cascade Options

The cascade configuration shown in Figure 24-3 provides an option to increase the MCWDT counter resolution. The
WDT_CASCADE0_1 bit [3] of the MCWDTx_CONFIG register cascades MCWDTx_WDT0 and MCWDTx_WDT1 and the
WDT_CASCADE1_2 bit [11] of the MCWDTx_CONFIG register cascades MCWDTx_WDT1 and MCWDTx_WDT2. Note that
cascading two 16-bit counters does not provide a 32-bit counter; instead, you get a 16-bit period counter with a 16-bit
prescaler. For example, when cascading MCWDTx_WDT0 and MCWDTx_WDT1, MCWDTx_WDT0 acts as a prescaler for
MCWDTx_WDT1 and the prescaler value is defined by the WDT_MATCH0 bits [15:0] in the MCWDTx_MATCH register. The
MCWDTx_WDT1 has a period defined by WDT_MATCH1 bits [31:16] in the MCWDTx_MATCH register. The same logic
applies to MCWDTx_WDT1 and MCWDTx_WDT2 cascading.
Table 24-5. Watchdog Cascade Options
Register [Bit_Pos] Bit_Name Description
Cascade MCWDTx_WDT0 and MCWDTx_WDT1
MCWDTx_CONFIG[3] WDT_CASCADE0_1 0: MCWDTx_WDT0 and MCWDTx_WDT1 are independent counters
1: MCWDTx_WDT1 increments two cycles after WDT_CTR0 == WDT_MATCH0
Cascade MCWDTx_WDT1 and MCWDTx_WDT2
MCWDTx_CONFIG[11] WDT_CASCADE1_2 0: MCWDTx_WDT1 and MCWDTx_WDT2 are independent counters
1: MCWDTx_WDT2 increments two cycles after WDT_CTR1 == WDT_MATCH1

When using cascade (WDT_CASCADE0_1 or WDT_CASCADE1_2 set), resetting the counters when the prescaler or lower
counter is at its match value with the counter configured to clear on match, results in the upper counter incrementing to 1
instead of remaining at 0. This behavior can be corrected by issuing a second reset to the upper counter after approximately
100 µs from the first reset. Note that the second reset is required only when the first reset is issued while the prescaler
counter value is at its match value. Figure 24-6 illustrates the behavior when MCWDTx_WDT0 and MCWDTx_WDT1 are
cascaded along with the second reset timing.
Figure 24-6. MCWDT Reset Behavior in Cascaded Mode

LFCLK

WDT_RESET0 First reset Second reset to

issued to correct the
both behavior
counters

WDT_RESET1
~100 µs

0x001F 0x0020 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005

WDT_CTR0
WDT_CTRx ==
WDT_MATCHx

0x0000 0x0001 0x0000

WDT_CTR1

Counter Counter Upper counter

reset increment reset (second)

Other settings:
WDT_CASCADE0_1 = 1
WDT_CLEAR0 = 1
WDT_MATCH0 = 0x0020

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 Watchdog Timer

In addition, the counters exhibit non-monotonicity in the 6. Lock the MCWDTx configuration by setting the
following cascaded conditions: WDT_LOCK bits of the MCWDTx_CTL register.
■ If WDT_CASCADE0_1 is set, then WDT_CTR1 does not 7. In the firmware, feed (reset) the watchdog as explained
increment the cycle after WDT_CTR0 = WDT_MATCH0. in step 4.
■ If WDT_CASCADE1_2 is set, then WDT_CTR2 does not Do not reset watchdog in the WDT ISR. It is also not
increment the cycle after WDT_CTR1 = WDT_MATCH1. recommended to use the same watchdog counter to
■ If both WDT_CASCADE0_1 and WDT_CASCADE1_2 generate a system reset and interrupt. For example, if
are set, then WDT_CTR2 does not increment the cycle MCWDTx_WDT0 is used to generate system reset against
after WDT_CTR1 = WDT_MATCH1 and WDT_CTR1 crashes, then MCWDTx_WDT1 or MCWDTx_WDT2 should
does not increment the cycle after WDT_CTR0 = be used for periodic interrupt generation.
WDT_MATCH0.
When cascading is enabled, always read the WDT_CTR1 or 24.4.5 MCWDT Interrupt
WDT_CTR2 counter value only when the prescaler counter When configured to generate an interrupt, the WDT_INTx
(WDT_CTR0 or WDT_CTR1) value is not 0. This makes bits of the MCWDTx_INTR register provide the status of any
sure the upper counter is incremented after a match event in pending watchdog interrupts. The firmware must clear the
the prescaler counter. interrupt by setting the WDT_INTx. The WDT_INTx bits of
the MCWDTx_INTR_MASK register mask the
24.4.4 MCDWT Reset corresponding WDTx interrupt of the MCWDTx block to the
CPU.
MCWDTx_WDT0 and MCWDTx_WDT1 can be configured
to generate a device reset similar to the free-running WDT Follow these steps to use WDT as a periodic interrupt
reset. Note that when the debug probe is connected, the generator:
device reset is blocked but an interrupt is generated if 1. Write the desired match value to the WDT_MATCH
configured. Follow these steps to use the MCWDTx_WDT0 register for MCWDTx_WDT0/WDT1 or the WDT_BITS2
or MCWDTx_WDT1 counter of a MCWDTx block to value to the MCWDTx_CONFIG register for
generate a system reset: MCWDTx_WDT2. Note: The legal value for the
1. Configure the MCWDT to generate a reset using the WDT_MATCH field is 1 to 65535.
WDT_MODEx bits in MCWDTx_CONFIG. Configure the 2. Configure the WDTx to generate an interrupt using the
WDT_MODE0 or WDT_MODE1 bits in WDT_MODEx bits in MCWDTx_CONFIG. Configure the
MCWDTx_CONFIG to ‘2’ (reset on match) or ‘3’ WDT_MODE0 or WDT_MODE1 bits in
(interrupt on match and reset on the third unhandled MCWDTx_CONFIG for MCWDTx_WDT0 or
interrupt). MCWDTx_WDT1 to ‘1’ (interrupt on match) or ‘3’
2. Optionally, set the WDT_CLEAR0 or WDT_CLEAR1 bit (interrupt on match and reset on third unhandled
in the MCWDTx_CONFIG register for MCWDTx_WDT0 interrupt). For MCWDTx_WDT2, set the WDT_MODE2
or MCWDTx_WDT1 to reset the corresponding bit in the MCWDTx_CONFIG register.
watchdog counter to ‘0’ on a match event. Otherwise, 3. Set the WDT_INT bit in MCWDTx_INTR to clear any
the counters are free running. See Table 24-2 on pending interrupt.
page 289 for details.
4. Set the WDT_CLEAR0 or WDT_CLEAR1 bit in the
3. Calculate the watchdog reset period such that firmware MCWDTx_CONFIG register for MCWDTx_WDT0 or
is able to reset the watchdog at least once during the MCWDTx_WDT1 to reset the corresponding watchdog
period, even along the longest firmware delay path. For counter to ‘0’ on a match event.
WDT_MODEx == 2, match value is same as the
5. Mask the WDTx interrupt to the CPU by setting the
watchdog period. For WDT_MODEx == 3, match value
WDT_INTx bit in the MCWDTx_INTR_MASK register
is one-third of the watchdog period. Write the calculated
match value to the WDT_MATCH register for 6. Enable WDTx by setting the WDT_ENABLEx bit in the
MCWDTx_WDT0 or MCWDTx_WDT1. Optionally, MCWDTx_CTL register. Wait until the WDT_ENABLEDx
enable cascading to increase the interval. Note: The bit is set.
legal value for the WDT_MATCH field is 1 to 65535. 7. Enable MCWDTx interrupt to the CPU by configuring the
4. For WDT_MODEx == 2, set the WDT_RESETx bit in the appropriate ISER register. Refer to the
MCWDTx_CONFIG register to reset the WDTx counter Interrupts chapter on page 56.
to 0. For WDT_MODEx == 3, set the WDT_INTx bit in 8. In the ISR, clear the WDTx interrupt by setting the
MCWDTx_INTR to clear any pending interrupts. WDT_INTx bit in the MCWDTx_INTR register.
5. Enable WDTx by setting the WDT_ENABLEx bit in the Note that interrupts from all three WDTx counters of the
MCWDTx_CTL register. Wait until the WDT_ENABLEDx MCWDT block are mapped as a single interrupt to the CPU.
bit is set. In the interrupt service routine, the WDT_INTx bits of the

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 292
 Watchdog Timer

MCWDTx_INTR register can be read to identify the interrupt 24.5 Reset Cause Detection
source. However, each MCWDT block has its own interrupt
to the CPU. For details on interrupts, see the The RESET_WDT bit [0] in the RES_CAUSE register
Interrupts chapter on page 56. indicates the reset generated by the free-running WDT. The
RESET_MCWDTx bit in the RES_CAUSE register indicates
The MCWDT block can send interrupt requests to the CPU
the reset generated by the MCWDTx block. These bits
in Active power mode and to the WIC in Sleep and Deep
remain set until cleared or until a power-on reset (POR),
Sleep power modes. It works similar to the free-running
brownout reset (BOD), or external reset (XRES) occurs. All
WDT.
other resets leave this bit unaltered.
For more details, see the Reset System chapter on
page 257.

24.6 Register List

Table 24-6. WDT Registers
Name Description
WDT_CTL Watchdog Counter Control Register
WDT_CNT Watchdog Counter Count Register
WDT_MATCH Watchdog Counter Match Register
MCWDTx_MCWDT_CNTLOW Multi-counter WDT Sub-counters 0/1
MCWDTx_MCWDT_CNTHIGH Multi-counter WDT Sub-counter 2
MCWDTx_MCWDT_MATCH Multi-counter WDT Counter Match Register for counters 0 and 1
MCWDTx_MCWDT_CONFIG Multi-counter WDT Counter Configuration, including bit toggle interrupt generation for counter 2
MCWDTx_MCWDT_CTL Multi-counter WDT Counter Control
MCWDTx_MCWDT_INTR Multi-counter WDT Counter Interrupt Register
MCWDTx_MCWDT_INTR_SET Multi-counter WDT Counter Interrupt Set Register
MCWDTx_MCWDT_INTR_MASK Multi-counter WDT Counter Interrupt Mask Register
MCWDTx_MCWDT_INTR_MASKED Multi-counter WDT Counter Interrupt Masked Register
CLK_SELECT Clock Selection Register
CLK_ILO_CONFIG ILO Configuration
SRSS_INTR SRSS Interrupt Register
SRSS_INTR_SET SRSS Interrupt Set Register
SRSS_INTR_MASK SRSS Interrupt Mask Register
SRSS_INTR_MASKED SRSS Interrupt Masked Register
RES_CAUSE Reset Cause Observation Register

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 293
 25. Trigger Multiplexer Block

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

Every peripheral in the PSoC 6 MCU is interconnected using trigger signals. Trigger signals are means by which peripherals
denote an occurrence of an event or a state. These triggers are used as means to affect or initiate some action in other
peripherals. The trigger multiplexer block helps to route triggers from a source peripheral block to a destination.

25.1 Features
■ Ability to connect any trigger signal from one peripheral to another
■ Supports a software trigger, which can trigger any signal in the block
■ Supports multiplexing of triggers between peripherals
■ One-to-one trigger paths for dedicated triggers that are more commonly routed
■ Ability to configure a trigger multiplexer with trigger manipulation features in hardware such as inversion and edge/level
detection
■ Ability to block triggers in debug mode

25.2 Architecture
The trigger signals in the PSoC 6 MCU are digital signals generated by peripheral blocks to denote a state such as FIFO
level, or an event such as the completion of an action. These trigger signals typically serve as initiator of other actions in other
peripheral blocks. An example is an ADC peripheral block sampling three channels. After the conversion is complete, a
trigger signal will be generated, which in turn triggers a DMA channel that transfers the ADC data to a memory buffer. This
example is shown in Figure 25-1.
Figure 25-1. Trigger Signal Example
Ch1
DMA
Ch2 ADC
Ch3 EoC
Trigger signal

A PSoC 6 MCU has multiple peripheral bocks; each of these blocks can be connected to other blocks through trigger signals,
based on the system implementation. To support this, the PSoC 6 MCU has hardware, which is a series of multiplexers used
to route the trigger signals from potential sources to destinations. This hardware is called the trigger multiplexer block. The
trigger multiplexer can connect to any trigger signal emanating out of any peripheral block in the PSoC 6 MCU and route it to
any other peripheral to initiate or affect an operation at the destination peripheral block.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 294
 Trigger Multiplexer Block

25.2.1 Trigger Multiplexer Group

The trigger multiplexer block is implemented using several trigger multiplexers. A trigger multiplexer selects a signal from a
set of trigger output signals from different peripheral blocks to route it to a specific trigger input of another peripheral block.
The multiplexers are grouped into trigger groups. All the trigger multiplexers in a trigger group have similar input options and
are designed to feed similar destination signals. Hence the trigger group can be considered as a block that multiplexes
multiple inputs to multiple outputs. This concept is illustrated in Figure 25-2. Both the trigger multiplexers and the one-to-one
triggers offer trigger manipulation, which includes inversion or specifies the output signal as edge or level triggered. For edge
triggering, the trigger is synchronized to the consumer block’s (the peripheral block that is receiving the trigger) clock and a
two-cycle pulse is generated on this clock.
Figure 25-2. Trigger Multiplexer Groups
In_1

Out_0

In_(N-1)

In [0:N-1] Out [0:M-1]

Out_1

Trigger multiplexer group takes N

inputs and routes to M outputs

Out_(M-1)

An equivalent implementation of
a trigger multiplexer group with N
inputs and M outputs

25.2.2 One-to-one Trigger

In addition to trigger multiplexers, there are dedicated trigger paths called one-to-one triggers. These trigger paths/routes are
between fixed source and destination peripherals and cannot be multiplexed. These paths can be enabled or disabled. A
group of registers in the format PERI_TR_1TO1_GR[X]_TR_CTL[Y], with X being the trigger group and Y being the output
trigger number from the one-to-one trigger, can be used to enable or disable the triggers path.

25.2.3 Trigger Multiplexer Block

The trigger multiplexer block has two types of trigger routings: trigger multiplexers that are capable of selecting from multiple
trigger sources to a specific trigger destination and one-to-one triggers that are predetermined fixed trigger paths that can be
enabled or disabled. See Table 25-2 for more information on each trigger group and its description.
Note: The triggers output into different peripherals, which may have more routing than is shown on the trigger routing
diagram. For more information on this routing, go to the trigger destination peripheral block.
Figure 25-3 shows the trigger multiplexer architecture.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 295
 Trigger Multiplexer Block

Figure 25-3. Trigger Multiplexer Block Architecture

SW Input Trigger Mux Group 0
Cpuss.zero[0] 1 [0]
Trigger 1-to-1 Group 0
DW0 Tr_out[0:7] 8 [1:8]

DW1 Tr_out[0:7] 8 [9:16]

12[17:28] 12 12
*TCPWM0(32-bit) 8 DW0 Tr_in[0:7] SCB DW0 tr_in[16:27]
Tr_overflow[0:3] 36[29:64] tr_tx_req[0:5]
Tr_compare_match[0:3] 4 [65:68] tr_rx_req[0:5]
Tr_underflow[0:3]
14 [69:82]
*TCPWM1(16-bit) 2 [83:84]
Tr_overflow[0:11] Trigger 1-to-1 Group 1
Tr_compare_match[0:11] 2 [85:86]
Tr_underflow[0:11]
Trigger Group 1
SCB 14 14 DW1 tr_in[8:21]
1 [0]
tr_tx_req[6:12]
*TCPWM0(32-bit) 8 [1:8]
tr_rx_req[6:12]
Tr_overflow[4:7] 8 [9:16]
Tr_compare_match[4:7]
Tr_underflow[4:7] 12[17:28]
36 [29:64] 8 DW1 Tr_in[0:7] Trigger 1-to-1 Group 2
*TCPWM1
Tr_overflow[12:23] 4 [65:68]
Tr_compare_match[12:23] 1 [69]
Tr_underflow[12:23] Trigger Group 6
14 [70:83] SAR tr_out 1 1 DW0 tr_in[28]
LPCOMP DCI [0:1] 2 [84:85]
1 [0]
24 [1:24] 4
DMAC tr_in[0:3]
2 [25:26]
HSIOM Tr_out[0:13] Trigger Group 2
1 [0] Trigger 1-to-1 Group 3
HSIOM Tr_out[14:27] 8 [1:8]
24[9:32]
TCPWM1(16-bit) 24 [33:56] SMIF Tr_tx/rx_req 2 2 DW1 tr_in[22:23]
Tr_overflow[0:7] 4 [57:60]
Tr_compare_match[0:7]
Tr_underflow[0:7] 39 [61:99]
2 [100:101]
SMIF Tr_tx/rx_req
8 [102:109] Trigger 1-to-1 Group 4
USB Dma_req[0:7] 14
3 [110:112]
*TCPWM0(32-bit)
tr_in[0:13]
2 [113:114]

PASS tr_sar_out 1 [115] 5 5

AUDIOSS DW1 tr_in[24:28]
CSD dsi_sense_out 1 [116] Tr_i2s_tx_req[0]
Tr_i2s_rx_req[0]
CSD tr_adc_done[0] 14 [117:130]
Tr_pdm_rx_req[0]
2 [131:132] Trigger Group 7 Tr_i2s_tx_req[1]
TCPWM0(32-bit) Tr_i2s_rx_req[1]
2 [133:134] Trigger 1-to-1 Group 5
Tr_overflow[0:7]
1 [0]
Tr_compare_match[0:7] 1
2 [1:2] PERI tr_dbg_freeze
Tr_underflow[0:7]
Trigger Group 3
1 [0] 8 8 DW0 tr_in[8:15]
USB dma_req[0:7]
DMAC Tr_out[0:3] 8 [1:8]
24 [9:32]
SCB
24 [33:56]
Tr_i2c_scl_filtered[0:12]
Tr_tx_req[0:12] 4 [57:60]
Tr_rx_req[0:12] 39 [61:99] Trigger 1-to-1 Group 6
2 [100:101]
8 [102:109] 14
3 [110:112] *TCPWM1(16-bit)
AUDIOSS0 tr_in[0:13] 8 8
2 [113:114] DW0 tr_out[8:15] USB dma_burstend[0:7]
Tr_i2s_tx_req
Tr_i2s_rx_req 1 [115]
Tr_pdm_rx_req 1 [116]
14 [117:130]
2 [131:132]
2 [133:134]
AUDIOSS1
Tr_i2s_tx_req
Tr_i2s_rx_req
Trigger Group 4
1 [0]
DW0 Tr_out[0:28] 29 [1:29]
DW1 Tr_out[0:28] 29 [30:58]
24 [59:82]
72 [83:154]
4 [155:158]
39 [159:197]
2 [198:199]
8 [200:207]
2
3 [208:210] HSOIM tr_io_output[0:1]
2 [211:212]
1 [213] Trigger Group 8
1 [0]
CSD dsi_sample_out 1 [214]
1 [215] 24[1:24]
72[25:96]
1 [216] 1
14[97:110] CSD dsi_start
2 [217:218]
2 [219:220] 14[111:124]
2 [221:222] 2 [125:126]

Trigger Group 9
Trigger Group 5 1 [0]
1 [0] 24 [1:24]
29 [1:29] 72 [25:96] 1
29 [30:58] PASS tr_sar_in
14 [97:110]
24 [59:82] 14 [111:124]
72 [83:154] 2 [125:126]
*TCPWM1(16-bit)
4 [155:158]
Tr_overflow[0:23]
Tr_compare_match[0:23] 39 [159:197]
Tr_underflow[0:23] 2 [198:199]
8 [200:207]
3 [208:210] 2
CTI tr_in[0:1]
2 [211:212] 1 PROFILE tr_start
1 [213] 1 PROFILE tr_stop
1 [214]
1 [215]
1 [216]
14 [217:230]
14 [231:244]
FAULT Tr_out[0:1] 2 [245:246]
CTI Tr_out[0:1] 2 [247:248]
2 [249:250]

Note: * indicates that Figure 25-4 shows details about the TCPWM and SCB inputs.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 296
 Trigger Multiplexer Block

Figure 25-4. TCPWM and Multiplexer SCB Input Layout

Trigger Mux Group 0

[17]
Tr_overflow[0]
[18]
Tr_compare_match[0]
[19]
TCPWM0(32-bit) Tr_underflow[0]
Tr_overflow[0:3] 12[17:28] ...
...
Tr_compare_match[0:3] ... [26]
Tr_underflow[0:3] Tr_overflow[3]
[27]
Tr_compare_match[3]
[28]
Tr_underflow[3]

Trigger Mux Group 2

[61]
Tr_i2c_scl_filtered[0]
[62]
Tr_tx_req[0]
[63]
SCB Tr_rx_req[0]
Tr_i2c_scl_filtered[0:12] 39 [61:99] ...
...
Tr_tx_req[0:12] ... [97]
Tr_rx_req[0:12] Tr_i2c_scl_filtered[12]
[98]
Tr_tx_req[12]
[99]
Tr_tx_req[12]

Note: The format in these diagrams apply to all TCPWM and SCB connections in the trigger groups that have these
connections. The trigger input line number will change between trigger groups and will not always start at 17 and 61 as shown
in the TCPWM and SCB diagrams.

25.2.4 Software Triggers

All input and output signals to a trigger multiplexer can be triggered from software. This is accomplished by writing into the
PERI_TR_CMD register. This register allows you to trigger the corresponding signal for a number of peripheral clock cycles.
The PERI_TR_CMD[GROUP_SEL] bitfield selects the trigger group of the signal being activated. The
PERI_TR_CMD[OUT_SEL] bitfield determines whether the trigger signal is in output or input of the multiplexer.
PERI_TR_CMD[TR_SEL] selects the specific line in the trigger group.
The PERI_TR_CMD[COUNT] bitfield sets up the number of peripheral clocks the trigger will be activated.
The PERI_TR_CMD[ACTIVATE] bitfield is set to ‘1’ to activate the trigger line specified. Hardware resets this bit after the
trigger is deactivated after the number of cycles set by the PERI_TR_CMD[COUNT].

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 Trigger Multiplexer Block

25.3 Register List

Table 25-1. Register List
Register Name Description
Trigger command register. The control enables software activation of a specific input trigger or
PERI_TR_CMD
output trigger of the trigger multiplexer structure.
This register specifies the input trigger for a specific output trigger in a trigger group. It can
also invert the signal and specify if the output signal should be treated as a level-sensitive or
PERI_TR_GR[X]_TR_OUT_CTL[Y] edge-sensitive trigger. Every trigger multiplexer has a group of registers, the number of
registers being equal to the output bus size from the multiplexer. In the register format, X is the
trigger group and Y is the output trigger line number from the multiplexer.
This register specifies the input trigger for a specific output trigger in a one-to-one trigger
group. It also includes trigger manipulation that can invert the signal and specify if the output
signal should be treated as a level-sensitive or edge-sensitive trigger. Every one-to-one trigger
PERI_TR_1TO1_GR[X]_TR_OUT_CTL[Y]
multiplexer has a group of registers, the number of registers being equal to the output bus size
from the multiplexer. The registers are formated with X as the trigger group and Y as the
output trigger line number from the multiplexer.

Table 25-2. Trigger Group

Trigger Group Number Description
0 Routes all input trigger signals to DMA0
1 Routes all input trigger signals to DMA1
2 Routes all input trigger signals to TCPWM0(32-bit)
3 Routes all input trigger signals to TCPWM1(16-bit)
4 Routes all input trigger signals to HSIOM
5 Routes all input trigger signals to CPUSS CTI and the Profiler
6 Routes all input trigger signals to DMAC
7 Routes all input trigger signals to trigger freeze operation
8 Routes all input trigger signals to CSD ADC start
9 Routes all input trigger signals to PASS ADC start
Trigger 1-to-1 Group
0 Connects SCB triggers to DMA0
1 Connects SCB triggers to DMA1
2 Connects SAR triggers to DMA0
3 Connects SMIF triggers to DMA1
4 Connects AUDIOSS triggers to DMA1
5 Connects USB triggers to DMA0
6 Connects DMA0 to USB

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 298
 26. Profiler

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU Profiler provides counters that can measure duration or number of events of a particular peripheral.
Functions such as DMA transfers or buffered serial communications can happen asynchronously, and are not directly tied to
the CPU or code execution. The profiler provides additional insight into the device so you can identify an asynchronous
activity that could not be monitored previously.
The profiler manages a set of counters. You configure an available counter to monitor a particular source. Depending on the
nature of the source, you count either duration (reference clock cycles) or the number of events.
The ability to monitor specific peripherals enables you to understand and optimize asynchronous hardware, including:
■ Identify the activity of a particular peripheral
■ Identify asynchronous activity

26.1 Features
The profiler has these features and capabilities:
■ A variety of sources you can monitor (see Table 26-1)
■ Support for eight counters, to monitor up to eight sources simultaneously
■ For each counter you specify:
❐ what source to monitor (can be changed dynamically if required)
❐ what to measure (duration or events)
❐ what reference clock to use for the count (only affects duration)
■ Provides ability to easily detect active peripherals that may be difficult to measure by external monitoring
■ Provides an absolute count of events or reference clock cycles for each monitored source

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 Profiler

26.2 Architecture
Figure 26-1. Profiler Block Diagram

The profiler supports up to 32 counters. The actual number of counters is hardware dependent. This device supports up to
eight counters.

26.2.1 Profiler Design

With the profiler you can monitor:
■ Peripherals that operate asynchronously to software
■ CPU activity
This includes flash access, DMA, and other processes. See Available Monitoring Sources on page 301.
You can measure total energy consumption directly using external hardware. The profiler can monitor internal hardware with
no external probe or measuring device.
The profiler counts either the amount of time that a source is active (duration) or the number of events that occur. The profiler
does not report the actual amount of energy consumed.
Your application may use a system resource or peripheral that is not among the profiler sources. A complete understanding of
your application’s energy consumption requires that you profile those parts of your code that use those other systems. For
example, you could determine the time the peripheral is in use, and then derive energy use based on power consumption
data from the data sheet, or external power monitoring.
All counters that are in use start and stop at the same time. The time between start and stop is called the profiling window, or
the profiling session. During the profiling session, each counter increments at its own rate based on the monitored signal and
(if measuring duration) the selected reference clock. See Start and Stop Profiling on page 303.
Before starting a profiling session, configure the counters you want to use. See Configure and Enable a Counter on page 303.
You can get interim results during a profiling session, or final results after you stop profiling. See Get the Results on page 304.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 300
 Profiler

26.2.2 Available Monitoring Sources

You specify which source a counter monitors. The available sources vary per device series. You can find constants in a
header file named <series>_config.h (part of the Peripheral Driver Library). For example, Table 26-1 lists the sources in
psoc63_config.h.

Table 26-1. Available Signals to Monitor

Value Symbol Count Description
0 PROFILE_ONE Duration Constant One
1 CPUSS_MONITOR_CM0 Events CM0+ active cycle count
2 CPUSS_MONITOR_CM4 Events CM4 active cycle count
3 CPUSS_MONITOR_FLASH Events Flash read count
4 CPUSS_MONITOR_DW0_AHB Events DW0 AHB transfer count (DMA transfer)
5 CPUSS_MONITOR_DW1_AHB Events DW1 AHB transfer count (DMA transfer)
6 CPUSS_MONITOR_CRYPTO Events Crypto memory access count
7 USB_MONITOR_AHB Events USB AHB transfer count
8 SCB0_MONITOR_AHB Events SCB 0 AHB transfer count
9 SCB1_MONITOR_AHB Events SCB 1 AHB transfer count
10 SCB2_MONITOR_AHB Events SCB 2 AHB transfer count
11 SCB3_MONITOR_AHB Events SCB 3 AHB transfer count
12 SCB4_MONITOR_AHB Events SCB 4 AHB transfer count
13 SCB5_MONITOR_AHB Events SCB 5 AHB transfer count
14 SCB6_MONITOR_AHB Events SCB 6 AHB transfer count
15 SCB7_MONITOR_AHB Events SCB 7 AHB transfer count
16 SCB8_MONITOR_AHB Events SCB 8 AHB transfer count
17–20 Reserved
21 SMIF_MONITOR_SMIF_SPI_SELECT0 Duration SPI select to memory 0 active
22 SMIF_MONITOR_SMIF_SPI_SELECT1 Duration SPI select to memory 1 active
23 SMIF_MONITOR_SMIF_SPI_SELECT2 Duration SPI select to memory 2 active
24 SMIF_MONITOR_SMIF_SPI_SELECT3 Duration SPI select to memory 3 active
25 SMIF_MONITOR_SMIF_SPI_SELECT_ANY Duration SPI select to any of the memories 0-3 active

26.2.3 Reference Clocks

Each monitored source has its own clock reference, called the sample clock. Table 26-2 lists the six choices for the sample
clock. You may use one of two CLK_PROFILE sources, or one of four CLK_REF sources.
The counter units of the profiler are clocked using either CLK_HF or CLK_PERI as CLK_PROFILE. You configure CLK_HF in
system resources and CLK_PERI in the CPU subsystem. See Clocking System chapter on page 242 for details on clocks. In
addition, there are four available reference clocks: CLK_TIMER, CLK_IMO, CLK_ECO, and CLK_LF. Any of the six clock
sources can be used as the sample clock.
If you measure events, the sample clock is selected automatically to be either CLK_HF or CLK_PERI depending on the
monitored source. The count represents the number of events that occurred during the profiling session. The profiler counts
the edges of the monitored signal, using either CLK_HF or CLK_PERI to detect edges.
If you measure duration, you specify the sample clock from one of the six choices listed in Table 26-2. When you measure
duration, while the monitored source is active, the counter increments at each cycle of the sample clock. The profiler
synchronizes reference clocks with CLK_PROFILE. As a result the four available reference clocks cannot exceed
CLK_PROFILE/2.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 301
 Profiler

To measure duration accurately, the sample clock should have a stable frequency throughout the profiling session. If your
application remains in active power states, you can use CLK_HF as the sample clock. CLK_HF gives you the greatest
resolution in your results.
The profiler can be enabled in CPU Active and Sleep modes. However, clock frequencies can change based on the power
state of the application. The source clock frequency should be stable throughout the profiling session to ensure reliable data.
High-frequency clocks are not available in System Deep Sleep and Hibernate power modes, so the profiler is disabled. The
configuration registers maintain state through Deep Sleep. Profiler data is lost (registers are not maintained) in Hibernate
mode. See the Device Power Modes chapter on page 225.

Table 26-2. Available Sample Clock Sources for the Profiler

Value Clock Source Symbol Clock Type
0 Timer CLK_TIMER CLK_REF
1 Internal main oscillator CLK_IMO CLK_REF
2 External crystal oscillator CLK_ECO CLK_REF
3 Low frequency clock CLK_LF CLK_REF
4 High-frequency clock CLK_HF CLK_PROFILE
5 Peripheral clock CLK_PERI CLK_PROFILE

26.3 Using the Profiler

This section describes the steps required to use the profiler effectively. To use the profiler, you add instrumentation code to
your application, to set or read values in particular registers. See the registers TRM for details.
At the highest level you perform these tasks:
■ Enable the profiling block
■ Configure and enable counters
■ Start and stop profiling
■ Handle counter overflow
■ Get the results
■ Exit gracefully
You can monitor as many sources as there are available counters. The actual number of available counters is hardware
dependent. The value is defined in the symbol PROFILE_PRFL_CNT_NR in the <series>_config.h file. For example, the
psoc63_config.h file defines this value as ‘8’.
Instead of manipulating registers directly, you can use the Peripheral Driver Library (PDL). The PDL provides a software API
to manage the profiler and an interrupt to handle counter overflow. The software driver maintains an array of data for each
counter, including the source you want to monitor, whether you are monitoring duration or events, the reference clock, and an
overflow count for each counter. It provides function calls to configure and enable a counter, start and stop a profiling session,
and calculate the results for each counter. The PDL API handles all register and bit access.
Refer to the PDL API Reference for more information. The PDL installer puts the documentation here:
<PDL directory>\doc\pdl_api_reference_manual.html

26.3.1 Enable or Disable the Profiler

Before performing any operations, enable the profiling block. See Table 26-3. This does not enable individual counters or start
a profiling session.

Table 26-3. Enabling the Profiler

Task Register Bitfield Value
Enable the profiler PROFILE_CTL ENABLED 0 = disabled; 1 = enabled

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 Profiler

26.3.2 Configure and Enable a Counter

Each counter has a PROFILE_CTL register that holds configuration information. For each counter you specify:
■ The source you want to monitor
■ What you want to measure (events or duration)
■ The reference clock for the counter (affects only duration)
You also enable each counter individually. Only the enabled counters will start when START_TR is set to one. See Table 26-4.

Table 26-4. Configuring and Enabling a Counter

Task Register Bitfield Value
Specify source PROFILE_CTL MON_SEL Table 26-1 on page 301
Specify events or duration PROFILE_CTL CNT_DURATION 0 = events; 1 = duration. See Table 26-1 on page 301
Specify the reference clock PROFILE_CTL REF_CLK_SEL Table 26-2 on page 302
Enable the counter PROFILE_CTL ENABLED 0 = disabled; 1 = enabled

The count value is a 32-bit register. If that is not a sufficiently large number for your purposes, you must also enable the
profiling interrupt for the counter. See Handle Counter Overflow on page 303.
When gathering data, you may want to know the actual number of clock cycles that occurred during the profiling session. To
get this number, configure a counter to use:
■ PROFILE_ONE as the monitored source
■ duration (not events)
■ a reference clock
The count for that counter is the actual number of reference clock cycles that occurred during the profiling session.

26.3.3 Start and Stop Profiling

After configuring and enabling the counters you want to use, you can start and stop a profiling session. You may wish to
ensure that all counters are set to zero before beginning the profiling session. The PROFILE_CMD register applies to all
counters, meaning that all enabled counters will be started at the same time. See Table 26-5.

Table 26-5. Starting or Stopping a Profiling Session

Task Register Bitfield Value
Clear all counters PROFILE_CMD CLEAR_ALL_CNT 1 = reset all counters to zero
Start profiling PROFILE_CMD START_TR 1 = start profiling
Stop profiling PROFILE_CMD STOP_TR 1 = stop profiling

By design, all counters that are in use start and stop simultaneously. During the profiling session, each counter increments at
its own rate based on the monitored signal and (if measuring duration) the reference clock.

26.3.4 Handle Counter Overflow

Each profiling counter is a 32-bit number. If this is not sufficient for your purposes, then you must handle counter overflow. To
do so you must:
■ Enable the profiling interrupt for the particular counter
■ Provide an interrupt handler
For example, your interrupt handler could maintain an overflow counter for each profiling counter. See the Interrupts chapter
on page 56 for details about interrupts.
Counter overflow involves the interaction of three registers, INTR, INTR_MASK, and INTR_MASKED. Each of these registers
has one bit per profiling counter.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 303
 Profiler

When an overflow occurs for a particular counter, hardware sets the corresponding bit in the INTR register. You typically do
not read this register.
To enable the profiling interrupt for a particular counter, set the corresponding bit in the INTR_MASK register.
When an interrupt occurs, your interrupt handler reads the bits in the INTR_MASKED register. This register reflects a bitwise
AND between the INTR register (an overflow interrupt has occurred for a particular counter) and the INTR_MASK register
(this counter has the interrupt enabled). When a bit is set in the INTR_MASKED register, the corresponding counter is
enabled and has experienced an overflow.
You can artificially trigger an overflow interrupt to test your code. The INTR_SET register also has one bit per counter. For
debug purposes, software can set the appropriate bit to activate a specific overflow interrupt. This enables debug of the
interrupt without waiting for hardware to cause the interrupt.

26.3.5 Get the Results

For each of your enabled counters, read the counter value in the CNT register for that counter. This is your absolute count. If
you are tracking counter overflow, then the absolute count is 0x1 0000 0000 * overflow count + counter value.
The common use case is to get results after you stop profiling. However, you can get a snapshot of the results without
stopping the profiler. In this case, however, the profiler is still counting and the results are changing as you gather the data.
After completing a profiling session, you may wish to repeat the same profile. Clear all counters to zero, and then start and
stop profiling. See Start and Stop Profiling on page 303. If you are handling counter overflow, set your overflow counters to
zero as well.
You can also reconfigure any or all counters to gather different data. See Configure and Enable a Counter on page 303.
Reconfigure the profiler, and start another profiling session.

26.3.6 Exit Gracefully

When finished, you should disable the profiler. To do this make sure that you:
■ Stop profiling (see Start and Stop Profiling on page 303)
■ Clear any profiling configuration (see Configure and Enable a Counter on page 303)
■ Disable the profiling interrupt if you have set it up (see Handle Counter Overflow on page 303)
■ Disable the profiler itself (see Enable or Disable the Profiler on page 302)

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 304
 Section D: Digital Subsystem

This section encompasses the following chapters:

■ Secure Digital Host Controller (SDHC) chapter on page 307
■ Serial Communications Block (SCB) chapter on page 318
■ Serial Memory Interface (SMIF) chapter on page 375
■ Timer, Counter, and PWM (TCPWM) chapter on page 392
■ Inter-IC Sound Bus chapter on page 429
■ PDM-PCM Converter chapter on page 441
■ Universal Serial Bus (USB) Device Mode chapter on page 450
■ Universal Serial Bus (USB) Host chapter on page 466
■ LCD Direct Drive chapter on page 483

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 305
 Digital Subsystem

Top Level Architecture

Figure D-1. Digital System Block Diagram

2x Smart I/O Ports

Peripheral clock (PCLK)

I/O Subsystem: Up to 102 GPIOs (including 6 OVT), 128-TQFP Package

Peripheral Interconnect (MMIO, PPU)
SCB
System Interconnect (Multi Layer AHB, IPC, MPU/SMPU)

Boundary Scan
Audio Subsystem

Color Key:
Power Modes and
Domains

System LP/ULP Mode

CPUs Active/Sleep

System
DeepSleep Mode

System
Hibernate Mode

Backup USB
Domain PHY

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 306
 27. Secure Digital Host Controller (SDHC)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The secure digital host controller (SDHC) in the PSoC 6 MCU allows interfacing with embedded multimedia card (eMMC)-
based memory devices, secure digital (SD) cards, and secure digital input output (SDIO) cards. The block supports all three
interfaces – SD, SDIO, and eMMC. The block can also work with devices providing SDIO interface, such as Cypress' Wi-Fi
products (for example, CYW4343W). Figure 27-1 illustrates a typical application using the SDHC block.
Figure 27-1. Typical SDHC Application
PSoC 6

SDHC[0] configured for

Cypress Wi-Fi Device
SDIO

27.1 Features
■ Complies with eMMC 5.1, SD 6.0, and SDIO 4.10 standards
■ Supports host controller interface (HCI) 4.2 shared by eMMC and SD
■ SD interface supports 1-bit and 4-bit bus interfaces, and the following speed modes. The specified data rate is for a 4-bit
bus.
❐ 3.3-V signal voltage: Default speed (12.5 MB/s at 25 MHz) and high speed (25 MB/s at 50 MHz)
❐ UHS-I modes using 1.8-V signal voltage: SDR12 (12.5 MB/s at 25 MHz), SDR25 (25 MB/s at 50 MHz), SDR40 (40
MB/s at 80 MHz), and DDR40 (40 MB/s at 40 MHz)
■ eMMC interface supports 1-bit and 4-bit bus interfaces, and the following speed modes. The specified data rate is for a 4-
bit bus.
❐ Legacy (13 MB/s at 26 MHz), high-speed SDR (26 MB/s at 52 MHz), and high-speed DDR (52 MB/s at 52 MHz)
■ Supports three DMA modes – SDMA, ADMA2, and ADMA3 – through a dedicated DMA engine
■ Provides 1KB SRAM for buffering up to two 512-byte blocks
■ Provides I/O interfaces for bus interface voltage selection (3.3 V/1.8 V) and for power enable/disable
■ Provides I/O interfaces for functions such as card detection, mechanical write protection, eMMC card reset, and LED
control

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 Secure Digital Host Controller (SDHC)

27.1.1 Features Not Supported

The SDHC block does not support the following features.
■ SD/SDIO operation in UHS-II mode
■ Command queuing engine (CQE)
■ eMMC boot operation in dual data rate mode
■ Read wait operation by DAT[2] signaling in an SDIO card
■ Suspend/resume operation in an SDIO card
■ Interrupt input pins for embedded SD systems
■ SPI protocol mode of operation

27.2 Block Diagram

Figure 27-2. SDHC Block Diagram

SDHC

To System
Interconnect
AHB Master DMA Engine
Interface (SDMA, ADMA2, ADMA3) IOSS
clk_card
card_cmd

card_dat_3to0[3:0]
To Peripheral To I/O
Interconnect Sub-System
AHB Slave Configuration eMMC/SD/SDIO
Interface Registers Interface

Interrupts io_volt_sel
to CPU card_detect_n
Sub-System card_mech_write_prot
card_if_pwr_en

SRAM Controller

CLK_HF[i]

CLK_SYS
1 KB Packet
CLK_SLOW
Buffer SRAM

The SDHC controller supports all three interfaces – SD, SDIO, and eMMC; it supports up to 4-bit bus width. The AHB master
interface helps to transfer data to and from the system memory and the AHB slave interface provides access to the
configuration registers. The register set comprises the standard SD host controller interface (HCI) registers as specified in the
SD Specifications Part A2 SD Host Controller Standard Specification. These registers are described in the registers TRM. The
DMA engine handles direct data transfer between the SDHC logic and system memory. It supports SDMA, ADMA2, and
ADMA3 modes based on the configuration.
The SDHC block complies with the following standards. Refer to the specifications documents for more information on the
protocol and operations.
■ SD Specifications Part 1 Physical Layer Specification Version 6.00
■ SD Specifications Part A2 SD Host Controller Standard Specification Version 4.20
■ SD Specifications Part E1 SDIO Specifications Version 4.10
■ Embedded Multi-Media Card (eMMC) Electrical Standard 5.1

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 Secure Digital Host Controller (SDHC)

27.3 Clocking
Table 27-1 lists the different clocks used in the SDHC block. While configuring the clock for SDHC make sure that clk_slow 
clk_sys  clk_card.

Table 27-1. Clocks in SDHC

Source SDHC Clock Function
Used for core SDHC functions including the packet buffer SRAM; it is sourced from the slow
Core SDHC Clock
clock (clk_slow); it must be  AHB slave clock.
CLK_SLOW
Used by the AHB master interface; it is sourced from the slow clock (clk_slow); it must be 
AHB Master Interface Clock
AHB slave clock.
Used by the AHB slave interface; it is clocked by the PERI group clock (clk_sys); it must be
 clk_card. The group clock is derived from the PERI clock (clk_peri) using a divider.
CLK_SYS AHB Slave Interface Clock Because this divider can remain at the default value of ‘1’ for most applications, clk_peri can
be considered as clk_sys for SDHC. See Clocking System chapter on page 242 for informa-
tion on clk_sys and clk_peri.
Used for sourcing the SD/eMMC interface clock (clk_card); it is derived from CLK_HF[i]; it
must be set to 100 MHz to be compatible with the Capabilities register. See 27.3.2 Base
Base Clock/Card Clock
CLK_HF[i] Clock (CLK_HF[i]) Configuration for details. See High-Frequency Root Clocks on page 251
to know which CLK_HF[i] drives an SDHC instance.
Timer Clock Used for command and data timeout functions; it is derived from CLK_HF[i].

27.3.1 Clock Gating sourced from CLK_HF[i] as explained in Table 27-1. SDCLK
frequency is equal to base clock frequency when the divider
All the clocks except the slave interface clock can be gated value is zero.
internally to enter standby mode (See Power Modes on
page 310). In standby mode, you can also stop the clocks SDCLK Frequency = Base Clock Frequency / (2 × 10-bit
externally if required. The slave clock cannot be gated divider value)
because it is used for wakeup logic (see Interrupts to CPU These fields are set automatically, based on the selected
on page 310) during the standby mode. Bus Speed mode, to a value specified in one of the preset
The card clock is gated by clearing the SD_CLK_EN bit and registers when HOST_CTRL2_R.PRESET_VAL_ENABLE
other clocks are gated by clearing the INTERNAL_CLK_EN is set. The preset registers are selected according to
bit of the CLK_CTRL_R register. See Clock Setup on Table 27-2.
page 316 for the sequence to be followed while modifying
this bit. 27.3.4 Timeout (TOUT) Configuration
An internal timer is used for command and data timeouts.
27.3.2 Base Clock (CLK_HF[i]) The timeout value is specified through the
Configuration TOUT_CTRL_R.TOUT_CNT register field. The timer clock
(TMCLK) frequency indicated by the read-only fields
The HCI register (Capabilities) has a read-only field
TOUT_CLK_FREQ and TOUT_CLK_UNIT of
(BASE_CLK_FREQ) to indicate the base clock frequency so
CAPABILITIES1_R register is 1 MHz. Timer clock is derived
that an SD HCI-compatible driver can easily configure the
by dividing the CLK_HF[i], which means that CLK_HF[i]
divider for the required bus speed. This value is set to 0x64
must be set to 100 MHz to be compatible with the
(100 MHz) and hence CLK_HF[i] must be set to 100 MHz. If
Capabilities register.
this compatibility is not required, CLK_HF[i] can be set to
any value. See 27.3.4 Timeout (TOUT) Configuration.

27.3.3 Card Clock (SDCLK) Configuration

The SDCLK or card clock frequency is set by configuring the
10-bit divider in the CLK_CTRL_R register and selecting the
10-bit divided clock mode by clearing the
CLK_GEN_SELECT bit of the same register. The default
value of this bit is zero. The UPPER_FREQ_SEL field holds
the upper two bits (9:8) and the FREQ_SEL field holds the
lower eight bits (7:0) of the divider. Base clock frequency is

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 Secure Digital Host Controller (SDHC)

27.4 Bus Speed Modes

The SDHC block can operate in either SD/SDIO mode or in eMMC mode. The SDHC block operates in eMMC mode when
the EMMC_CTRL_R.CARD_IS_EMMC bit is set; otherwise, it operates in SD/SDIO mode. The speed mode is configured
through HOST_CTRL1_R and HOST_CTRL2_R registers as per Table 27-2. The HOST_CTRL2_R.UHS2_IF_ENABLE bit
should remain at its default value of zero because the block does not support UHS-II mode. The card clock must be
configured according to the selected speed mode through the CLK_CTRL_R register. See 27.3.3 Card Clock (SDCLK)
Configuration for more information.

Table 27-2. Bus Speed Mode Configuration

HOST_CTRL1_R Field HOST_CTRL2_R Fields
Bus Speed Mode Selected Preset Register
HIGH_SPEED_EN SIGNALING_EN UHS_MODE_SEL
SD Default Speed (DS) 0 0 Don't care PRESET_DS_R
SD High Speed (HS) 1 0 Don't care PRESET_HS_R
SDR12/eMMC Legacy Don't care 1 000b PRESET_SDR12_R
SDR25/eMMC High Speed Don't care 1 001b PRESET_SDR25_R
SDR50 Don't care 1 010b PRESET_SDR50_R
DDR50/eMMC High Speed
Don't care 1 100b PRESET_DDR50_R
DDR

27.5 Power Modes insertion. See 27.5.1 Standby Mode for details. As card
insertion and removal is not applicable to an embedded
The block can operate during active and sleep system device, wakeup interrupt should not be used in this case.
power modes. It does not support deep sleep mode and However it can still be used for SDIO card interrupt.
cannot wake up from events such as card insertion and ■ General Interrupt Signal – Triggered on all other events,
removal when the system is in deep sleep. All the core in either normal conditions or error conditions.
registers except the packet buffer SRAM are retained when
the system enters deep sleep mode and the SRAM is A host driver must not enable the wakeup and general
switched off to save power. Retention is performed so that interrupt signals at the same time.
the block can resume operation immediately after wakeup To use only the wakeup interrupt signal, clear the
from deep sleep without requiring reconfiguration. Make NORMAL_INT_STAT_R and
sure that no AHB traffic (such as register read/write and NORMAL_INT_SIGNAL_EN_R registers, and then set the
DMA operation) is present, the SD/SDIO/eMMC bus enable bits of the required wakeup events in the
interface is idle, and no data packets are pending in the WUP_CTRL_R and NORMAL_INT_STAT_EN registers.
packet buffer SRAM when the system transitions into deep
sleep mode. To use only the general interrupt signal, clear the
WUP_CTRL_R and NORMAL_INT_STAT_R registers.
Then, set the required bits in
27.5.1 Standby Mode NORMAL_INT_SIGNAL_EN_R and
The block can be put into standby mode to save power NORMAL_INT_STAT_EN registers.
during the active and sleep system power modes by turning
These interrupts remain asserted until the CPU clears the
off the clocks. See Clock Gating on page 309 for details.
interrupt status through one of the status registers –
The block can detect wakeup interrupts (see Interrupts to
NORMAL_INT_STAT_R and ERROR_INT_STAT_R.
CPU on page 310) in standby mode.
The SDIO card interrupt status bit, CARD_INTERRUPT, is a
read-only bit. The host driver may clear the
27.6 Interrupts to CPU NORMAL_INT_STAT_EN_R.CARD_INTERRUPT_STAT_E
N bit before servicing the SDIO card interrupt and may set
The block provides two interrupt signals to CPUSS:
this bit again after all interrupt requests from the card are
■ Wakeup Interrupt Signal – Triggered on events such as cleared to prevent inadvertent interrupts.
card insertion, removal, and SDIO card interrupt. This
interrupt source cannot wake up the system from deep
sleep mode and is provided so that a host driver can
take appropriate action on those events. For example,
resuming operation from standby mode on card

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 Secure Digital Host Controller (SDHC)

Following is the list of registers used in interrupt configuration.

Table 27-3. Interrupt Control Registers

Register Description
Enables or disables different wakeup interrupts. Host driver must maintain voltage on the SD bus by set-
WUP_CTRL_R ting PWR_CTRL_R.SD_BUS_PWR_VDD1 bit for these interrupts to occur. These interrupts cannot
wakeup the device from deep sleep.
Reflects the status of wakeup interrupts and non-error general interrupts. It also has a bit to indicate
NORMAL_INT_STAT_R
whether any of the bits in ERROR_INT_STAT_R is set.
ERROR_INT_STAT_R Reflects the status of general interrupts that are triggered by error conditions.
NORMAL_INT_STAT_EN_R Provides mask bits for wakeup interrupts and non-error general interrupts.
ERROR_INT_STAT_EN_R Provides mask bits for general interrupts that are triggered by error conditions.
Setting any of these bits to ‘1’ enables interrupt generation for wakeup interrupts and non-error general
NORMAL_INT_SIGNAL_EN_R
interrupts.
Setting any of these bits to ‘1’ enables interrupt generation for general interrupts that are triggered by
ERROR_INT_SIGNAL_EN_R
error conditions.
FORCE_ERROR_INT_STAT_R Forces an error interrupt to occur when the corresponding bit is set.

27.6.1 SDIO Interrupt

The SDIO interrupt function is supported on card_dat_3to0[1] line (SD pin 8). See the SDIO specifications for details on this
feature. The CARD_INTERRUPT_STAT_EN bit in the NORMAL_INT_STAT_EN_R register and the
CARD_INTERRUPT_SIGNAL_EN bit in the NORMAL_INT_SIGNAL_EN_R register must be set to enable this interrupt. To
use this interrupt as wakeup interrupt, use WUP_CTRL_R.WUP_CARD_INT instead of NORMAL_INT_SIGNAL_EN_R.

27.7 I/O Interface

SDHC block provides the signals shown in Table 27-4, which can be routed to pins through the I/O subsystem (IOSS). Refer
to the I/O System chapter on page 261 to configure the I/Os, and the PSoC 61 datasheet/PSoC 62 datasheet for specific pins
available for each signal. SDHC also supports SDIO interrupt on DAT[1] line (card_data_3to0[1]). The output signals must be
configured in strong drive mode, bi-directional signals in strong drive with the input buffer ON, and the input pins in high-
impedance mode when an external pull-up resistor is available; otherwise, they must be configured in internal pull-up mode.
Input buffer must be enabled for the input pins. The drive mode of the DAT lines must be set to high impedance after card
removal. See Card Detection on page 314 for details. In addition to configuring the drive mode and HSIOM registers in IOSS,
the SDHC_CORE.GP_OUT_R register must be configured to enable the required signals. See Table 27-4. The
card_detect_n and card_write_prot should be connected to ground if an eMMC or an embedded SDIO device is connected.

Table 27-4. I/O Signal Interface

Signal Function Register Configuration
clk_card Clock output GP_OUT_R.CARD_CLOCK_OE
card_cmd Command (bi-directional) Always enabled
card_dat_3to0[3:0] Data (bi-directional) HOST_CTRL1_R.DAT_XFER_WIDTH
card_detect_n Card detect signal input, Active low GP_OUT_R.CARD_DETECT_EN
card_mech_write_prot Mechanical write protect signal input, Active low GP_OUT_R.CARD_MECH_WRITE_PROT_EN
Signaling voltage select output (see 27.7.1 Switching Signaling
io_volt_sel GP_OUT_R.IO_VOLT_SEL_OE
Voltage from 3.3 V to 1.8 V)
card_if_pwr_en Card interface power enable output GP_OUT_R.CARD_IF_PWR_EN_OE

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 Secure Digital Host Controller (SDHC)

27.7.1 Switching Signaling Voltage from transfers to the cards do not occur simultaneously, a single
shared buffer is used for read and write operations. During
3.3 V to 1.8 V the data transfer command handshake, the read/write bit of
The I/Os operate at the voltage level supplied through the the command register is sampled and stored. This internal
external VDDIO pin. The SD mode supports switching the bit defines whether the SDHC is in read or write mode.
signaling voltage from 3.3 V to 1.8 V after negotiation with
Figure 27-3 shows how data flows from the card interface to
the SD card. The block sets the
the AHB master interface through the packet buffer for a
HOST_CTRL2_R.SIGNALING_EN bit to indicate the switch.
card read transfer. Received data from the card interface is
This value is reflected on the io_volt_sel pin, which can be
written into packet buffer. When one block of data is
connected to an external regulator powering VDDIO to switch
received, DMA starts transmitting that data to the system by
between 3.3 V and 1.8 V. Note that PSoC 6 does not
reading it from the packet buffer. For a card write transfer,
provide an internal regulator to power the SD interface I/Os.
data flows in the reverse direction. DMA writes data into a
packet buffer that is subsequently read by the card interface
27.8 Packet Buffer SRAM logic. DMA and card interface logic can work simultaneously
because read and write to packet buffer can be interleaved.
SRAM that is internal to the SDHC block is used as a packet For card read, DMA can send out the previous block while
buffer to store data packets while carrying out data transfer card interface logic is receiving the current block. For card
to and from the card. The size of the SRAM is 1KB to write, DMA can write the current block into packet buffer
support buffering of two 512 bytes blocks. As write and read while card interface logic is sending out the previous block.
Figure 27-3. Data Flow in a Read Transfer

Card
SRAM
AHB DMA Interface
Controller SD/eMMC
Master Logic
Bus

Packet Buffer
(SRAM)

27.8.1 Packet Buffer Full/Empty is moving data during task execution (for CMD46 and
CMD47).
When the packet buffer becomes full in card read, the clock
■ Prefetches data for back-to-back eMMC write
to the card is stopped to prevent the card from sending the
commands.
next data block. When packet buffer is empty, data block is
not sent. In both cases, card interface logic is idle. SDHC ■ Writes back the received data packets to system
does not support SDIO Read Wait signaling through DAT[2]. memory.
Therefore, the I/O command (CMD52) cannot be performed Figure 27-4 shows the data flow between the host driver and
during a multiple read cycle because the card clock is SD bus. The host driver can transfer data using either a
stopped. programmed I/O (PIO) method in which the internal buffer is
accessed through the buffer data port (BUF_DATA_R)
register or using any of the defined DMA methods. PIO
27.9 DMA Engine mode is much slower and burdens the processor. Do not
The DMA engine handles data transfer between SDHC and use the PIO mode for large transfers.
system memory. Following are the features of this unit:
■ Supports SDMA, ADMA2, and ADMA3 modes based on
the configuration.
■ The same DMA engine is used to interleave data
transfer and descriptor fetch. This enables new task
descriptor fetches (for CMD44 and CMD45) while DMA

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 Secure Digital Host Controller (SDHC)

Figure 27-4. Data Flow Refer to the respective specifications documents listed in
Block Diagram on page 308 to learn more about the DMA
Host Driver operation.

27.10 Initialization Sequence

DMA Interface Figure 27-5 shows the sequence for initializing SDHC to
work with SD/SDIO/eMMC cards. Subsequent sections
describe each step. After initialization, SDHC is ready to
communicate with the card. Refer to the corresponding
Registers Buffer specifications document for information on other sequences
such as card initialization and identification, changing bus
speed mode, signal voltage switch procedure, transaction
generation, and error recovery.
CMD Control DATA Control
Figure 27-5. SDHC Programming Sequence
START

CMD SD Bus Interface DAT[7:0] Enable SDHC

YES IS
DMA supports both single block and multi-block transfers. EMBEDDED
The control bits in the block gap control (BGAP_CTRL_R) CARD?
Card detect
register is used to stop and restart a DMA operation. SDMA NO interrupt occurs
mode is used for short data transfer because it generates
interrupts at page boundaries. These interrupts disturb the
IS CARD NO Configure interrupt
CPU to reprogram the new system address. Only one SD PRESENT? for card detection
command transaction can be executed for every SDMA
operation. YES

ADMA2 and ADMA3 are used for long data transfers. They Initialize SDHC
adopt scatter gather algorithm so that higher data transfer
speed is available. The host driver can program a list of data
transfers between system memory and SD card to the Setup Clock
descriptor table. ADMA2 performs one read/write SD
command operation at a time. ADMA3 can program multiple Initialize Card
read/write SD command operation in a descriptor table.
In SDMA and ADMA2 modes, writing the CMD_R register
Card Read/Write
triggers the DMA operation. In ADMA3 mode, writing
ADMA_ID_LOW_R register triggers the DMA operation.
SD mode commands are generated by writing into the END
following registers – system address (SDMASA_R), block
size (BLOCKSIZE_R), block count (BLOCKCOUNT_R),
transfer mode (XFER_MODE_R), and command (CMD_R). 27.10.1 Enabling SDHC
When HOST_CTRL2_R.HOST_VER4_EN = 0, SDMA uses
SDMASA_R as system address register and hence Auto Ensure clk_sys is configured to be greater than or equal to
CMD23 cannot be used with SDMA because this register is clk_card and is running. Then, follow the sequence in
assigned for Auto CMD23 as the 32-bit block count register. Figure 27-6 to enable the block. The internal clock can also
When HOST_CTRL2_R.HOST_VER4_EN = 1, SDMA uses be enabled later during clock setup. It must be enabled to
ADMA_SA_LOW_R as system address register and detect card insertion or removal through general interrupts
SDMASA_R is reassigned to 32-bit block count and hence when SDHC is not in standby mode. See 27.10.2 Card
SDMA may use Auto CMD23. Detection for details.

To use the 32-bit block count register when

HOST_CTRL2_R.HOST_VER4_EN = 1, it must be
programmed with a non-zero value and the value of the 16-
bit block count register BLOCK_COUNT_R must be zero.

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 Secure Digital Host Controller (SDHC)

Figure 27-6. SDHC Enable Sequence Figure 27-7. Card Status Check Sequence
START START

SDHC_WRAP_CTL.ENABLE = 1 GP_OUT_R.CARD_DETECT_EN = 1
CLK_CTRL_R.INTERNAL_CLK_EN = 1

IS NO
PSTATE_REG.CARD
IS _STABLE = 1?
CLK_CTRL_R.INTER
NO
NAL_CLK_STABLE =
1?
YES

YES
Card is not
IS present
END PSTATE_REG.CARD
_INSERTED = 1?

27.10.2 Card Detection Card is

present
Check if the card is already inserted by following the
END
sequence shown in Figure 27-7. This step is required for a
removable card. After the card is detected, the host driver
can supply power and clock to the card. If the card is
inserted, then proceed with SDHC initialization. To detect
card insertion or removal through interrupt when the internal
clock is already enabled, follow the sequence shown in
Figure 27-8. To detect the card status through interrupt
when the internal clock is disabled (when SDHC is in
standby mode), the bits in the WUP_CTRL_R register must
be set and the NORMAL_INT_SIGNAL_EN register must be
cleared. See Interrupts to CPU on page 310 for details. To
detect SDIO card interrupt on DAT[1] line, a separate bit is
provided in these registers, which must be configured.
SDHC clears the PWR_CTRL_R.SD_BUS_PWR_VDD1 bit
when the card is removed and drives the DAT lines low.
Therefore, the drive mode of the DAT lines must be changed
from strong (with input buffer ON) to HI-Z when the card is
removed to keep the lines pulled high. After detecting card
insertion, the drive mode must be configured back to strong
(with input buffer ON) mode only after
PWR_CTRL_R.SD_BUS_PWR_VDD1 is set to 1.

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 Secure Digital Host Controller (SDHC)

Figure 27-8. Card Detection Through Interrupt

START

GP_OUT_R.CARD_DETECT_EN = 1

Enable interrupt for Card Detect

WUP_CTRL_R = 0
NORMAL_INT_STAT_EN_R.CARD_INSERTION_STAT_EN = 1
NORMAL_INT_SIGNAL_EN_R.CARD_INSERTION_SIGNAL_EN = 1
NORMAL_INT_STAT_EN_R.CARD_REMOVAL_STAT_EN = 1
NORMAL_INT_SIGNAL_EN_R.CARD_REMOVAL_SIGNAL_EN = 1

Card detect interrupt

is triggered

Card is
IS YES Clear interrupt status:
NORMAL_INT_STAT_
present
R.CARD_INSERTION
NORMAL_INT_STAT_R.
= 1? CARD_INSERTION = 1

NO

Card is not
IS YES Clear interrupt status: present
NORMAL_INT_STAT_
R.CARD_REMOVAL
NORMAL_INT_STAT_R.
= 1? CARD_REMOVAL = 1

NO

END

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 Secure Digital Host Controller (SDHC)

27.10.3 SDHC Initialization Figure 27-10. Clock Setup

START
To initialize SDHC, configure the basic settings as shown in
Figure 27-9. This step can also be executed immediately
after enabling SDHC. Divider = CLK_HF/2/SD clock frequency

Figure 27-9. SDHC Setup

CLK_CTRL_R.CLK_GEN_SELECT = 0
START CLK_CTRL_R.UPPER_FREQ_SEL = divider[9:8]
CLK_CTRL_R.FREQ_SEL = divider[7:0]

Enable power to the card

CLK_CTRL_R.INTERNAL_CLK_EN = 1
GP_OUT_R.CARD_IF_PWR_EN_OE = 1
PWR_CTRL_R.SD_BUS_PWR_VDD1 = 1
GP_OUT_R.IO_VOLT_SEL_OE = 1
HOST_CTRL2_R.SIGNALING_EN = 0 On timeout
of 150 ms IS
CLK_CTRL_R.INTER NO
NAL_CLK_STABLE =
1?

Is Card Type = NO
eMMC? YES

YES Configure
GP_OUT_R.CARD_CLOCK_OUT_DLY and
GP_OUT_R.CARD_CLOCK_IN_DLY
EMMC_CTRL_R.CARD_IS_EMMC = 1 as per speed mode*

CLK_CTRL_R.PLL_ENABLE = 1
Configure DMA type through
HOST_CTRL1_R.DMA_SEL

Enable mechanical write protection through

On timeout
GP_OUT_R.CARD_MECH_WRITE_PROT_EN = 1
of 150 ms IS
CLK_CTRL_R.INTER NO
Configure interrupts the interrupt status enable and NAL_CLK_STABLE =
signal enable registers 1?

YES

Clock Setup CLK_CTRL_R.SD_CLK_EN = 1

HOST_CTRL2_R.HOST_VER4_ENABLE = 1
Failed
HOST_CTRL2_R.ASYNC_INT_ENABLE = 1

END
END

* See the CY8C62x8, CY8C62xA Registers TRM for details.

27.10.4 Clock Setup
Enable the internal clock followed by the card clock (SD 27.11 Error Detection
clock) by following the sequence shown in Figure 27-10.
SDHC can detect different types of errors in SD and eMMC
The SD clock frequency must be 100 kHz to 400 kHz during
transactions. Error is detected in either the command or
the card initialization. See Card Clock (SDCLK)
data portion of the transaction. When an error is detected,
Configuration on page 309 for details. SD clock can be
the ERR_INTERRUPT bit in the NORMAL_INT_STAT_R
started and stopped by toggling the
register is set. The exact error can then be identified through
CLK_CTRL_R.SD_CLK_EN bit. The same sequence
the ERROR_INT_STAT_R register. The Abort command is
excluding the step of enabling the internal clock can be used
used to recover from an error detected during data transfer.
to change the SD clock frequency. The SD clock must be
In addition to these two registers, SDHC has two other error
stopped before changing its frequency. Note that
status registers – Auto CMD Error Status
GP_OUT_R.CARD_CLOCK_OE should have been set to ‘1’
(AUTO_CMD_STAT_R) and ADMA Error Status
for the card clock to appear on the pin.
(ADMA_ERR_STAT_R). The following table lists the errors
detected by SDHC.

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 Secure Digital Host Controller (SDHC)

Table 27-5. Errors Detected by SHDC

Type Error
Command Timeout Error
Command CRC Error
Command End Bit Error
Command Errors
Command Index Error
Command Conflict Error
Response Error
Command not issued by Auto CMD12 Error
Auto Command Timeout Error
Auto Command CRC Error
Auto Command Errors Auto Command End Bit Error
Auto Command Index Error
Auto Command Conflict Error
Auto CMD response Error
Data Timeout Error
Data CRC Error
Data Errors Data End Bit Error
ADMA Error
Tuning Error

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 317
 28. Serial Communications Block (SCB)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Serial Communications Block (SCB) supports three serial communication protocols: Serial Peripheral Interface (SPI),
Universal Asynchronous Receiver Transmitter (UART), and Inter Integrated Circuit (I2C or IIC). Only one of the protocols is
supported by an SCB at any given time. The number of SCBs in a PSoC 6 MCU varies by part number; consult the PSoC 61
datasheet/PSoC 62 datasheet to determine number of SCBs and the SCB pin locations. Not all SCBs support all three modes
(SPI, UART, and I2C); consult the PSoC 61 datasheet/PSoC 62 datasheet to determine which modes are supported by which
SCBs. Not all SCBs operate in deep sleep, consult the PSoC 61 datasheet/PSoC 62 datasheet to determine which SCBs
operate in deep sleep.

28.1 Features
The SCB supports the following features:
■ Standard SPI master and slave functionality with Motorola, Texas Instruments, and National Semiconductor protocols
■ Standard UART functionality with SmartCard reader, Local Interconnect Network (LIN), and IrDA protocols
❐ Standard LIN slave functionality with LIN v1.3 and LIN v2.1/2.2 specification compliance
■ Standard I2C master and slave functionality
■ Trigger outputs for connection to DMA
■ Multiple interrupt sources to indicate status of FIFOs and transfers
■ Features available only on Deep Sleep-capable SCB:
❐ EZ mode for SPI and I2C slaves; allows for operation without CPU intervention
❐ CMD_RESP mode for SPI and I2C slaves; allows for operation without CPU intervention
❐ Low-power (Deep Sleep) mode of operation for SPI and I2C slaves (using external clocking)
❐ Deep Sleep wakeup on I2C slave address match or SPI slave selection

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28.2 Architecture CMD_RESP mode is available only for SPI slave and I2C
slave. It is available only on the Deep Sleep-capable SCB.
The operation modes supported by SCB are described in
the following sections. CMD_RESP mode operation is available in Active, Sleep,
and Deep Sleep power modes.
28.2.1 Buffer Modes
28.2.2 Clocking Modes
Each SCB has 256 bytes of dedicated RAM for transmit and
receive operation. This RAM can be configured in three The SCB can be clocked either by an internal clock provided
different modes (FIFO, EZ, or CMD_RESP). The following by the peripheral clock dividers (referred to as clk_scb in this
sections give a high-level overview of each mode. The document), or it can be clocked by the external master.
sections on each protocol will provide more details. ■ UART, SPI master, and I2C master modes must use
■ Masters can only use FIFO mode clk_scb.
■ I2C and SPI slaves can use all three modes. Note: EZ ■ Only SPI slave and I2C slave can use the clock from and
Mode and CMD Response Mode are available only on external master, and only the Deep Sleep capable SCB
the Deep Sleep-capable SCB supports this.
■ UART only uses FIFO mode Internally- and externally-clocked slave functionality is
determined by two register fields of the SCB CTRL register:
Note: This document discusses hardware implementation of
the EZ mode; for the firmware implementation, see the PDL. ■ EC_AM_MODE indicates whether SPI slave selection or
I2C address matching is internally (‘0’) or externally (‘1’)
28.2.1.1 FIFO Mode clocked.
■ EC_OP_MODE indicates whether the rest of the
In this mode the RAM is split into two 128-byte FIFOs, one protocol operation (besides SPI slave selection and I2C
for transmit (TX) and one for receive (RX). The FIFOs can address matching) is internally (‘0’) or externally (‘1’)
be configured to be 8 bits x 128 elements or 16 bits x 64 clocked.
elements; this is done by setting the BYTE_MODE bit in the
SCB control register. Notes:
■ FIFO mode supports an internally- or externally-clocked
FIFO mode of operation is available only in Active and Sleep
address match (EC_AM_MODE is ‘0’ or ‘1’); however,
power modes. However, the I2C address or SPI slave select
data transfer must be done with internal clocking.
can be used to wake the device from Deep Sleep on the
(EC_OP_MODE is ‘1’).
Deep Sleep-capable SCB.
■ EZ and CMD_RESP modes are supported with
Statuses are provided for both the RX and TX FIFOs. There externally clocked operation (EC_OP_MODE is ‘1’).
are multiple interrupt sources available, which indicate the
status of the FIFOs, such as full or empty; see “SCB Table 28-1 provides an overview of the clocking and buffer
Interrupts” on page 366. modes supported for each communication mode.

28.2.1.2 EZ Mode
In easy (EZ) mode the RAM is used as a single 256-byte
buffer. The external master sets a base address and reads
and writes start from that base address.

EZ Mode is available only for SPI slave and I2C slave. It is

available only on the Deep Sleep capable SCB.
EZ mode is available in Active, Sleep, and Deep Sleep
power modes.
Note: This document discusses hardware implementation of
the EZ mode; for the firmware implementation, see the PDL.

28.2.1.3 CMD_RESP Mode

Command Response (CMD_RESP) mode is similar to EZ
mode except that the base address is provided by the CPU
not the external master.

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 Serial Communications Block (SCB)

Table 28-1. Clock Mode Compatibility

Externally clocked (EC)
Internally clocked (IC)
(Deep Sleep SCB only)
FIFO EZ CMD_RESP FIFO EZ CMD_RESP
I2C master Yes No No No No No
2 Yes Yes No a Yes Yes
I C slave Yes
I2C master-slave Yes No No No No No
SPI master Yes No No No No No
SPI slave Yes Yes No Yesb Yes Yes
UART transmitter Yes No No No No No
UART receiver Yes No No No No No
a. In Deep Sleep mode the external-clocked logic can handle slave address matching, it then triggers an interrupt to wake up the CPU. The slave can be
programmed to stretch the clock, or NACK until internal logic takes over. This applies only to the Deep Sleep-capable SCB.
b. In Deep Sleep mode the external-clocked logic can handle slave selection detection, it then triggers an interrupt to wake up the CPU. Writes will be ignored
and reads will return 0xFF until internal logic takes over. This applies only to the Deep Sleep-capable SCB.

Table 28-2. Clock Configuration and Mode support

EC_AM_MODE is '0'; 'EC_AM_MODE is '1'; 'EC_AM_MODE is '1';
Mode
EC_OP_MODE is ‘0’ EC_OP_MODE is '0’ EC_OP_MODE is '1'
FIFO mode Yes Yes No
EZ mode Yes Yes Yes
CMD_RESP mode No No Yes

28.3 Serial Peripheral Interface (SPI)

The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master
initiates the data transfer. The SCB supports single-master-multiple-slaves topology for SPI. Multiple slaves are supported
with individual slave select lines.

28.3.1 Features
■ Supports master and slave functionality
■ Supports three types of SPI protocols:
❐ Motorola SPI – modes 0, 1, 2, and 3
❐ Texas Instruments SPI, with coinciding and preceding data frame indicator – mode 1 only
❐ National Semiconductor (MicroWire) SPI – mode 0 only
■ Master supports up to four slave select lines
❐ Each slave select has configurable active polarity (high or low)
❐ Slave select can be programmed to stay active for a whole transfer, or just for each byte
■ Master supports late sampling for better timing margin
■ Master supports continuous SPI clock
■ Data frame size programmable from 4 bits to 16 bits
■ Programmable oversampling
■ MSb or LSb first
■ Median filter available for inputs (when using the median filter, the minimum oversample factor is increased)
■ Supports FIFO Mode
■ Supports EZ Mode (slave only) and CMD_RESP mode (slave only) on the Deep Sleep-capable SCB

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28.3.2 General Description

Figure 28-1 illustrates an example of SPI master with four slaves.
Figure 28-1. SPI Example

SCLK
MOSI
SPI
SPI MISO Slave 1
Master Slave Select (SS) 1

SPI
Slave 2
Slave Select (SS) 2

SPI
Slave 3
Slave Select (SS) 3

SPI
Slave 4
Slave Select (SS) 4

A standard SPI interface consists of four signals as follows.

■ SCLK: Serial clock (clock output from the master, input to the slave).
■ MOSI: Master-out-slave-in (data output from the master, input to the slave).
■ MISO: Master-in-slave-out (data input to the master, output from the slave).
■ Slave Select (SS): Typically an active low signal (output from the master, input to the slave).
A simple SPI data transfer involves the following: the master selects a slave by driving its SS line, then it drives data on the
MOSI line and a clock on the SCLK line. The slave uses either of the edges of SCLK depending on the configuration to
capture the data on the MOSI line; it also drives data on the MISO line, which is captured by the master.

28.3.2.1 Transfer Separation

This parameter determines if individual data transfers are separated by slave select deselection, which is controlled by
SCB_SPI_CTRL.SSEL_CONTINUOUS (only applicable for Master mode):
■ Continuous – The slave select line is held in active state until the end of transfer (default).
The master assigns the slave select output after data has been written into the TX FIFO and keeps it active as long as
there are data elements to transmit. The slave select output becomes inactive when all data elements have been transmit-
ted from the TX FIFO and shifter register.
Note: This can happen even in the middle of the transfer if the TX FIFO is not loaded fast enough by the CPU or DMA. To
overcome this behavior, the slave select can be controlled by firmware.
■ Separated – Every data frame 4-16 bits is separated by slave select line deselection by one SCLK period.
By default, the SPI interface supports a data frame size of eight bits (1 byte). The data frame size can be configured to any
value in the range 4 to 16 bits. The serial data can be transmitted either most significant bit (MSb) first or least significant bit
(LSb) first.

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Three different variants of the SPI protocol are supported by the SCB:
■ Motorola SPI: This is the original SPI protocol.
■ Texas Instruments SPI: A variation of the original SPI protocol, in which data frames are identified by a pulse on the SS
line.
■ National Semiconductors SPI: A half-duplex variation of the original SPI protocol.

28.3.3 SPI Modes of Operation

28.3.3.1 Motorola SPI
The original SPI protocol was defined by Motorola. It is a full duplex protocol. Multiple data transfers may happen with the SS
line held at ‘0’. When not transmitting data, the SS line is held at ‘1’.

Clock Modes of Motorola SPI

The Motorola SPI protocol has four different clock modes based on how data is driven and captured on the MOSI and MISO
lines. These modes are determined by clock polarity (CPOL) and clock phase (CPHA).
Clock polarity determines the value of the SCLK line when not transmitting data. CPOL = ‘0’ indicates that SCLK is ‘0’ when
not transmitting data. CPOL = ‘1’ indicates that SCLK is ‘1’ when not transmitting data.
Clock phase determines when data is driven and captured. CPHA = 0 means sample (capture data) on the leading (first)
clock edge, while CPHA = 1 means sample on the trailing (second) clock edge, regardless of whether that clock edge is rising
or falling. With CPHA = 0, the data must be stable for setup time before the first clock cycle.
■ Mode 0: CPOL is ‘0’, CPHA is ‘0’: Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
■ Mode 1; CPOL is ‘0’, CPHA is ‘1’: Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
■ Mode 2: CPOL is ‘1’, CPHA is ‘0’: Data is driven on a rising edge of SCLK. Data is captured on a falling edge of SCLK.
■ Mode 3: CPOL is ‘1’, CPHA is ‘1’: Data is driven on a falling edge of SCLK. Data is captured on a rising edge of SCLK.
Figure 28-2 illustrates driving and capturing of MOSI/MISO data as a function of CPOL and CPHA.
Figure 28-2. SPI Motorola, 4 Modes
CPOL = 0 CPHA = 0

SCLK

MISO / MSb LSb

MOSI

CPOL = 0 CPHA = 1

SCLK

MISO /
MSb LSb
MOSI

CPOL = 1 CPHA = 0

SCLK

MISO /
MSb LSb
MOSI

CPOL = 1 CPHA = 1

SCLK

MISO /
MOSI MSb LSb

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Figure 28-3 illustrates a single 8-bit data transfer and two successive 8-bit data transfers in mode 0 (CPOL is ‘0’, CPHA is ‘0’).
Figure 28-3. SPI Motorola Data Transfer Example
CPOL = 0, CPHA = 0 single data transfer

SCLK

SS

MOSI MSb LSb

MISO MSb LSb

CPOL = 0, CPHA = 0 two successive data transfers

SCLK

SS

MSb LSb MSb LSb

MOSI

MISO MSb LSb MSb LSb

Figure 28-4. SELECT and SCLK Timing Correlation

CPHA = 0, CPOL = 0
Oversampling = 5 (1 SCLK period contains 6 clk_scb periods)

clk_scb

SS0

SCLK

¾ SCLK ¼ SCLK

CPHA = 1, CPOL = 0
Oversampling = 5 (1 SCLK period contains 6 clk_scb periods)

clk_scb

SS0

SCLK

¼ SCLK ¾ SCLK

For example above: OversamplingReg = 6 – 1 = 5.

¾ * SCLK = ((5 / 2) + 1) + (5 / 4 + 1)) * clk_scb = (3 + 2) * clk_scb = 5 * clk_scb.
¼ * SCLK = ((5 / 4) + 1) * clk_scb = 2 * clk_scb.

Note The value ¾ * SCLK is equal to (((OversamplingReg / 2) + 1) + (OversamplingReg / 4) + 1)),

where OversamplingReg = Oversampling – 1.
The value ¼ * SCLK is equal to ((OversamplingReg / 4) + 1).
The result of any division operation is rounded down to the nearest integer.
Note The provided timings are guaranteed by SCB block but do not take into account signal propagation time from SCB block to
pins.

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Configuring SCB for SPI Motorola Mode

To configure the SCB for SPI Motorola mode, set various register bits in the following order:
1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register.
2. Select SPI Motorola mode by writing ‘00’ to the MODE (bits [25:24]) of the SCB_SPI_CTRL register.
3. Select the clock mode in Motorola by writing to the CPHA and CPOL fields (bits 2 and 3 respectively) of the
SCB_SPI_CTRL register.
4. Follow steps 2 to 4 mentioned in “Enabling and Initializing SPI” on page 334.
For more information on these registers, see the registers TRM.

28.3.3.2 Texas Instruments SPI

The Texas Instruments’ SPI protocol redefines the use of the SS signal. It uses the signal to indicate the start of a data
transfer, rather than a low active slave select signal, as in the case of Motorola SPI. The start of a transfer is indicated by a
high active pulse of a single bit transfer period. This pulse may occur one cycle before the transmission of the first data bit, or
may coincide with the transmission of the first data bit. The TI SPI protocol supports only mode 1 (CPOL is ‘0’ and CPHA is
‘1’): data is driven on a rising edge of SCLK and data is captured on a falling edge of SCLK.
Figure 28-5 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse precedes the
first data bit. Note how the SELECT pulse of the second data transfer coincides with the last data bit of the first data transfer.
Figure 28-5. SPI TI Data Transfer Example
CPOL=0, CPHA=1 single data transfer

SCLK

SS

MOSI MSb LSb

MISO MSb LSb

CPOL=0, CPHA=1 two successive data transfers

SCLK

SS

MOSI MSb LSb MSb LSb

MISO MSb LSb MSb LSb

Figure 28-6 illustrates a single 8-bit data transfer and two successive 8-bit data transfers. The SELECT pulse coincides with
the first data bit of a frame.

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 Serial Communications Block (SCB)

Figure 28-6. SPI TI Data Transfer Example

CPOL=0, CPHA=1 single data transfer

SCLK

SS

MOSI MSb LSb

MISO MSb LSb

CPOL=0, CPHA=1 two successive data transfers

SCLK

SS

MOSI
MSb LSb MSb LSb

MISO MSb LSb MSb LSb

Configuring SCB for SPI TI Mode

To configure the SCB for SPI TI mode, set various register bits in the following order:
1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register.
2. Select SPI TI mode by writing ‘01’ to the MODE (bits [25:24]) of the SCB_SPI_CTRL register.
3. Select the mode of operation in TI by writing to the SELECT_PRECEDE field (bit 1) of the SCB_SPI_CTRL register (‘1’
configures the SELECT pulse to precede the first bit of next frame and ‘0’ otherwise).
4. Set the CPHA bit of the SCB_SPI_CONTROL register to ‘0’, and the CPOL bit of the same register to ‘1’.
5. Follow steps 2 to 4 mentioned in “Enabling and Initializing SPI” on page 334.
For more information on these registers, see the registers TRM.

28.3.3.3 National Semiconductors SPI

The National Semiconductors’ SPI protocol is a half-duplex protocol. Rather than transmission and reception occurring at the
same time, they take turns. The transmission and reception data sizes may differ. A single ‘idle’ bit transfer period separates
transfers from reception. However, successive data transfers are not separated by an idle bit transfer period.
The National Semiconductors SPI protocol supports only mode 0.
Figure 28-7 illustrates a single data transfer and two successive data transfers. In both cases, the transmission data transfer
size is eight bits and the reception data transfer size is four bits.

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Figure 28-7. SPI NS Data Transfer Example

CPOL=0, CPHA=0 single data transfer

SCLK

SS

MSb LSb
MOSI

MISO MSb LSb

idle 0 cycle

CPOL=0, CPHA=0 two successive data transfers

SCLK

SS

MOSI MSb LSb MSb

MISO MSb LSb

idle 0 cycle
No idle cycle

Configuring SCB for SPI NS Mode

To configure the SCB for SPI NS mode, set various register bits in the following order:
1. Select SPI by writing ‘01’ to the MODE (bits [25:24]) of the SCB_CTRL register.
2. Select SPI NS mode by writing ‘10’ to the MODE (bits [25:24]) of the SCB_SPI_CTRL register.
3. Set the CPOL and CHPA bits of the SCB_SPI_CTRL register to ‘0’.
4. Follow steps 2 to 4 mentioned in “Enabling and Initializing SPI” on page 334.
For more information on these registers, see the registers TRM.

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28.3.4 SPI Buffer Modes

SPI can operate in three different buffer modes – FIFO, EZ, and CMD_RESP modes. The buffer is used in different ways in
each of these modes. The following subsections explain each of these buffer modes in detail.

28.3.4.1 FIFO Mode

The FIFO mode has a TX FIFO for the data being transmitted and an RX FIFO for the data received. Each FIFO is
constructed out of the SRAM buffer. The FIFOs are either 64 elements deep with 16-bit data elements or 128 elements deep
with 8-bit data elements. The width of a FIFO is configured using the BYTE_MODE bitfield of the SCB.CTRL register.
FIFO mode of operation is available only in Active and Sleep power modes, and not in the Deep Sleep mode.
Transmit and receive FIFOs allow write and read accesses. A write access to the transmit FIFO uses the TX_FIFO_WR
register. A read access from the receive FIFO uses the RX_FIFO_RD register. For SPI master mode, data transfers are
started when data is written into the TX FIFO. Note that when a master is transmitting and the FIFO becomes empty the slave
is de-selected.
Transmit and receive FIFO status information is available through status registers, TX_FIFO_STATUS and
RX_FIFO_STATUS, and through the INTR_TX and INTR_RX registers.
Each FIFO has a trigger output. This trigger output can be routed through the trigger mux to various other peripheral on the
device such as DMA or TCPWMs. The trigger output of the SCB is controlled through the TRIGGER_LEVEL field in the
RX_CTRL and TX_CTRL registers.
■ For a TX FIFO a trigger is generated when the number of entries in the transmit FIFO is less than
TX_FIFO_CTRL.TRIGGER_LEVEL.
■ For the RX FIFO a trigger is generated when the number of entries in the FIFO is greater than the
RX_FIFO_CTRL.TRIGGER_LEVEL.
Note that the DMA has a trigger deactivation setting. For the SCB this should be set to 16.

Active to Deep Sleep Transition

Before going to deep sleep ensure that all active communication is complete. For a master this can easily be done by
checking the SPI_DONE bit in the INTR_M register, and ensuring the TX FIFO is empty.
For a slave this can be achieved by checking the BUS_BUSY bit in the SPI Status register. Also the RX FIFO should be
empty before going to deep sleep. Any data in the FIFO will be lost during deep sleep.
Also before going to deep sleep the clock to the SCB needs to be disabled. This can be done by setting the
SDA_IN_FILT_TRIM[1] bit in the I2C_CFG register to "0".
Lastly, when the device goes to deep sleep the SCB stops driving the GPIO lines. This leads to floating pins and can lead to
undesirable current during deep sleep power modes. To avoid this condition before entering deep sleep mode change the
HSIOM settings of the SCB pins to GPIO driven, then change the drive mode and drive state to the appropriate state to avoid
floating pins. Consult the I/O System chapter on page 261 for more information on pin drive modes.
Note: Before going into deep sleep the wakeup interrupt should be cleared. See the “SPI Interrupts” on page 367 for more
details.

Deep Sleep to Active Transition

EC_AM = 1, EC_OP = 0, FIFO Mode.
When the SPI Slave Select line is asserted the device will be awoken by an interrupt. After the device is awoken change the
SPI pin drive modes and HSIOM settings back to what they were before deep sleep. When clk_hf[0] is at the desired
frequency set SDA_IN_FILT_TRIM[1] to ‘1’ to enable the clock to the SCB. Then write data into the TX FIFO. At this point the
master can read valid data from the slave. Before that any data read by the master will be invalid.

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Figure 28-8. SPI Slave Wakeup from Deep Sleep (Motorola, CPHA = 0, CPOL = 0)
Wakeup event

SS0

SCLK

MOSI Wakeup byte (ignored) Data

MISO 0xFF Data

Active Deep Sleep DS -> A Active

TDEEPSLEEP

Load TX buffer

28.3.4.2 EZSPI Mode

The easy SPI (EZSPI) protocol only works in the Motorola mode, with any of the clock modes. It allows communication
between master and slave without the need for CPU intervention. In the PSoC 6 MCU, only the deep sleep-capable SCB
supports EZSPI mode.
The EZSPI protocol defines a single memory buffer with an 8-bit EZ address that indexes the buffer (256-entry array of eight
bit per entry) located on the slave device. The EZ address is used to address these 256 locations. All EZSPI data transfers
have 8-bit data frames.
The CPU writes and reads to the memory buffer through the SCB_EZ_DATA registers. These accesses are word accesses,
but only the least significant byte of the word is used.
EZSPI has three types of transfers: a write of the EZ address from the master to the slave, a write of data from the master to
an addressed slave memory location, and a read by the master from an addressed slave memory location.
Note: When multiple bytes are read or written the master must keep SSEL low during the entire transfer.

EZ Address Write
A write of the EZ address starts with a command byte (0x00) on the MOSI line indicating the master’s intent to write the EZ
address. The slave then drives a reply byte on the MISO line to indicate that the command is acknowledged (0xFE) or not
(0xFF). The second byte on the MOSI line is the EZ address.

Memory Array Write

A write to a memory array index starts with a command byte (0x01) on the MOSI line indicating the master’s intent to write to
the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was registered (0xFE) or
not (0xFF). Any additional bytes on the MOSI line are written to the memory array at locations indicated by the communicated
EZ address. The EZ address is automatically incremented by the slave as bytes are written into the memory array. When the
EZ address exceeds the maximum number of memory entries (256), it remains there and does not wrap around to 0. The EZ
base address is reset to the address written in the EZ Address Write phase on each slave selection.

Memory Array Read

A read from a memory array index starts with a command byte (0x02) on the MOSI line indicating the master’s intent to read
from the memory array. The slave then drives a reply byte on the MISO line to indicate that the command was registered
(0xFE) or not (0xFF). Any additional read data bytes on the MISO line are read from the memory array at locations indicated
by the communicated EZ address. The EZ address is automatically incremented by the slave as bytes are read from the
memory array. When the EZ address exceeds the maximum number of memory entries (256), it remains there and does not

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 Serial Communications Block (SCB)

wrap around to 0. The EZ base address is reset to the address written in the EZ Address Write phase on each slave
selection.
Figure 28-9 illustrates the write of EZ address, write to a memory array and read from a memory array operations in the
EZSPI protocol.
Figure 28-9. EZSPI Example
Command 0x00 : Write EZ address

SCLK

SS

MOSI Command 0x00 EZ Address

MISO

EZ address (8 bits)
EZ address
Command 0x01 : Write DATA

SCLK

SS

MOSI Command 0x01 Write DATA

MISO

Write
DATA

EZ address EZ buffer
(32 bytes SRAM)
Read
DATA

Command 0x02 : Read DATA

SCLK

SS

MOSI Command 0x02

MISO Read DATA

LEGEND :
CPOL : Clock Polarity 0x00 : Write EZ address
CPHA : Clock Phase 0x01 : Write DATA
SCLK : SPI Interface Clock 0x02 : Read DATA
MISO : SPI Master-In-Slave-Out 0xFE : slave ready
MOSI : SPI Master-Out-Slave-In 0xFF : slave busy

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Configuring SCB for EZSPI Mode The CPU writes and reads to the memory buffer through the
SCB_EZ_DATA registers. These accesses are word
By default, the SCB is configured for non-EZ mode of accesses, but only the least significant byte of the word is
operation. To configure the SCB for EZSPI mode, set the used.
register bits in the following order:
1. Select EZ mode by writing ‘1’ to the EZ_MODE bit (bit The slave interface accesses the memory buffer using the
10) of the SCB_CTRL register. current addresses. At the start of a write transfer (SPI slave
selection), the base write address is copied to the current
2. Set the EC_AM and EC_OP modes in the SCB_CTRL write address. A data element write is to the current write
register as appropriate. address location. After the write access, the current address
3. Set the BYTE_MODE bit of the SCB_CTRL register to is incremented by ‘1’. At the start of a read transfer, the base
‘1’. read address is copied to the current read address. A data
4. Follow the steps in “Configuring SCB for SPI Motorola element read is to the current read address location. After
Mode” on page 324. the read data element is transmitted, the current read
address is incremented by ‘1’.
5. Follow steps 2 to 4 mentioned in “Enabling and Initializ-
ing SPI” on page 334. If the current addresses equal the last memory buffer
address (address equals 255), the current addresses are
For more information on these registers, see the registers
not incremented. Subsequent write accesses will overwrite
TRM.
any previously written value at the last buffer address.
Subsequent read accesses will continue to provide the
Active to Deep Sleep Transition
(same) read value at the last buffer address. The bus
Before going to deep sleep ensure the master is not master should be aware of the memory buffer capacity in
currently transmitting to the slave. This can be done by command-response mode.
checking the BUS_BUSY bit in the SPI_STATUS register.
The base addresses are provided through
If the bus is not busy, disable the clock to the SCB by setting CMD_RESP_CTRL. The current addresses are provided
the SDA_IN_FILT_TRIM[1] bit to ‘0’ in the I2C_CFG register. through CMD_RESP_STATUS. At the end of a transfer (SPI
slave de-selection), the difference between a base and
Deep Sleep to Active Transition current address indicates how many read/write accesses
were performed. The block provides interrupt cause fields to
■ EC_AM = 1, EC_OP = 0, EZ Mode. MISO transmits
identify the end of a transfer. Command-response mode
0xFF until the internal clock is enabled. Data on MOSI is
operation is available in Active, Sleep, and Deep Sleep
ignored until the internal clock is enabled. Do not enable
power modes.
the internal clock until clk_hf[0] is at the desired
frequency. After clk_hf[0] is at the desired frequency set The command-response mode has two phases of operation:
the SDA_IN_FILT_TRIM[1] bit to ‘1’ to enable the clock. ■ Write phase – The write phase begins with a selection
The external master needs to be aware that when it byte, which has its last bit set to ‘0’ indicating a write.
reads 0xFF on MISO the device is not ready yet. The master writes 8-bit data elements to the slave’s
■ EC_AM = 1, EC_OP = 1, EZ Mode. Do not enable the memory buffer following the selection byte. The slave’s
internal clock until clk_hf[0] is at the desired frequency. current write address is set to the slave’s base write
After clk_hf[0] is at the desired frequency set the address. Received data elements are written to the
SDA_IN_FILT_TRIM[1] bit to ‘1’ to enable the clock. current write address memory location. After each
memory write, the current write address is incremented.
28.3.4.3 Command-Response Mode ■ Read phase – The read phase begins with a selection
The command-response mode is defined only for an SPI byte, which has its last bit set to ‘1’ indicating a read. The
slave. In the PSoC 6 MCU, only the deep sleep-capable master reads 8-bit data elements from the slave’s
SCB supports this mode. This mode has a single memory memory buffer. The slave’s current read address is set
buffer, a base read address, a current read address, a base to the slave’s base read address. Transmitted data
write address, and a current write address that are used to elements are read from the current address memory
index the memory buffer. The base addresses are provided location. After each read data element is transferred, the
by the CPU. The current addresses are used by the slave to current read address is incremented.
index the memory buffer for sequential accesses of the During the reception of the first byte, the slave (MISO)
memory buffer. The memory buffer holds 256 8-bit data transmits either 0x62 (ready) or a value different from 0x62
elements. The base and current addresses are in the range (busy). When disabled or reset, the slave transmits 0xFF
[0, 255]. This mode is only supported by the Motorola mode (busy). The byte value can be used by the master to
of operation. determine whether the slave is ready to accept the SPI
request.

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 Serial Communications Block (SCB)

Figure 28-10. Command-Response Mode Example

write phase (command byte 0x00)

spi_clk

spi_select

spi_mosi 0x00 write data

spi_miso
ready (0x62 byte)

LEGEND: base_wr_addr curr_wr_addr SRAM

spi_clk: SPI interface clock
spi_select: SPI slave select Memory
spi_mosi: SPI Master Out / Slave In of n x 8-bits
spi_miso: SPI Master In / Slave Out +1

0x00: write CMD_RESP data

0x01: read CMD_RESP data
!0x62: slave not ready base_rd_addr +1 curr_rd_addr
0x62: slave ready

read phase (command byte 0x01)

spi_clk

spi_select

spi_mosi 0x01

spi_miso read data

ready (0x62 byte)

Note that a slave’s base addresses are updated by the CPU Configuring SCB for CMD_RESP Mode
and not by the master.
By default, the SCB is configured for non-CMD_RESP mode
Active to Deep Sleep Transition of operation. To configure the SCB for CMD_RESP mode,
set the register bits in the following order:
Before going to deep sleep ensure the master is not 1. Select the CMD_RESP mode by writing ‘1’ to the
currently transmitting to the slave. This can be done by CMD_RESP_MODE bit (bit 12) of the SCB_CTRL
checking the BUS_BUSY bit in the SPI_STATUS register. register.
If the bus is not busy, disable the clock to the SCB by setting 2. Set the EC_AM and EC_OP modes to ‘1’ in the
the SDA_IN_FILT_TRIM[1] bit to 0 in the I2C_CFG register. SCB_CTRL register.
3. Set the BYTE_MODE bit in the SCB_CTRL register.
Deep Sleep to Active Transition
4. Follow the steps in “Configuring SCB for SPI Motorola
EC_AM = 1, EC_OP = 1, CMD_RESP Mode. Mode” on page 324.
Do not enable the internal clock until clk_hf[0] is at the 5. Follow steps 2 to 4 mentioned in“Enabling and
desired frequency. When clk_hf[0] is at the desired Initializing SPI” on page 334.
frequency, set the SDA_IN_FILT_TRIM[1] bit to ‘1’ to enable For more information on these registers, see the registers
the clock. TRM.

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 Serial Communications Block (SCB)

28.3.5 Clocking and Oversampling the reception of the command byte. In Active power
mode, the slave (MISO) transmits a ready (0xFE)
28.3.5.1 Clock Modes byte during the reception of the command byte.
❐ CMD_RESP mode: Not supported. The slave trans-
The SCB SPI supports both internally and externally clocked mits (MISO) a value different from a ready (0x62)
operation modes. Two bitfields (EC_AM_MODE and byte during the reception of the first byte.
EC_OP MODE) in the SCB_CTRL register determine the
SCB clock mode. EC_AM_MODE indicates whether SPI ■ EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘1’. Use this
slave selection is internally (0) or externally (1) clocked. mode when both Active and Deep Sleep functionality are
EC_OP_MODE indicates whether the rest of the protocol required. When the slave is selected,
operation (besides SPI slave selection) is internally (0) or INTR_SPI_EC.WAKE_UP is set to ‘1’. The associated
externally (1) clocked. Deep Sleep functionality interrupt brings the system into
Active power mode. When the slave is deselected,
An externally-clocked operation uses a clock provided by INTR_SPI_EC.EZ_STOP and/or
the external master (SPI SCLK). Note: In the PSoC 6 MCU INTR_SPI_EC.EZ_WRITE_STOP are set to ‘1’.
only the Deep Sleep-capable SCB supports externally- ❐ FIFO mode: Not supported.
clocked mode of operation and only for SPI slave mode.
❐ EZ mode: Supported.
An internally-clocked operation uses the programmable ❐ CMD_RESP mode: Supported.
clock dividers. For SPI, an integer clock divider must be
used for both master and slave. For more information on If EC_OP_MODE is ‘1’, the external interface logic accesses
system clocking, see the Clocking System chapter on the memory buffer on the external interface clock (SPI
page 242. SCLK). This allows for EZ and CMD_RESP mode
functionality in Active and Deep Sleep power modes.
The SCB_CTRL bitfields EC_AM_MODE and
EC_OP_MODE can be configured in the following ways. In Active system power mode, the memory buffer requires
■ EC_AM_MODE is ‘0’ and EC_OP_MODE is ‘0’: Use this arbitration between external interface logic (on SPI SCLK)
configuration when only Active mode functionality is and the CPU interface logic (on system peripheral clock).
required. This arbitration always gives the highest priority to the
external interface logic (host accesses). The external
❐ FIFO mode: Supported. interface logic takes two serial interface clock/bit periods for
❐ EZ mode: Supported. SPI. During this period, the internal logic is denied service to
❐ Command-response mode: Not supported. The the memory buffer. The PSoC 6 MCU provides two
slave (MISO) transmits a value different from a ready programmable options to address this “denial of service”:
(0x62) byte during the reception of the first byte if ■ If the BLOCK bitfield of SCB_CTRL is ‘1’: An internal
command-response mode is attempted in this logic access to the memory buffer is blocked until the
configuration. memory buffer is granted and the external interface logic
■ EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘0’: Use this has completed access. This option provides normal SCB
configuration when both Active and Deep Sleep register functionality, but the blocking time introduces
functionality are required. This configuration relies on the additional internal bus wait states.
externally-clocked functionality to detect the slave ■ If the BLOCK bitfield of SCB_CTRL is ‘0’: An internal
selection and relies on the internally-clocked logic access to the memory buffer is not blocked, but
functionality to access the memory buffer. fails when it conflicts with an external interface logic
The “hand over” from external to internal functionality access. A read access returns the value 0xFFFF:FFFF
relies on a busy/ready byte scheme. This scheme relies and a write access is ignored. This option does not
on the master to retry the current transfer when it introduce additional internal bus wait states, but an
receives a busy byte and requires the master to support access to the memory buffer may not take effect. In this
busy/ready byte interpretation. When the slave is case, the following failures are detected:
selected, INTR_SPI_EC.WAKE_UP is set to ‘1’. The ❐ Read Failure: A read failure is easily detected
associated Deep Sleep functionality interrupt brings the because the returned value is 0xFFFF:FFFF. This
system into Active power mode. value is unique as non-failing memory buffer read
❐ FIFO mode: Supported. The slave (MISO) transmits accesses return an unsigned byte value in the range
0xFF until the CPU is awoken and the TX FIFO is 0x0000:0000-0x0000:00ff.
populated. Any data on the MOSI line will be ❐ Write Failure: A write failure is detected by reading
dropped until clk_scb is enabled see “Deep Sleep to back the written memory buffer location, and con-
Active Transition” on page 331 for more details firming that the read value is the same as the written
❐ EZ mode: Supported. In Deep Sleep power mode, value.
the slave (MISO) transmits a busy (0xFF) byte during

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 Serial Communications Block (SCB)

For both options, a conflicting internal logic access to the memory buffer sets INTR_TX.BLOCKED field to ‘1’ (for write
accesses) and INTR_RX.BLOCKED field to ‘1’ (for read accesses). These fields can be used as either status fields or as
interrupt cause fields (when their associated mask fields are enabled).
If a series of read or write accesses is performed and CTRL.BLOCKED is ‘0’, a failure is detected by comparing the “logical-
or” of all read values to 0xFFFF:FFFF and checking the INTR_TX.BLOCKED and INTR_RX.BLOCKED fields to determine
whether a failure occurred for a series of write or read operations.

Table 28-3. SPI Modes Compatibility

Internally clocked (IC) Externally clocked (EC) (Deep Sleep SCB only)
FIFO EZ CMD_RESP FIFO EZ CMD_RESP
SPI master Yes No No No No No
SPI slave Yes Yes No Yesa Yes Yes
a. In SPI slave FIFO mode, the external-clocked logic does selection detection, then triggers an interrupt to wake up the CPU. Writes will be ignored and reads
will return 0xFF until the CPU is ready and the FIFO is populated.

28.3.5.2 Using SPI Master to Clock Slave

In a normal SPI Master mode transmission, the SCLK is generated only when the SCB is enabled and data is being
transmitted. This can be changed to always generate a clock on the SCLK line while the SCB is enabled. This is used when
the slave uses the SCLK for functional operations other than just the SPI functionality. To enable this, write ‘1’ to the
SCLK_CONTINUOUS (bit 5) of the SCB_SPI_CTRL register.

28.3.5.3 Oversampling and Bit Rate

SPI Master Mode

The SPI master does not support externally clocked mode. In internally clocked mode, the logic operates under internal clock.
The internal clock has higher frequency than the interface clock (SCLK), such that the master can oversample its input
signals (MISO).
The OVS (bits [3:0]) of the SCB_CTRL register specify the oversampling. The oversampling rate is calculated as the value in
OVS register + 1. In SPI master mode, the valid range for oversampling is 4 to 16, when MISO is used; if MISO is not used
then the valid range is 2 to 16. The bit rate is calculated as follows.

Bit Rate = clk_scb/OVS

Equation 28-1
Hence, with clk_scb at 100 MHz, the maximum bit rate is 25 Mbps with MISO, or 50 Mbps without MISO.
The numbers above indicate how fast the SCB hardware can run SCLK. It does not indicate that the master will be able to
correctly receive data from a slave at those speeds. To determine that, the path delay of MISO must be calculated. It can be
calculated using the following equation:

1
--- t SCLK  t SCLK_PCB_D + t DSO + t SCLK_PCB_D + t DSI
2 Equation 28-2
Where:
tSCLK is the period of the SPI clock

tSCLK_PCB_D is the SCLK PCB delay from master to slave

tDSO is the total internal slave delay, time from SCLK edge at slave pin to MISO edge at slave pin

tSCLK_PCB_D is the MISO PCB delay from slave to master

tDSI is the master setup time

Most slave datasheets will list tDSO, It may have a different name; look for MISO output valid after SCLK edge. Most master
datasheets will also list tDSI, or master setup time. tSCLK_PCB_D and tSCLK_PCB_D must be calculated based on specific
PCB geometries.

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 Serial Communications Block (SCB)

If after doing these calculations the desired speed cannot be achieved, then consider using the MISO late sample feature of
the SCB. This can be done by setting the SPI_CTRL.LATE_MISO_SAMPLE register. Late sampling addresses the round-trip
delay associated with transmitting SCLK from the master to the slave and transmitting MISO from the slave to the master.
MISO late sample tells the SCB to sample the incoming MISO signal on the next edge of SCLK, thus allowing for ½ SCLK
cycle more timing margin, see Figure 28-11.
Figure 28-11. MISO Sampling Timing

spi_ select CPOL: 0 , CPHA: 0

spi_clk
spi_ mosi
MSb LSb
spi_ miso
MSb LSb

late MISO sample

normal MISO sample

This changes the equation to:

t SCLK  t SCLK_PCB_D + t DSO + t SCLK_PCB_D + t DSI

Equation 28-3
Because late sample allows for better timing, leave it enabled all the time. The tDSI specification in the PSoC 6 MCU
datasheet assumes late sample is enabled.
Note: The SPI_CTRL.LATE_MISO_SAMPLE is set to ‘0’ by default.

SPI Slave Mode

In SPI slave mode, the OVS field (bits [3:0]) of SCB_CTRL register is not used. The data rate is determined by Equation 26-2
and Equation 26-3. Late MISO sample is determined by the external master in this case, not by
SPI_CTRL.LATE_MISO_SAMPLE.
For PSoC 6 MCUs, tDSO is given in the PSoC 61 datasheet/PSoC 62 datasheet. For internally-clocked mode, it is proportional
to the frequency of the internal clock. For example it may be 20 ns + 3 *tCLK_SCB. Assuming 0 ns PCB delays, and a 0 ns
external master tDSI Equation 26-1 can be re-arranged to tCLK_SCB  ((tSCLK) – 40 ns)/6.

28.3.6 Enabling and Initializing SPI

The SPI must be programmed in the following order:
1. Program protocol specific information using the SCB_SPI_CTRL register. This includes selecting the sub-modes of the
protocol and selecting master-slave functionality. EZSPI and CMD_RESP can be used with slave mode only.
2. Program the OVS field and configure clk_scb as appropriate. See the Clocking System chapter on page 242 for more
information on how to program clocks and connect it to the SCB.
3. Configure SPI GPIO by setting appropriate drive modes and HSIOM settings.
4. Select the desired Slave Select line and polarity in the SCB_SPI_CTRL register.
5. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers:
a. Specify the data frame width. This should always be 8 for EZSPI and CMD_RESP.
b. Specify whether MSb or LSb is the first bit to be transmitted/received. This should always be MSb first for EZSPI and
CMD_RESP.
6. Program the transmitter and receiver FIFOs using the SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL registers respec-
tively, as shown in SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL registers. Only for FIFO mode.
a. Set the trigger level.
b. Clear the transmitter and receiver FIFO and Shift registers.
7. Enable the block (write a ‘1’ to the ENABLED bit of the SCB_CTRL register). After the block is enabled, control bits should
not be changed. Changes should be made after disabling the block; for example, to modify the operation mode (from

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 Serial Communications Block (SCB)

Motorola mode to TI mode) or to go from externally clocked to internally clocked operation. The change takes effect only
after the block is re-enabled. Note: Re-enabling the block causes re-initialization and the associated state is lost (for
example, FIFO content).

28.3.7 I/O Pad Connection

28.3.7.1 SPI Master
Figure 28-12 and Table 28-4 list the use of the I/O pads for SPI Master.
Figure 28-12. SPI Master I/O Pad Connections

spi_clk_out_en spi_clk_out_en spi_ctl

spi_clk_out spi_clk_out

spi_clk
spi_clk_in spi_clk_in
Normal
output mode

spi_select_out_en spi_select_out_en spi_ctl

spi_select_out spi_select_out

spi_select
spi_select_in spi_select_in
Normal
output mode

spi_mosi_out_en spi_mosi_out_en spi_ctl

spi_mosi_out spi_mosi_out

spi_mosi
spi_mosi_in spi_mosi_in
Normal
output mode

0 spi_miso_out_en spi_ctl

don t care spi_miso_out

spi_miso
spi_miso_in spi_miso_in
Input only

Table 28-4. SPI Master I/O Pad Connection Usage

I/O Pads Drive Mode On-chip I/O Signals Usage
spi_clk_out_en
spi_clk Normal output mode Transmit a clock signal
spi_clk_out
spi_select_out_en
spi_select Normal output mode Transmit a select signal
spi_select_out
spi_mosi_out_en
spi_mosi Normal output mode Transmit a data element
spi_mosi_out
spi_miso Input only spi_miso_in Receive a data element

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 Serial Communications Block (SCB)

28.3.7.2 SPI Slave

Figure 28-13 and Table 28-5 list the use of I/O pads for SPI Slave.
Figure 28-13. SPI Slave I/O Pad Connections
0 spi_clk_out_en spi_ctl

don t care spi_clk_out

spi_clk
spi_clk_in spi_clk_in
Input only

0 spi_select_out_en spi_ctl

don t care spi_select_out

spi_select
spi_select_in spi_select_in
Input only

0 spi_mosi_out_en spi_ctl

don t care spi_mosi_out

spi_mosi
spi_mosi_in spi_mosi_in
Input only

i2c_ic_block_ec spi_ctl
spi_miso_out_en

spi_miso_out

spi_miso
spi_miso_in spi_miso_in
Normal output mode
Or
Open-drain mode
spi_ec_miso_out_en spi_ec_ctl

spi_ec_miso_out

Open_Drain is set in the TX_CTRL register. In this mode the SPI MISO pin is actively driven low, and then high-z for driving
high. This means an external pull-up is required for the line to go high. This mode is useful when there are multiple slaves on
the same line. This helps to avoid bus contention issues.

Table 28-5. SPI Slave I/O Signal Description

I/O Pads Drive Mode On-chip I/O Signals Usage
spi_clk Input mode spi_clk_in Receive a clock signal
spi_select Input mode spi_select_in Receive a select signal
spi_mosi Input mode spi_mosi_in Receive a data element
spi_miso_out_en
spi_miso Normal output mode Transmit a data element
spi_miso_out

28.3.7.3 Glitch Avoidance at System Reset

The SPI outputs are in high-impedance digital state when the device is coming out of system reset. This can cause glitches
on the outputs. This is important if you are concerned with SPI master SS0 – SS3 or SCLK output pins activity at either device
startup or when coming out of Hibernate mode. External pull-up or pull-down resistor can be connected to the output pin to
keep it in the inactive state.

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 Serial Communications Block (SCB)

28.3.7.4 Median Filter

This parameter applies a three-tap digital median filter on the input line. The master has one input line: MISO, and the slave
has three input lines: SCLK, MOSI, and SS. This filter reduces the susceptibility to errors. However, minimum oversampling
factor value is increased. The default value is ‘Disabled’. To enable the median filter write a ‘1’ to RX_CTRL.MEDIAN.

28.3.8 SPI Registers

The SPI interface is controlled using a set of 32-bit control and status registers listed in Table 28-6. Some of these registers
are used specifically with the Deep Sleep SCB; for more information on these registers, see the registers TRM.

Table 28-6. SPI Registers

Register Name Operation

SCB_CTRL Enables the SCB, selects the type of serial interface (SPI, UART, I2C), and selects internally and externally
clocked operation, and EZ and non-EZ modes of operation.
SCB_STATUS (Deep Sleep
In EZ mode, this register indicates whether the externally clocked logic is potentially using the EZ memory.
SCB only)
Configures the SPI as either a master or a slave, selects SPI protocols (Motorola, TI, National) and clock-
SCB_SPI_CTRL
based submodes in Motorola SPI (modes 0,1,2,3), selects the type of SS signal in TI SPI.
SCB_SPI_STATUS Indicates whether the SPI bus is busy and sets the SPI slave EZ address in the internally clocked mode.
SCB_TX_CTRL Specifies the data frame width and specifies whether MSb or LSb is the first bit in transmission.
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. Also decides
SCB_RX_CTRL
whether a median filter is to be used on the input interface lines.
Specifies the trigger level, clears the transmitter FIFO and shift registers, and performs the FREEZE opera-
SCB_TX_FIFO_CTRL
tion of the transmitter FIFO.
SCB_RX_FIFO_CTRL Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver.
SCB_TX_FIFO_WR Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation.
Holds the data frame read from the receiver FIFO. Reading a data frame removes the data frame from the
SCB_RX_FIFO_RD FIFO - behavior is similar to that of a POP operation. This register has a side effect when read by software:
a data frame is removed from the FIFO.
Holds the data frame read from the receiver FIFO. Reading a data frame does not remove the data frame
SCB_RX_FIFO_RD_SILENT
from the FIFO; behavior is similar to that of a PEEK operation.
Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by
SCB_TX_FIFO_STATUS the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides
whether the transmitter FIFO holds the valid data.
SCB_RX_FIFO_STATUS Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver.
SCB_EZ_DATA (Deep Sleep
Holds the data in EZ memory location
SCB only)

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 Serial Communications Block (SCB)

28.4 UART A typical UART transfer consists of a start bit followed by

multiple data bits, optionally followed by a parity bit and
The Universal Asynchronous Receiver/Transmitter (UART) finally completed by one or more stop bits. The start and
protocol is an asynchronous serial interface protocol. UART stop bits indicate the start and end of data transmission. The
communication is typically point-to-point. The UART parity bit is sent by the transmitter and is used by the
interface consists of two signals: receiver to detect single bit errors. Because the interface
■ TX: Transmitter output does not have a clock (asynchronous), the transmitter and
receiver use their own clocks; thus, the transmitter and
■ RX: Receiver input receiver need to agree on the baud rate.
Additionally, two side-band signals are used to implement By default, UART supports a data frame width of eight bits.
flow control in UART. Note that the flow control applies only However, this can be configured to any value in the range of
to TX functionality. 4 to 9. This does not include start, stop, and parity bits. The
■ Clear to Send (CTS): This is an input signal to the number of stop bits can be in the range of 1 to 4. The parity
transmitter. When active, the receiver signals to the bit can be either enabled or disabled. If enabled, the type of
transmitter that it is ready to receive. parity can be set to either even parity or odd parity. The
■ Ready to Send (RTS): This is an output signal from the option of using the parity bit is available only in the Standard
receiver. When active, it indicates that the receiver is UART and SmartCard UART modes. For IrDA UART mode,
ready to receive data. the parity bit is automatically disabled.

Not all SCBs support UART mode; refer to the PSoC 61 Note: UART interface does not support external clocking
datasheet/PSoC 62 datasheet for details. operation. Hence, UART operates only in the Active and
Sleep system power modes. UART also supports only the
FIFO buffer mode.
28.4.1 Features
■ Supports UART protocol 28.4.3 UART Modes of Operation
❐ Standard UART
❐ Multi-processor mode 28.4.3.1 Standard Protocol
■ SmartCard (ISO7816) reader A typical UART transfer consists of a start bit followed by
■ IrDA multiple data bits, optionally followed by a parity bit and
■ Supports Local Interconnect Network (LIN) finally completed by one or more stop bits. The start bit
value is always ‘0’, the data bits values are dependent on
❐ Break detection the data transferred, the parity bit value is set to a value
❐ Baud rate detection guaranteeing an even or odd parity over the data bits, and
❐ Collision detection (ability to detect that a driven bit the stop bit value is ‘1’. The parity bit is generated by the
value is not reflected on the bus, indicating that transmitter and can be used by the receiver to detect single
another component is driving the same bus) bit transmission errors. When not transmitting data, the TX
line is ‘1’ – the same value as the stop bits.
■ Data frame size programmable from 4 to 16 bits
■ Programmable number of STOP bits, which can be set Because the interface does not have a clock, the transmitter
in terms of half bit periods between 1 and 4 and receiver must agree upon the baud rate. The transmitter
and receiver have their own internal clocks. The receiver
■ Parity support (odd and even parity)
clock runs at a higher frequency than the bit transfer
■ Median filter on RX input frequency, such that the receiver may oversample the
■ Programmable oversampling incoming signal.
■ Start skipping The transition of a stop bit to a start bit is represented by a
■ Hardware flow control change from ‘1’ to ‘0’ on the TX line. This transition can be
used by the receiver to synchronize with the transmitter
28.4.2 General Description clock. Synchronization at the start of each data transfer
allows error-free transmission even in the presence of
Figure 28-14 illustrates a standard UART TX and RX. frequency drift between transmitter and receiver clocks. The
required clock accuracy is dependent on the data transfer
Figure 28-14. UART Example
size.
Rx
Tx
The stop period or the amount of stop bits between
UART UART successive data transfers is typically agreed upon between
Rx transmitter and receiver, and is typically in the range of 1 to
Tx
3-bit transfer periods.

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 Serial Communications Block (SCB)

Figure 28-15 illustrates the UART protocol.

Figure 28-15. UART, Standard Protocol Example

Two successive data transfers (7data bits, 1 parity bit, 2 stop bits)
Tx / Rx

IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA

LEGEND:
Tx / Rx : Transmit or Receive line

The receiver oversamples the incoming signal; the value of the sample point in the middle of the bit transfer period (on the
receiver’s clock) is used. Figure 28-16 illustrates this.
Figure 28-16. UART, Standard Protocol Example (Single Sample)

Tx clock

Tx / Rx
IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA

Rx clock

Sample points Sample points

Synchronisation Synchronisation

LEGEND:
Tx / Rx : Transmit or Receive line

Alternatively, three samples around the middle of the bit transfer period (on the receiver’s clock) are used for a majority vote
to increase accuracy; this is enabled by enabling the MEDIAN filter in the SCB_RX_CTRL register. Figure 28-17 illustrates
this.
Figure 28-17. UART, Standard Protocol (Multiple Samples)

Tx clock

Tx / Rx
IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA

Rx clock

Sample points Sample points

Synchronisation Synchronisation

LEGEND:
Tx / Rx : Transmit or Receive line

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 Serial Communications Block (SCB)

Parity
This functionality adds a parity bit to the data frame and is used to identify single-bit data frame errors. The parity bit is always
directly after the data frame bits.
The transmitter calculates the parity bit (when UART_TX_CTRL.PARITY_ENABLED is 1) from the data frame bits, such that
data frame bits and parity bit have an even (UART_TX_CTRL.PARITY is 0) or odd (UART_TX_CTRL.PARITY is 1) parity. The
receiver checks the parity bit (when UART_RX_CTRL.PARITY_ENABLED is 1) from the received data frame bits, such that
data frame bits and parity bit have an even (UART_RX_CTRL.PARITY is 0) or odd (UART_RX_CTRL.PARITY is 1) parity.
Parity applies to both TX and RX functionality and dedicated control fields are available.
■ Transmit functionality: UART_TX_CTRL.PARITY and UART_TX_CTRL.PARITY_ENABLED.
■ Receive functionality: UART_RX_CTRL.PARITY and UART_RX_CTRL.PARITY_ENABLED.
When a receiver detects a parity error, the data frame is either put in RX FIFO
(UART_RX_CTRL.DROP_ON_PARITY_ERROR is 0) or dropped (UART_RX_CTRL.DROP_ON_PARITY_ERROR is 1).
The following figures illustrate the parity functionality (8-bit data frame).
Figure 28-18. UART Parity Examples
parity enabled, even parity
P
uart_tx/uart_rx STOP START 1 0 1 0 1 0 1 0 0 STOP
st nd rd th th th th th th
1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit
parity enabled, even parity
P
uart_tx/uart_rx STOP START 1 1 1 0 1 0 1 0 1 STOP

parity enabled, odd parity

P
uart_tx/uart_rx STOP START 1 0 1 0 1 0 1 0 1 STOP

parity enabled, odd parity

P
uart_tx/uart_rx STOP START 1 1 1 0 1 0 1 0 0 STOP

Start Skipping
Start skipping applies only to receive functionality. The standard UART mode supports “start skipping”. Regular receive
operation synchronizes on the START bit period (a 1 to 0 transition on the UART RX line), start skipping receive operation
synchronizes on the first received data frame bit, which must be a ‘1’ (a 0 to 1 transition on UART RX).
Start skipping is used to allow for wake up from system Deep Sleep mode using UART. The process is described as follows:
1. Before entering Deep Sleep power mode, UART receive functionality is disabled and the GPIO is programmed to set an
interrupt cause to ‘1’ when UART RX line has a ‘1’ to ‘0’ transition (START bit).
2. While in Deep Sleep mode, the UART receive functionality is not functional.
3. The GPIO interrupt is activated on the START bit and the system transitions from Deep Sleep to Active power mode.
4. The CPU enables UART receive functionality, with UART_RX_CTRL.SKIP_START bitfield set to ‘1’.
5. The UART receiver synchronizes data frame receipt on the next ‘0’ to ‘1’ transition. If the UART receive functionality is
enabled in time, this is the transition from the START bit to the first received data frame bit.
6. The UART receiver proceeds with normal operation; that is, synchronization of successive data frames is on the START
bit period.
Figure 28-19 illustrates the process.

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 Serial Communications Block (SCB)

Figure 28-19. UART Start Skip and Wakeup from Deep Sleep
uart_rx IDLE/STOP START D START
st
1 bit

power mode Active A -> DS Deep Sleep DS -> A Active

2 UART not operational 5 UART RX synchronizes

4 CPU enables Rx functionality

UART Rx
1 Setup IOSS/GPIO 3 IOSS/GPIO wake up interrupt 6
synchronizes

Note that the above process works only for lower baud rates. The Deep Sleep to Active power mode transition and CPU
enabling the UART receive functionality should take less than 1-bit period to ensure that the UART receiver is active in time to
detect the ‘0’ to ‘1’ transition.
In step 4 of the above process, the firmware takes some time to finish the wakeup interrupt routine and enable the UART
receive functionality before the block can detect the input rising edge on the UART RX line.
If the above steps cannot be completed in less than 1 bit time, first send a “dummy” byte to the device to wake it up before
sending real UART data. In this case, the SKIP_START bit can be left as 0. For more information on how to perform this in
firmware, visit the UART section of the PDL.

Break Detection
Break detection is supported in the standard UART mode. This functionality detects when UART RX line is low (0) for more
than UART_RX_CTRL.BREAK_WIDTH bit periods. The break width should be larger than the maximum number of low (0) bit
periods in a regular data transfer, plus an additional 1-bit period. The additional 1-bit period is a minimum requirement and
preferably should be larger. The additional bit periods account for clock inaccuracies between transmitter and receiver.
For example, for an 8-bit data frame with parity support, the maximum number of low (0) bit periods is 10 (START bit, 8 ‘0’
data frame bits, and one ‘0’ parity bit). Therefore, the break width should be larger than 10 + 1 = 11
(UART_RX_CTRL.BREAK_WIDTH can be set to 11).
Note that the break detection applies only to receive functionality. A UART transmitter can generate a break by temporarily
increasing TX_CTRL.DATA_WIDTH and transmitting an all zeroes data frame. A break is used by the transmitter to signal a
special condition to the receiver. This condition may result in a reset, shut down, or initialization sequence at the receiver.
Break detection is part of the LIN protocol. When a break is detected, the INTR_RX.BREAK_DETECT interrupt cause is set
to ‘1’. Figure 28-20 illustrates a regular data frame and break frame (8-bit data frame, parity support, and a break width of 12-
bit periods).
Figure 28-20. UART – Regular Frame and Break Frame
Regular frame

uart_rx STOP START D D D D D D D D P STOP

st nd rd th th th th th th
1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit
Break frame (12 low/0-bit periods)

uart_rx STOP START STOP

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 Serial Communications Block (SCB)

Flow Control
The standard UART mode supports flow control. Modem flow control controls the pace at which the transmitter transfers data
to the receiver. Modem flow control is enabled through the UART_FLOW_CTRL.CTS_ENABLED register field. When this
field is ‘0’, the transmitter transfers data when its TX FIFO is not empty. When ‘1’, the transmitter transfers data when UART
CTS line is active and its TX FIFO is not empty.
Note that the flow control applies only to TX functionality. Two UART side-band signal are used to implement flow control:
■ UART RTS (uart_rts_out): This is an output signal from the receiver. When active, it indicates that the receiver is ready to
receive data (RTS: Ready to Send).
■ UART CTS (uart_cts_in): This is an input signal to the transmitter. When active, it indicates that the transmitter can trans-
fer data (CTS: Clear to Send).
The receiver’s uart_rts_out signal is connected to the transmitter’s uart_cts_in signal. The receiver’s uart_rts_out signal is de-
rived by comparing the number of used receive FIFO entries with the UART_FLOW_CTRL.TRIGGER_LEVEL field. If the
number of used receive FIFO entries are less than UART_FLOW_CTRL.TRIGGER_LEVEL, uart_rts_out is activated.
Typically, the UART side-band signals are active low. However, sometimes active high signaling is used. Therefore, the
polarity of the side-band signals can be controlled using bitfields UART_FLOW_CTRL.RTS_POLARITY and
UART_FLOW_CTRL.CTS_POLARITY. Figure 28-21 gives an overview of the flow control functionality.
Figure 28-21. UART Flow Control Connection
Receiver (Rx) Transmitter (Tx)
uart_rx_ctl uart_tx_ctl
Rx FIFO Tx FIFO
uart_rx_in uart_tx_out

<
UART_FLOW_CTRL.TRIGGER_LEVEL[] uart_rts_out uart_cts_in

UART_FLOW_CTRL.RTS_POLARITY UART_FLOW_CTRL.CTS_ENABLED

UART_FLOW_CTRL.CTS_POLARITY

UART Multi-Processor Mode

The UART_MP (multi-processor) mode is defined with single-master-multi-slave topology, as Figure 28-22 shows. This mode
is also known as UART 9-bit protocol because the data field is nine bits wide. UART_MP is part of Standard UART mode.
Figure 28-22. UART MP Mode Bus Connections

UART MP
Master

Tx Rx
Master Tx

Master Rx

Tx Rx Tx Rx Tx Rx

UART MP UART MP UART MP

Slave 1 Slave 2 Slave 3

The main properties of UART_MP mode are:

■ Single master with multiple slave concept (multi-drop network).
■ Each slave is identified by a unique address.
■ Using 9-bit data field, with the ninth bit as address/data flag (MP bit). When set high, it indicates an address byte; when
set low it indicates a data byte. A data frame is illustrated in Figure 28-23.
■ Parity bit is disabled.

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 Serial Communications Block (SCB)

Figure 28-23. UART MP Address and Data Frame

DATA Field

IDLE START DATA DATA DATA DATA DATA DATA DATA DATA MP STOP

The SCB can be used as either master or slave device in UART_MP mode. Both SCB_TX_CTRL and SCB_RX_CTRL
registers should be set to 9-bit data frame size. When the SCB works as UART_MP master device, the firmware changes the
MP flag for every address or data frame. When it works as UART_MP slave device, the MP_MODE field of the
SCB_UART_RX_CTRL register should be set to ‘1’. The SCB_RX_MATCH register should be set for the slave address and
address mask. The matched address is written in the RX_FIFO when ADDR_ACCEPT field of the SCB_CTRL register is set
to ‘1’. If the received address does not match its own address, then the interface ignores the following data, until next address
is received for compare.

Configuring the SCB as Standard UART Interface

To configure the SCB as a standard UART interface, set various register bits in the following order:
1. Configure the SCB as UART interface by writing ‘10b’ to the MODE field (bits [25:24]) of the SCB_CTRL register.
2. Configure the UART interface to operate as a Standard protocol by writing ‘00’ to the MODE field (bits [25:24]) of the
SCB_UART_CTRL register.
3. To enable the UART MP Mode or UART LIN Mode, write ‘1’ to the MP_MODE (bit 10) or LIN_MODE (bit 12) respectively
of the SCB_UART_RX_CTRL register.
4. Follow steps 2 to 4 described in “Enabling and Initializing the UART” on page 348.
For more information on these registers, see the registers TRM.

28.4.3.2 UART Local Interconnect Network (LIN) Mode

The LIN protocol is supported by the SCB as part of the standard UART. LIN is designed with single-master-multi-slave
topology. There is one master node and multiple slave nodes on the LIN bus. The SCB UART supports both LIN master and
slave functionality. The LIN specification defines both physical layer (layer 1) and data link layer (layer 2). Figure 28-24
illustrates the UART_LIN and LIN transceiver.
Figure 28-24. UART_LIN and LIN Transceiver
LIN Master 1 LIN Slave 1 LIN Slave 2

UART LIN UART LIN UART LIN

Tx Rx Tx Rx Tx Rx

LIN Transceiver LIN Transceiver LIN Transceiver

LIN BUS

LIN protocol defines two tasks:

■ Master task: This task involves sending a header packet to initiate a LIN transfer.
■ Slave task: This task involves transmitting or receiving a response.
The master node supports master task and slave task; the slave node supports only slave task, as shown in Figure 28-25.

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 Serial Communications Block (SCB)

Figure 28-25. LIN Bus Nodes and Tasks

Master Node Slave Node Slave Node

Master Task

Slave Task Slave Task Slave Task

LIN bus

LIN Frame Structure

LIN is based on the transmission of frames at pre-determined moments of time. A frame is divided into header and response
fields, as shown in Figure 28-26.
■ The header field consists of:
❐ Break field (at least 13 bit periods with the value ‘0’).
❐ Sync field (a 0x55 byte frame). A sync field can be used to synchronize the clock of the slave task with that of the mas-
ter task.
❐ Identifier field (a frame specifying a specific slave).
■ The response field consists of data and checksum.
Figure 28-26. LIN Frame Structure

In LIN protocol communication, the least significant bit (LSb) of the data is sent first and the most significant bit (MSb) last.
The start bit is encoded as zero and the stop bit is encoded as one. The following sections describe all the byte fields in the
LIN frame.

Break Field
Every new frame starts with a break field, which is always generated by the master. The break field has logical zero with a
minimum of 13 bit times and followed by a break delimiter. The break field structure is as shown in Figure 28-27.
Figure 28-27. LIN Break Field

Sync Field
This is the second field transmitted by the master in the header field; its value is 0x55. A sync field can be used to synchronize
the clock of the slave task with that of the master task for automatic baud rate detection. Figure 28-28 shows the LIN sync
field structure.
Figure 28-28. LIN Sync Field

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 Serial Communications Block (SCB)

Protected Identifier (PID) Field more unconditional frames. The unconditional frames
associated with an event triggered frame should:
A protected identifier field consists of two sub-fields: the
frame identifier (bits 0-5) and the parity (bit 6 and bit 7). The ■ Have equal length
PID field structure is shown in Figure 28-29. ■ Use the same checksum model (either classic or
■ Frame identifier: The frame identifiers are divided into enhanced)
three categories ■ Reserve the first data field to its protected identifier
❐ Values 0 to 59 (0x3B) are used for signal carrying ■ Be published by different slave nodes
frames ■ Not be included directly in the same schedule table as
❐ 60 (0x3C) and 61 (0x3D) are used to carry diagnostic the event-triggered frame
and configuration data
❐ 62 (0x3E) and 63 (0x3F) are reserved for future pro- Sporadic Frame. The purpose of the sporadic frames is to
tocol enhancements merge some dynamic behavior into the schedule table
without affecting the rest of the schedule table. These
■ Parity: Frame identifier bits are used to calculate the
frames have a group of unconditional frames that share the
parity
frame slot. When the sporadic frame is due for transmission,
Figure 28-29 shows the PID field structure. the unconditional frames are checked whether they have
any updated signals. If no signals are updated, no frame will
Figure 28-29. PID Field be transmitted and the frame slot will be empty.

Diagnostic Frames. Diagnostic frames always carry

transport layer, and contains eight data bytes.
Data. In LIN, every frame can carry a minimum of one byte The frame identifier for diagnostic frame is:
and maximum of eight bytes of data. Here, the LSb of the ■ Master request frame (0x3C), or
data byte is sent first and the MSb of the data byte is sent
■ Slave response frame (0x3D)
last.
Before transmitting a master request frame, the master task
Checksum. The checksum is the last byte field in the LIN queries its diagnostic module to see whether it will be
frame. It is calculated by inverting the 8-bit sum along with transmitted or whether the bus will be silent. A slave
carryover of all data bytes only or the 8-bit sum with the response frame header will be sent unconditionally. The
carryover of all data bytes and the PID field. There are two slave tasks publish and subscribe to the response according
types of checksums in LIN frames. They are: to their diagnostic modules.
■ Classic checksum: the checksum calculated over all the
data bytes only (used in LIN 1.x slaves). Reserved Frames. These frames are reserved for future
use; their frame identifiers are 0x3E and 0x3F.
■ Enhanced checksum: the checksum calculated over all
the data bytes along with the protected identifier (used in
LIN Go-To-Sleep and Wake-Up
LIN 2.x slaves).
The LIN protocol has the feature of keeping the LIN bus in
LIN Frame Types Sleep mode, if the master sends the go-to-sleep command.
The go-to-sleep command is a master request frame (ID =
The type of frame refers to the conditions that need to be
0x3C) with the first byte field is equal to 0x00 and rest set to
valid to transmit the frame. According to the LIN
0xFF. The slave node application may still be active after the
specification, there are five different types of LIN frames. A
go-to-sleep command is received. This behavior is
node or cluster does not have to support all frame types.
application specific. The LIN slave nodes automatically
enter Sleep mode if the LIN bus inactivity is more than four
Unconditional Frame. These frames carry the signals and
seconds.
their frame identifiers (of 0x00 to 0x3B range). The
subscriber will receive the frames and make it available to Wake-up can be initiated by any node connected to the LIN
the application; the publisher of the frame will provide the bus – either LIN master or any of the LIN slaves by forcing
response to the header. the bus to be dominant for 250 µs to 5 ms. Each slave
should detect the wakeup request and be ready to process
Event-Triggered Frame. The purpose of an event- headers within 100 ms. The master should also detect the
triggered frame is to increase the responsiveness of the LIN wakeup request and start sending headers when the slave
cluster without assigning too much of the bus bandwidth to nodes are active.
polling of multiple slave nodes with seldom occurring
events. Event-triggered frames carry the response of one or To support LIN, a dedicated (off-chip) line driver/receiver is
required. Supply voltage range on the LIN bus is 7 V to 18 V.

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 Serial Communications Block (SCB)

Typically, LIN line drivers will drive the LIN line with the value may be sent from the receiver to the transmitter. A NACK is
provided on the SCB TX line and present the value on the always ‘0’. Both master and slave may drive the same line,
LIN line to the SCB RX line. By comparing TX and RX lines although never at the same time.
in the SCB, bus collisions can be detected (indicated by the
A SmartCard transfer has the transmitter drive the start bit
SCB_UART_ARB_LOST field of the SCB_INTR_TX
and data bits (and optionally a parity bit). After these bits, it
register).
enters its stop period by releasing the bus. Releasing results
in the line being ‘1’ (the value of a stop bit). After one bit
28.4.3.3 SmartCard (ISO7816)
transfer period into the stop period, the receiver may drive a
ISO7816 is asynchronous serial interface, defined with NACK on the line (a value of ‘0’) for one bit transfer period.
single-master-single slave topology. ISO7816 defines both This NACK is observed by the transmitter, which reacts by
Reader (master) and Card (slave) functionality. For more extending its stop period by one bit transfer period. For this
information, refer to the ISO7816 Specification. Only the protocol to work, the stop period should be longer than one
master (reader) function is supported by the SCB. This bit transfer period. Note that a data transfer with a NACK
block provides the basic physical layer support with takes one bit transfer period longer, than a data transfer
asynchronous character transmission. The UART_TX line is without a NACK. Typically, implementations use a tristate
connected to SmartCard I/O line by internally multiplexing driver with a pull-up resistor, such that when the line is not
between UART_TX and UART_RX control modules. transmitting data or transmitting the Stop bit, its value is ‘1’.
The SmartCard transfer is similar to a UART transfer, with Figure 28-30 illustrates the SmartCard protocol.
the addition of a negative acknowledgement (NACK) that
Figure 28-30. SmartCard Example
Two successive data transfers (7 data bits, 1 parity bit, 2 stop bits) without NACK
Tx / Rx

IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP START DATA DATA DATA

Two successive data transfers (7data bits, 1 parity bit, 2 stop bits) with NACK
Tx / Rx

IDLE START DATA DATA DATA DATA DATA DATA DATA PAR STOP NACK STOP START DATA DATA

LEGEND:
Tx / Rx : Transmit or Receive line

The communication Baud rate while using SmartCard is given as:

Baud rate = Fscbclk/Oversample

Configuring SCB as UART SmartCard Interface

To configure the SCB as a UART SmartCard interface, set various register bits in the following order; note that ModusToolbox
does all this automatically with the help of GUIs. For more information on these registers, see the registers TRM.
1. Configure the SCB as UART interface by writing ‘10b’ to the MODE (bits [25:24]) of the SCB_CTRL register.
2. Configure the UART interface to operate as a SmartCard protocol by writing ‘01’ to the MODE (bits [25:24]) of the
SCB_UART_CTRL register.
3. Follow steps 2 to 4 described in “Enabling and Initializing the UART” on page 348.

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 Serial Communications Block (SCB)

28.4.3.4 Infrared Data Association (IrDA)

The SCB supports the IrDA protocol for data rates of up to 115.2 kbps using the UART interface. It supports only the basic
physical layer of IrDA protocol with rates less than 115.2 kbps. Hence, the system instantiating this block must consider how
to implement a complete IrDA communication system with other available system resources.
The IrDA protocol adds a modulation scheme to the UART signaling. At the transmitter, bits are modulated. At the receiver,
bits are demodulated. The modulation scheme uses a Return-to-Zero-Inverted (RZI) format. A bit value of ‘0’ is signaled by a
short ‘1’ pulse on the line and a bit value of ‘1’ is signaled by holding the line to ‘0’. For these data rates (<=115.2 kbps), the
RZI modulation scheme is used and the pulse duration is 3/16 of the bit period. The sampling clock frequency should be set
16 times the selected baud rate, by configuring the SCB_OVS field of the SCB_CTRL register. In addition, the PSoC 6 MCU
SCB supports a low-power IrDA receiver mode, which allows it to detect pulses with a minimum width of 1.41 µs.
Different communication speeds under 115.2 kbps can be achieved by configuring clk_scb frequency. Additional allowable
rates are 2.4 kbps, 9.6 kbps, 19.2 kbps, 38.4 kbps, and 57.6 kbps. Figure 28-31 shows how a UART transfer is IrDA
modulated.
Figure 28-31. IrDA Example

Two successive data transfers (7 data bits, 1 parity bit, 2 stop bits)
Tx / Rx

IDLE START PAR STOP START

IrDA
Tx / Rx

LEGEND:
Tx / Rx : Transmit or Receive line

Configuring the SCB as a UART IrDA Interface

To configure the SCB as a UART IrDA interface, set various register bits in the following order; note that ModusToolbox does
all this automatically with the help of GUIs. For more information on these registers, see the registers TRM.
1. Configure the SCB as a UART interface by writing ‘10b’ to the MODE (bits [25:24]) of the SCB_CTRL register.
2. Configure the UART interface to operate as IrDA protocol by writing ‘10’ to the MODE (bits [25:24]) of the SCB_UART_C-
TRL register.
3. Enable the Median filter on the input interface line by writing ‘1’ to MEDIAN (bit 9) of the SCB_RX_CTRL register.
4. Configure the SCB as described in “Enabling and Initializing the UART” on page 348.

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 Serial Communications Block (SCB)

28.4.4 Clocking and Oversampling 28.4.5 Enabling and Initializing the UART
The UART protocol is implemented using clk_scb as an The UART must be programmed in the following order:
oversampled multiple of the baud rate. For example, to 1. Program protocol specific information using the
implement a 100-kHz UART, clk_scb could be set to 1 MHz UART_TX_CTRL, UART_RX_CTRL, and
and the oversample factor set to ‘10’. The oversampling is UART_FLOW_CTRL registers. This includes selecting
set using the SCB_CTRL.OVS register field. The the submodes of the protocol, transmitter-receiver
oversampling value is SCB_CTRL.OVS + 1. In the UART functionality, and so on.
standard sub-mode (including LIN) and the SmartCard sub-
2. Program the generic transmitter and receiver information
mode, the valid range for the OVS field is [7, 15].
using the SCB_TX_CTRL and SCB_RX_CTRL
In UART transmit IrDA sub-mode, this field indirectly registers.
specifies the oversampling. Oversampling determines the a. Specify the data frame width.
interface clock per bit cycle and the width of the pulse. This
b. Specify whether MSb or LSb is the first bit to be
sub-mode has only one valid OVS value–16 (which is a
transmitted or received.
value of 0 in the OVS field of the SCB_CTRL register); the
pulse width is roughly 3/16 of the bit period (for all bit rates). 3. Program the transmitter and receiver FIFOs using the
SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL
In UART receive IrDA sub-mode (1.2, 2.4, 9.6, 19.2, 38.4, registers, respectively.
57.6, and 115.2 kbps), this field indirectly specifies the
a. Set the trigger level.
oversampling. In normal transmission mode, this pulse is
approximately 3/16 of the bit period (for all bit rates). In low- b. Clear the transmitter and receiver FIFO and Shift
power transmission mode, this pulse is potentially smaller registers.
(down to 1.62 µs typical and 1.41 µs minimal) than 3/16 of 4. Enable the block (write a ‘1’ to the ENABLE bit of the
the bit period (for less than 115.2 kbps bit rates). SCB_CTRL register). After the block is enabled, control
bits should not be changed. Changes should be made
Pulse widths greater than or equal to two SCB input clock
after disabling the block; for example, to modify the
cycles are guaranteed to be detected by the receiver. Pulse
operation mode (from SmartCard to IrDA). The change
widths less than two clock cycles and greater than or equal
takes effect only after the block is re-enabled. Note that
to one SCB input clock cycle may be detected by the
re-enabling the block causes re-initialization and the
receiver. Pulse widths less than one SCB input clock cycle
associated state is lost (for example FIFO content).
will not be detected by the receiver. Note that the
SCB_RX_CTRL.MEDIAN should be set to ‘1’ for IrDA
receiver functionality.
The SCB input clock and the oversampling together
determine the IrDA bit rate. Refer to the registers TRM for
more details on the OVS values for different baud rates.

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 Serial Communications Block (SCB)

28.4.6 I/O Pad Connection

28.4.6.1 Standard UART Mode
Figure 28-32 and Table 28-7 list the use of the I/O pads for the Standard UART mode.
Figure 28-32. Standard UART Mode I/O Pad Connections

1 uart_tx_out_en uart_tx_ctl

uart_tx_out uart_tx_out

uart_tx
uart_tx_in uart_tx_in
Normal
output mode
0 uart_rx_out_en uart_rx_ctl

don t care uart_rx_out

uart_rx
uart_rx_in uart_rx_in
Input only

Table 28-7. UART I/O Pad Connection Usage

I/O Pads Drive Mode On-chip I/O Signals Usage
uart_tx_out_en
uart_tx Normal output mode Transmit a data element
uart_tx_out
uart_rx Input only uart_rx_in Receive a data element

28.4.6.2 SmartCard Mode

Figure 28-33 and Table 28-8 list the use of the I/O pads for the SmartCard mode.
Figure 28-33. SmartCard Mode I/O Pad Connections
uart_tx_out_en uart_tx_out_en uart_tx_ctl
uart_tx_out
Open drain uart_tx_out
(pull-up)

uart_tx
uart_tx_in uart_tx_in

uart_rx_out_en uart_rx_ctl

uart_rx_out

uart_rx_in

Table 28-8. SmartCard Mode I/O Pad Connections

On-chip I/O
I/O Pads Drive Mode Usage
Signals
Used to receive a data element.
uart_tx_in
Open drain with Receive a negative acknowledgement of a transmitted data element
uart_tx
pull-up uart_tx_out_en Transmit a data element.
uart_tx_out Transmit a negative acknowledgement to a received data element.

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 Serial Communications Block (SCB)

28.4.6.3 LIN Mode

Figure 28-34 and Table 28-9 list the use of the I/O pads for LIN mode.
Figure 28-34. LIN Mode I/O Pad Connections

1 uart_tx_out_en uart_tx_ctl

Normal uart_tx_out uart_tx_out

output mode

LIN uart_tx
uart_tx_in uart_tx_in
transceiver
chip
0 uart_rx_out_en uart_rx_ctl
LIN

Input only don t care uart_rx_out

uart_rx
uart_rx_in uart_rx_in

Table 28-9. LIN Mode I/O Pad Connections

On-chip I/O
I/O Pads Drive Mode Usage
Signals
Normal output uart_tx_out_en
uart_tx Transmit a data element.
mode uart_tx_out
uart_rx Input only uart_rx_in Receive a data element.

28.4.6.4 IrDA Mode

Figure 28-35 and Table 28-10 list the use of the I/O pads for IrDA mode.
Figure 28-35. IrDA Mode I/O Pad Connections

1 uart_tx_out_en uart_tx_ctl
Normal
uart_tx_out uart_tx_out
output mode

IrDA uart_tx
uart_tx_in uart_tx_in
transducer
module
0 uart_rx_out_en uart_rx_ctl
IrDA
don t care uart_rx_out
Input only

uart_rx
uart_rx_in uart_rx_in

Table 28-10. IrDA Mode I/O Pad Connections

On-chip I/O
I/O Pads Drive Mode Usage
Signals
Normal output uart_tx_out_en
uart_tx Transmit a data element.
mode uart_tx_out
uart_rx Input only uart_rx_in Receive a data element.

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 Serial Communications Block (SCB)

28.4.7 UART Registers

The UART interface is controlled using a set of 32-bit registers listed in Table 28-11. For more information on these registers,
see the registers TRM.

Table 28-11. UART Registers

Register Name Operation
SCB_CTRL Enables the SCB; selects the type of serial interface (SPI, UART, I2C)
Used to select the sub-modes of UART (standard UART, SmartCard, IrDA), also used for local loop back
SCB_UART_CTRL
control.
Used to specify the BR_COUNTER value that determines the bit period. This is used to set the accuracy
SCB_UART_RX_STATUS
of the SCB clock. This value provides more granularity than the OVS bit in SCB_CTRL register.
Used to specify the number of stop bits, enable parity, select the type of parity, and enable retransmission
SCB_UART_TX_CTRL
on NACK.
Performs same function as SCB_UART_TX_CTRL but is also used for enabling multi processor mode,
SCB_UART_RX_CTRL
LIN mode drop on parity error, and drop on frame error.
SCB_TX_CTRL Used to specify the data frame width and to specify whether MSb or LSb is the first bit in transmission.
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. Also decides
SCB_RX_CTRL
whether a median filter is to be used on the input interface lines.
SCB_UART_FLOW_CONTROL Configures flow control for UART transmitter.

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 Serial Communications Block (SCB)

28.5 Inter Integrated Circuit (I2C)

This section explains the I2C implementation in the PSoC 6 MCU. For more information on the I2C protocol specification, refer
to the I2C-bus specification available on the NXP website.

28.5.1 Features
This block supports the following features:
■ Master, slave, and master/slave mode
■ Standard-mode (100 kbps), fast-mode (400 kbps), and fast-mode plus (1000 kbps) data-rates
■ 7-bit slave addressing
■ Clock stretching
■ Collision detection
■ Programmable oversampling of I2C clock signal (SCL)
■ Auto ACK when RX FIFO not full, including address
■ General address detection
■ FIFO Mode
■ EZ and CMD_RESP modes

28.5.2 General Description

Figure 28-36 illustrates an example of an I2C communication network.

Figure 28-36. I2C Interface Block Diagram

VDD

Rp Rp

SCL

SDA

I2C
Master I2C Slave I2C Slave I2C Slave

The standard I2C bus is a two wire interface with the following lines:
■ Serial Data (SDA)
■ Serial Clock (SCL)
I2C devices are connected to these lines using open collector or open-drain output stages, with pull-up resistors (Rp). A
simple master/slave relationship exists between devices. Masters and slaves can operate as either transmitter or receiver.
Each slave device connected to the bus is software addressable by a unique 7-bit address.

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28.5.3 External Electrical Connections

As shown in Figure 28-37, the I2C bus requires external pull-up resistors. The pull-up resistors (RP) are primarily determined
by the supply voltage, bus speed, and bus capacitance. For detailed information on how to calculate the optimum pull-up
resistor value for your design Cypress recommends using the UM10204 I2C-bus specification and user manual Rev. 6,
available from the NXP website at www.nxp.com.
Figure 28-37. Connection of Devices to the I2C Bus
+VDD

pull-up
Rp Rp
resistors

SDA (Serial Data Line)

SCL (Serial Clock Line)

Device 1 Device 2

For most designs, the default values shown inTable 28-12 provide excellent performance without any calculations. The
default values were chosen to use standard resistor values between the minimum and maximum limits.

Table 28-12. Recommended Default Pull-up Resistor Values

Standard Mode (0 – 100 kbps) Fast Mode (0 – 400 kbps) Fast Mode Plus (0 – 1000 kbps) Units
4.7 k, 5% 1.74 k, 1% 620, 5% 

These values work for designs with 1.8 V to 5.0 V VDD, less than 200 pF bus capacitance (CB), up to 25 µA of total input
leakage (IIL), up to 0.4 V output voltage level (VOL), and a max VIH of 0.7 * VDD. Calculation of custom pull-up resistor values
is required if your design does not meet the default assumptions, you use series resistors (RS) to limit injected noise, or you
want to maximize the resistor value for low power consumption. Calculation of the ideal pull-up resistor value involves finding
a value between the limits set by three equations detailed in the NXP I2C specification. These equations are:

RPMIN = (VDD(max) – VOL(max)) / IOL(min)

Equation 28-4

RPMAX = TR(max) / 0.8473 x CB(max)

Equation 28-5

RPMAX = VDD(min) – (VIH(min) + VNH(min)) / IIH(max)

Equation 28-6
Equation parameters:
■ VDD = Nominal supply voltage for I2C bus
■ VOL = Maximum output low voltage of bus devices
■ IOL= Low-level output current from I2C specification
■ TR = Rise time of bus from I2C specification
■ CB = Capacitance of each bus line including pins and PCB traces
■ VIH = Minimum high-level input voltage of all bus devices
■ VNH = Minimum high-level input noise margin from I2C specification
■ IIH = Total input leakage current of all devices on the bus

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 Serial Communications Block (SCB)

The supply voltage (VDD) limits the minimum pull-up resistor 28.5.4.1 Clock Stretching
value due to bus devices maximum low output voltage (VOL)
specifications. Lower pull-up resistance increases current When a slave device is not yet ready to process data, it may
through the pins and can therefore exceed the spec drive a ‘0’ on the SCL line to hold it down. Due to the
conditions of VOH. Equation 26-4 is derived using Ohm's law implementation of the I/O signal interface, the SCL line
to determine the minimum resistance that will still meet the value will be ‘0’, independent of the values that any other
VOL specification at 3 mA for standard and fast modes, and master or slave may be driving on the SCL line. This is
20 mA for fast mode plus at the given VDD. known as clock stretching and is the only situation in which
a slave drives the SCL line. The master device monitors the
Equation 26-5 determines the maximum pull-up resistance SCL line and detects it when it cannot generate a positive
due to bus capacitance. Total bus capacitance is comprised clock pulse (‘1’) on the SCL line. It then reacts by delaying
of all pin, wire, and trace capacitance on the bus. The higher the generation of a positive edge on the SCL line, effectively
the bus capacitance the lower the pull-up resistance synchronizing with the slave device that is stretching the
required to meet the specified bus speeds rise time due to clock. The SCB on the PSoC 6 MCU can and will stretch the
RC delays. Choosing a pull-up resistance higher than clock.
allowed can result in failing timing requirements resulting in
communication errors. Most designs with five of fewer I2C 28.5.4.2 Bus Arbitration
devices and up to 20 centimeters of bus trace length have
less than 100 pF of bus capacitance. The I2C protocol is a multi-master, multi-slave interface. Bus
arbitration is implemented on master devices by monitoring
A secondary effect that limits the maximum pull-up resistor the SDA line. Bus collisions are detected when the master
value is total bus leakage calculated in Equation 26-6. The observes an SDA line value that is not the same as the
primary source of leakage is I/O pins connected to the bus. value it is driving on the SDA line. For example, when
If leakage is too high, the pull-ups will have difficulty master 1 is driving the value ‘1’ on the SDA line and master
maintaining an acceptable VIH level causing communication 2 is driving the value ‘0’ on the SDA line, the actual line
errors. Most designs with five or fewer I2C devices on the value will be ‘0’ due to the implementation of the I/O signal
bus have less than 10 µA of total leakage current. interface. Master 1 detects the inconsistency and loses
control of the bus. Master 2 does not detect any
28.5.4 Terms and Definitions inconsistency and keeps control of the bus.
Table 28-13 explains the commonly used terms in an I2C
communication network. 28.5.5 I2C Modes of Operation
I2C is a synchronous single master, multi-master, multi-slave
Table 28-13. Definition of I2C Bus Terminology
serial interface. Devices operate in either master mode,
Term Description slave mode, or master/slave mode. In master/slave mode,
Transmitter The device that sends data to the bus the device switches from master to slave mode when it is
Receiver The device that receives data from the bus addressed. Only a single master may be active during a
data transfer. The active master is responsible for driving the
The device that initiates a transfer, generates
Master
clock signals, and terminates a transfer clock on the SCL line. Table 28-14 illustrates the I2C modes
of operation.
Slave The device addressed by a master

Multi-master
More than one master can attempt to control Table 28-14. I2C Modes
the bus at the same time
Mode Description
Procedure to ensure that, if more than one
master simultaneously tries to control the bus, Slave Slave only operation (default)
Arbitration
only one is allowed to do so and the winning Master Master only operation
message is not corrupted Multi-master Supports more than one master on the bus
Procedure to synchronize the clock signals of
Synchronization
two or more devices

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 Serial Communications Block (SCB)

Table 28-15 lists some common bus events that are part of 28.5.5.1 Write Transfer
an I2C data transfer. The Write Transfer and Read Transfer
sections explain the I2C bus bit format during data transfer. ■ A typical write transfer begins with the master generating
a START condition on the I2C bus. The master then
Table 28-15. I2C Bus Events Terminology
writes a 7-bit I2C slave address and a write indicator (‘0’)
Bus Event Description after the START condition. The addressed slave
A HIGH to LOW transition on the SDA line while transmits an acknowledgment byte by pulling the data
START
SCL is HIGH line low during the ninth bit time.
A LOW to HIGH transition on the SDA line while ■ If the slave address does not match any of the slave
STOP
SCL is HIGH devices or if the addressed device does not want to
The receiver pulls the SDA line LOW and it acknowledge the request, it transmits a no
remains LOW during the HIGH period of the clock acknowledgment (NACK) by not pulling the SDA line
ACK pulse, after the transmitter transmits each byte. low. The absence of an acknowledgement, results in an
This indicates to the transmitter that the receiver SDA line value of ‘1’ due to the pull-up resistor
received the byte properly.
implementation.
The receiver does not pull the SDA line LOW and
■ If no acknowledgment is transmitted by the slave, the
it remains HIGH during the HIGH period of clock
NACK pulse after the transmitter transmits each byte. master may end the write transfer with a STOP event.
This indicates to the transmitter that the receiver The master can also generate a repeated START
did not receive the byte properly. condition for a retry attempt.
Repeated START condition generated by master at the end ■ The master may transmit data to the bus if it receives an
START of a transfer instead of a STOP condition acknowledgment. The addressed slave transmits an
SDA status change while SCL is LOW (data acknowledgment to confirm the receipt of every byte of
DATA changing), and no change while SCL is HIGH data written. Upon receipt of this acknowledgment, the
(data valid) master may transmit another data byte.
■ When the transfer is complete, the master generates a
With all of these modes, there are two types of transfer - STOP condition.
read and write. In write transfer, the master sends data to
slave; in read transfer, the master receives data from slave.
Figure 28-38. Master Write Data Transfer

W rite d a ta tra n sfe r (M a ste r w rite s th e d a ta )

SDA M Sb LSb

SCL

START S lave a ddre ss (7 bits) W rite ACK D ata (8 b its) ACK STO P

LE G E N D :
SDA: S e ria l D a ta L in e
SCL: S e ria l C lo c k Lin e (a lw a y s d riv e n by the m a s te r)

S lav e T ra n s m it / M a ster R e c eiv e

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 Serial Communications Block (SCB)

28.5.5.2 Read Transfer

Figure 28-39. Master Read Data Transfer
Read data transfer (Master reads the data)
SDA MSb LSb

SCL

START Slave address (7 bits) Read ACK Data (8 bits) NACK STOP

LEGEND :
SDA: Serial Data Line
SCL: Serial Clock Line (always driven by the master)

Slave Transmit / Master Receive

■ A typical read transfer begins with the master generating 28.5.6.1 FIFO Mode
a START condition on the I2C bus. The master then
writes a 7-bit I2C slave address and a read indicator (‘1’) The FIFO mode has a TX FIFO for the data being
after the START condition. The addressed slave transmitted and an RX FIFO for the data being received.
transmits an acknowledgment by pulling the data line Each FIFO is constructed out of the SRAM buffer. The
low during the ninth bit time. FIFOs are either 64 elements deep with 16-bit data
elements or 128 elements deep with 8-bit data elements.
■ If the slave address does not match with that of the
The width of the data elements are configured using the
connected slave device or if the addressed device does
CTRL.BYTE_MODE bitfield of the SCB. For I2C, put the
not want to acknowledge the request, a no
FIFO in BYTE mode because all transactions are a byte
acknowledgment (NACK) is transmitted by not pulling
wide.
the SDA line low. The absence of an acknowledgment,
results in an SDA line value of ‘1’ due to the pull-up The FIFO mode operation is available only in Active and
resistor implementation. Sleep power modes, not in the Deep Sleep power mode.
■ If no acknowledgment is transmitted by the slave, the However, on the Deep Sleep-capable SCB the slave
master may end the read transfer with a STOP event. address can be used to wake the device from sleep.
The master can also generate a repeated START A write access to the transmit FIFO uses register
condition for a retry attempt. TX_FIFO_WR. A read access from the receive FIFO uses
■ If the slave acknowledges the address, it starts register RX_FIFO_RD.
transmitting data after the acknowledgment signal. The
Transmit and receive FIFO status information is available
master transmits an acknowledgment to confirm the
through status registers TX_FIFO_STATUS and
receipt of each data byte sent by the slave. Upon receipt
RX_FIFO_STATUS. When in debug mode, a read from this
of this acknowledgment, the addressed slave may
register behaves as a read from the
transmit another data byte.
SCB_RX_FIFO_RD_SILENT register; that is, data will not
■ The master can send a NACK signal to the slave to stop be removed from the FIFO.
the slave from sending data bytes. This completes the
read transfer. Each FIFO has a trigger output. This trigger output can be
routed through the trigger mux to various other peripheral on
■ When the transfer is complete, the master generates a
the device such as DMA or TCPWMs. The trigger output of
STOP condition.
the SCB is controlled through the TRIGGER_LEVEL field in
■ When the slave transmits a NACK, even if a new byte is the RX_CTRL and TX_CTRL registers.
written into the TX FIFO it will wait for the NACK to
■ For a TX FIFO a trigger is generated when the number
complete.
of entries in the transmit FIFO is less than
TX_FIFO_CTRL.TRIGGER_LEVEL.
28.5.6 I2C Buffer Modes ■ For the RX FIFO a trigger is generated when the number
I2C can operate in three different buffered modes – FIFO, of entries in the FIFO is greater than the
EZ, and CMD_RESP modes. The buffer is used in different RX_FIFO_CTRL.TRIGGER_LEVEL.
ways in each of the modes. The following subsections Note that the DMA has a trigger deactivation setting. For the
explain each of these buffered modes in detail. SCB this should be set to 16.

Active to Deep Sleep Transition

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Before going to deep sleep ensure that all active address is used to address these 256 locations. The CPU
communication is complete. This can be done by checking writes and reads to the memory buffer through the
the BUS_BUSY bit in the I2C_Status register. EZ_DATA registers. These accesses are word accesses,
but only the least significant byte of the word is used.
Ensure that the TX and RX FIFOs are empty as any data will
be lost during deep sleep. The slave interface accesses the memory buffer using the
current address. At the start of a transfer (I2C START/
Before going to deep sleep the clock to the SCB needs to be
RESTART), the base address is copied to the current
disabled. This can be done by setting the
address. A data element write or read operation is to the
SDA_IN_FILT_TRIM[1] bit in the I2C_CFG register to ‘0’.
current address location. After the access, the current
address is incremented by ‘1’.
Deep Sleep to Active Transition
If the current address equals the last memory buffer address
EC_AM = 1, EC_OP = 0, FIFO Mode.
(255), the current address is not incremented. Subsequent
The following descriptions only apply to slave mode. write accesses will overwrite any previously written value at
the last buffer address. Subsequent read accesses will
Master Write: continue to provide the (same) read value at the last buffer
■ I2C_CTRL.S_NOT_READY_ADDR_NACK = 0, address. The bus master should be aware of the memory
I2C_CTRL.S_READY_ADDR_ACK = 1. The clock is buffer capacity in EZ mode.
stretched until SDA_IN_FILT_TRIM[1] is set to ‘1’. After
that bit is set to 1, the clock stretch will be released The I2C base and current addresses are provided through
I2C_STATUS. At the end of a transfer, the difference
■ I2C_CTRL.S_NOT_READY_ADDR_NACK = 0, between the base and current addresses indicates how
I2C_CTRL.S_READY_ADDR_ACK = 0. The clock is many read or write accesses were performed. The block
stretched until SDA_IN_FILT_TRIM[1] is set to ‘1’, and provides interrupt cause fields to identify the end of a
S_ACK or S_NACK is set in the I2C_S_CMD register. transfer. EZI2C can be implemented through firmware or
■ I2C_CTRL.S_NOT_READY_ADDR_NACK = 1, hardware. All SCBs can implement EZI2C through a
I2C_CTRL.S_READY_ADDR_ACK = x. The incoming firmware implementation in both Active and Sleep power
address is NACK’d until SDA_IN_FILT_TRIM[1] is set to modes. The Deep Sleep SCB can implement a hardware-
‘1’. After that bit is set to 1, the slave will respond with an and firmware-based EZI2C with a Deep Sleep power mode.
ACK to a master address. This document focuses on hardware-implemented EZI2C;
for more information on software implementation, see the
Master Read:
PDL.
■ I2C_CTRL.S_NOT_READY_ADDR_NACK = 0,
I2C_CTRL.S_READY_ADDR_ACK = x. The incoming EZI2C distinguishes three operation phases:
address is stretched until SDA_IN_FILT_TRIM[1] is set ■ Address phase: The master transmits an 8-bit address
to ‘1’. After that bit is set to 1, the clock stretch will be to the slave. This address is used as the slave base and
released. current address.
■ I2C_CTRL.S_NOT_READY_ADDR_NACK = 1, ■ Write phase: The master writes 8-bit data element(s) to
I2C_CTRL.S_READY_ADDR_ACK = x. The incoming the slave’s memory buffer. The slave’s current address
address is NACK’d until SDA_IN_FILT_TRIM[1] is set to is set to the slave’s base address. Received data
‘1’. After that bit is set to 1, the slave will ACK. elements are written to the current address memory
Note: When doing a repeated start after a write, wait location. After each memory write, the current address is
until the UNDERFLOW interrupt status is asserted incremented.
before setting the I2C_M_CMD.START bit and writing ■ Read phase: The master reads 8-bit data elements from
the new address into the TX_FIFO. Otherwise, the the slave’s memory buffer. The slave’s current address
address in the FIFO will be sent as data and not as an is set to the slave’s base address. Transmitted data
address. elements are read from the current address memory
location. After each memory read, the current address is
28.5.6.2 EZI2C Mode incremented.
The Easy I2C (EZI2C) protocol is a unique communication Note that a slave’s base address is updated by the master
scheme built on top of the I2C protocol by Cypress. It uses a and not by the CPU.
meta protocol around the standard I2C protocol to
communicate to an I2C slave using indexed memory
transfers. This removes the need for CPU intervention.
The EZI2C protocol defines a single memory buffer with an
8-bit address that indexes the buffer (256-entry array of 8-bit
per entry is supported) located on the slave device. The EZ

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Figure 28-40. EZI2C Write and Read Data Transfer

Write data transfer (single write data)
SDA MSb LSb

SCL

START Slave address (7 bits) Write ACK EZ address (8 bits) ACK Write Data (8 bits) ACK STOP

EZ address

Data

EZ Buffer
(32 bytes SRAM)

Address

Read data transfer (single read data)

SDA MSb LSb

SCL

START Slave address (7 bits) Read ACK Read Data (8 bits) NACK STOP

LEGEND :
SDA: Serial Data Line
SCL: Serial Clock Line (always driven by the master)

Slave Transmit / Master Receive

Active to Deep Sleep Transition

Before going to deep sleep ensure that all active communication is complete. This can be done by checking the BUS_BUSY
bit in the I2C_Status register.
Ensure that the TX and RX FIFOs are empty as any data will be lost during deep sleep.
Before going to deep sleep the clock to the SCB needs to be disabled. This can be done by setting the
SDA_IN_FILT_TRIM[1] bit in the I2C_CFG register to ‘0’.

Deep Sleep to Active Transition

EC_AM = 1, EC_OP = 0, EZ Mode.
■ S_NOT_READY_ADDR_NACK = 0, S_READY_ADDR_ACK = 1. The clock is stretched until SDA_IN_FILT_TRIM[1] is
set to ‘1’. After that bit is set to 1, the clock stretch will be released.
■ S_NOT_READY_ADDR_NACK = 1, S_READY_ADDR_ACK = x. The incoming address is NACK’d until
SDA_IN_FILT_TRIM[1] is set to ‘1’. After that bit is set to 1, the slave will ACK.

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 Serial Communications Block (SCB)

28.5.6.3 Command-Response Mode the last buffer address. The bus master should be aware of
the memory buffer capacity in command-response mode.
This mode has a single memory buffer, a base read
address, a current read address, a base write address, and The base addresses are provided through
a current write address that are used to index the memory CMD_RESP_CTRL. The current addresses can be viewed
buffer. The base addresses are provided by the CPU. The in CMD_RESP_STATUS. At the end of a transfer (I2C stop),
current addresses are used by the slave to index the the difference between a base and current address
memory buffer for sequential accesses of the memory indicates how many read/write accesses were performed.
buffer. The memory buffer holds 256 8-bit data elements. This block provides interrupts to identify the end of a
The base and current addresses are in the range [0 to 255]. transfer, which can be found in SCB8_INTR_I2C_EC and
SCB8_INTR_SPI_EC register sections. Command-
The CPU writes and reads to the memory buffer through the response mode operation is available in Active, Sleep, and
SCB_EZ_DATA registers. These are word accesses, but Deep Sleep power modes. The command-response mode
only the least significant byte of the word is used. has two phases of operation:
The slave interface accesses the memory buffer using the ■ Write phase - The write phase begins with a START/
current addresses. At the start of a write transfer (I2C RESTART followed by the slave address with read/write
START/RESTART), the base write address is copied to the bit set to ‘0’ indicating a write. The slave’s current write
current write address. A data element write is to the current address is set to the slave’s base write address.
write address location. After the write access, the current Received data elements are written to the current write
address is incremented by ‘1’. At the start of a read transfer, address memory location. After each memory write, the
the base read address is copied to the current read address. current write address is incremented.
A data element read is to the current read address location. ■ Read phase - The read phase begins with a START/
After the read data element is transmitted, the current read RESTART followed by the slave address with read/write
address is incremented by ‘1’. bit set to ‘1’ indicating a read. The slave’s current read
If the current addresses equal the last memory buffer address is set to the slave’s base read address.
address (255), the current addresses are not incremented. Transmitted data elements are read from the current
Subsequent write accesses will overwrite any previously address memory location. After each read data element
written value at the last buffer address. Subsequent read is transferred, the current read address is incremented.
accesses will continue to provide the (same) read value at

Figure 28-41. I2C Command-Response Mode

write phase

I2C bus S address W A data A P

write data (8 bits)

LEGEND:
S: Start base_wr_addr curr_wr_addr
RS: Repeated start SRAM
P: Stop Memory of
A: ACK written by CPU 256 x 8-bits
N: NACK +1
written by CPU

base_rd_addr +1 curr_rd_addr
read data (8 bits)

I2C bus S address R A data N P

read phase

Note: A slave’s base addresses are updated by the CPU and not by the master.

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 Serial Communications Block (SCB)

28.5.7 Clocking and Oversampling Deep Sleep functionality interrupt brings the system into
Active power mode. When the slave is deselected,
The SCB I2C supports both internally and externally clocked INTR_I2C_EC.EZ_STOP and/or
operation modes. Two bitfields (EC_AM_MODE and INTR_I2C_EC.EZ_WRITE_STOP are set to ‘1’.
EC_OP MODE) in the SCB_CTRL register determine the
❐ FIFO mode: Not supported.
SCB clock mode. EC_AM_MODE indicates whether I2C
address matching is internally (0) or externally (1) clocked. ❐ EZ mode: Supported.
I2C address matching comprises the first part of the I2C ❐ CMD_RESP mode: Supported.
protocol. EC_OP_MODE indicates whether the rest of the
An externally-clocked operation uses a clock provided by
protocol operation (besides I2C address matching) is
the serial interface. The externally clocked mode does not
internally (0) or externally (1) clocked. The externally
support FIFO mode. If EC_OP_MODE is ‘1’, the external
clocked mode of operation is supported only in the I2C slave
interface logic accesses the memory buffer on the external
mode.
interface clock (I2C SCL). This allows for EZ and
An internally-clocked operation uses the programmable CMD_RESP mode functionality in Active and Deep Sleep
clock dividers. For I2C, an integer clock divider must be power modes.
used for both master and slave. For more information on
In Active system power mode, the memory buffer requires
system clocking, see the Clocking System chapter on
arbitration between external interface logic (on I2C SCL) and
page 242. The internally-clocked mode does not support the
the CPU interface logic (on system peripheral clock). This
command-response mode.
arbitration always gives the highest priority to the external
The SCB_CTRL bitfields EC_AM_MODE and interface logic (host accesses). The external interface logic
EC_OP_MODE can be configured in the following ways. takes one serial interface clock/bit periods for the I2C.
■ EC_AM_MODE is ‘0’ and EC_OP_MODE is ‘0’: Use this During this period, the internal logic is denied service to the
configuration when only Active mode functionality is memory buffer. The PSoC 6 MCU provides two
required. programmable options to address this “denial of service”:
❐ FIFO mode: Supported. ■ If the BLOCK bitfield of SCB_CTRL is ‘1’: An internal
logic access to the memory buffer is blocked until the
❐ EZ mode: Supported.
memory buffer is granted and the external interface logic
❐ Command-response mode: Not supported. The has completed access. For a 100-kHz I2C interface, the
slave NACKs every slave address. maximum blocking period of one serial interface bit
■ EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘0’: Use this period measures 10 µs (approximately 208 clock cycles
configuration when both Active and Deep Sleep on a 48 MHz SCB input clock). This option provides
functionality are required. This configuration relies on the normal SCB register functionality, but the blocking time
externally clocked functionality for the I2C address introduces additional internal bus wait states.
matching and relies on the internally clocked ■ If the BLOCK bitfield of SCB_CTRL is ‘0’: An internal
functionality to access the memory buffer. The “hand logic access to the memory buffer is not blocked, but
over” from external to internal functionality relies either fails when it conflicts with an external interface logic
on an ACK/NACK or clock stretching scheme. The access. A read access returns the value 0xFFFF:FFFF
former may result in termination of the current transfer and a write access is ignored. This option does not
and relies on a master retry. The latter stretches the introduce additional internal bus wait states, but an
current transfer after a matching address is received. access to the memory buffer may not take effect. In this
This mode requires the master to support either NACK case, following failures are detected:
generation (and retry) or clock stretching. When the I2C
❐ Read Failure: A read failure is easily detected, as the
address is matched, INTR_I2C_EC.WAKE_UP is set to
returned value is 0xFFFF:FFFF. This value is unique
‘1’. The associated Deep Sleep functionality interrupt
as non-failing memory buffer read accesses return
brings the system into Active power mode.
an unsigned byte value in the range 0x0000:0000-
❐ FIFO mode: See “Deep Sleep to Active Transition” 0x0000:00FF.
on page 357
❐ Write Failure: A write failure is detected by reading
❐ EZ mode: See “Deep Sleep to Active Transition” on back the written memory buffer location, and con-
page 358. firming that the read value is the same as the written
❐ CMD_RESP mode: Not supported. The slave value.
NACKs every slave address.
For both options, a conflicting internal logic access to the
■ EC_AM_MODE is ‘1’ and EC_OP_MODE is ‘1’. Use this memory buffer sets INTR_TX.BLOCKED field to ‘1’ (for write
mode when both Active and Deep Sleep functionality are access-es) and INTR_RX.BLOCKED field to ‘1’ (for read
required. When the slave is selected, accesses). These fields can be used as either status fields
INTR_I2C_EC.WAKE_UP is set to ‘1’. The associated

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 Serial Communications Block (SCB)

or as interrupt cause fields (when their associated mask i2c_sda_in input signals (AF_in) to filter glitches of up to 50
fields are enabled). ns. An analog glitch filter is also applied on the i2c_sda_out
output signal (AF_out). Analog glitch filters are enabled and
If a series of read or write accesses is performed and
disabled in the SCB.I2C_CFG register. Do not change the
CTRL.BLOCKED is ‘0’, a failure is detected by comparing
_TRIM bitfields; only change the _SEL bitfields in this
the logical OR of all read values to 0xFFFF:FFFF and
register.
checking the INTR_TX.BLOCKED and
INTR_RX.BLOCKED fields to determine whether a failure Digital glitch filters are applied on the i2c_scl_in and
occurred for a (series of) write or read operation(s). i2c_sda_in input signals (DF_in). The digital glitch filter is
enabled in the SCB.RX_CTRL register via the MEDIAN
28.5.7.1 Glitch Filtering bitfield.
The PSoC 6 MCU SCB I2C has analog and digital glitch
filters. Analog glitch filters are applied on the i2c_scl_in and

Figure 28-42. I2C Glitch Filtering Connection

i2c_ctl
i2c_ic_scl_out
i2c_scl_out i2c_ic_sda_out

i2c_scl DF_in
AF_in i2c_scl_in i2c_scl_in

i2c_sda_in DF_in

AF_out
i2c_ec_scl_out i2c_ec_ctl
i2c_ec_sda_out
i2c_sda
AF_in i2c_sda_in

i2c_scl_in
i2c_sda_in

The following table lists the useful combinations of glitch filters.

Table 28-16. Glitch Filter Combinations

AF_in AF_out DF_in Comments
0 0 1 Used when operating in internally-clocked mode and in master in fast-mode plus (1-MHz speed mode)
1 0 0 Used when operating in internally-clocked mode (EC_OP_MODE is '0')
1 1 0 Used when operating in externally-clocked mode (EC_OP_MODE is '1'). Only slave mode.

When operating in EC_OP_MODE = 1, the 100-kHz, 400-kHz, and 1000-kHz modes require the following settings for AF_out:

AF_in AF_out DF_in

100-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3
1 1 0 400-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 3
1000-kHz mode: I2C_CFG.SDA_OUT_FILT_SEL = 1

28.5.7.2 Oversampling and Bit Rate

Internally-clocked Master
The PSoC 6 MCU implements the I2C clock as an oversampled multiple of the SCB input clock. In master mode, the block
determines the I2C frequency. Routing delays on the PCB, on the chip, and the SCB (including analog and digital glitch filters)
all contribute to the signal interface timing. In master mode, the block operates off clk_scb and uses programmable
oversampling factors for the SCL high (1) and low (0) times. For high and low phase oversampling, see

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 Serial Communications Block (SCB)

I2C_CTRL.LOW_PHASE_OVS and I2C_CTRL.HIGH_PHASE_OVS registers. For simple manipulation of the oversampling

factor, see the SCB_CTRL.OVS register.

Table 28-17. I2C Frequency and Oversampling Requirements in I2C Master Mode
Supported clk_scb
AF_in AF_out DF_in Mode LOW_PHASE_OVS HIGH_PHASE_OVS
Frequency Frequency
100 kHz [62, 100] kHz [9, 15] [9, 15] [1.98-3.2] MHz
0 0 1 400 kHz [264, 400] kHz [13, 5] [7, 15] [8.45-10] MHz
1000 kHz [447, 1000] kHz [8, 15] [5, 15] [14.32-25.8] MHz
100 kHz [48, 100] kHz [7, 15] [7, 15] [1.55-3.2] MHz
1 0 0 400 kHz [244, 400] kHz [12, 15] [7, 15] [7.82-10] MHz
1000 kHz Not supported

Table 28-17 assumes worst-case conditions on the I2C bus. The following equations can be used to determine the settings for
your own system. This will involve measuring the rise and fall times on SCL and SDA lines in your system.
tCLK_SCB(Min) = (tLOW + tF)/LOW_PHASE_OVS
If clk_scb is any faster than this, the tLOW of the I2C specification will be violated. tF needs to be measured in your system.
tCLK_SCB(Max) = (tVD – tRF – 100 ns)/3 (When analog filter is enabled and digital disabled)
tCLK_SCB(Max) = (tVD – tRF)/4 (When analog filter is disabled and analog filter is enabled)
tRF is the maximum of either the rise or fall time. If clk_scb is slower than this frequency, tVD will be violated.

I2C Master Clock Synchronization

The HIGH_PHASE_OVS counter does not start counting until the SCB detects that the SCL line is high. This is not the same
as when the SCB sets the SCL high. The differences are explained by three delays:
1. Delay from SCB to I/O pin
2. I2C bus tR
3. Input delay (filters and synchronization)

Figure 28-43. I2C SCL Turnaround Path

SCL_out

SCL_bus
1 2 3

SCL_in

If the above three delays combined are greater than one clk_scb cycle, then the high phase of the SCL will be extended. This
may cause the actual data rate on the I2C bus to be slower than expected. This can be avoided by:
■ Decreasing the pull-up resistor, or decreasing the bus capacitance to reduce tR.
■ Reducing the I2C_CTRL.HIGH_PHASE_OVS value.

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 Serial Communications Block (SCB)

Internally-clocked Slave
In slave mode, the I2C frequency is determined by the incoming I2C SCL signal. To ensure proper operation, clk_scb must be
significantly higher than the I2C bus frequency. Unlike master mode, this mode does not use programmable oversampling
factors.

Table 28-18. SCB Input Clock Requirements in I2C Slave Mode

AF_in AF_out DF_in Mode clk_scb Frequency Range
100 kHz [1.98-12.8] MHz
0 0 1 400 kHz [8.45-17.14] MHz
1000 kHz [14.32-44.77] MHz
100 kHz [1.55-12.8] MHz
1 0 0 400 kHz [7.82-15.38] MHz
1000 kHz [15.84-89.0] MHz

tCLK_SCB(Max) = (tVD – tRF – 100 ns) / 3 (When analog filter is enabled and digital disabled)

tCLK_SCB(Max) = (tVD – tRF) / 4 (When analog filter is disabled and analog filter is enabled)

tRF is the maximum of either the rise or fall time. If clk_scb is slower than this frequency, tVD will be violated.

The minimum period of clk_scb is determined by one of the following equations:

tCLK_SCB(MIN) = (tSU;DAT(min) + tRF) /16

or
tCLK_SCB(Min) = (0.6 * tF – 50 ns)/2 (When analog filter is enabled and digital disabled)

tCLK_SCB(Min) = (0.6 * tF)/3 (When analog filter is disabled and digital enabled)

The result that yields the largest period from the two sets of equations above should be used to set the minimum period of
clk_scb.

Master-Slave
In this mode, when the SCB is acting as a master device, the block determines the I2C frequency. When the SCB is acting as
a slave device, the block does not determine the I2C frequency. Instead, the incoming I2C SCL signal does.
To guarantee operation in both master and slave modes, choose clock frequencies that work for both master and slave using
the tables above.

28.5.8 Enabling and Initializing the I2C

The following section describes the method to configure the I2C block for standard (non-EZ) mode and EZI2C mode.

28.5.8.1 Configuring for I2C FIFO Mode

The I2C interface must be programmed in the following order.
1. Program protocol specific information using the SCB_I2C_CTRL register. This includes selecting master - slave function-
ality.
2. Program the generic transmitter and receiver information using the SCB_TX_CTRL and SCB_RX_CTRL registers.
3. Set the SCB_CTRL.BYTE_MODE to ‘1’ to enable the byte mode.
4. Program the SCB_CTRL register to enable the I2C block and select the I2C mode. For a complete description of the I2C
registers, see the registers TRM.

28.5.8.2 Configuring for EZ and CMD_RESP Modes

To configure the I2C block for EZ and CMD_RESP modes, set the following I2C register bits

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 Serial Communications Block (SCB)

1a. Select the EZI2C mode by writing ‘1’ to the EZ_MODE bit (bit 10) of the SCB_CTRL register.
1b. Select CMD_RESP mode by writing a 1 to the CMD_RESP bit (bit 12) of the SCB_CTRL register.
2. Set the S_READY_ADDR_ACK (bit 12) and S_READY_DATA_ACK (bit 13) bits of the SCB_I2C_CTRL register.
Note: For all modes clk_scb must also be configured. For information on configuring a peripheral clock and connecting it to
the SCB consult the Clocking System chapter on page 242.
The GPIO must also be connected to the SCB; see the following section for more details.

28.5.9 I/O Pad Connections

Figure 28-44. I2C I/O Pad Connections

oe i2c_ic_block_ec
1 i2c_ctl
Open drain i2c_ic_scl_out
(pull-up) i2c_ic_sda_out

i2c_scl
Filter i2c_scl_in i2c_scl_in
i2c_sda_in
1

Filter i2c_ec_ctl
i2c_ec_scl_out
i2c_ec_sda_out
i2c_sda
Filter i2c_sda_in

i2c_scl_in
Open drain i2c_sda_in
(pull-up)

Table 28-19. I2C I/O Pad Descriptions

I/O Pads Drive Mode On-chip I/O Signals Usage
i2c_scl_in Receive a clock
i2c_scl Open drain with external pull-up
i2c_scl_out Transmit a clock
i2c_sda_in Receive data
i2c_sda Open drain with external pull-up
i2c_sda_out Transmit data

When configuring the I2C SDA/SCL lines, the following sequence must be followed. If this sequence is not followed, the I2C
lines may initially have overshoot and undershoot.
1. Set SCB_CTRL_MODE to ‘0’.
2. Configure HSIOM for SCL and SDA to connect to the SCB.
3. Set TX_CTRL.OPEN_DRAIN to ‘1’.
4. Configure I2C pins for high-impedance drive mode.
5. Configure SCB for I2C
6. Enable SCB
7. Configure I2C pins for Open Drain Drives Low.

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 Serial Communications Block (SCB)

28.5.10 I2C Registers

The I2C interface is controlled by reading and writing a set of configuration, control, and status registers, as listed in
Table 28-20.

Table 28-20. I2C Registers

Register Function

SCB_CTRL Enables the SCB block and selects the type of serial interface (SPI, UART, I2C). Also used to select inter-
nally and externally clocked operation and EZ and non-EZ modes of operation.
SCB_I2C_CTRL Selects the mode (master, slave) and sends an ACK or NACK signal based on receiver FIFO status.
Indicates bus busy status detection, read/write transfer status of the slave/master, and stores the EZ slave
SCB_I2C_STATUS
address.
SCB_I2C_M_CMD Enables the master to generate START, STOP, and ACK/NACK signals.
SCB_I2C_S_CMD Enables the slave to generate ACK/NACK signals.
Indicates whether the externally clocked logic is using the EZ memory. This bit can be used by software to
SCB_STATUS
determine whether it is safe to issue a software access to the EZ memory.
SCB_I2C_CFG Configures filters, which remove glitches from the SDA and SCL lines.
SCB_TX_CTRL Specifies the data frame width; also used to specify whether MSb or LSb is the first bit in transmission.
Specifies the trigger level, clearing of the transmitter FIFO and shift registers, and FREEZE operation of the
SCB_TX_FIFO_CTRL
transmitter FIFO.
Indicates the number of bytes stored in the transmitter FIFO, the location from which a data frame is read by
SCB_TX_FIFO_STATUS the hardware (read pointer), the location from which a new data frame is written (write pointer), and decides
if the transmitter FIFO holds the valid data.
SCB_TX_FIFO_WR Holds the data frame written into the transmitter FIFO. Behavior is similar to that of a PUSH operation.
Performs the same function as that of the SCB_TX_CTRL register, but for the receiver. Also decides
SCB_RX_CTRL
whether a median filter is to be used on the input interface lines.
SCB_RX_FIFO_CTRL Performs the same function as that of the SCB_TX_FIFO_CTRL register, but for the receiver.
SCB_RX_FIFO_STATUS Performs the same function as that of the SCB_TX_FIFO_STATUS register, but for the receiver.
Holds the data read from the receiver FIFO. Reading a data frame removes the data frame from the FIFO;
SCB_RX_FIFO_RD behavior is similar to that of a POP operation. This register has a side effect when read by software: a data
frame is removed from the FIFO.
Holds the data read from the receiver FIFO. Reading a data frame does not remove the data frame from the
SCB_RX_FIFO_RD_SILENT
FIFO; behavior is similar to that of a PEEK operation.
SCB_RX_MATCH Stores slave device address and is also used as slave device address MASK.
SCB_EZ_DATA Holds the data in an EZ memory location.

Note: Detailed descriptions of the I2C register bits are available in the registers TRM.

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 Serial Communications Block (SCB)

28.6 SCB Interrupts

SCB supports interrupt generation on various events. The interrupts generated by the SCB block vary depending on the
mode of operation.

Table 28-21. SCB Interrupts

Active/Deep
Interrupt Functionality Registers
Sleep
INTR_M,
INTR_M_SET,
interrupt_master I2C master and SPI master functionality Active
INTR_M_MASK,
INTR_M_MASKED
INTR_S,
INTR_S_SET,
interrupt_slave I2C slave and SPI slave functionality Active
INTR_S_MASK,
INTR_S_MASKED
INTR_TX,
INTR_TX_SET,
interrupt_tx UART transmitter and TX FIFO functionality Active
INTR_TX_MASK,
INTR_TX_MASKED
INTR_RX,
INTR_RX_SET,
interrupt_rx UART receiver and RX FIFO functionality Active
INTR_RX_MASK,
INTR_RX_MASKED
INTR_I2C_EC,
interrupt_i2c_ec Externally clocked I2C slave functionality Deep Sleep INTR_I2C_EC_MASK,
INTR_I2C_EC_MASKED
INTR_ISPI_EC,
interrupt_spi_ec Externally clocked SPI slave functionality Deep Sleep INTR_SPI_EC_MASK,
INTR_SPI_EC_MASKED

Note: To avoid being triggered by events from previous transactions, whenever the firmware enables an interrupt mask
register bit, it should clear the interrupt request register in advance.
Note: If the DMA is used to read data out of RX FIFO, the NOT_EMPTY interrupt may never trigger. This can occur when
clk_peri (clocking DMA) is running much faster than the clock to the SCB. As a workaround to this issue, set the
RX_FIFO_CTRL.TRIGGER_LEVEL to ‘1’ (not 0); this will allow the interrupt to fire.
The following register definitions correspond to the SCB interrupts:
■ INTR_M: This register provides the instantaneous status of the interrupt sources. A write of ‘1’ to a bit will clear the
interrupt.
■ INTR_M_SET: A write of ‘1’ into this register will set the interrupt.
■ INTR_M_MASK: The bit in this register masks the interrupt sources. Only the interrupt sources with their masks enabled
can trigger the interrupt.
■ INTR_M_MASKED: This register provides the instantaneous value of the interrupts after they are masked. It provides
logical and corresponding request and mask bits. This is used to understand which interrupt triggered the event.
Note: While registers corresponding to INTR_M are used here, these definitions can be used for INTR_S, INTR_TX,
INTR_RX, INTR_I2C_EC, and INTR_SPI_EC.
Figure 28-45 shows the physical interrupt lines. All the interrupts are OR'd together to make one interrupt source that is the
OR of all six individual interrupts. All the externally-clocked interrupts make one interrupt line called interrupt_ec, which is the
OR'd signal of interrupt_i2C_ec and interrupt_spi_ec. All the internally-clocked interrupts make one interrupt line called
interrupt_ic, which is the OR'd signal of interrupt_master, interrupt_slave, interrupt_tx, and interrupt_rx. The Active
functionality interrupts are generated synchronously to clk_peri while the Deep Sleep functionality interrupts are generated
asynchronously to clk_peri.

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 Serial Communications Block (SCB)

Figure 28-45. Interrupt Lines

Interrupt Lines
Interrupt_master
INTR_M_MASKED[...]

Interrupt_slave
INTR_S_MASKED[...]
Interrupt_ic
Interrupt_tx
INTR_TX_MASKED[...]

Interrupt_rx
INTR_RX_MASKED[...] Interrupt

Interrupt_i2c_ec

Interrupt_ec
Interrupt_spi_ec

28.6.1 SPI Interrupts

The SPI interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked
(EC) mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the
section. For example, the TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal
goes high when any of the enabled TX interrupt sources are true. The SCB also provides an interrupt cause register (SCB_
INTR_CAUSE) that can be used to determine interrupt source. The interrupt registers are cleared by writing ‘1’ to the
corresponding bitfield. Note that certain interrupt sources are triggered again as long as the condition is met even if the
interrupt source was cleared. For example, the TX_FIFO_EMPTY is set as long as the transmit FIFO is empty even if the
interrupt source is cleared. For more information on interrupt registers, see the registers TRM. The SPI supports interrupts on
the following events:
■ SPI Master Interrupts
❐ SPI master transfer done – All data from the TX FIFO are sent. This interrupt source triggers later than TX_FI-
FO_EMPTY by the amount of time it takes to transmit a single data element. TX_FIFO_EMPTY triggers when the last
data element from the TX FIFO goes to the shifter register. However, SPI Done triggers after this data element is
transmitted. This means SPI Done will be asserted one SCLK clock cycle earlier than the completion of data element
reception.
■ SPI Slave Interrupts
❐ SPI Bus Error – Slave deselected at an unexpected time in the SPI transfer. The firmware may decide to clear the TX
and RX FIFOs for this error.
❐ SPI slave deselected after any EZSPI transfer occurred.
❐ SPI slave deselected after a write EZSPI transfer occurred.
■ SPI TX
❐ TX FIFO has less entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL.
❐ TX FIFO not full – At least one data element can be written into the TX FIFO.
❐ TX FIFO empty – The TX FIFO is empty.
❐ TX FIFO overflow – Firmware attempts to write to a full TX FIFO.
❐ TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. This happens when the SCB is ready to
transfer data and EMPTY is ‘1’.
❐ TX FIFO trigger – Less entries in the TX FIFO than the value specified by TX_FIFO_CTRL.TRIGGER_LEVEL.
■ SPI RX
❐ RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL.
❐ RX FIFO full - RX FIFO is full.
❐ RX FIFO not empty - RX FIFO is not empty. At least one data element is available in the RX FIFO to be read.
❐ RX FIFO overflow - Hardware attempt to write to a full RX FIFO.
❐ RX FIFO underflow - Firmware attempts to read from and empty RX FIFO.

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 Serial Communications Block (SCB)

❐ RX FIFO trigger - More entries in the RX FIFO than the value specified by RX_FIFO_CTRL.TRIGGER_LEVEL.
■ SPI Externally Clocked
❐ Wake up request on slave select – Active on incoming slave request (with address match). Only set when EC_AM is
‘1’.
❐ SPI STOP detection at the end of each transfer – Activated at the end of every transfer (I2C STOP). Only set for a
slave request with an address match, in EZ and CMD_RESP modes, when EC_OP is ‘1’.
❐ SPI STOP detection at the end of a write transfer – Activated at the end of a write transfer (I2C STOP). This event is
an indication that a buffer memory location has been written to. For EZ mode, a transfer that only writes the base
address does not activate this event. Only set for a slave request with an address match, in EZ and CMD_RESP
modes, when EC_OP is ‘1’.
❐ SPI STOP detection at the end of a read transfer – Activated at the end of a read transfer (I2C STOP). This event is an
indication that a buffer memory location has been read from. Only set for a slave request with an address match, in EZ
and CMD_RESP modes when EC_OP is ‘1’.
Figure 28-46 and Figure 28-47 show how each of the interrupts are triggered. Figure 28-46 shows the TX buffer and the
corresponding interrupts while Figure 28-47 shows all the corresponding interrupts for the RX buffer. The FIFO has 256 split
into 128 bytes for TX and 128 bytes for RX instead of the 8 bytes shown in the figures. For more information on how to
implement and clear interrupts, see the SPI (SCB_SPI_PDL) datasheet and the PDL.
Figure 28-46. TX Interrupt Source Operation

Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes

TX FIFO Empty =1 TX FIFO Empty =1 TX FIFO Empty = 0 (W1C) TX FIFO Empty =1 TX FIFO Empty =0
TX FIFO Level =1 TX FIFO Level =1 TX FIFO Level =1 TX FIFO Level = 0 (W1C) TX FIFO Level =0
TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 0 (W1C)
SPI Done =0 SPI Done =0 SPI Done =0 SPI Done =0 SPI Done =0

TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO

Level = 4 Level = 4 Level = 4 Level = 4 Level = 4

Used = 0 Used = 0 Used = 1 Used = 5

TX Shifter TX Shifter TX Shifter TX Shifter TX Shifter

Transmit 1 byte Transmit 3 more bytes Transmit 4 more bytes Transmit 7 more bits Transmit last bit

TX FIFO Empty =0 TX FIFO Empty =0 TX FIFO Empty =1 TX FIFO Empty =1 TX FIFO Empty =1
TX FIFO Level =0 TX FIFO Level =1 TX FIFO Level =1 TX FIFO Leve l =1 TX FIFO Level =1
TX FIFO Not F ull =1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull =1
SPI Done =0 SPI Done =0 SPI Done =0 SPI Done =1 TX FIFO Underflo w = 1

TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO

Level = 4 Level = 4 Level = 4 Level = 4 Level = 4

Used = 7 Used = 4 Used = 0 Used = 0 Used = 0

TX Shifter TX Shifter TX Shifter TX Shifter TX Shifter

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 368
 Serial Communications Block (SCB)

Figure 28-47. RX Interrupt Source Operation

Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes

RX FIFO Not Empty = 1

RX FIFO Not Empty = 0 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1
RX FIFO Level =1
RX FIFO Level =0 RX FIFO Level =0 RX FIFO Level =1 RX FIFO Level =1 RX FIFO Full = 1
RX FIFO Full = 0 RX FIFO Full = 0 RX FIFO Full = 0 RX FIFO Full = 1 RX FIFO Oveflow = 1

RX FIFO RX FIFO RX FIFO RX FIFO RX FIFO

Level = 4 Level = 4 Level = 4 Level = 4 Level = 4

Dropped

Used = 0 Used = 0 Used = 5

RX Shifter RX Shifter RX Shifter RX Shifter RX Shifter

Read 1 byte Read 3 more bytes Read 4 more bytes

RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 0 (W1C)
RX FIFO Level =1 RX FIFO Level = 0 (W1C) RX FIFO Level =0
RX FIFO Full = 0 (W1C) RX FIFO Full = 0 RX FIFO Full = 0

RX FIFO RX FIFO RX FIFO

Level = 4 Level = 4 Level = 4

Used = 7 Used = 4 Used = 0

RX Shifter RX Shifter RX Shifter

28.6.2 UART Interrupts

The UART interrupts can be classified as TX interrupts and RX interrupts. Each interrupt output is the logical OR of the group
of all possible interrupt sources classified under the section. For example, the TX interrupt output is the logical OR of the
group of all possible TX interrupt sources. This signal goes high when any of the enabled TX interrupt sources are true. The
SCB also provides an interrupt cause register (SCB_ INTR_CAUSE) that can be used to determine interrupt source. The
interrupt registers are cleared by writing ‘1’ to the corresponding bitfield. Note that certain interrupt sources are triggered
again as long as the condition is met even if the interrupt source was cleared. For example, the TX_FIFO_EMPTY is set as
long as the transmit FIFO is empty even if the interrupt source is cleared. For more information on interrupt registers, see the
registers TRM. The UART block generates interrupts on the following events:
■ UART TX
❐ TX FIFO has fewer entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL.
❐ TX FIFO not full – TX FIFO is not full. At least one data element can be written into the TX FIFO.
❐ TX FIFO empty – The TX FIFO is empty.
❐ TX FIFO overflow – Firmware attempts to write to a full TX FIFO.

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 Serial Communications Block (SCB)

❐ TX FIFO underflow – Hardware attempts to read from an empty TX FIFO. This happens when the SCB is ready to
transfer data and EMPTY is ‘1’.
❐ TX NACK – UART transmitter receives a negative acknowledgment in SmartCard mode.
❐ TX done – This happens when the UART completes transferring all data in the TX FIFO and the last stop field is trans-
mitted (both TX FIFO and transmit shifter register are empty).
❐ TX lost arbitration – The value driven on the TX line is not the same as the value observed on the RX line. This condi-
tion event is useful when transmitter and receiver share a TX/RX line. This is the case in LIN or SmartCard modes.
■ UART RX
❐ RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL.
❐ RX FIFO full – RX FIFO is full. Note that received data frames are lost when the RX FIFO is full.
❐ RX FIFO not empty – RX FIFO is not empty.
❐ RX FIFO overflow – Hardware attempts to write to a full RX FIFO.
❐ RX FIFO underflow – Firmware attempts to read from an empty RX FIFO.
❐ Frame error in received data frame – UART frame error in received data frame. This can be either a start of stop bit
error:
Start bit error: After the beginning of a start bit period is detected (RX line changes from 1 to 0), the middle of the start
bit period is sampled erroneously (RX line is ‘1’). Note: A start bit error is detected before a data frame is received.
Stop bit error: The RX line is sampled as ‘0’, but a ‘1’ was expected. A stop bit error may result in failure to receive
successive data frames. Note: A stop bit error is detected after a data frame is received.
❐ Parity error in received data frame – If UART_RX_CTL.DROP_ON_PARITY_ERROR is ‘1’, the received frame is
dropped. If UART_RX_CTL.DROP_ON_PARITY_ERROR is ‘0’, the received frame is sent to the RX FIFO. In Smart-
Card sub mode, negatively acknowledged data frames generate a parity error. Note that firmware can only identify the
erroneous data frame in the RX FIFO if it is fast enough to read the data frame before the hardware writes a next data
frame into the RX FIFO.
❐ LIN baud rate detection is completed – The receiver software uses the UART_RX_STATUS.BR_COUNTER value to
set the clk_scb to guarantee successful receipt of the first LIN data frame (Protected Identifier Field) after the synchro-
nization byte.
❐ LIN break detection is successful – The line is ‘0’ for UART_RX_CTRL.BREAK_WIDTH + 1 bit period. Can occur at
any time to address unanticipated break fields; that is, “break-in-data” is supported. This feature is supported for the
UART standard and LIN submodes. For the UART standard submodes, ongoing receipt of data frames is not affected;
firmware is expected to take proper action. For the LIN submode, possible ongoing receipt of a data frame is stopped
and the (partially) received data frame is dropped and baud rate detection is started. Set to ‘1’, when event is detected.
Write with '1' to clear bit.
Figure 28-48 and Figure 28-49 show how each of the interrupts are triggered. Figure 28-48 shows the TX buffer and the
corresponding interrupts while Figure 28-49 shows all the corresponding interrupts for the RX buffer. The FIFO has 256 split
into 128 bytes for TX and 128 bytes for RX instead of the 8 bytes shown in the figures. For more information on how to
implement and clear interrupts see the UART (SCB_UART_PDL) datasheet and the PDL.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 370
 Serial Communications Block (SCB)

Figure 28-48. TX Interrupt Source Operation

Component Started Write 1 byte Write 1 more byte Write 4 more bytes Write 3 more bytes

TX FIFO Empty =1 TX FIFO Empty =1 TX FIFO Empty = 0 (W1C) TX FIFO Empty =1 TX FIFO Empty =0
TX FIFO Level =1 TX FIFO Level =1 TX FIFO Level =1 TX FIFO Level = 0 (W1C) TX FIFO Level =0
TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 0 (W1C)
UART Done =0 UART Done =0 UART Do ne = 0 UART Do ne =0 UART Do ne =0

TX FIFO TX FIFO TX FIFO TX FIFO TX FIFO

Level = 4 Level = 4 Level = 4 Level = 4 Level = 4

Used = 0 Used = 0 Used = 1 Used = 5

TX Shifter TX Shifter TX Shifter TX Shifter TX Shifter

Transmit 1 byte Transmit 3 more bytes Transmit 4 more bytes Transmit last bit

TX FIFO Empty =0 TX FIFO Empty =0 TX FIFO Empty =1 TX FIFO Empty =1

TX FIFO Level =0 TX FIFO Level =1 TX FIFO Level =1 TX FIFO Level =1
TX FIFO Not F ull =1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1 TX FIFO Not F ull = 1
UART Do ne =0 UART Do ne =0 UART Do ne =0 UART Do ne =1

TX FIFO TX FIFO TX FIFO TX FIFO

Level = 4 Level = 4 Level = 4 Level = 4

Used = 7 Used = 4 Used = 0 Used = 0

TX Shifter TX Shifter TX Shifter TX Shifter

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 371
 Serial Communications Block (SCB)

Figure 28-49. RX Interrupt Source Operation

Component Started Recevice 1 byte Receive 4 more byte Receive 3 more bytes Receive 3 more bytes

RX FIFO Not Empty = 1

RX FIFO Not Empty = 0 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 1
RX FIFO Level =1
RX FIFO Level =0 RX FIFO Level =0 RX FIFO Level =1 RX FIFO Level =1 RX FIFO Full = 1
RX FIFO Full = 0 RX FIFO Full = 0 RX FIFO Full = 0 RX FIFO Full = 1 RX FIFO Oveflow = 1

RX FIFO RX FIFO RX FIFO RX FIFO RX FIFO

Level = 4 Level = 4 Level = 4 Level = 4 Level = 4

Dropped

Used = 0 Used = 0 Used = 5

RX Shifter RX Shifter RX Shifter RX Shifter RX Shifter

Read 1 byte Read 3 more bytes Read 4 more bytes

RX FIFO Not Empty = 1 RX FIFO Not Empty = 1 RX FIFO Not Empty = 0 (W1C)
RX FIFO Level =1 RX FIFO Level = 0 (W1C) RX FIFO Level =0
RX FIFO Full = 0 (W1C) RX FIFO Full = 0 RX FIFO Full = 0

RX FIFO RX FIFO RX FIFO

Level = 4 Level = 4 Level = 4

Used = 7 Used = 4 Used = 0

RX Shifter RX Shifter RX Shifter

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 372
 Serial Communications Block (SCB)

28.6.3 I2C Interrupts

I2C interrupts can be classified as master interrupts, slave interrupts, TX interrupts, RX interrupts, and externally clocked (EC)
mode interrupts. Each interrupt output is the logical OR of the group of all possible interrupt sources classified under the
section. For example, the TX interrupt output is the logical OR of the group of all possible TX interrupt sources. This signal
goes high when any of the enabled TX interrupt sources are true. The SCB also provides an interrupt cause register (SCB_
INTR_CAUSE) that can be used to determine interrupt source. The interrupt registers are cleared by writing ‘1’ to the
corresponding bitfield. Note that certain interrupt sources are triggered again as long as the condition is met even if the
interrupt source was cleared. For example, the TX_FIFO_EMPTY is set as long as the transmit FIFO is empty even if the
interrupt source is cleared. For more information on interrupt registers, see the registers TRM. The I2C block generates
interrupts for the following conditions.
■ I2C Master
❐ I2C master lost arbitration – The value driven by the master on the SDA line is not the same as the value observed on
the SDA line.
❐ I2C master received NACK – When the master receives a NACK (typically after the master transmitted the slave
address or TX data).
❐ I2C master received ACK – When the master receives an ACK (typically after the master transmitted the slave
address or TX data).
❐ I2C master sent STOP – When the master has transmitted a STOP.
❐ I2C bus error – Unexpected stop/start condition is detected.
■ I2C Slave
❐ I2C slave lost arbitration – The value driven on the SDA line is not the same as the value observed on the SDA line
(while the SCL line is ‘1’). This should not occur; it represents erroneous I2C bus behavior. In case of lost arbitration,
the I2C slave state machine aborts the ongoing transfer. Software may decide to clear the TX and RX FIFOs in case of
this error.
❐ I2C slave received NACK – When the slave receives a NACK (typically after the slave transmitted TX data).
❐ I2C slave received ACK – When the slave receives an ACK (typically after the slave transmitted TX data).
❐ I2C slave received STOP – I2C STOP event for I2C (read or write) transfer intended for this slave (address matching is
performed). When STOP or REPEATED START event is detected. The REPEATED START event is included in this
interrupt cause such that the I2C transfers separated by a REPEATED START can be distinguished and potentially
treated separately by the firmware. Note that the second I2C transfer (after a REPEATED START) may be to a differ-
ent slave address.
The event is detected on any I2C transfer intended for this slave. Note that an I2C address intended for the slave
(address matches) will result in an I2C_STOP event independent of whether the I2C address is ACK'd or NACK'd.
❐ I2C slave received START – When START or REPEATED START event is detected. In the case of an externally-
clocked address matching (CTRL.EC_AM_MODE is ‘1’) and clock stretching is performed (until the internally-clocked
logic takes over) (I2C_CTRL.S_NOT_READY_ADDR_NACK is ‘0’), this field is not set. Firmware should use
INTR_S_EC.WAKE_UP, INTR_S.I2C_ADDR_MATCH, and INTR_S.I2C_GENERAL.
❐ I2C slave address matched – I2C slave matching address received. If CTRL.ADDR_ACCEPT, the received address
(including the R/W bit) is available in the RX FIFO. In the case of externally-clocked address matching
(CTRL.EC_AM_MODE is ‘1’) and internally-clocked operation (CTRL.EC_OP_MODE is '0'), this field is set when the
event is detected.
❐ I2C bus error – Unexpected STOP/START condition is detected
■
2
I C TX
❐ TX trigger – TX FIFO has fewer entries than the value specified by TRIGGER_LEVEL in SCB_TX_FIFO_CTRL.
❐ TX FIFO not full – At least one data element can be written into the TX FIFO.
❐ TX FIFO empty – The TX FIFO is empty.
❐ TX FIFO overflow – Firmware attempts to write to a full TX FIFO.
❐ TX FIFO underflow – Hardware attempts to read from an empty TX FIFO.
■
2
I C RX
❐ RX FIFO has more entries than the value specified by TRIGGER_LEVEL in SCB_RX_FIFO_CTRL.

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 Serial Communications Block (SCB)

❐ RX FIFO is full – The RX FIFO is full.

❐ RX FIFO is not empty – At least one data element is available in the RX FIFO to be read.
❐ RX FIFO overflow – Hardware attempts to write to a full RX FIFO.
❐ RX FIFO underflow – Firmware attempts to read from an empty RX FIFO.
■
2
I C Externally Clocked
❐ Wake up request on address match – Active on incoming slave request (with address match). Only set when EC_AM
is ‘1’.
❐ I2C STOP detection at the end of each transfer – Only set for a slave request with an address match, in EZ and
CMD_RESP modes, when EC_OP is ‘1’.
❐ I2C STOP detection at the end of a write transfer – Activated at the end of a write transfer (I2C STOP). This event is an
indication that a buffer memory location has been written to. For EZ mode, a transfer that only writes the base address
does not activate this event. Only set for a slave request with an address match, in EZ and CMD_RESP modes, when
EC_OP is ‘1’.
❐ I2C STOP detection at the end of a read transfer – Activated at the end of a read transfer (I2C STOP). This event is an
indication that a buffer memory location has been read from. Only set for a slave request with an address match, in EZ
and CMD_RESP modes, when EC_OP is ‘1’.
For more information on how to implement and clear interrupts see the I2C (SCB_I2C_PDL) datasheet and the PDL.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 374
 29. Serial Memory Interface (SMIF)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The SMIF block implements a single-SPI, dual-SPI, quad-SPI, or octal-SPI communication to interface with external memory
chips. The SMIF block’s primary use case is to set up the external memory and have it mapped to the PSoC 6 MCU memory
space using the hardware. This mode of operation, called the XIP mode, allows the bus masters in the PSoC 6 MCU to
directly interact with the SMIF for memory access to an external memory location.
A graphical interface is provided with the ModusToolbox for configuring the QSPI (SMIF) block. For more information, see the
ModusToolbox QSPI Configurator Guide.

29.1 Features
The Serial Memory Interface (SMIF) block provides a master interface to serial memory devices that supports the following
functionality.
■ Interfacing up to four memory devices (slaves) at a time
■ SPI protocol
❐ SPI mode 0: clock polarity (CPOL) and clock phase (CPHA) are both ‘0’
❐ Support for single, dual, quad, and octal SPI protocols
❐ Support for dual-quad SPI mode: the use of two quad SPI memory devices to increase data bandwidth for SPI read
and write transfers
❐ Support for configurable MISO sampling time and programmable receiver clock
■ Support for device capacities in the range of 64 KB to 128 MB
■ eXecute In Place (XIP) enables mapping the external memory into an internal memory address
■ Command mode enables using the SMIF block as a simple communication hardware
■ Supports a 4-KB read cache in memory mapped (XIP) mode
■ Supports on-the-fly 128-bit encryption and decryption

29.2 Architecture
Figure 29-1 shows a high-level block diagram of the SMIF hardware in PSoC 6 MCUs. Notice that the block is divided into
multiple clock domains. This enables multiple domains to access the SMIF and still enable maintaining an asynchronous
clock for the communication interface.
The SMIF block can also generate DMA triggers and interrupt signals. This allows events in the SMIF block to trigger actions
in other parts of the system.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 375
 Serial Memory Interface (SMIF)

The SMIF interface is implemented using eight data lines, four slave select lines, and a clock line.
The access to the SMIF block can be by two modes: Command mode or XIP mode. The Command mode gives access to the
SMIF’s peripheral registers and the internal FIFOs. This mode is used when the user code is responsible for constructing the
command structure for the external memory. Typically, this mode is used when the SMIF writes to an external flash memory.
The MMIO interface is also used to configure the SMIF hardware block, including configuring the device registers that set up
the XIP operation of the SMIF block.
The XIP mode of operation maps the external memory space to a range of addresses in the PSoC 6 MCU’s address space.
Refer to the registers TRM for details. When this address range is accessed, the hardware automatically generates the
commands required to initiate the associated transfer from the external memory. The typical use case for the XIP mode is to
execute code placed in external memory. Thus executing code from external memory is seamless.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 376
 Serial Memory Interface (SMIF)

Figure 29-1. SMIF Hardware Block Diagram

SMIF

XIP XIP MMIO AHB-Lite

clk_slow domain

clk_fast domain

clk_sys domain
AHB-Lite AHB-Lite interface
interface 0 interface 1

4 KB 4 KB MMIO
cache cache

Port arbiter

tr_tx_req
Cryptography tr_rx_req
interrupt
XIP

clk_hf domain
Mode multiplexer

FIFOs

Tx data Tx command Rx data

clk_if_rx domain
clk_if_tx domain

FIFO FIFO FIFO

Tx state machine Rx state machine

Capture
Logic
clk_if domain

Memory interface logic

IOSS

clk select[3:0] data[7:0]

The SMIF block has three AHB-Lite interfaces: specified by SMIFn_CTL.XIP_MODE. The operation mode
■ An AHB-Lite interface to access the SMIF’s MMIO should not be modified when the SMIF is busy
registers. (STATUS.BUSY is ‘1’).
■ Two AHB-Lite interfaces to support execute-in-place In the MMIO AHB-Lite interface, access is supported
(XIP). through software writes to transmit (Tx) FIFOs and software
reads from receive (Rx) FIFOs. The FIFOs are mapped on
All interfaces provide access to external memory devices. At
SMIF registers. This interface provides the flexibility to
any time, either the MMIO AHB-Lite interface or the two XIP
implement any memory device transfer. For example,
AHB-Lite interfaces have access to the memory interface
memory device transfers to setup, program, or erase the
logic and external memory devices. The operation mode is
external memory devices.

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 Serial Memory Interface (SMIF)

In an XIP AHB-Lite interface, access is supported through memory interface. The TX_COUNT command specifies
XIP: AHB-Lite read and write transfers are automatically (by the width of the data transfer and always constitutes the
the hardware) translated in memory device read and write last phase of the memory transfer (implicit “last
transfers. This interface provides efficient implementation of command” indication - de-asserts the slave select). Note
memory device read and write transfers, but does NOT that the TX_COUNT command does not assert the slave
support other types of memory device transfers. To improve select lines. This must be done by a Tx command
XIP performance, the XIP AHB-Lite interface has a 4-KB preceding it.
read cache. ■ RX_COUNT command. The RX_COUNT command
As mentioned, Command mode and XIP mode are mutually specifies the number of bytes to be received from the Rx
exclusive. The operation modes share Tx and Rx FIFOs and data FIFO. This command relies on the Rx data FIFO to
memory interface logic. In Command mode, the Tx and Rx accept the bytes that are received over the memory
FIFOs are accessed through the SMIF registers and under interface. The RX_COUNT command specifies the width
software control. In XIP mode, the Tx and Rx FIFOs are of the data transfer and always constitutes the last
under hardware control. The memory interface logic is phase of the memory transfer (implicit “last command”
controlled through the Tx and Rx FIFOs and is agnostic of indication - de-asserts the slave select). Note that the
the operation mode. RX_COUNT command does not assert the slave select
lines. This must be done by a Tx command preceding it.
29.2.1 Tx and Rx FIFOs ■ DUMMY_COUNT command. The DUMMY_COUNT
command specifies a number of dummy cycles. Dummy
The SMIF block has two Tx FIFOs and one Rx FIFO. These cycles are used to implement a turn-around (TAR) time
FIFOs provide an asynchronous clock domain transfer in which the memory master changes from a transmitter
between clk_hf logic and clk_if_tx/clk_if_rx memory driving the data lines to a receiver receiving on the same
interface logic. The memory interface logic is completely data lines. The DUMMY_COUNT command never
controlled through the Tx and Rx FIFOs. constitutes the last phase of the memory transfer
■ The Tx command FIFO transmits memory commands to (implicit NOT “last command” indication - de-asserts the
the memory interface logic. slave select); that is, it must be followed by another
command. Note that the DUMMY COUNT command
■ The Tx data FIFO transmits write data to the memory
does not assert the slave select lines. This must be done
interface transmit logic.
by a Tx command preceding it.
■ The Rx data FIFO receives read data from the memory
interface receive logic. Together, the four command types can be used to construct
any SPI transfer. The Tx command FIFO is used by both the
29.2.1.1 Tx Command FIFO memory interface transmit and receive logic. This ensures
lockstep operation. The Tx command is a representation of
The Tx command FIFO consists of four 20-bit entries. Each a queue of commands that are to be processed.
entry holds a command. A memory transfer consists of a
series of commands. In other words, a command specifies a The software will write the sequence of commands into the
phase of a memory transfer. Four different types of Tx command FIFO to generate a sequence responsible for
commands are supported: the communication with slave device. The software can read
the number of used Tx command FIFO entries through the
■ Tx command. A memory transfer must start with a Tx
TX_CMD_FIFO_STATUS.USED[2:0] register field.
command. The Tx command includes a byte that is to be
transmitted over the memory interface. The Tx The software can write to the Tx command FIFO through the
command specifies the width of the data transfer (single, MMIO TX_CMD_FIFO_WR register. If software attempts to
dual, quad, or octal data transfer). The Tx command write to a full Tx command FIFO, the MMIO CTL.BLOCK
specifies whether the command is for the last phase of field specifies the behavior:
the memory transfer (explicit “last command” indication). ■ If CTL.BLOCK is ‘0’, an AHB-Lite bus error is generated.
The Tx command specifies which of the four external
■ If CTL.BLOCK is ‘1’, the AHB-Lite write transfer is
devices are selected (multiple devices can be selected
extended until an entry is available. This increases
simultaneously); that is, the device selection as encoded
latency.
by the Tx command is used for the complete memory
transfer. The Tx command asserts the corresponding
slave select lines. This is the reason every memory
29.2.1.2 Tx Data FIFO
transfer should start with this command. The Tx data FIFO consists of eight 8-bit entries. A Tx
■ TX_COUNT command. The TX_COUNT command command FIFO TX_COUNT command specifies the
specifies the number of bytes to be transmitted from the number of bytes to be transmitted; that is, specifies the
Tx data FIFO. This command relies on the Tx data FIFO number of Tx data FIFO entries used. The Tx data FIFO is
to provide the bytes that are to be transmitted over the used by the memory interface transmit logic.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 378
 Serial Memory Interface (SMIF)

Software can read the number of used Tx data FIFO entries reads from the Rx FIFO. The Tx command FIFO has
through the TX_DATA_FIFO_STATUS.USED[3:0] register formatted commands (Tx, TX_COUNT, RX_COUNT, and
field. DUMMY_COUNT) that are described in the registers TRM.
Software can write to the Tx data FIFO through the Software should ensure that it generates correct memory
TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, and transfers and accesses the FIFOs correctly. For example, if
TX_DATA_FIFO_WR4 registers: a memory transfer is generated to read four bytes from a
■ The TX_DATA_FIFO_WR1 register supports a write of a memory device, software should read the four bytes from
single byte to the FIFO. the Rx data FIFO. Similarly, if a memory transfer is
generated to write four bytes to a memory device, software
■ The TX_DATA_FIFO_WR2 register supports a write of
should write the four bytes to the Tx command FIFO or Tx
two bytes to the FIFO.
data FIFO.
■ The TX_DATA_FIFO_WR4 register supports a write of
four bytes to the FIFO. If software attempts to write more Incorrect software behavior can lock up the memory
bytes than available entries in the Tx data FIFO, the interface. For example, a memory transfer to read 32 bytes
MMIO CTL.BLOCK field specifies the behavior: from a memory device, without software reading the Rx data
FIFO will lock up the memory transfer as the memory
■ If CTL.BLOCK is ‘0’, an AHB-Lite bus error is generated.
interface cannot provide more than eight bytes to the Rx
■ If CTL.BLOCK is ‘1’, the AHB-Lite write transfer is data FIFO (the Rx data FIFO has eight entries). This will
extended until the required entries are available. prevent any successive memory transfers from taking place.
Hence, the software should make sure that it read the FIFOs
29.2.1.3 Rx Data FIFO to avoid congestion. Note that a locked up memory transfer
due to Tx or Rx FIFO states is still compliant to the memory
The Rx data FIFO consists of eight 8-bit entries. A Tx
bus protocol (but undesirable): the SPI protocol allows
command FIFO RX_COUNT command specifies the
shutting down the interface clock in the middle of a memory
number of bytes to be received; that is, specifies the number
transfer.
of Rx data FIFO entries used. The memory interface
transmit logic will stop generating the SPI clock when the Rx
data FIFO is full. This is how flow control is achieved. 29.2.3 XIP Mode
Software can read the number of used Rx data FIFO entries If CTL.XIP_MODE is ‘1’, the SMIF is in XIP mode. Hardware
through the RX_DATA_FIFO_STATUS.USED[3:0] register automatically (without software intervention) generates
field. memory transfers by accessing the Tx FIFOs and Rx FIFO.
Hardware supports only memory read and write transfers.
Software can read from the Rx data FIFO through the MMIO Other functionality such as status reads are not supported.
RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, and This means operations such as writing into a flash device
RX_DATA_FIFO_RD4 registers: may not be supported by XIP mode. This is because the
■ The RX_DATA_FIFO_RD1 register supports a read of a writing operation into a flash memory involves not only a
single byte from the FIFO. write command transfer, but also a status check to verify the
■ The RX_DATA_FIFO_RD2 register supports a read of status of the operation.
two bytes from the FIFO. ■ Hardware generates a memory read transfer for an
■ The RX_DATA_FIFO_RD4 register supports a read of AHB-Lite read transfer (to be precise: only for AHB-Lite
four bytes from the FIFO. If software attempts to read read transfers that miss in the cache).
more bytes than available in the Rx data FIFO, the ■ Hardware generates a memory write transfer for an
MMIO CTL.BLOCK field specifies the behavior: AHB-Lite write transfer.
■ If BLOCK is ‘0’, an AHB-Lite bus error is generated and Each slave device slot has a set of associated device
hard fault occurs. configuration registers. To access a memory device in XIP
If BLOCK is ‘1’, the AHB-Lite read transfer is extended until mode, the corresponding device configuration registers
the bytes are available. (SMIFn_DEVICEn) should be initialized. The device
configuration register sets up the following parameters for
Software can also read the first byte of the RX data FIFO memory:
without changing the status of the FIFO through the
■ Write enable (WR_EN): Used to disable writes in XIP
RX_DATA_FIFO_RD1_SILENT register.
mode.
■ Crypto enable (CRYPTO_EN): When enabled, all read
29.2.2 Command Mode access to the memory is decrypted and write access
If CTL.XIP_MODE is ‘0’, the SMIF is in Command mode. encrypted automatically.
Software generates SPI transfers by accessing the Tx ■ Data Select (DATA_SEL): Selects the data lines to be
FIFOs and Rx FIFO. Software writes to the Tx FIFOs and used (Connecting SPI Memory Devices on page 382).

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 Serial Memory Interface (SMIF)

■ Base address and size: Sets up the mapped memory cache. Read transfers that “miss” result in a XIP memory
space. Any access in this space is converted to the read transfer.
access to the external memory automatically.
If CA_CTL.PREF_EN is ‘1’, prefetching is enabled and if
■ Read and write commands: Used to communicate with CA_CTL.PREF_EN is ‘0’, prefetching is disabled. If prefetch
the external memory device. These commands are is enabled, a cache miss results in a 16 B (subsector) refill
defined by multiple settings. for the missing data AND a 16 B prefetch for the next
As different memory devices support different types of sequential data (independent of whether this data is already
memory read and write commands, you must provide the in the cache or not).
hardware with device specifics, such that it can perform the Cache coherency is not supported by the hardware. For
automatic translations. To this end, each memory device example, an XIP interface 0 write to an address in the XIP
has a set of MMIO registers that specify its memory read interface 0 cache invalidates (clears) the associated cache
and write transfers. This specification includes: subsector in the XIP interface 0 cache, but not in the XIP
■ Presence and value of the SPI command byte. interface 1 cache. This means XIP interface 1 cache now
■ Number of address bytes. has outdated data. The user code can manually invalidate
cache by using the SLOW_CA_CMD[INV] or
■ Presence and value of the mode byte.
FAST_CA_CMD[INV] register.
■ Number of dummy cycles.
Caches should also be invalidated upon mode transitions.
■ Specified data transfer widths.
For example, in Command mode, a write to an address in
The XIP interface logic produces an AHB-Lite bus error the cache interface will cause the data in the cache interface
under the following conditions: to be outdated. The cache should be invalidated when
■ The SMIF is disabled (SMIFn_CTL.ENABLED is ‘0’). transitioning to XIP mode to ensure that only valid data is
used.
■ The SMIF is not in XIP_MODE (SMIFn_CTL.XIP_MODE
is ‘0’).
29.2.5 Arbitration
■ The transfer request is not in a memory region.
■ The transfer is a write and the identified memory region The SMIF provides two AHB-Lite slave interfaces to CPUSS
does not support writes (one fast interface and one slow interface). Both interfaces
(SMIFn_DEVICEn_CTL.WR_EN is ‘0’). have a cache (as described in 29.2.4 Cache) and can
generate XIP requests to the external memory devices.
■ In XIP mode (CTL.XIP_MODE is ‘1’) and dual quad SPI
mode (ADDR_CTL.DIV2 is ‘1’) or the transfer address is An arbitration component (as shown in Figure 29-1)
not a multiple of 2. arbitrates between the two interfaces. Arbitration is based
■ In XIP mode (CTL.XIP_MODE is ‘1’) and dual quad SPI on the master identifier of the AHB-Lite transfer. The
mode (ADDR_CTL.DIV2 is ‘1’), the transfer size is not a arbitration priority is specified by a system wide priority.
multiple of 2. Each master identifier has a 2-bit priority level (“0” is the
highest priority level and “3” is the lowest priority level).
Master identifiers with the same priority level are within the
29.2.4 Cache same priority group. Within a priority group, round-robin
To improve XIP performance, the XIP AHB-Lite interface arbitration is performed.
has a cache. The cache is defined as follows:
■ 4 KB capacity. 29.2.6 Deselect Delay
■ Read-only cache. Write transfers bypass the cache. A The SMIF supports configuration of deselect delay between
write to an address, which is prefetched in the cache, transfers. The SMIFn_CTL.DESELECT_DELAY field
invalidates the associated cache subsector. If there is a controls the minimum number of interface cycles to hold the
write to a memory in Command mode then you must chip select line inactive.
invalidate the cache while switching back to XIP mode.
■ Four-way set associative, with a least recently used 29.2.7 Cryptography
(LRU) replacement scheme.
In XIP mode, a cryptography component supports on-the-fly
Each XIP interface implements a 4-KB cache memory, encryption for write data and on-the-fly decryption for read
enabled by default. Any XIP access can be cached if a data. The use of on-the-fly cryptography is determined by a
cache is enabled. There are separate cache registers for the device’s MMIO CTL.CRYPTO_EN field. In Command mode,
slow cache (in the clk_slow domain) and fast cache (in the the cryptography component is accessible through a
clk_fast domain). The cache can be enabled using the register interface to support offline encryption and
SLOW_CA_CTL[ENABLED] or FAST_CA_CTL[ENABLED] decryption.
registers. Read transfers that “hit” are processed by the

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 Serial Memory Interface (SMIF)

The usage scenario for cryptography is: data is encrypted in hardware, by applying AES-128 with KEY[127:0] on a
the external memory devices. Therefore, memory read and plaintext PT[127:0], we get a ciphertext CT[127:0].
write data transfers require decryption and encryption
In XIP mode, the XIP address is used as the plaintext PT[].
functionality respectively. By storing data encrypted in the
The resulting ciphertext CT[] is used on-the-fly and not
external memory devices (nonvolatile devices), leakage of
software accessible. The XIP address is extended with the
sensitive data is avoided.
CRYPTO_INPUT3, …, CRYPTO_INPUT0 registers.
Encryption and decryption are based on the AES-128
In Command mode, the MMIO CRYPTO_INPUT3, …,
forward block cipher: advanced encryption standard block
CRYPTO_INPUT0 registers provide the plaintext PT[]. The
cipher with a 128-bit key. KEY[127:0] is a secret (private)
resulting ciphertext CT[] is provided through the MMIO
key programmed into the CRYPTO_KEY3, …,
CRYPTO_OUTPUT3, …, CRYPTO_OUTPUT0 registers.
CRYPTO_KEY0 registers. These registers are software
write-only: a software read returns “0”. In the SMIF Figure 29-2 illustrates the functionality in XIP and Command
modes.
Figure 29-2. Cryptography in XIP and Command Modes
XIP mode MMIO mode

On-the-fly
{CRYPTO_OUTPUT3,
usage CRYPTO_OUTPUT2,
CRYPTO_OUTPUT1,
ciphertext CT[127:0] CRYPTO_OUTPUT0}

{CRYPTO_KEY3, {CRYPTO_KEY3,
AES-128 AES-128
CRYPTO_KEY2, CRYPTO_KEY2,
forward block forward block
CRYPTO_KEY1, CRYPTO_KEY1,
cipher cipher
CRYPTO_KEY0} CRYPTO_KEY0}

{CRYPTO_INPUT3, {CRYPTO_INPUT3,
CRYPTO_INPUT2, CRYPTO_INPUT2,
CRYPTO_INPUT1, CRYPTO_INPUT1,
A[31:4], CRYPTO_INPUT0}
CRYPT0_INPUT0.INPUT[3:0]}

In XIP mode, the resulting ciphertext CT[] (of the encrypted address) is XOR’d with the memory transfer’s read data or write
data. Note that the AES-128 block cipher is on the address of the data and not on the data itself. For memory read transfers,
this means that as long as the latency of the memory transfer’s read data is longer than the AES-128 block cipher latency, the
on-the-fly decryption does not add any delay. Figure 29-3 illustrates the complete XIP mode functionality.
The XIP mode only encrypts the address and XORs with the data; to implement the same in Command mode, you must
provide the address as the PT[] into the crypto_INPUTx registers.
Figure 29-3. XIP Mode Functionality
encrypted read data encrypted write data

128 128
ciphertext CT[127:0]

{CRYPTO_KEY3,
AES-128
CRYPTO_KEY2,
forward block
CRYPTO_KEY1,
cipher
CRYPTO_KEY0}
128 128

{CRYPTO_INPUT3, decrypted read data decrypted write data

CRYPTO_INPUT2,
CRYPTO_INPUT1,
A[31:4],
CRYPT0_INPUT0.INPUT[3:0]}

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 Serial Memory Interface (SMIF)

29.3 Memory Device Signal ■ The definition of a write transfer to support XIP mode.

Interface Each memory device uses a dedicated device select signal:

memory device 0 uses select[0], memory device 1 uses
The SMIF acts as a master for SPI applications. SPI select[1], and so on. In other words, there is a fixed, one-to-
requires the definition of clock polarity and phase. In SPI one connection between memory device, register set, and
mode, the SMIF supports a single clock polarity and phase select signal connection.
configuration:
In XIP mode, the XIP AHB-Lite bus transfer address is
■ Clock polarity (CPOL) is ‘0’: the base value of the clock compared with the device region. If the address is within the
is 0. device region, the device select signal is activated. If an XIP
■ Clock phase (CPHA) is ‘0’: driving of data is on the AHB-Lite bus transfer address is within multiple regions (this
falling edge of the clock; capturing of data is specified by is possible if the device regions overlap), all associated
CTL.CLOCK_IF_RX_SEL. device select signals are activated. This overlap enables
XIP in dual-quad SPI mode: the command, address, and
The above configuration is also known as SPI configuration mode bytes can be driven to two quad SPI devices
0 and is supported by SPI memory devices. simultaneously.

29.3.1 Specifying Memory Devices In XIP mode, dual quad SPI mode requires the
ADDR_CTL.DIV2 field of the selected memory devices to be
The SMIF requires that the memory devices are defined for set to ‘1’. When this field is ‘1’, the transfer address is
their operation in XIP mode. The SMIF supports up to four divided by 2 and the divided by 2 address is provided to the
memory devices. Each memory device is defined by a set of memory devices.
registers. The memory device specific register structure
In dual quad SPI mode, each memory device contributes a
includes:
4-bit nibble for each 8-bit byte. However, both memory
■ The device base address and capacity. The ADDR devices are quad SPI memories with a byte interface.
register specifies the memory device’s base address in Therefore, the transfer size must be a multiple of 2.
the PSoC 6 MCU address space and the MASK register
specifies the memory device’s size/capacity. If a memory The XIP_ALIGNMENT_ERROR interrupt cause is set under
device is not present or is disabled, the ADDR and the following conditions (in XIP mode and when
MASK registers specify a memory device with 0 B ADDR_CTL.DIV2 is ‘1’):
capacity. Typically, the devices’ address regions in the ■ The transfer address is not a multiple of 2. In this case
PSoC 6 MCU address space are non-overlapping the divided by 2 address for the memory devices is
(except for dual-quad SPI mode) to ensure that the incorrect.
activation of select signals is mutually exclusive. ■ The transfer size is not a multiple of 2. In this case, the
■ The device data signal connections (as described in memory devices contribute only a nibble of a byte. This
Connecting SPI Memory Devices on page 382). is not supported as the memory devices have a byte
■ The definition of a read transfer to support XIP mode. interface.

29.3.2 Connecting SPI Memory Devices

Memory device I/O signals (SCK, CS, SI/IO0, SO/IO1, IO2, IO3, IO4, IO5, IO6, IO7) are connected to the SMIF I/O signals
(clk, select[3:0], and spi_data[7:0]). Not all memory devices provide the same number of I/O signals.

Table 29-1. Memory Device I/O Signals

Memory Device IO Signals
Single SPI memory SCK, CS, SI, SO. This memory device has two data signals (SI and SO).
Dual SPI memory SCK, CS, IO0, IO1. This memory device has two data signals (IO0, IO1).
Quad SPI memory SCK, CS, IO0, IO1, IO2, IO3. This memory device has four data signals (IO0, IO1, IO2, IO3).
SCK, CS, IO0, IO1, IO2, IO3, IO4, IO5, IO6, IO7. This memory device has eight data signals (IO0, IO1, IO2,
Octal SPI memory
IO3, IO4, IO5, IO6, IO7).

Table 29-1 illustrates that each memory has a single clock signal SCK, a single (low active) select signal (CS), and multiple
data signals (IO0, IO1, …).
Each memory device has a fixed select signal connection (to select[3:0]).

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 Serial Memory Interface (SMIF)

Each memory device has programmable data signal connections (to data[7:0]): the CTL.DATA_SEL[1:0] field specifies how a
device’s data signals are connected. The CTL.DATA_SEL[1:0] is responsible for configuring the selection of data lines to be
used by a slave. This is not to be confused with the select lines that are used for addressing the four slaves of the SMIF
master. This information is used by the SMIF interface to drive out data on the correct spi_data[] outputs and capture data
from the correct spi_data[] inputs. If multiple device select signals are activated, the same data is driven to all selected
devices simultaneously.
Not all data signal connections are legal/supported. Supported connections are dependent on the type of memory device.

Table 29-2. Data Signal Connections

DATA_SEL[1:0] Single SPI Device Dual SPI Device Quad SPI Device Octal SPI Device
spi_data[0] = IO0 spi_data[0] = IO0
spi_data[0] = SI spi_data[0] = IO0
0 … …
spi_data[1] = SO spi_data[1] = IO1
spi_data[3] = IO3 spi_data[7] = IO7
spi_data[2] = SI spi_data[2] = IO0
1 Illegal Illegal
spi_data[3] = SO spi_data[3] = IO1
spi_data[4] = IO0
spi_data[4] = SI spi_data[4] = IO0
2 … Illegal
spi_data[5] = SO spi_data[5] = IO1
spi_data[7] = IO3
spi_data[6] = SI spi_data[6] = IO0
3 Illegal Illegal
spi_data[7] = SO spi_data[7] = IO1

Memory devices can:

■ Use shared data signal connections.
■ Use dedicated data signal connections. This reduces the load on the data lines allowing faster signal level changes, which
in turn allows for a faster I/O interface.
Note that dual-quad SPI mode requires dedicated data signals to enable read and/or write data transfer from and to two quad
SPI devices simultaneously.
Figure 29-4 illustrates memory device 0, which is a single SPI memory with data signals connections to spi_data[1:0].
Figure 29-4. Single SPI Memory Device 0 Connected to spi_data[1:0]

CTL.DATA_SEL[1:0] = 0
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
SO

spi_data[0]
spi_data[1]

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 Serial Memory Interface (SMIF)

Because of the pin layout, you might want to connect a memory device to specific data lines. Figure 29-5 illustrates memory
device 0, which is a single SPI memory with data signals connections to spi_data[7:6].
Figure 29-5. Single SPI Memory Device 0 Connected to spi_data[7:6]

CTL.DATA_SEL[1:0] = 3
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
SO

spi_data[6]
spi_data[7]

Figure 29-6 illustrates memory devices 0 and 1, both of which are single SPI memories. Each device uses dedicated data
signal connections. The device address regions in the PSoC 6 MCU address space must be non-overlapping to ensure that
the activation of select[0] and select[1] are mutually exclusive.
Figure 29-6. Single SPI Memory Devices 0 and 1 - Dedicated Data Signal

CTL.DATA_SEL[1:0] = 0
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
spi_select[1]
SO

CTL.DATA_SEL[1:0] = 3
Device 1: SPI
spi_data[0] SCK memory

spi_data[1] CS
SI
SO

spi_data[6]
spi_data[7]

Figure 29-7 illustrates memory devices 0 and 1, both of which are single SPI memories. Both devices use shared data signal
connections. The devices’ address regions in the PSoC 6 MCU address space must be non-overlapping to ensure that the
activation of select[0] and select[1] are mutually exclusive. Note that this solution increases the load on the data lines, which
may result in a slower I/O interface.

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 Serial Memory Interface (SMIF)

Figure 29-7. Single SPI Memory Devices 0 and 1 - Shared Data Signal

CTL.DATA_SEL[1:0] = 0
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
spi_select[1]
SO

CTL.DATA_SEL[1:0] = 0
Device 1: SPI
spi_data[0] SCK memory

spi_data[1] CS
SI
SO

Figure 29-8 illustrates memory device 0, which is a quad SPI memory with data signals connections to spi_data[7:4].
Figure 29-8. Quad SPI Memory Device 0

CTL.DATA_SEL[1:0] = 0
SoC Device 0:
Quad SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI/IO0
SO/IO1
WP/IO2
HOLD/IO3
spi_data[0]
spi_data[1]
spi_data[2]
spi_data[3]

Figure 29-9 illustrates memory devices 0 and 1, device 0 is a single SPI memory and device 1 is a quad SPI memory. Each
device uses dedicated data signal connections. The device address regions in the PSoC 6 MCU address space must be non-
overlapping to ensure that the activation of select[0] and select[1] are mutually exclusive.

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 Serial Memory Interface (SMIF)

Figure 29-9. Single SPI Memory 0 and Quad SPI Memory 1 - Dedicated Data Signal

CTL.DATA_SEL[1:0] = 0
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
spi_select[1]
SO

CTL.DATA_SEL[1:0] = 2
Device 1:
Quad SPI
spi_data[0] SCK memory
spi_data[1] CS
SI/IO0
SO/IO1
spi_data[4] WP/IO2
spi_data[5] HOLD/IO3
spi_data[6]
spi_data[7]

Figure 29-10 illustrates memory devices 0 and 1, device 0 is a single SPI memory and device 1 is a quad SPI memory. Both
devices use shared data signal connections. The device address regions in the PSoC 6 MCU address space must be non-
overlapping to ensure that the activation of select[0] and select[1] are mutually exclusive.
Figure 29-10. Single SPI Memory Device 0 and Quad SPI Memory Device 1 - Shared Data Signal

CTL.DATA_SEL[1:0] = 0
SoC Device 0: SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI
spi_select[1]
SO

CTL.DATA_SEL[1:0] = 0
Device 1:
Quad SPI
spi_data[0] SCK memory
spi_data[1] CS
spi_data[2] SI/IO0
spi_data[3] SO/IO1
WP/IO2
HOLD/IO3

Figure 29-11 illustrates memory devices 0 and 1, both of which are quad SPI memories. Each device uses dedicated data
signal connections. The device address regions in the PSoC 6 MCU address space are the same to ensure that the activation
of select[0] and select[1] are the same (in XIP mode). This is known as a dual-quad configuration: during SPI read and write
transfers, each device provides a nibble of a byte.

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 Serial Memory Interface (SMIF)

Figure 29-11. Quad SPI Memory Devices 0 and 1

CTL.DATA_SEL[1:0] = 0
SoC Device 0:
Quad SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI/IO0
spi_select[1]
SO/IO1
WP/IO2
HOLD/IO3
spi_data[0]
CTL.DATA_SEL[1:0] = 2
spi_data[1] Device 1:
Quad SPI
spi_data[2] SCK memory
spi_data[3] CS
spi_data[4] SI/IO0
spi_data[5] SO/IO1
spi_data[6] WP/IO2
spi_data[7] HOLD/IO3

Figure 29-12 illustrates memory device 0, which is a octal SPI memory with data signals connections to spi_data[7:0].
Figure 29-12. Octal SPI Memory Device 0

CTL.DATA_SEL[1:0] = 0
Device 0:
SoC
Octal SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
IO0
IO1
IO2
IO3
spi_data[0] IO4
spi_data[1] IO5
spi_data[2] IO6
spi_data[3] IO7
spi_data[4]
spi_data[5]
spi_data[6]
spi_data[7]

29.3.3 SPI Data Transfer

SPI data transfer uses most-significant-bit (MSb) for the first data transfer. This means that for a byte B, consisting of bits b7,
b6, …, b0, bit b7 is transferred first, followed by bit b6, and so on. For dual, quad, dual quad, and octal SPI transfers, multiple

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 Serial Memory Interface (SMIF)

bits are transferred per cycle. For a single SPI device and device data signal connections to spi_data[1:0] (DATA_SEL is “0”),
Table 29-3 summarizes the transfer of byte B.

Table 29-3. Single Data Transfer

Cycle Data Transfer
For a write transfer: b7 is transferred on data[0] and SI/IO0.
0
For a read transfer: b7 is transferred on data[1] and SO/IO1.
For a write transfer: b6 is transferred on data[0] and SI/IO0.
1
For a read transfer: b6 is transferred on data[1] and SO/IO1.
For a write transfer: b5 is transferred on data[0] and SI/IO0.
2
For a read transfer: b5 is transferred on data[1] and SO/IO1.
For a write transfer: b4 is transferred on data[0] and SI/IO0.
3
For a read transfer: b4 is transferred on data[1] and SO/IO1.
For a write transfer: b3 is transferred on data[0] and SI/IO0.
4
For a read transfer: b3 is transferred on data[1] and SO/IO1.
For a write transfer: b2 is transferred on data[0] and SI/IO0.
5
For a read transfer: b2 is transferred on data[1] and SO/IO1.
For a write transfer: b1 is transferred on data[0] and SI/IO0.
6
For a read transfer: b1 is transferred on data[1] and SO/IO1.
For a write transfer: b0 is transferred on data[0] and SI/IO0.
7
For a read transfer: b0 is transferred on data[1] and SO/IO1.

Note that in single SPI data transfer, the data signals are uni-directional: in the table, data[0] is exclusively used for write data
connected to the device SI input signal and data[1] is exclusively used for read data connected to the device SO output
signal.
For a dual SPI device and device data signal connections to data[1:0] (DATA_SEL is “0”), Table 29-4 summarizes the transfer
of byte B.

Table 29-4. Dual Data Transfer

Cycle Data Transfer
0 b7, b6 are transferred on data[1:0] and IO1, IO0.
1 b5, b4 are transferred on data[1:0] and IO1, IO0.
2 b3, b2 are transferred on data[1:0] and IO1, IO0.
3 b1, b0 are transferred on data[1:0] and IO1, IO0.

For a quad SPI device and device data signal connections to data[3:0] (DATA_SEL is “0”), Table 29-5 summarizes the
transfer of byte B.

Table 29-5. Quad Data Transfer

Cycle Data Transfer
0 b7, b6, b5, b4 are transferred on data[3:0] and IO3, IO2, IO1, IO0.
1 b3, b2, b1, b0 are transferred on data[3:0] and IO3, IO2, IO1, IO0.

For a octal SPI device and device data signal connections to data[7:0] (DATA_SEL is “0”), Table 29-6 summarizes the transfer
of byte B.

Table 29-6. Octal Data Transfer

Cycle Data Transfer
0 b7, b6, b5, b4, b3, b2, b1, b0 are transferred on data[7:0] and IO7, IO6, IO5, IO4, IO3, IO2, IO1, IO0.

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 Serial Memory Interface (SMIF)

In dual-quad SPI mode, two quad SPI devices are used.

■ The first device (the device with the lower device structure index) should have device data signal connections to data[3:0]
(DATA_SEL is 0).
■ The second device (the device with the higher device structure index) should have device data signal connection to
data[7:4] (DATA_SEL is 2).
The command and data phases of the SPI transfer use different width data transfers:
■ The command, address, and mode bytes use quad SPI data transfer.
■ The read data and write data use octal data transfer. Each device provides a nibble of each data byte: the first device
provides the lower nibble and the second device provides the higher nibble.
Table 29-7 summarizes the transfer of a read data and write data byte B.

Table 29-7. Dual-quad SPI Mode, Octal Data Transfer

Cycle Data transfer
b7, b6, b5, b4 are transferred on data[7:4] and second device IO3, IO2, IO1, IO0.
0
b3, b2, b1, b0 are transferred on data[3:0] and first device IO3, IO2, IO1, IO0.

29.3.4 Example of Setting up SMIF

Devices 0 and 1 are used to implement the dual-quad SPI mode. Both devices are 1 MB / 8 Mb; the address requires 3 bytes.
Device 0 has device data signal connections to data[3:0] and device 1 has device data signal connections to data[7:4].
Figure 29-13. Setting up SMIF

CTL.DATA_SEL[1:0] = 0
SoC Device 0:
Quad SPI
spi_clk SCK memory
SMIF
CS
spi_select[0]
SI/IO0
spi_select[1]
SO/IO1
WP/IO2
HOLD/IO3
spi_data[0]
CTL.DATA_SEL[1:0] = 2
spi_data[1] Device 1:
Quad SPI
spi_data[2] SCK memory
spi_data[3] CS
spi_data[4] SI/IO0
spi_data[5] SO/IO1
spi_data[6] WP/IO2
spi_data[7] HOLD/IO3

For dual quad SPI mode, the AHB-Lite bus transfer address is divided by two. Cryptography and write functionality are
disabled in the following example.
#define MASK_1MB 0xfff00000;
DEV0_ADDR = CPUSS_SMIF_BASE;
DEV0_MASK = MASK_1MB // MASK: 1 MB region
DEV0_CTL =(0 << SMIF_DEVICE_CTL_DATA_SEL_Pos) // DATA_SEL: data[3:0]
| (0 << SMIF_DEVICE_CTL_CRYPTO_EN_Pos) // CRYPTO_EN
| (0 << SMIF_DEVICE_CTL_WR_EN_Pos)); // WR_EN
DEV0_ADDR_CTL = (1 << SMIF_DEVICE_ADDR_CTL_DIV2_Pos) // DIV2: enabled
| ((3-1) << SMIF_DEVICE_ADDR_CTL_SIZE2_Pos)); // SIZE: 3 B address

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 Serial Memory Interface (SMIF)

DEV1_ADDR = CPUSS_SMIF_BASE;
DEV1_MASK = 0xfff00000; // MASK: 1 MB region
DEV1_CTL = (2 << SMIF_DEVICE_CTL_DATA_SEL_Pos) // DATA_SEL: data[7:4]
| (0 << SMIF_DEVICE_CTL_CRYPTO_EN_Pos) // CRYPTO_EN
| (1 << SMIF_DEVICE_CTL_WR_EN_Pos)); // WR_EN
DEV1_ADDR_CTL = (1 << SMIF_DEVICE_ADDR_CTL_DIV2_Pos) // DIV2: enabled
| ((3-1) << SMIF_DEVICE_ADDR_CTL_SIZE2_Pos)); // SIZE: 3 B address
For XIP read transfers, the 0xEB command/instruction is used (Figure 29-14 illustrates a two-byte transfer from devices 0 and
1 in dual quad SPI mode).
Figure 29-14. Two-Bye Transfer in Dual Quad SPI Mode
0xEB instruction, instruction 1 bit/cycle; address, mode, data 4 bits/cycle

spi_select[0]

spi_select[1]
0 7 8 13 14 15 16 19 20 21
spi_clk
4 dummy
instruction (0xeb) 24 bit address
mode cycles 8-bit data

spi_data[0] 20 16 12 0 4 0 0 0

spi_data[1] 21 17 13 1 5 1 1 1

spi_data[2] 22 18 14 2 6 2 2 2

spi_data[3] 23 19 15 3 7 3 3 3

spi_data[4] 20 16 12 0 4 0 4 4

spi_data[5] 21 17 13 1 5 1 5 5

spi_data[6] 22 18 14 2 6 2 6 6

spi_data[7] 23 19 15 3 7 3 7 7

single quad octal

The definition of a read transfer is as follows:

DEV0_RD_CMD_CTL = (1UL << SMIF_DEVICE_RD_CMD_CTL_PRESENT_Pos) // PRESENT
| (0 << SMIF_DEVICE_RD_CMD_CTL_WIDTH_Pos) // WIDTH: single data transfer
| 0xeb); // CODE
DEV0_RD_ADDR_CTL = (2 << SMIF_DEVICE_RD_ADDR_CTL_WIDTH_Pos)); // WIDTH: quad data transfer
DEV0_RD_MODE_CTL = (1UL << SMIF_DEVICE_RD_MODE_CTL_PRESENT_Pos) // PRESENT
| (2 << SMIF_DEVICE_RD_MODE_CTL_WIDTH_Pos) // WIDTH: quad data transfer
| 0x00); // CODE
DEV0_RD_DUMMY_CTL= (1UL << SMIF_DEVICE_RD_DUMMY_CTL_PRESENT_Pos) // PRESENT
| ((4-1) << SMIF_DEVICE_RD_DUMMY_CTL_SIZE5_Pos)); // SIZE: 4 dummy cycles
DEV0_RD_DATA_CTL = (3 << SMIF_DEVICE_RD_DATA_CTL_WIDTH_Pos)); // WIDTH: octal data transfer
Note that the command uses single data transfer, the address and mode byte use quad data transfer, and the read data byte
uses octal data transfer.

29.4 Triggers
The SMIF has two level-sensitive triggers:
■ tr_tx_req is associated with the Tx data FIFO.
■ tr_rx_req is associated with the Rx data FIFO.

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 Serial Memory Interface (SMIF)

If the SMIF is enabled (CTL.ENABLED is ‘1’) and Command operation mode is selected (CTL.XIP_MODE is ‘0’), the trigger
functionality is enabled. If the SMIF is disabled (CTL.ENABLED is ‘0’) or the XIP operation mode is selected (CTL.XIP_MODE
is ‘1’), the triggers functionality is disabled. The trigger functionality is defined as follows:
■ The MMIO TX_DATA_FIFO_CTL.TRIGGER_LEVEL field specifies a number of FIFO entries. The tr_tx_req trigger is
active when the number of used Tx data FIFO entries is smaller or equal than the specified number; that is,
TX_DATA_FIFO_STATUS.USED  TRIGGER_LEVEL.
■ The MMIO RX_DATA_FIFO_CTL.TRIGGER_LEVEL field specifies a number of FIFO entries. The tr_rx_req trigger is
active when the number of used Rx data FIFO entries is greater than the specified number; that is,
RX_DATA_FIFO_STATUS.USED > TRIGGER_LEVEL.

29.5 Interrupts
The SMIF has a single interrupt output with six interrupt causes:
■ INTR.TR_TX_REQ. This interrupt cause is activated in Command mode when the tr_tx_req trigger is activated.
■ INTR.TR_RX_REQ. This interrupt cause is activated in Command mode when the tr_rx_req trigger is activated.
■ INTR.XIP_ALIGNMENT_ERROR. This interrupt cause is activated in XIP mode when the selected device’s
ADDR_CTL.DIV2 field is ‘1’ and the AHB-Lite bus address is not a multiple of 2, or the requested transfer size is not a
multiple of 2. This interrupt cause identifies erroneous behavior in dual-quad SPI mode (the selected device
ADDR_CTL.DIV2 field is set to ‘1’).
■ INTR.TX_CMD_FIFO_OVERFLOW. This interrupt cause is activated in Command mode, on an AHB-Lite write transfer to
the Tx command FIFO (TX_CMD_FIFO_WR) with insufficient free entries.
■ INTR.TX_DATA_FIFO_OVERFLOW. This interrupt cause is activated in Command mode, on an AHB-Lite write transfer
to the Tx data FIFO (TX_DATA_FIFO_WR1, TX_DATA_FIFO_WR2, and TX_DATA_FIFO_WR4) with insufficient free
entries.
■ INTR.RX_DATA_FIFO_OVERFLOW. This interrupt cause is activated in Command mode, on an AHB-Lite read transfer
from the Rx data FIFO (RX_DATA_FIFO_RD1, RX_DATA_FIFO_RD2, and RX_DATA_FIFO_RD4) with insufficient free
entries.

29.6 Sleep Operation

The SMIF hardware is operational in the Sleep and Active power modes. In the Sleep power mode, only DMA driven
transactions can be performed because the CPU acting as the SPI master is not active.

29.7 Performance
Accesses to the external memory will have some latency, which is dependent upon the mode of SMIF operation, the amount
of data being transferred, caching, and cryptography. In Command mode, the number of interface clock cycles per transfer is
determined by the equation:

opcode size address size mode size data size

Time to Transfer N bytes =   ---------------------------------- +  ------------------------------------ +  ----------------------------- + dummycycles +  --------------------------- 
(in interface clock cycles)   opcode width   address width   mode width   data width 

For example, in Figure 29-14, the equation to calculate the number of cycles would be (22 cycles = [8 bit instruction/1 single
width] + [24 bit address/4 width] + [8 bit mode/4 width] + 4 dummy cycles + [16 bit data/8 width]).
In XIP Mode, the performance is affected by the cache. For data reads that hit in the cache, the read will not incur any
interface cycles. Read operations that miss in the cache will occur as a normal SMIF read operation and, if prefetching is
enabled, will result in two 16 B cache sub-sector refills. Writes to external memory in XIP mode will occur as a normal SMIF
write operation.
Enabling cryptography may impact SMIF performance. The AES-128 block cipher has a typical latency of 13 clk_hf cycles.
This means that for transfers that take more than 13 cycles, the on-the-fly decryption does not add any delay. If the transfer is
less than 13 cycles, the transfer latency will be 13 cycles. When the cache is enabled, the 13-cycle latency for encryption is
incurred only once for every 16 B fetched for the cache.

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 30. Timer, Counter, and PWM (TCPWM)

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Timer, Counter, Pulse Width Modulator (TCPWM) block in the PSoC 6 MCU uses a 16- or 32-bit counter, which can be
configured as a timer, counter, pulse width modulator (PWM), or quadrature decoder. The block can be used to measure the
period and pulse width of an input signal (timer), find the number of times a particular event occurs (counter), generate PWM
signals, or decode quadrature signals. This chapter explains the features, implementation, and operational modes of the
TCPWM block.

30.1 Features
■ The TCPWM block supports the following operational modes:
❐ Timer-counter with compare
❐ Timer-counter with capture
❐ Quadrature decoding
❐ Pulse width modulation
❐ Pseudo-random PWM
❐ PWM with dead time
■ Up, Down, and Up/Down counting modes.
■ Clock prescaling (division by 1, 2, 4, ... 64, 128)
■ 16- or 32-bit counter widths
■ Double buffering of compare/capture and period values
■ Underflow, overflow, and capture/compare output signals
■ Supports interrupt on:
❐ Terminal count – Depends on the mode; typically occurs on overflow or underflow
❐ Capture/compare – The count is captured to the capture register or the counter value equals the value in the compare
register
■ Complementary output for PWMs
■ Selectable start, reload, stop, count, and capture event signals (events refer to peripheral generated signals that trigger
specific functions in each counter in the TCPWM block) for each TCPWM – with rising edge, falling edge, both edges, and
level trigger options

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 Timer, Counter, and PWM (TCPWM)

30.2 Architecture
Figure 30-1. TCPWM Block Diagram

1
C o u n te r i 2 ...
i

Synchronization
T rig g e r in p u ts

Trigger
E ve n t C o n fig u ra tio n
16 1 6-b it o r 3 2-b it co u n te r
G e n e ra tio n re g iste rs

3
co u n te r_ e n 2 pwm ,
u n d e rflo w , in te rru p t pwm _n
F o r e a ch o ve rflo w ,
C o u n te r i cc_ m a tch (ca p tu re o r co m p a re )

The TCPWM block can contain up to 32 counters. Each counter can be 16- or 32-bit wide. The three main registers that
control the counters are:
■ TCPWM_CNT_CC is used to capture the counter value in CAPTURE mode. In all other modes this value is compared to
the counter value.
■ TCPWM_CNT_COUNTER holds the current counter value.
■ TCPWM_CNT_PERIOD holds the upper value of the counter. When the counter counts for n cycles, this field should be
set to n–1.
The number of 16- and 32-bit counters are device specific; refer to the PSoC 61 datasheet/PSoC 62 datasheet for details.
In this chapter, a TCPWM refers to the entire block and all the counters inside. A counter refers to the individual counter
inside the TCPWM. Within a TCPWM block the width of each counter is the same.
TCPWM has these interfaces:
■ I/O signal interface: Consists of input triggers (such as reload, start, stop, count, and capture) and output signals (such as
pwm, pwm_n, overflow (OV), underflow (UN), and capture/compare (CC)). All of these input signals are used to trigger an
event within the counter, such as a reload trigger generating a reload event. The output signals are generated by internal
events (underflow, overflow, and capture/compare) and can be connected to other peripherals to trigger events.
■ Interrupts: Provides interrupt request signals from each counter, based on TC or CC conditions.
The TCPWM block can be configured by writing to the TCPWM registers. See “TCPWM Registers” on page 428 for more
information on all registers required for this block.

30.2.1 Enabling and Disabling Counters in a TCPWM Block

A counter can be enabled by setting the corresponding bit of the TCPWM_CTRL_SET register. It can be disabled by setting
the bit in the TCPWM_CTRL_CLR register. These registers are used to avoid race-conditions on read-modify-write attempts
to the TCPWM_CTRL register, which controls the enable/disable fields of the counters.
Note: The counter must be configured before enabling it. Disabling the counter retains the values in the configuration
registers.

30.2.2 Clocking
Each TCPWM counter can have its own clock source and the only source for the clock is from the configurable peripheral
clock dividers generated by the clocking system; see the Clocking System chapter on page 242 for details. To select a clock
divider for a particular counter inside a TCPWM, use the CLOCK_CTL register from the PERI register space.

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 Timer, Counter, and PWM (TCPWM)

In this section the clock to the counter will be called clk_counter. Event generation is performed on clk_counter. Another clock,
clk_sys is used for the pulse width of the output triggers. clk_sys is synchronous to clk_peri (see “CLK_PERI” on page 253),
but can be divided using CLOCK_CTL from the PERI_GROUP_STRUCT register space.

30.2.2.1 Clock Prescaling

clk_counter can be further divided inside each counter, with values of 1, 2, 4, 8…64, 128. This division is called prescaling.
The prescaling is set in the GENERIC field of the TCPWM_CNT_CTLR register.
Note: Clock prescaling is not available in quadrature mode and pulse width modulation mode with dead time.

30.2.2.2 Count Input

The counter increments or decrements on a prescaled clock in which the count input is active – “active count”.
When the count input is configured as level, the count value is changed on each prescaled clk_counter edge in which the
count input is high.
When the count input is configured as rising/falling the count value is changed on each prescaled clk_counter edge in which
an edge is detected on the count input.
The next section contains additional details on edge detection configuration.
Note: Count events are not supported in quadrature and pulse-width modulation pseudo-random modes; the clk_counter is
used in these cases instead of the active count prescaled clock.
Figure 30-2. Counter Clock Generation
not s upported in all m odes
count event
active count
C o u n ter
P re -scalin g pre-scaled pre-scaled
clk_counter fu n ctio n ality
counter clock counter clock

Note: The count event and pre-scaled counter clock are AND together, which means that a count event must occur to
generate an active count pre-scaled counter clock.

30.2.3 Trigger Inputs

Each TCPWM block has 14 Trigger_In signals, which come from other on-chip resources such as other TCPWMs, SCBs, or
DMA. The Trigger_In signals are shared with all counters inside of one TCPWM block. Use the Trigger Mux registers to
configure which signals get routed to the Trigger_In for each TCPWM block. See the Trigger Multiplexer Block chapter on
page 294 for more details. Two constant trigger inputs ‘0’ and ‘1’ are available in addition to the 14 Trigger_In. For each
counter, the trigger input source is selected using the TCPWM_CNT_TR_CTRL0 register.
Each counter can select any of the 16 trigger signals to be the source for any of the following events:
■ Reload
■ Start
■ Stop/Kill
■ Count
■ Capture/swap
When starting a TCPWM for the first time it is recommended that a reload is used, because a reload will generate an overflow
or underflow on startup. If start is used, an overflow or underflow will not be generated on startup.
The TCPWM_CMD_RELOAD, TCPWM_CMD_STOP, TCPWM_CMD_START, and TCPWM_CMD_CAPTURE registers can
be used to trigger the reload, stop, start, and capture respectively from software.
The sections describing each TCPWM mode will describe the function of each input in detail.
Typical operation uses the reload input to initialize and start the counter and the stop input to stop the counter. When the
counter is stopped, the start input can be used to start the counter with its counter value unmodified from when it was
stopped.

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 Timer, Counter, and PWM (TCPWM)

If stop, reload, and start coincide, the following precedence relationship holds:
■ A stop has higher priority than a reload.
■ A reload has higher priority that a start.
As a result, when a reload or start coincides with a stop, the reload or start has no effect.
Before going to the counter each Trigger_IN can pass through a positive edge detector, negative edge detector, both edge
detector, or pass straight through to the counter. This is controlled using TCPWM_CNT_TR_CTRL1. In the quadrature mode,
edge detection is done using clk_counter. For all other modes, edge detection is done using the clk_peri.
Multiple detected events are treated as follows:
■ In the rising edge and falling edge modes, multiple events are effectively reduced to a single event. As a result, events
may be lost (see Figure 30-3).
■ In the rising/falling edge mode, an even number of events are not detected and an odd number of events are reduced to a
single event. This is because the rising/falling edge mode is typically used for capture events to determine the width of a
pulse. The current functionality will ensure that the alternating pattern of rising and falling is maintained (see Figure 30-4).
Figure 30-3. Multiple Rising Edge Capture
MODE = CAPTURE
UP_DOWN_MODE = COUNT_UP
CAPTURE_EDGE = RISING_EDGE Missed capture event
reload

capture
1 CC_BUFF
1 3 CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
CC_MATCH

Figure 30-4. Multiple Both Edge Capture

MODE = CAPTURE
UP_DOWN_MODE = COUNT_UP
Even number of capture Odd number of capture
CAPTURE_EDGE = BOTH_EDGES
events => no capture events => single capture
reload

capture
CC_BUFF
3 CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

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 Timer, Counter, and PWM (TCPWM)

Figure 30-5. TCPWM Input Events

Trigger input sources Rising edge detect 0

0 Falling edge detect 1

1 Rising or Falling
edge detect 2 event
Trigger_In[14]
No edge detect 3
TCPWM_CMD registers
(software generated)

TCPWM_CNT_TR_CTRL0
TCPWM_CNT_TR_CTRL1

Notes:
■ All trigger inputs are synchronized to clk_peri.
■ When more than one event occurs in the same clk_counter period, one or more events may be missed. This can happen
for high-frequency events (frequencies close to the counter frequency) and a timer configuration in which a pre-scaled
(divided) clk_counter is used.

30.2.4 Trigger Outputs

Each counter can generate three trigger output events. These trigger output events can be routed through the trigger mux to
other peripherals on the device. The three trigger outputs are:
■ Overflow (OV): An overflow event indicates that in up-counting mode, COUNTER equals the PERIOD register, and is
changed to a different value.
■ Underflow (UN): An underflow event indicates that in down-counting mode, COUNTER equals 0, and is changed to a
different value.
■ Compare/Capture (CC): This event is generated when the counter is running and one of the following conditions occur:
❐ Counter equals the compare value. This event is either generated when the match is about to occur (COUNTER does
not equal the CC register and is changed to CC) or when the match is not about to occur (COUNTER equals CC and
is changed to a different value).
❐ A capture event has occurred and the CC/CC_BUFF registers are updated.
Note: These signals remain high only for two cycles of clk_sys.

30.2.5 Interrupts
The TCPWM block provides a dedicated interrupt output for each counter. This interrupt can be generated for a terminal
count (TC) or CC event. A TC is the logical OR of the OV and UN events.
Four registers are used to handle interrupts in this block, as shown in Table 30-1.

Table 30-1. Interrupt Register

Interrupt Registers Bits Name Description
0 TC This bit is set to ‘1’, when a terminal count is detected. Write '1' to clear this bit.
TCPWM_CNT_INTR
(Interrupt request register) This bit is set to ‘1’ when the counter value matches capture/compare register value.
1 CC_MATCH
Write '1' to clear this bit.
Write '1' to set the corresponding bit in the interrupt request register. When read, this reg-
0 TC
TCPWM_CNT_INTR_SET ister reflects the interrupt request register status.
(Interrupt set request register) Write '1' to set the corresponding bit in the interrupt request register. When read, this reg-
1 CC_MATCH
ister reflects the interrupt request register status.

TCPWM_CNT_INTR_MASK 0 TC Mask bit for the corresponding TC bit in the interrupt request register.
(Interrupt mask register) 1 CC_MATCH Mask bit for the corresponding CC_MATCH bit in the interrupt request register.

TCPWM_CNT_INTR_MASKED 0 TC Logical AND of the corresponding TC request and mask bits.

(Interrupt masked request register) 1 CC_MATCH Logical AND of the corresponding CC_MATCH request and mask bits.

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 Timer, Counter, and PWM (TCPWM)

30.2.6 PWM Outputs

Each counter has two outputs, pwm (line_out) and pwm_n (line_compl_out) (complementary of pwm). Note that the OV, UN,
and CC conditions are used to drive pwm and pwm_n, by configuring the TCPWM_CNT_TR_CTRL2 register (Table 30-2).

Table 30-2. Configuring Output for OV, UN, and CC Conditions

Field Bit Value Event Description
0 Set pwm to '1

CC_MATCH_MODE 1 Clear pwm to '0 Configures output line on a compare

1:0
Default Value = 3 2 Invert pwm match (CC) event

3 No change
0 Set pwm to '1

OVERFLOW_MODE 1 Clear pwm to '0 Configures output line on a overflow

3:2
Default Value = 3 2 Invert pwm (OV) event

3 No change
0 Set pwm to '1

UNDERFLOW_MODE 1 Clear pwm to '0 Configures output line on a underflow

5:4
Default Value = 3 2 Invert pwm (UN) event

3 No change

30.2.7 Power Modes

The TCPWM block works in Active and Sleep modes. The TCPWM block is powered from VCCD. The configuration registers
and other logic are powered in Deep Sleep mode to keep the states of configuration registers. See Table 30-3 for details.

Table 30-3. Power Modes in TCPWM Block

Power Mode Block Status
CPU Active This block is fully operational in this mode with clock running and power switched on.
CPU Sleep The CPU is in sleep but the block is still functional in this mode. All counter clocks are on.
CPU Deep Sleep Both power and clocks to the block are turned off, but configuration registers retain their states.
System Hibernate In this mode, the power to this block is switched off. Configuration registers will lose their state.

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 Timer, Counter, and PWM (TCPWM)

30.3 Operation Modes

The counter block can function in six operational modes, as shown in Table 30-4. The MODE [26:24] field of the counter
control register (TCPWM_CNTx_CTRL) configures the counter in the specific operational mode.

Table 30-4. Operational Mode Configuration

MODE Field
Mode Description
[26:24]
The counter increments or decrements by '1' at every clk_counter cycle in which a count event is detected.
Timer 000
The Compare/Capture register is used to compare the count.
The counter increments or decrements by '1' at every clk_counter cycle in which a count event is detected. A
Capture 010
capture event copies the counter value into the capture register.
Quadrature decoding. The counter is decremented or incremented based on two phase inputs according to
Quadrature 011
an X1, X2, or X4 decoding scheme.
PWM 100 Pulse width modulation.
PWM_DT 101 Pulse width modulation with dead time insertion.
Pseudo-random PWM using a 16- or 32-bit linear feedback shift register (LFSR) to generate pseudo-random
PWM_PR 110
noise.

The counter can be configured to count up, down, and up/down by setting the UP_DOWN_MODE[17:16] field in the
TCPWM_CNT_CTRL register, as shown in Table 30-5.

Table 30-5. Counting Mode Configuration

UP_DOWN_
Counting Modes Description
MODE[17:16]
Increments the counter until the period value is reached. A Terminal Count (TC) and Over-
UP Counting Mode 00
flow (OV) condition is generated when the counter changes from the period value.
Decrements the counter from the period value until 0 is reached. A TC and Underflow (UN)
DOWN Counting Mode 01
condition is generated when the counter changes from a value of ‘0’.
Increments the counter until the period value is reached, and then decrements the counter
UP/DOWN Counting Mode 1 10 until ‘0’ is reached. TC and UN conditions are generated only when the counter changes
from a value of ‘0’.
Similar to up/down counting mode 1 but a TC condition is generated when the counter
changes from ‘0’ and when the counter value changes from the period value. OV and UN
UP/DOWN Counting Mode 2 11
conditions are generated similar to how they are generated in UP and DOWN counting
modes respectively.

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 Timer, Counter, and PWM (TCPWM)

30.3.1 Timer Mode

The timer mode can be used to measure how long an event takes or the time difference between two events. The timer
functionality increments/decrements a counter between 0 and the value stored in the PERIOD register. When the counter is
running, the count value stored in the COUNTER register is compared with the compare/capture register (CC). When the
counter changes from a state in which COUNTER equals CC, the cc_match event is generated.
Timer functionality is typically used for one of the following:
■ Timing a specific delay – the count event is a constant ‘1’.
■ Counting the occurrence of a specific event – the event should be connected as an input trigger and selected for the count
event.

Table 30-6. Timer Mode Trigger Input Description

Trigger Inputs Usage

Sets the counter value and starts the counter. Behavior is dependent on UP_DOWN_MODE:
■ COUNT_UP: The counter is set to “0” and count direction is set to “up”.
Reload ■ COUNT_DOWN: The counter is set to PERIOD and count direction is set to “down”.
■ COUNT_UPDN1/2: The counter is set to “1” and count direction is set to “up”.
Can be used when the counter is running or not running.
Starts the counter. The counter is not initialized by hardware. The current counter value is used. Behavior is
dependent on UP_DOWN_MODE. When the counter is not running:
■ COUNT_UP: The count direction is set to “up”.
Start ■ COUNT_DOWN: The count direction is set to “down”.
■ COUNT_UPDN1/2: The count direction is not modified.
Note that when the counter is running, the start event has no effect.
Can be used when the counter is running or not running.
Stop Stops the counter.
Count Count event increments/decrements the counter.
Capture Not used.

Incrementing and decrementing the counter is controlled by the count event and the counter clock clk_counter. Typical
operation will use a constant ‘1’ count event and clk_counter without pre-scaling. Advanced operations are also possible; for
example, the counter event configuration can decide to count the rising edges of a synchronized input trigger.

Table 30-7. Timer Mode Supported Features

Supported Features Description

Clock pre-scaling Pre-scales the counter clock clk_counter.
Counter is stopped by hardware, after a single period of the counter:
One-shot ■ COUNT_UP: on an overflow event.
■ COUNT_DOWN, COUNT_UPDN1/2: on an underflow event.

Auto reload CC CC and CC_BUFF are exchanged on a cc_match event (when specified by CTRL.AUTO_RELOAD_CC)
Specified by UP_DOWN_MODE:
■ COUNT_UP: The counter counts from 0 to PERIOD.
Up/down modes
■ COUNT_DOWN: The counter counts from PERIOD to 0.
■ COUNT_UPDN1/2: The counter counts from 1 to PERIOD and back to 0.

Table 30-6 lists the trigger outputs and the conditions when they are triggered.

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Table 30-8. Timer Mode Trigger Outputs

Trigger Outputs Description

cc_match (CC) Counter changes from a state in which COUNTER equals CC.
Underflow (UN) Counter is decrementing and changes from a state in which COUNTER equals “0”.
Overflow (OV) Counter is incrementing and changes from a state in which COUNTER equals PERIOD.

Note: Each output is only two clk_sys wide and is represented by an arrow in the timing diagrams in this chapter, for example
see Figure 30-7.

Table 30-9. Timer Mode Interrupt Outputs

Interrupt Outputs Description

Specified by UP_DOWN_MODE:
■ COUNT_UP: The tc event is the same as the overflow event.
tc ■ COUNT_DOWN: The tc event is the same as the underflow event.
■ COUNT_UPDN1: The tc event is the same as the underflow event.
■ COUNT_UPDN2: The tc event is the same as the logical OR of the overflow and underflow events.

cc_match (CC) Counter changes from a state in which COUNTER equals CC.

Table 30-10. Timer Mode PWM Outputs

PWM Outputs Description

pwm Not used.
pwm_n Not used.

Figure 30-6. Timer Functionality

Timer Interrupt
tc interrupt
Reload generation
Start PERIOD
cc_match tr_cc_match
Stop == Trigger
underflow tr_underflow
Count generation
COUNTER overflow tr_overflow

==
CC

clk_counter
CC_BUFF

Notes:
■ The timer functionality uses only PERIOD (and not PERIOD_BUFF).
■ Do not write to COUNTER when the counter is running.
Figure 30-7 illustrates a timer in up-counting mode. The counter is initialized (to 0) and started with a software-based reload
event.
Notes:
■ PERIOD is 4, resulting in an effective repeating counter pattern of 4+1 = 5 clk_counter periods. The CC register is 2, and
sets the condition for a cc_match event.
■ When the counter changes from a state in which COUNTER is 4, overflow and tc events are generated.
■ When the counter changes from a state in which COUNTER is 2, a cc_match event is generated.

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■ A constant count event of ‘1’ and clk_counter without prescaling is used in the following scenarios. If the count event is ‘0’
and a reload event is triggered, the reload will be registered only on the first clock edge when the count event is ‘1’. This
means that the first clock edge when the count event is ‘1’ will not be used for counting. It will be used for reload.
Figure 30-7. Timer in Up-counting Mode
MODE = TIMER
UP_DOWN_MODE = COUNT_UP COUNTER starts with 0 period is PERIOD+1

reload
4 PERIOD = 4
COUNTER

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no TC event CC event on leaving the
COUNTER value

Figure 30-8 illustrates a timer in “one-shot” operation mode. Note that the counter is stopped on a tc event.
Figure 30-8. Timer in One-shot Mode
MODE = TIMER
UP_DOWN_MODE = COUNT_UP
ONE_SHOT = 1

reload
4 PERIOD = 4
COUNTER

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Figure 30-9 illustrates clock pre-scaling. Note that the counter is only incremented every other counter cycle.
Figure 30-9. Timer Clock Pre-scaling
MODE = TIMER
UP_DOWN_MODE = COUNT_UP
ONE_SHOT = 1
PRESCALE = DIV_BY_2

reload
4 PERIOD = 4
COUNTER

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Figure 30-10 illustrates a counter that is initialized and started (reload event), stopped (stop event), and continued/started
(start event). Note that the counter does not change value when it is not running (STATUS.RUNNING).

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Figure 30-10. Counter Start/Stopped/Continued

MODE = TIMER
UP_DOWN_MODE = COUNT_UP

reload
stop
start
4 PERIOD = 4
COUNTER
3

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

RUNNING

Figure 30-11 illustrates a timer that uses both CC and CC_BUFF registers. Note that CC and CC_BUFF are exchanged on a
cc_match event.
Figure 30-11. Use of CC and CC_BUFF Register Bits
MODE = TIMER
UP_DOWN_MODE = COUNT_UP
AUTO_RELOAD_CC = 1

0 3 0 3 0 3 0 3 0 3 CC_BUFF
reload 3 0 3 0 3 0 3 0 3 0 CC
4 PERIOD = 4
COUNTER

Underflow (UV)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Figure 30-12 illustrates a timer in down counting mode. The counter is initialized (to PERIOD) and started with a software-
based reload event.
Notes:
■ When the counter changes from a state in which COUNTER is 0, a UN and TC events are generated.
■ When the counter changes from a state in which COUNTER is 2, a cc_match event is generated.
■ PERIOD is 4, resulting in an effective repeating counter pattern of 4+1 = 5 counter clock periods.

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Figure 30-12. Timer in Down-counting Mode

MODE = TIMER
UP_DOWN_MODE = COUNT_DOWN COUNTER starts with PERIOD period is PERIOD+1

reload
4 PERIOD = 4

COUNTER
3

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no TC event CC event on leaving the
COUNTER value

Figure 30-13 illustrates a timer in up/down counting mode 1. The counter is initialized (to 1) and started with a software-based
reload event.
Notes:
■ When the counter changes from a state in which COUNTER is 4, an overflow is generated.
■ When the counter changes from a state in which COUNTER is 0, an underflow and tc event are generated.
■ When the counter changes from a state in which COUNTER is 2, a cc_match event is generated.
■ PERIOD is 4, resulting in an effective repeating counter pattern of 2*4 = 8 counter clock periods.
Figure 30-13. Timer in Up/Down Counting Mode 1
MODE = TIMER
UP_DOWN_MODE = COUNT_UPDN1 COUNTER starts with 1 period is 2*PERIOD

reload
4 PERIOD = 4
COUNTER

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no TC event CC event on leaving the
COUNTER value

Figure 30-14 illustrates a timer in up/down counting mode 1, with different CC values.
Notes:
■ When CC is 0, the cc_match event is generated at the start of the period (when the counter changes from a state in which
COUNTER is 0).
■ When CC is PERIOD, the cc_match event is generated at the middle of the period (when the counter changes from a
state in which COUNTER is PERIOD).

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Figure 30-14. Up/Down Counting Mode with Different CC Values

MODE = TIMER
UP_DOWN_MODE = COUNT_UPDN1

reload 1 0 4 CC
4 PERIOD = 4

COUNTER
3

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
cc_match‫ﺴ‬event at the
start of the period

Figure 30-15 illustrates a timer in up/down counting mode 2. This mode is same as up/down counting mode 1, except for the
TC event, which is generated when either underflow or overflow event occurs.
Figure 30-15. Up/Down Counting Mode 2
MODE = TIMER
UP_DOWN_MODE = COUNT_UPDN2 COUNTER starts with 1 period is 2*PERIOD

reload
4 PERIOD = 4
COUNTER

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no TC event CC event on leaving the
COUNTER value

30.3.1.1 Configuring Counter for Timer Mode

The steps to configure the counter for Timer mode of operation and the affected register bits are as follows.
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select Timer mode by writing ‘000’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required 16- or 32-bit period in the TCPWM_CNT_PERIOD register.
4. Set the 16- or 32-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPW-
M_CNT_CC_BUFF register.
5. Set AUTO_RELOAD_CC field of the TCPWM_CNT_CTRL register, if required to swap values at every CC condition.
6. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register.
7. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register.
8. The timer can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the
ONE_SHOT[18] field of the TCPWM_CNT_CTRL register.
9. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (reload, start, stop, capture, and
count).
10. Set the TCPWM_CNT_TR_CTRL1 register to select the edge of the trigger that causes the event (reload, start, stop, cap-
ture, and count).
11. If required, set the interrupt upon TC or CC condition.
12. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

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30.3.2 Capture Mode

The capture functionality increments and decrements a counter between 0 and PERIOD. When the capture event is activated
the counter value COUNTER is copied to CC (and CC is copied to CC_BUFF).
The capture functionality can be used to measure the width of a pulse (connected as one of the input triggers and used as
capture event).
The capture event can be triggered through the capture trigger input or through a firmware write to command register
(TCPWM_CMD_CAPTURE).

Table 30-11. Capture Mode Trigger Input Description

Trigger Inputs Usage

Sets the counter value and starts the counter. Behavior is dependent on UP_DOWN_MODE:
■ COUNT_UP: The counter is set to “0” and count direction is set to “up”.
reload ■ COUNT_DOWN: The counter is set to PERIOD and count direction is set to “down”.
■ COUNT_UPDN1/2: The counter is set to “1” and count direction is set to “up”.
Can be used only when the counter is not running.
Starts the counter. The counter is not initialized by hardware. The current counter value is used. Behavior is
dependent on UP_DOWN_MODE:
■ COUNT_UP: The count direction is set to “up”.
start
■ COUNT_DOWN: The count direction is set to “down”.
■ COUNT_UPDN1/2: The count direction is not modified.
Can be used only when the counter is not running.
stop Stops the counter.
count Count event increments/decrements the counter.
capture Copies the counter value to CC and copies CC to CC_BUFF.

Table 30-12. Capture Mode Supported Features

Supported Features Description

Clock pre-scaling Pre-scales the counter clock clk_counter.
Counter is stopped by hardware, after a single period of the counter:
One-shot ■ COUNT_UP: on an overflow event.
■ COUNT_DOWN, COUNT_UPDN1/2: on an underflow event.

Specified by UP_DOWN_MODE:
■ COUNT_UP: The counter counts from 0 to PERIOD.
Up/down modes
■ COUNT_DOWN: The counter counts from PERIOD to 0.
■ COUNT_UPDN1/2: The counter counts from 1 to PERIOD and back to 0.

Table 30-13. Capture Mode Trigger Output Description

Trigger Outputs Description

cc_match (CC) CC is copied to CC_BUFF and counter value is copied to CC (cc_match equals capture event).
Underflow (UN) Counter is decrementing and changes from a state in which COUNTER equals “0”.
Overflow (OV) Counter is incrementing and changes from a state in which COUNTER equals PERIOD.

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Table 30-14. Capture Mode Interrupt Outputs

Interrupt Outputs Description

Specified by UP_DOWN_MODE:
■ COUNT_UP: tc event is the same as the overflow event.
tc ■ COUNT_DOWN: tc event is the same as the underflow event.
■ COUNT_UPDN1: tc event is the same as the underflow event.
■ COUNT_UPDN2: tc event is the same as the logical OR of the overflow and underflow events.

cc_match (CC) CC is copied to CC_BUFF and counter value is copied to CC (cc_match equals capture event).

Table 30-15. Capture Mode PWM Outputs

PWM Outputs Description

pwm Not used.
pwm_n Not used.

Figure 30-16. Capture Functionality

Capture Interrupt
Reload tc interrupt
generation
Start PERIOD
Stop cc_match tr_cc_match
== Trigger
Count underflow tr_underflow
generation
Capture COUNTER overflow tr_overflow

==
CC

clk_counter
CC_BUFF

Figure 30-17 illustrates capture behavior in the up counting mode.

Notes:
■ The capture event detection uses rising edge detection. As a result, the capture event is remembered until the next “active
count” pre-scaled counter clock.
■ When a capture event occurs, COUNTER is copied into CC. CC is copied to CC_BUFF.
■ A cc_match event is generated when the counter value is captured.
Figure 30-17. Capture in Up Counting Mode
MODE = CAPTURE
UP_DOWN_MODE = COUNT_UP
CAPTURE_EDGE = RISING_EDGE
reload

capture
1 4 CC_BUFF
1 4 3 CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

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When multiple capture events are detected before the next “active count” pre-scaled counter clock, capture events are
treated as follows:
■ In the rising edge and falling edge modes, multiple events are effectively reduced to a single event.
■ In the rising/falling edge mode, an even number of events is not detected and an odd number of events is reduced to a
single event.
This behavior is illustrated by Figure 30-18, in which a pre-scaler by a factor of 4 is used.
Figure 30-18. Multiple Events Detected before Active-Count
MODE = CAPTURE
UP_DOWN_MODE = COUNT_UP
CAPTURE_EDGE = RISING_EDGE missed capture event
reload

capture
1 CC_BUFF
1 3 CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

30.3.2.1 Configuring Counter for Capture Mode

The steps to configure the counter for Capture mode operation and the affected register bits are as follows.
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select Capture mode by writing ‘010’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register.
5. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register.
6. Counter can be configured to run either in continuous mode or one-shot mode by writing 0 or 1, respectively to the ONE_-
SHOT[18] field of the TCPWM_CNT_CTRL register.
7. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (reload, start, stop, capture, and
count).
8. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, stop, capture, and
count).
9. If required, set the interrupt upon TC or CC condition.
10. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

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30.3.3 Quadrature Decoder Mode

Quadrature functionality increments and decrements a counter between 0 and 0xFFFF or 0xFFFFFFFF (32-bit mode).
Counter updates are under control of quadrature signal inputs: index, phiA, and phiB. The index input is used to indicate an
absolute position. The phiA and phiB inputs are used to determine a change in position (the rate of change in position can be
used to derive speed). The quadrature inputs are mapped onto triggers (as described in Table 30-16).

Table 30-16. Quadrature Mode Trigger Input Description

Trigger Input Usage

This event acts as a quadrature index input. It initializes the counter to the counter midpoint 0x8000 (16-bit)
reload/index or 0x8000000 (32-bit mode) and starts the quadrature functionality. Rising edge event detection or falling
edge detection mode must be used.
This event acts as a quadrature phiB input. Pass through (no edge detection) event detection mode must be
start/phiB
used.
stop Stops the quadrature functionality.
This event acts as a quadrature phiA input. Pass through (no edge detection) event detection mode must be
count/phiA
used.
capture Not used.

Table 30-17. Quadrature Mode Supported Features

Supported Features Description

Three encoding schemes for the phiA and phiB inputs are supported (as specified by CTRL.QUADRA-
TURE_MODE):
Quadrature encoding X1 encoding.
X2 encoding.
X4 encoding.

Note: Clock pre-scaling is not supported and the count event is used as a quadrature input phiA. As a result, the quadrature
functionality operates on the counter clock (clk_counter), rather than on an “active count” prescaled counter clock.

Table 30-18. Quadrature Mode Trigger Output Description

Trigger Outputs Description

cc_match (CC) Counter value COUNTER equals 0 or 0xFFFF or 0xFFFFFFFF (32-bit mode) or a reload/index event.
Underflow (UN) Not used.
Overflow (OV) Not used.

Table 30-19. Quadrature Mode Interrupt Outputs

Interrupt Outputs Description

cc_match (CC) Counter value COUNTER equals 0 or 0xFFFF or 0xFFFFFFFF (32-bit mode) or a reload/index event.
tc Reload/index event.

Table 30-20. Quadrature Mode PWM Outputs

PWM Outputs Description

pwm Not used.
pwm_n Not used.

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Figure 30-19. Quadrature Functionality (16-bit example)

Quadrature Interrupt
0x0000 tc interrupt
Reload/Index generation
0x8000 (+/- 1)
Start/phiB
Stop == Trigger
cc_match tr_cc_match
Count/phiA generation
COUNTER
==
CC

clk_counter 0xFFFF
CC_BUFF

Quadrature functionality is described as follows:

■ A software-generated reload event starts quadrature operation. As a result, COUNTER is set to 0x8000 (16-bit) or
0x80000000 (32-bit), which is the counter midpoint (the COUNTER is set to 0x7FFF or 0x7FFFFFFF if the reload event
coincides with a decrement event; the COUNTER is set to 0x8001 or 0x80000001 if the reload event coincides with an
increment event). Note that a software-generated reload event is generated only once, when the counter is not running.
All other reload/index events are hardware-generated reload events as a result of the quadrature index signal.
■ During quadrature operation:
❐ The counter value COUNTER is incremented or decremented based on the specified quadrature encoding scheme.
❐ On a reload/index event, CC is copied to CC_BUFF, COUNTER is copied to CC, and COUNTER is set to 0x8000/
0x80000000. In addition, the tc and cc_match events are generated.
❐ When the counter value COUNTER is 0x0000, CC is copied to CC_BUFF, COUNTER (0x0000) is copied to CC, and
COUNTER is set to 0x8000/0x80000000. In addition, the cc_match event is generated.
❐ When the counter value COUNTER is 0xFFFF/0xFFFFFFFF, CC is copied to CC_BUFF, COUNTER (0xFFFF/
0xFFFFFFFF) is copied to CC, and COUNTER is set to 0x8000/0x80000000. In addition, the cc_match event is gen-
erated.
Note: When the counter reaches 0x0000 or 0xFFFF/0xFFFFFFFF, the counter is automatically set to 0x8000/0x80000000
without an increase or decrease event.
The software interrupt handler uses the tc and cc_match interrupt cause fields to distinguish between a reload/index event
and a situation in which a minimum/maximum counter value was reached (about to wrap around). The CC and CC_BUFF
registers are used to determine when the interrupt causing event occurred.
Note that a counter increment/decrement can coincide with a reload/index/tc event or with a situation cc_match event. Under
these circumstances, the counter value set to either 0x8000+1 or 0x80000000+1 (increment) or 0x8000–1 or 0x80000000–1
(decrement).
Counter increments (incr1 event) and decrements (decr1 event) are determined by the quadrature encoding scheme as
illustrated by Figure 30-20.

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Figure 30-20. Quadrature Mode Waveforms

phiA

phiB

Quadrature decoding
QUADRATURE_MODE = X1

incr1
decr1
Quadrature decoding
QUADRATURE_MODE = X2
Two times the events of X1 mode

incr1
decr1
Quadrature decoding
QUADRATURE_MODE = X4
Four times the events of X1 mode

incr1
decr1

Figure 30-21 illustrates quadrature functionality as a function of the reload/index, incr1, and decr1 events. Note that the first
reload/index event copies the counter value COUNTER to CC.
Figure 30-21. Quadrature Mode Reload/Index Timing
Quadrature decoding
increment behavior, no coinciding counter cycle overflow with incr1 event overflow without incr1 event
reload and increment events

Reload / Index
incr1
decr1

COUNTER X 0x8000 0x8001 0x8002 0x8003 0xFFFE 0xFFFF 0x8001 0xFFFE 0xFFFF 0x8000

CC Y X X 0xFFFF 0xFFFF 0xFFFF

CC_BUFF Z Y Y X X 0xFFFF

tc
cc_match
RUNNING

Figure 30-22 illustrate quadrature functionality for different event scenarios (including scenarios with coinciding events). In all
scenarios, the first reload/index event is generated by software when the counter is not yet running.

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Figure 30-22. Quadrature Mode Timing Cases

Quadrature decoding
decrement behavior, no coinciding counter cycle underflow with decr1 event underflow without decr1 event
reload and decrement events

Reload / Index
incr1
decr1

COUNTER X 0x8000 0x7FFFF 0x7ffe 0x7ffd 0x0001 0x0000 0x7FFF 0x0001 0x0000 0x8000

CC Y X X 0x0000 0x0000 0x0000

CC_BUFF Z Y Y X X 0x0000

tc
cc_match
RUNNING

Quadrature decoding
decrement/increment behavior, no counter cycle underflow with incr1 event overflow with decr1 event
coinciding reload events

Reload / Index
incr1
decr1

COUNTER X 0x8000 0x7FFF 0x7FFE 0x7FFD 0x0001 0x0000 0x8001 0xFFFE 0xFFFF 0x7FFF

CC Y X X 0x0000 0x0000 0xFFFF

CC_BUFF Z Y Y X X 0x0000

tc
cc_match
RUNNING

Quadrature decoding
counter cycle reload event and reload event and
decrement/increment behavior,
underflow with decr1 event overflow with incr1 event
coinciding reload events

Reload / Index
incr1
decr1

COUNTER X 0x8000 0x7FFF 0x7FFE 0x7FFD 0x0001 0x0000 0x7FFF 0xFFFE 0xFFFF 0x8001

CC Y X X 0x0000 0x0000 0xFFFF

CC_BUFF Z Y Y X X 0x0000

tc
cc_match
RUNNING

Quadrature decoding counter cycle reload event and

decrement behavior and reload events decr1 event coincide

Reload / Index
incr1
decr1

COUNTER X 0x8000 0x7FFF 0x7FFE 0x7FFF 0x7FFE 0x7FFD 0x8000 0x7FFF 0x7FFE 0x7FFD

CC Y X 0x7FFE 0x7FFD

CC_BUFF Z Y Y 0x7FFE

tc
cc_match
RUNNING

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30.3.3.1 Configuring Counter for Quadrature Mode

The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows.
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select Quadrature mode by writing ‘011’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required encoding mode by writing to the QUADRATURE_MODE[21:20] field of the TCPWM_CNT_CTRL regis-
ter.
4. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Index and Stop).
5. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Index and Stop).
6. If required, set the interrupt upon TC or CC condition.
7. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

30.3.4 Pulse Width Modulation Mode

The PWM can output left, right, center, or asymmetrically-aligned PWM. The PWM signal is generated by incrementing or
decrementing a counter between 0 and PERIOD, and comparing the counter value COUNTER with CC. When COUNTER
equals CC, the cc_match event is generated. The pulse-width modulated signal is then generated by using the cc_match
event along with overflow and underflow events. Two pulse-width modulated signals “pwm” and “pwm_n” are output from the
PWM.

Table 30-21. PWM Mode Trigger Input Description

Trigger Inputs Usage

Sets the counter value and starts the counter. Behavior is dependent on UP_DOWN_MODE:
■ COUNT_UP: The counter is set to “0” and count direction is set to “up”.
reload ■ COUNT_DOWN: The counter is set to PERIOD and count direction is set to “down”.
■ COUNT_UPDN1/2: The counter is set to “1” and count direction is set to “up”.
Can be used only when the counter is not running.
Starts the counter. The counter is not initialized by hardware. The current counter value is used. Behavior is
dependent on UP_DOWN_MODE:
■ COUNT_UP: The count direction is set to “up”.
start
■ COUNT_DOWN: The count direction is set to “down”.
■ COUNT_UPDN1/2: The count direction is set to “up”.
Can be used only when the counter is not running.
Stops the counter or suppresses the PWM output, depending on PWM_STOP_ON_KILL and PWM_SYN-
stop/kill
C_KILL.
count Count event increments/decrements the counter.
This event acts as a swap event. When this event is active, the CC/CC_BUFF and PERIOD/PERIOD_BUFF
registers are exchanged on a tc event (when specified by CTRL.AUTO_RELOAD_CC and CTRL.AUTO_RE-
LOAD_PERIOD).
A swap event requires rising, falling, or rising/falling edge event detection mode. Pass-through mode is not
capture/swap supported, unless the selected event is a constant '0' or '1'.
Note: When COUNT_UPDN2 mode exchanges PERIOD and PERIOD_BUFF at a tc event that coincides
with an OV event, software should ensure that the PERIOD and PERIOD_BUFF values are the same.
When a swap event is detected and the counter is running, the event is kept pending until the next tc event.
When a swap event is detected and the counter is not running, the event is cleared by hardware.

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 Timer, Counter, and PWM (TCPWM)

Table 30-22. PWM Mode Supported Features

Supported Features Description

Clock pre-scaling Pre-scales the counter clock “clk_counter”.
Counter is stopped by hardware, after a single period of the counter:
One-shot ■ COUNT_UP: on an overflow event.
■ COUNT_DOWN and COUNT_UPDN1/2: on an underflow event.

CC and CC_BUFF are exchanged on a swap event and tc event (when specified by CTRL.AUTO_RE-
Compare Swap
LOAD_CC).
PERIOD and PERIOD_BUFF are exchanged on a swap event and tc event (when specified by
CTRL.AUTO_RELOAD_PERIOD). Note: When COUNT_UPDN2/Asymmetric mode exchanges PERIOD
Period Swap
and PERIOD_BUFF at a tc event that coincides with an overflow event, software should ensure that the
PERIOD and PERIOD_BUFF values are the same.
Specified by UP_DOWN_MODE:
■ COUNT_UP: The counter counts from 0 to PERIOD. Generates a left-aligned PWM output.
Alignment (Up/Down modes) ■ COUNT_DOWN: The counter counts from PERIOD to 0. Generates a right-aligned PWM output.
■ COUNT_UPDN1/2: The counter counts from 1 to PERIOD and back to 0. Generates a center-aligned/
asymmetric PWM output.
Specified by PWM_STOP_ON_KILL and PWM_SYNC_KILL:
■ PWM_STOP_ON_KILL = ‘1’ (PWM_SYNC_KILL = don’t care): Stop on Kill mode. This mode
stops the counter on a stop/kill event. Reload or start event is required to restart counting.
■ PWM_STOP_ON_KILL = ‘0’ and PWM_SYNC_KILL = ‘0’: Asynchronous kill mode. This
Kill modes mode keeps the counter running, but suppresses the PWM output signals and continues to
do so for the duration of the stop/kill event.
■ PWM_STOP_ON_KILL = ‘0’ and PWM_SYNC_KILL = ‘1’: Synchronous kill mode. This mode
keeps the counter running, but suppresses the PWM output signals and continues to do so
until the next tc event without a stop/kill event.

Note that the PWM mode does not support dead time insertion. This functionality is supported by the separate PWM_DT
mode.

Table 30-23. PWM Mode Trigger Output Description

Trigger Output Description

Specified by UP_DOWN_MODE:
cc_match (CC) ■ COUNT_UP and COUNT_DOWN: The counter changes to a state in which COUNTER equals CC.
■ COUNT_UPDN1/2: counter changes from a state in which COUNTER equals CC.

Underflow (UN) Counter is decrementing and changes from a state in which COUNTER equals “0”.
Overflow (OV) Counter is incrementing and changes from a state in which COUNTER equals PERIOD.

Table 30-24. PWM Mode Interrupt Output Description

Interrupt Outputs Description

Specified by UP_DOWN_MODE:
■ COUNT_UP: tc event is the same as the overflow event.
tc ■ COUNT_DOWN: tc event is the same as the underflow event.
■ COUNT_UPDN1: tc event is the same as the underflow event.
■ COUNT_UPDN2: tc event is the same as the logical OR of the overflow and underflow events.

Specified by UP_DOWN_MODE:
cc_match (CC) ■ COUNT_UP and COUNT_DOWN: The counter changes to a state in which COUNTER equals CC.
■ COUNT_UPDN1/2: counter changes from a state in which COUNTER equals CC.

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 Timer, Counter, and PWM (TCPWM)

Table 30-25. PWM Mode PWM Outputs

PWM Outputs Description

pwm PWM output.
pwm_n Complementary PWM output.

Note that the cc_match event generation in COUNT_UP and COUNT_DOWN modes are different from the generation in
other functional modes or counting modes. This is to ensure that 0 percent and 100 percent duty cycles can be generated.
Figure 30-23. PWM Mode Functionality

PWM
tc Interrupt
Reload interrupt
PERIOD_BUFF generation
Start
Stop/Kill
Count
Capture/Swap PERIOD
cc_match tr_cc_match
== Trigger
underflow tr_underflow
generation
COUNTER overflow tr_overflow

clk_counter == PWM
pwm_dt_input
generation
CC

CC_BUFF no dead time insertion

The generation of PWM output signals is a multi-step process and is illustrated in Figure 30-24. The PWM output signals are
generated by using the underflow, overflow, and cc_match events. Each of these events can be individually set to INVERT,
SET, or CLEAR pwm_dt_input.
Note: An underflow and cc_match or an overflow and cc_match can occur at the same time. When this happens, underflow
and overflow events take priority over cc_match. For example, if overflow = SET and cc_match = CLEAR then pwm_dt_input
will be SET to ‘1’ first and then CLEARED to ‘0’ immediately after. This can be seen in Figure 30-26.
Figure 30-24. PWM Output Generation
pwm polarity
pwm
underflow PWM Dead time
overflow generation pwm_dt_input insertion kill period
cc_match
pwm_n
pwm_n polarity
only supported in
TCPWM_CNT_TR_CTRL2 PWM_DT mode

PWM polarity and PWM_n polarity as seen in Figure 30-24, allow the PWM outputs to be inverted. PWM polarity is controlled
through CTRL.QUADRATURE_MODE[0] and PWM_n polarity is controlled through CTRL.QUADRATURE_MODE[1].
PWM behavior depends on the PERIOD and CC registers. The software can update the PERIOD_BUFF and CC_BUFF
registers, without affecting the PWM behavior. This is the main rationale for double buffering these registers.
Figure 30-25 illustrates a PWM in up counting mode. The counter is initialized (to 0) and started with a software-based reload
event.
Notes:
■ When the counter changes from a state in which COUNTER is 4, an overflow and tc event are generated.
■ When the counter changes to a state in which COUNTER is 2, a cc_match event is generated.
■ PERIOD is 4, resulting in an effective repeating counter pattern of 4+1 = 5 counter clock periods.

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 Timer, Counter, and PWM (TCPWM)

Figure 30-25. PWM in Up Counting Mode

MODE = PWM
UP_DOWN_MODE = COUNT_UP COUNTER starts with 0 period is PERIOD+1

reload
4 PERIOD = 4

COUNTER
3

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no tc event cc_match event on entering
the COUNTER value

Figure 30-26 illustrates a PWM in up counting mode generating a left-aligned PWM. The figure also illustrates how a right-
aligned PWM can be created using the PWM in up counting mode by inverting the OVERFLOW_MODE and
CC_MATCH_MODE and using a CC value that is complementary (PERIOD+1 - pulse width) to the one used for left-aligned
PWM. Note that CC is changed (to CC_BUFF, which is not depicted) on a tc event. The duty cycle is controlled by setting the
CC value. CC = desired duty cycle x (PERIOD+1).
Figure 30-26. PWM Left- and Right-Aligned Outputs
MODE = PWM
UP_DOWN_MODE = COUNT_UP

1 0 2 4 5 CC
reload
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Left aligned PWM

CC = pulse width
OVERFLOW_MODE = SET
CC_MATCH_MODE = CLEAR

pwm

Right aligned PWM

CC = (PERIOD+1) – pulse width
OVERFLOW_MODE = CLEAR
CC_MATCH_MODE = SET

pwm

Figure 30-27 illustrates a PWM in down counting mode. The counter is initialized (to PERIOD) and started with a software-
based reload event.
Notes:
■ When the counter changes from a state in which COUNTER is 0, an underflow and tc event are generated.
■ When the counter changes to a state in which COUNTER is 2, a cc_match event is generated.
■ PERIOD is 4, resulting in an effective repeating counter pattern of 4+1 = 5 counter clock periods.

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 Timer, Counter, and PWM (TCPWM)

Figure 30-27. PWM in Down Counting Mode

MODE = PWM
UP_DOWN_MODE = COUNT_DOWN COUNTER starts with PERIOD period is PERIOD+1

reload
4 PERIOD = 4

COUNTER
3

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no tc event cc_match event on entering
the COUNTER value

Figure 30-28 illustrates a PWM in down counting mode with different CC values. The figure also illustrates how a right-aligned
PWM can be creating using the PWM in down counting mode. Note that the CC is changed (to CC_BUFF, which is not
depicted) on a tc event.
Figure 30-28. Right- and Left-Aligned Down Counting PWM
MODE = PWM
UP_DOWN_MODE = COUNT_DOWN

reload 1 0 2 4 -1 / 0xFFFF CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Right aligned PWM

CC = pulse width - 1
UNDERFLOW_MODE = CLEAR
CC_MATCH_MODE = SET

pwm
Left aligned PWM
CC = PERIOD - pulse width
UNDERFLOW_MODE = SET
CC_MATCH_MODE = CLEAR
pwm

Figure 30-29 illustrates a PWM in up/down counting mode. The counter is initialized (to 1) and started with a software-based
reload event.
Notes:
■ When the counter changes from a state in which COUNTER is 4, an overflow is generated.
■ When the counter changes from a state in which COUNTER is 0, an underflow and tc event are generated.
■ When the counter changes from a state in which COUNTER is 2, a cc_match event is generated. Note that the actual
counter value COUNTER from before the reload event is NOT used, instead the counter value before the reload event is
considered to be 0.
■ PERIOD is 4, resulting in an effective repeating counter pattern of 2*4 = 8 counter clock periods.

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 Timer, Counter, and PWM (TCPWM)

Figure 30-29. Up/Down Counting PWM

MODE = PWM
UP_DOWN_MODE = COUNT_UPDN1 COUNTER starts with 1 period is 2*PERIOD

reload
4 PERIOD = 4

COUNTER
3

2 CC = 2

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
no tc event cc_match event on leaving
the COUNTER value

Figure 30-30 illustrates a PWM in up/down counting mode with different CC values. The figure also illustrates how a center-
aligned PWM can be creating using the PWM in up/down counting mode.
Note:
■ The actual counter value COUNTER from before the reload event is NOT used. Instead the counter value before the
reload event is considered to be 0. As a result, when the first CC value at the reload event is 0, a cc_match event is
generated.
■ CC is changed (to CC_BUFF, which is not depicted) on a tc event.
Figure 30-30. Up/Down Counting Center-Aligned PWM
MODE = PWM
UP_DOWN_MODE = COUNT_UPDN1

0 1 3 4 CC
reload
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)
cc_match event at the overflow and cc_match
start of the period events coincide
Center aligned PWM
CC = PERIOD – pulse width/2
UNDERFLOW_MODE = CLEAR
OVERFLOW_MODE = SET
CC_MATCH_MODE = INVERT

pwm

Different stop/kill modes exist. The mode is specified by PWM_STOP_ON_KILL and PWM_SYNC_KILL.
The following three modes are supported:
■ PWM_STOP_ON_KILL is ‘1’ (PWM_SYNC_KILL is don’t care): Stop on Kill mode. This mode stops the counter on a stop/
kill event. Reload or start event is required to restart the counter. Both software and external trigger input can be selected
as stop kill. Edge detection mode is required.
■ PWM_STOP_ON_KILL is ‘0’ and PWM_SYNC_KILL is ‘0’: Asynchronous Kill mode. This mode keeps the counter
running, but suppresses the PWM output signals synchronously on the next count clock (“active count” pre-scaled
clk_counter) and continues to do so for the duration of the stop/kill event. Only the external trigger input can be selected
as asynchronous kill. Pass through detection mode is required.

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 Timer, Counter, and PWM (TCPWM)

■ PWM_STOP_ON_KILL is ‘0’ and PWM_SYNC_KILL is ‘1’: Synchronous Kill mode. This mode keeps the counter running,
but suppresses the PWM output signals synchronously on the next count clock (“active count” pre-scaled clk_counter)
and continues to do so until the next tc event without a stop/kill event. Only the external trigger input can be selected as
synchronous kill. Rising edge detection mode is required.
Figure 30-31, Figure 30-32. and Figure 30-33 illustrate the above three modes.
Figure 30-31. PWM Stop on Kill
Right aligned PWM
PWM_STOP_ON_KILL = 1 pwm and pwm_n set to programmed
STOP_EDGE = RISING_EDGE kill event stops counter
polarity
pwm polarity = 0, pwm_n polarity = 0

tc
cc_match

pwm_dt_input

kill

pwm

pwm_n

Figure 30-32. PWM Async Kill

Right aligned PWM
PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 0 pwm and pwm_n set to programmed
STOP_EDGE = NON_EDGE_DET counter does NOT stop
polarity
pwm polarity = 0, pwm_n polarity = 0

tc
cc_match

pwm_dt_input

kill

pwm

pwm_n

kill period equals kill event

Figure 30-33. PWM Sync Kill

Right aligned PWM
PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 1 pwm and pwm_n set to programmed
STOP_EDGE = RISING_EDGE counter does NOT stop
polarity
pwm polarity = 0, pwm_n polarity = 0

tc
cc_match

pwm_dt_input

kill

pwm

pwm_n
kill event disappears, but kill period
kill event detected (rising edge) kill period ends at next tc
extended

Figure 30-34 illustrates center-aligned PWM with PERIOD/PERIOD_BUFF and CC/CC_BUFF registers (up/down counting
mode 1). At the TC condition, the PERIOD and CC registers are automatically exchanged with the PERIOD_BUFF and
CC_BUFF registers. The swap event is generated by hardware trigger 1, which is a constant ‘1’ and therefore always active
at the TC condition. After the hardware exchange, the software handler on the tc interrupt updates PERIOD_BUFF and
CC_BUFF.

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 Timer, Counter, and PWM (TCPWM)

Figure 30-34. PWM Mode CC Swap Event

MODE = PWM
UP_DOWN_MODE = COUNT_UPDN1

SW update SW update
4 0 1 4 3 CC_BUFF
0 4 1 CC
5 4 3 5 3 PERIOD_BUFF
reload 4 5 3 PERIOD
5

4
COUNTER
3

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

upcounting and CC = 0
=> cc_matchҸevent at
underflow

Asymmetric PWM
CC = PERIOD – pulse width/2
UNDERFLOW_MODE = CLEAR
OVERFLOW_MODE = SET
CC_MATCH_MODE = INVERT

pwm

The PERIOD swaps with PERIOD_BUFF on a terminal count. The CC swaps with CC_BUFF on a terminal count. Software
can then update PERIOD_BUFF and CC_BUFF so that on the next terminal count PERIOD and CC will be updated with the
values written into PERIOD_BUFF and CC_BUFF.
A potential problem arises when software updates are not completed before the next tc event with an active pending swap
event. For example, if software updates PERIOD_BUFF before the tc event and CC_BUFF after the tc event, swapping does
not reflect the CC_BUFF register update. To prevent this from happening, the swap event should be generated by software
through a register write after both the PERIOD_BUFF and CC_BUFF registers are updated. The swap event is kept pending
by the hardware until the next tc event occurs.
The previous section addressed synchronized updates of the CC/CC_BUFF and PERIOD/PERIOD_BUFF registers of a
single PWM using a software-generated swap event. During motor control, three PWMs work in unison and updates to all
period and compare register pairs should be synchronized. All three PWMs have synchronized periods and as a result have
synchronized tc events. The swap event for all three PWMs is generated by software through a single register write. The
software should generate the swap events after the PERIOD_BUFF and CC_BUFF registers of all three PWMs are updated.
Note: When the counter is not running ((temporarily) stopped or killed), the PWM output signal values are determined by their
respective polarity settings. When the counter is disabled the output values are low.
Figure 30-35. PWM Outputs When Killed
Right aligned PWM
PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 0
STOP_EDGE = NO_EDGE_DET
pwm polarity = 0, pwm_n polarity = 0

tc
cc_match

pwm_dt_input

kill

pwm

pwm_n

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 Timer, Counter, and PWM (TCPWM)

30.3.4.1 Asymmetric PWM

This PWM mode supports the generation of an asymmetric PWM. For an asymmetric PWM, the pwm_dt_input pulse is not
necessarily centered in the middle of the period. This functionality is realized by having a different CC value when counting up
and when counting down. The CC and CC_BUFF values are exchanged on an overflow event.
The COUNT_UPDN2 mode should use the same period value when counting up and counting down. When PERIOD and
PERIOD_BUFF are swapped on a tc event (overflow or underflow event), care should be taken to ensure that:
■ Within a PWM period (tc event coincides with an overflow event), the period values are the same (an overflow swap of
PERIOD and PERIOD_BUFF should not change the period value; that is, PERIOD_BUFF should be PERIOD)
■ Between PWM periods (tc event coincides with an underflow event), the period value can change (an underflow swap of
PERIOD and PERIOD_BUFF may change the period value; that is, PERIOD_BUFF may be different from PERIOD).
Figure 30-36 illustrates how the COUNT_UPDN2 mode is used to generate an asymmetric PWM.
Notes:
■ When up counting, when CC value at the underflow event is 0, a cc_match event is generated.
■ When down counting, when CC value at the overflow event is PERIOD, a cc_match event is generated.
■ A tc event is generated for both an underflow and overflow event. The tc event is used to exchange the CC and CC_BUFF
values.
Figure 30-36. Asymmetric PWM
MODE = PWM
UP_DOWN_MODE = COUNT_UPDN2

3 1 3 1 3 1 CC_BUFF
reload 1 3 1 3 1 3 CC
4 PERIOD = 4
COUNTER

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

Asymmetric PWM
CC = PERIOD – pulse width/2
UNDERFLOW_MODE = CLEAR
OVERFLOW_MODE = SET
CC_MATCH_MODE = INVERT

pwm

The previous waveform illustrated functionality when the CC values are neither “0” nor PERIOD. Corner case conditions in
which the CC values equal “0” or PERIOD are illustrated as follows.
Figure 30-37 illustrates how the COUNT_UPDN2 mode is used to generate an asymmetric PWM.
Notes:
■ When up counting, when CC value at the underflow event is 0, a cc_match event is generated.
■ When down counting, when CC value at the overflow event is PERIOD, a cc_match event is generated.
■ A tc event is generated for both an underflow and overflow event. The tc event is used to exchange the CC and CC_BUFF
values.
■ Software updates CC_BUFF and PERIOD_BUFF in an interrupt handler on the tc event (and overwrites the hardware
updated values from the CC/CC_BUFF and PERIOD/PERIOD_BUFF exchanges).

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 Timer, Counter, and PWM (TCPWM)

Figure 30-37. Asymmetric PWM when Compare = 0 or Period

MODE = PWM
UP_DOWN_MODE = COUNT_UPDN2

SW update SW update SW update SW update SW update

4 0 5 4 0 5 3 3 1 CC_BUFF
0 4 5 0 3 3 CC
4 5 4 5 3 5 3 4 PERIOD_BUFF
reload 4 4 5 5 3 3 PERIOD
5

4 COUNTER
3

Underflow (UN)
Overflow (OV)
Terminal Count (TC)
Compare/Capture (CC)

upcounting and CC = 0 downcounting and CC = downcounting and CC =

=> cc_matchҸevent at PERIOD => cc_matchҸ PERIOD => cc_matchҸ
underflow event at overflow event at overflow

Asymmetric PWM
CC = PERIOD – pulse width/2
UNDERFLOW_MODE = CLEAR
OVERFLOW_MODE = SET
CC_MATCH_MODE = INVERT

pwm

30.3.4.2 Configuring Counter for PWM Mode

The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select PWM mode by writing ‘100b’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register.
4. Set the required 16/32-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the TCPW-
M_CNT_PERIOD_BUFF register to swap values, if required.
5. Set the 16/32-bit compare value in the TCPWM_CNT_CC register and buffer compare value in the TCPWM_CNT_C-
C_BUFF register to swap values, if required.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to con-
figure left-aligned, right-aligned, or center-aligned PWM.
7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (reload, start, kill, swap, and count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, kill, swap, and count).
10. pwm and pwm_n can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and
UN conditions.
11. If required, set the interrupt upon TC or CC condition.
12. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

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 Timer, Counter, and PWM (TCPWM)

30.3.5 Pulse Width Modulation with Dead Time Mode

The PWM-DT functionality is the same as PWM functionality, except for the following differences:
■ PWM_DT supports dead time insertion; PWM does not support dead time insertion.
■ PWM_DT does not support clock pre-scaling; PWM supports clock pre-scaling.
Figure 30-38. PWM with Dead Time Functionality

PWM
Reload tc Interrupt
interrupt
Start PERIOD_BUFF generation
Stop/Kill
Count
Capture/Swap PERIOD
cc_match tr_cc_match
== Trigger
underflow tr_underflow
generation
COUNTER overflow tr_overflow

clk_counter == PWM
pwm_dt_input
CC generation

no clock pre-scaling

CC_BUFF

pwm polarity
pwm
underflow PWM Dead time
overflow generation pwm_dt_input insertion kill period
cc_match
pwm_n
pwm_n polarity
only supported in
TCPWM_CNT_TR_CTRL2 PWM_DT mode

Dead time insertion is a step that operates on a preliminary PWM output signal pwm_dt_input, as illustrated in Figure 30-38.
Figure 30-39 illustrates dead time insertion for different dead times and different output signal polarity settings.

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 Timer, Counter, and PWM (TCPWM)

Figure 30-39. Dead-time Timing

pwm_dt_input

MODE = PWM_DT
dead time = 0
pwm polarity = 0
pwm_n polarity = 0

pwm

pwm_n

MODE = PWM_DT
dead time = 1
pwm polarity = 0 dead time: 1
pwm_n polarity = 0

pwm

pwm_n

MODE = PWM_DT
dead time = 2
pwm polarity = 0 dead time: 2
pwm_n polarity = 0 pulse is gone

pwm

pwm_n

MODE = PWM_DT
dead time = 2
pwm polarity = 1 dead time: 2
pwm_n polarity = 1

pwm

pwm_n

Figure 30-40 illustrates how the polarity settings and stop/kill functionality combined control the PWM output signals “pwm”
and “pwm_n”.
Figure 30-40. Dead Time and Kill
Right aligned PWM
PWM_STOP_ON_KILL = 0, PWM_SYNC_KILL = 0
STOP_EDGE = NO_EDGE_DET dead time: 1
dead time = 1
pwm polarity = 0, pwm_n polarity = 1

reload
tc
cc_match

pwm_dt_input

kill

pwm

pwm_n

RUNNING
counter not running counter temporarily killed

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 Timer, Counter, and PWM (TCPWM)

30.3.5.1 Configuring Counter for PWM with Dead Time Mode

The steps to configure the counter for PWM with Dead Time mode of operation and the affected register bits are as follows:
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select PWM with Dead Time mode by writing ‘101’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required dead time by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register.
4. Set the required 16/32-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the
TCPWM_CNT_PERIOD_BUFF register to swap values, if required.
5. Set the 16/32-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the
TCPWM_CNT_CC_BUFF register to swap values, if required.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to
configure left-aligned, right-aligned, or center-aligned PWM.
7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (reload, start, kill, swap, and count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, kill, swap, and count).
10. pwm and pwm_n can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and
UN conditions.
11. If required, set the interrupt upon TC or CC condition.
12. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

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 Timer, Counter, and PWM (TCPWM)

30.3.6 Pulse Width Modulation Pseudo-Random Mode (PWM_PR)

The PWM_PR functionality changes the counter value using the linear feedback shift register (LFSR). This results in a
pseudo random number sequence. A signal similar to PWM signal is created by comparing the counter value COUNTER with
CC. The generated signal has different frequency/noise characteristics than a regular PWM signal.

Table 30-26. PWM_PR Mode Trigger Inputs

Trigger Inputs Usage

Same behavior as start event.
reload
Can be used only when the counter is not running.
Starts the counter. The counter is not initialized by hardware. The current counter value is used. Behavior is
start dependent on UP_DOWN_MODE.
Can be used only when the counter is not running.
stop/kill Stops the counter. Different stop/kill modes exist.
count Not used.
This event acts as a swap event. When this event is active, the CC/CC_BUFF and PERIOD/PERIOD_BUFF
registers are exchanged on a tc event (when specified by CTRL.AUTO_RELOAD_CC and CTRL.AUTO_RE-
LOAD_PERIOD).
capture A swap event requires rising, falling, or rising/falling edge event detection mode. Pass-through mode is not
supported, unless the selected event is a constant '0' or '1'.
When a swap event is detected and the counter is running, the event is kept pending until the next tc event.
When a swap event is detected and the counter is not running, the event is cleared by hardware.

Note: Event detection is on the peripheral clock, clk_peri.

Table 30-27. PWM_PR Supported Features

Supported Features Description

Clock pre-scaling Pre-scales the counter clock, clk_counter.
Counter is stopped by hardware, after a single period of the counter (counter value equals period value
One-shot
PERIOD).
CC and CC_BUFF are exchanged on a swap event AND tc event (when specified by CTRL.AUTO_RE-
Auto reload CC
LOAD_CC).
PERIOD and PERIOD_BUFF are exchanged on a swap event and tc event (when specified by
Auto reload PERIOD
CTRL.AUTO_RELOAD_PERIOD).
Kill modes Specified by PWM_STOP_ON_KILL. See memory map for further details.

Note: The count event is not used. As a result, the PWM_PR functionality operates on the pre-scaled counter clock
(clk_counter), rather than on an “active count” pre-scaled counter clock.

Table 30-28. PWM_PR Trigger Outputs

Trigger Outputs Description

cc_match (CC) Counter changes from a state in which COUNTER equals CC.
Underflow (UN) Not used.
Overflow (OV) Not used.

Table 30-29. PWM_PR Interrupt Outputs

Interrupt Outputs Description

cc_match (CC) Counter changes from a state in which COUNTER equals CC.
tc Counter changes from a state in which COUNTER equals PERIOD.

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 Timer, Counter, and PWM (TCPWM)

Table 30-30. PWM_PR PWM Outputs

PWM Outputs Description

pwm PWM output.
pwm_n Complementary PWM output.

Figure 30-41. PWM_PR Functionality

PWM_PR Interrupt
tc interrupt
Reload generation
PERIOD_BUFF
Start
Stop/Kill Trigger
cc_match tr_cc_match
Capture/Swap generation
PERIOD
==
pwm polarity
COUNTER pwm

clk_counter < pwm_dt_input kill period

CC pwm_n
pwm_n polarity

CC_BUFF

The PWM_PR functionality is described as follows:

■ The counter value COUNTER is initialized by software (to a value different from 0).
■ A reload or start event starts PWM_PR operation.
■ During PWM_PR operation:
❐ The counter value COUNTER is changed based on the LFSR polynomial: x16 + x14 + x13 + x11 + 1
(en.wikipedia.org/wiki/Linear_feedback_shift_register).
temp = (COUNTER >> (16-16)) ^ (COUNTER >> (16-14)) ^ (COUNTER >> (16-13)) ^ (COUNTER >> (16-11)) or
temp = (COUNTER >> 0) ^ (COUNTER >> 2) ^ (COUNTER >> 3) ^ (COUNTER >> 5);
(COUNTER = (temp << 15)) | (COUNTER >> 1)
This will result in a pseudo random number sequence for COUNTER. For example, when COUNTER is initialized to
0xACE1, the number sequence is: 0xACE1, 0x5670, 0xAB38, 0x559C, 0x2ACE, 0x1567, 0x8AB3… This sequence will
repeat itself after 216 – 1 or 65535 counter clock cycles.
❐ A 32-bit counter uses the LFSR polynomial: x^32 + x^30 + x^26 + x^25 + 1
❐ When the counter value COUNTER equals CC, a cc_match event is generated.
❐ When the counter value COUNTER equals PERIOD, a tc event is generated.
❐ On a tc event, the CC/CC_BUFF and PERIOD/PERIOD_BUFF can be conditionally exchanged under control of the
capture/swap event and the CTRL.AUTO_RELOAD_CC and CTRL.AUTO_RELOAD_PERIOD field (see PWM func-
tionality).
❐ The output pwm_dt_input reflects: COUNTER[14:0] < CC[15:0]. Note that only the lower 15 bits of COUNTER are
used for comparison, while the COUNTER itself can run up to 16- or 32-bit values. As a result, for CC greater or equal
to 0x8000, pwm_dt_input is always 1. The pwm polarity can be inverted (as specified by CTRL.QUADRATURE_-
MODE[0]).
As mentioned, different stop/kill modes exist. The mode is specified by PWM_STOP_ON_KILL (PWM_SYNC_KILL should be
‘0’ – asynchronous kill mode). The memory map describes the modes and the desired settings for the stop/kill event. The
following two modes are supported:
■ PWM_STOP_ON_KILL is ‘1’. This mode stops the counter on a stop/kill event.
■ PWM_STOP_ON_KILL is ‘0’. This mode keeps the counter running, but suppresses the PWM output signals immediately
and continues to do so for the duration of the stop/kill event.

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 Timer, Counter, and PWM (TCPWM)

Note that the LFSR produces a deterministic number sequence (given a specific counter initialization value). Therefore, it is
possible to calculate the COUNTER value after a certain number of LFSR iterations, n. This calculated COUNTER value can
be used as PERIOD value, and the tc event will be generated after precisely n counter clocks.
Figure 30-42 illustrates PWM_PR functionality.
Notes:
■ The grey shaded areas represent the counter region in which the pwm_dt_input value is ‘1’, for a CC value of 0x4000.
There are two areas, because only the lower 15 bits of the counter value are used.
■ When CC is set to 0x4000, roughly one-half of the counter clocks will result in a pwm_dt_input value of ‘1’.
Figure 30-42. PWM_PR Output
MODE = PWM_PR COUNTER is exactly
0xe771
reload
0xFFFF

PERIOD = 0xe771
COUNTER

CC = 0x4000

tc
cc_match

pwm_dt_input

Only the lower 15 bits of the

counter value are used.

30.3.6.1 Configuring Counter for Pseudo-Random PWM Mode

The steps to configure the counter for pseudo-random PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing ‘1’ to the TCPWM_CTRL_CLR register.
2. Select pseudo-random PWM mode by writing ‘110’ to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required period (16 bit) in the TCPWM_CNT_PERIOD register and buffer period value in the TCPWM_CNT_PE-
RIOD_BUFF register to swap values, if required.
4. Set the 16-bit compare value in the TCPWM_CNT_CC register and the buffer compare value in the TCPWM_CNT_C-
C_BUFF register to swap values.
5. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
6. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (reload, start, kill, and swap).
7. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (reload, start, kill, and swap).
8. pwm and pwm_n can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC, OV, and
UN conditions.
9. If required, set the interrupt upon TC or CC condition.
10. Enable the counter by writing ‘1’ to the TCPWM_CTRL_SET register. A reload trigger must be provided through firmware
(TCPWM_CMD_RELOAD register) to start the counter if the hardware reload signal is not enabled.

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 Timer, Counter, and PWM (TCPWM)

30.4 TCPWM Registers

Table 30-31. List of TCPWM Registers
Register Comment Features
TCPWM_CTRL TCPWM control register Enables the counter block
Used to avoid race-conditions on read-modify-write
TCPWM_CTRL_CLR TCPWM control clear register
attempt to the CTRL register
Used to avoid race-conditions on read-modify-write
TCPWM_CTRL_SET TCPWM control set register
attempt to the CTRL register
TCPWM_CMD_CAPTURE TCPWM capture command register Generate a capture trigger input from software
TCPWM_CMD_RELOAD TCPWM reload command register Generate a reload trigger input from software
TCPWM_CMD_STOP TCPWM stop command register Generate a stop trigger input from software
TCPWM_CMD_START TCPWM start command register Generate a start trigger input from software
TCPWM_INTR_CAUSE TCPWM counter interrupt cause register Determines the source of the combined interrupt signal
Configures counter mode, encoding modes, one-shot
TCPWM_CNT_CTRL Counter control register mode, swap mode, kill mode, dead time, clock pre-scal-
ing, and counting direction
Reads the direction of counting, dead time duration, and
TCPWM_CNT_STATUS Counter status register
clock pre-scaling; checks whether the counter is running
TCPWM_CNT_COUNTER Count register Contains the 16- or 32-bit counter value
Captures the counter value or compares the value with
TCPWM_CNT_CC Counter compare/capture register
counter value
Buffer register for counter CC register; swaps period
TCPWM_CNT_CC_BUFF Counter buffered compare/capture register
value
TCPWM_CNT_PERIOD Counter period register Contains upper value of the counter
Buffer register for counter period register; swaps compare
TCPWM_CNT_PERIOD_BUFF Counter buffered period register
value
TCPWM_CNT_TR_CTRL0 Counter trigger control register 0 Selects trigger for specific counter events
Determine edge detection for specific counter input sig-
TCPWM_CNT_TR_CTRL1 Counter trigger control register 1
nals
Controls counter output lines upon CC, OV, and UN con-
TCPWM_CNT_TR_CTRL2 Counter trigger control register 2
ditions
TCPWM_CNT_INTR Interrupt request register Sets the register bit when TC or CC condition is detected
TCPWM_CNT_INTR_SET Interrupt set request register Sets the corresponding bits in interrupt request register
TCPWM_CNT_INTR_MASK Interrupt mask register Mask for interrupt request register
TCPWM_CNT_INTR_MASKED Interrupt masked request register Bitwise AND of interrupt request and mask registers

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 31. Inter-IC Sound Bus

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Inter-IC Sound Bus (I2S) is a serial bus interface standard used to connect digital audio devices together. The
specification is from Philips® Semiconductor (I2S bus specification: February 1986, revised June 5, 1996). In addition to the
standard I2S format, the I2S block also supports the Left Justified (LJ) format and the Time Division Multiplexed (TDM) format.

31.1 Features
■ Supports standard Philips I2S, LJ, and eight-channel TDM digital audio interface formats
■ Supports both master and slave mode operation in all the digital audio formats
■ Supports independent operation of Receive (Rx) and Transmit (Tx) directions
■ Supports operating from an external master clock provided through an external IC such as audio codec
■ Provides configurable clock divider registers to generate the required sample rates
■ Supports data word length of 8-bit, 16-bit, 18-bit, 20-bit, 24-bit, and 32-bit per channel
■ Supports channel length of 8-bit, 16-bit, 18-bit, 20-bit, 24-bit, and 32-bit per channel (channel length fixed at 32-bit in TDM
format)
■ Provides two hardware FIFO buffers, one each for the Tx block and Rx block, respectively
■ Supports both DMA- and CPU-based data transfers

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 Inter-IC Sound Bus

31.2 Architecture
Figure 31-1. I2S Block Diagram

PSoC 6 MCU

Data Wire/
CPU DMA SRAM

AHB bus

clk_i2s_if

I2S tx_sck
TX tx_ws
External IC
tx_sdo (for example, Audio
Codec, I2S Microphones)
I2S rx_sck
RX rx_ws
rx_sdi
I2S

Audio subsystem

Figure 31-1 shows the high-level block diagram of the I2S block, which consists of two sub-blocks – I2S Transmitter (Tx) and
I2S Receiver (Rx). The digital audio interface format and master/slave mode configuration can be done independently for the
Tx and Rx blocks. In the master mode, the word select (ws) and serial data clock (sck) are generated by the I2S block in the
PSoC 6 MCU. In the slave mode, the ws and sck signals are inputs signals to the PSoC 6 MCU, and are generated by the
external master device. The I2S block configuration, control, and status registers, along with the FIFO data buffers are
accessible through the AHB bus. AHB bus masters such as CPU and DMA can access the I2S registers through the AHB
interface. Refer to the PSoC 61 datasheet/PSoC 62 datasheet for information on port pin assignments of the I2S block signals
and AC/DC electrical specifications.

31.3 Digital Audio Interface Formats

The I2S block supports the following digital audio interface formats.
■ Standard I2S format
■ Left Justified format
■ Time Division Multiplexed (TDM) format
The Tx and Rx sub-blocks can be independently configured to support one of the above formats in either master or slave
mode. The I2S_MODE bits in the I2S_TX_CTL and I2S_RX_CTL registers are used to configure the digital audio interface
format for the Tx and Rx blocks respectively. The MS (Master/Slave) bit in the I2S_TX_CTL and I2S_RX_CTL registers is
used to configure the blocks in master or slave mode.

31.3.1 Standard I2S Format

Figure 31-2 shows the timing diagrams for the different word length and channel length combinations in the standard I2S
digital audio format. In the standard I2S format, the word select signal (ws) is low for left channel data, and high for right
channel data. The ws signal transitions one bit-clock (sck) early relative to the start of the left/right channel data. All the serial
data (sd), ws signal transitions on the falling edge of the sck signal, and the read operations on the ws and sd lines are usually
done on the rising edge of sck. Therefore, the I2S Tx block writes to the serial data (tx_sdo) line on the falling edge of tx_sck,

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 Inter-IC Sound Bus

and the I2S Rx block reads the data (rx_sdi) on the rising edge of rx_sck. The serial data is transmitted most significant bit
(MSb) first. Depending on whether the block is in master or slave mode, the ws/sck signals are either generated by the block
(master mode) or input signals to the block (slave mode).
The I2S block supports configurable word length and channel length selection options. The word length for the Tx and Rx
blocks can be configured using the WORD_LEN bits in the I2S_TX_CTL and I2S_RX_CTL registers, respectively. The
channel length for the Tx and Rx blocks can be configured using the CH_LEN bits in the I2S_TX_CTL and I2S_RX_CTL
registers respectively. The channel length configuration should always be greater than or equal to the word length
configuration. Ensure that when the I2S Rx block is operated in slave mode, the master Tx device ensures that its channel
length configuration aligns with the I2S Rx block channel length setting. If there is channel length mismatch, the PSoC I2S Rx
block in slave mode will not operate correctly.
In the Tx block, when the channel length is greater than the word length, the unused bits can be transmitted either as ‘0’ or ‘1’.
This selection is made using the OVHDATA bit in the I2S_TX_CTL register. In the Rx block, when the word length is less than
32 bits, the unused most significant bits written to the 32-bit Rx FIFO register can either be set to ‘0’ or sign bit extended. This
selection is made using the BIT_EXTENSION bit in the I2S_RX_CTL register.

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 Inter-IC Sound Bus

Figure 31-2. Standard I2S Format (Word Length and Channel Length Combination Timing Diagrams)
(1) Channel Length = 32-bits
Left Channel Right Channel
(Channel Length = 32-bit) (Channel Length = 32-bit)
SCK ~ ~ ~ ~ ~ ~ ~ ~

WS ~ ~ ~ ~ ~ ~ ~ ~

Word Length = 32-bit mode

MSb LSb MSb LSb
SD 1 0 31 30 ~ 23 22 ~ 17 16 15 14 13 12 ~ 9 8 ~ 1 0 31 30 ~ 23 22 ~ 17 16 15 14 13 12 ~ 9 8 ~ 1 0
Word Length = 24-bit mode
MSb LSb MSb LSb
SD 23 22 ~ 15 14 ~ 9 8 7 6 5 4 ~ 1 0 ~ 23 22 ~ 15 14 ~ 9 8 7 6 5 4 ~ 1 0 ~
Word Length = 20-bit mode
MSb LSb MSb LSb
SD 19 18 ~ 13 12 ~ 5 4 3 2 1 0 ~ ~ 19 18 ~ 13 12 ~ 5 4 3 2 1 0 ~ ~
Word Length = 18-bit mode
MSb LSb MSb LSb
SD 17 16 ~ 11 10 ~ 3 2 1 0 ~ ~ 17 16 ~ 11 10 ~ 3 2 1 0 ~ ~
Word Length = 16-bit mode
MSb LSb MSb LSb
SD 15 14 ~ 9 8 ~ 1 0 ~ ~ 15 14 ~ 9 8 ~ 1 0 ~ ~
Word Length = 8-bit mode
MSb LSb MSb LSb
SD 7 6 ~ 1 0 ~ ~ ~ 7 6 ~ 1 0 ~ ~ ~

(2) Channel Length = 24-bits

Left Channel Right Channel
(Channel Length = 24-bit) (Channel Length = 24-bit)
SCK ~ ~ ~ ~ ~ ~

WS ~ ~ ~ ~ ~ ~

Word Length = 24-bit mode

MSb LSb MSb LSb
SD 1 0 23 22 ~ 15 14 ~ 9 8 7 6 5 4 ~ 1 0 23 22 ~ 15 14 ~ 9 8 7 6 5 4 ~ 1 0
Word Length = 20-bit mode
MSb LSb MSb LSb
SD 19 18 ~ 13 12 ~ 5 4 3 2 1 0 ~ 19 18 ~ 13 12 ~ 5 4 3 2 1 0 ~
Word Length = 18-bit mode
MSb LSb MSb LSb
SD 17 16 ~ 11 10 ~ 3 2 1 0 ~ 17 16 ~ 11 10 ~ 3 2 1 0 ~
Word Length = 16-bit mode
MSb LSb MSb LSb
SD 15 14 ~ 9 8 ~ 1 0 ~ 15 14 ~ 9 8 ~ 1 0 ~
Word Length = 8-bit mode
MSb LSb MSb LSb
SD 7 6 ~ 1 0 ~ ~ 7 6 ~ 1 0 ~ ~

(3) Channel Length = 20-bits

Left Channel Right Channel
(Channel Length = 20-bit) (Channel Length = 20-bit)
SCK ~ ~

WS ~ ~

Word Length = 20-bit mode

MSb LSb MSb LSb
SD 1 0 19 18 ~ 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 ~ 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word Length = 18-bit mode
MSb LSb MSb LSb
SD 17 16 ~ 11 10 9 8 7 6 5 4 3 2 1 0 17 16 ~ 11 10 9 8 7 6 5 4 3 2 1 0
Word Length = 16-bit mode
MSb LSb MSb LSb
SD 15 14 ~ 9 8 7 6 5 4 3 2 1 0 15 14 ~ 9 8 7 6 5 4 3 2 1 0
Word Length = 8-bit mode
MSb LSb MSb LSb
SD 7 6 ~ 1 0 7 6 ~ 1 0

(4) Channel Length = 8-bits

Left Channel Right Channel
(Channel Length = 8-bit) (Channel Length = 8-bit)
SCK

WS

Word Length = 8-bit mode

MSb LSb MSb LSb
SD 7 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Table 31-1 lists the supported word length and channel length combinations.

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 Inter-IC Sound Bus

Table 31-1. Word Length and Channel Length Combinations

Word Length
8-bit 16-bit 18-bit 20-bit 24-bit 32-bit
32-bit Valid Valid Valid Valid Valid Valid
24-bit Valid Valid Valid Valid Valid Invalid
30-bit Valid Valid Valid Valid Invalid Invalid
Channel Length
18-bit Valid Valid Valid Invalid Invalid Invalid
16-bit Valid Valid Invalid Invalid Invalid Invalid
8-bit Valid Invalid Invalid Invalid Invalid Invalid

31.3.2 Left Justified (LJ) Format

Figure 31-3 shows the timing diagrams for the Left Justified interface format using the 32-bit channel length and 32-bit word
length configuration as an example. The only differences between the standard I2S and LJ formats are:
■ In the standard I2S format, WS signal is low for left channel data and high for right channel data. In the LJ format, WS
signal is high for left channel data and low for right channel data.
■ In the standard I2S format, WS signal transitions one bit-clock (sck) early relative to the start of the channel data
(coincides with LSb of the previous channel). In the LJ format, there is no early transition, and the WS signal transitions
coincide with the start of the channel data.

Apart from these differences, all the features explained in the standard I2S format section apply to the LJ format as well.
Figure 31-3. Left Justified Digital Audio Format

Left Channel Right Channel

Word Length = 32 -bit mode

MSb LSb MSb LSb MSb
31 30 17 16 15 14 13 12 9 8 1 0 31 30 17 16 15 14 13 12 9 8 1 0 31

31.3.3 Time Division Multiplexed (TDM) Format

Figure 31-4 shows the timing diagrams for the two types of Time Division Multiplexed (TDM) formats supported by the I2S
block. The differences between the standard I2S/LJ formats and the TDM format are as follows:
■ Standard I2S/LJ formats support only two channels (left/right) per frame, while TDM format supports up to eight channels
per frame.
■ In the TDM format, channel length for all eight channels is fixed at 32 bits. In the standard I2S/LJ formats, the channel
length is configurable. The word length per channel is configurable similar to the standard I2S and the data is also
transmitted most significant bit first. Similar to I2S, when the word length per channel is less than the 32-bit channel length
for Tx block, the OVHDATA bit in the I2S_TX_CTL register is used to fill the unused least significant channel data bits with
either all zeros or all ones
■ In the TDM format, all eight channels of data are always present in a frame, and thus the frame width is fixed at 256 bits.
You have the option to configure the number of active channels in a frame by configuring the CH_NR bits in the
I2S_TX_CTL and I2S_RX_CTL registers. In the standard I2S/LJ format, the CH_NR should always be configured for two
channels. The number of active channels in the TDM format can be less than or equal to eight channels. The unused
(inactive) channels always follow the active channels in a frame. As an example, if CH_NR is set for four channels, CH0 to
CH3 are the active channels and CH4 to CH7 are the unused channels. The OVHDATA bit in the I2S_TX_CTL register is
used to fill the unused channels with either all zeros or all ones.

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 Inter-IC Sound Bus

■ The pulse width of the word select (WS) signal in the TDM format can be configured to be either one bit clock (sck) wide
or one channel wide. The selection is made using the WS_PULSE bit in the I2S_TX_CTL and I2S_RX_CTL registers. The
pulse width is fixed to one channel width in the I2S/LJ format.
■ Two types of TDM formats are supported. In TDM mode A, the WS rising edge signal to signify the start of frame coincides
with the start of CH0 data. In TDM mode B, the WS rising edge signal to signify the start of frame is one bit clock (sck)
early, relative to the start of CH0 data (coincides with the last bit of the previous frame). The selection between the two
TDM formats is made using the I2S_MODE bits in the I2S_TX_CTL and I2S_RX_CTL registers.
Figure 31-4. TDM Digital Audio Interface Format
TDM mode A format
Frame
(Frame Length = 256-bits)
Channel
(Channel Length = 32-bits)

SCK ~ ~ ~ ~ ~

WS ~ Pulse width is 1 SCK

~ period or 1 channel~length ~ ~

SD CH7 CH0 ~ CH1 ~ ~ CH6 ~ CH7 ~ CH0

TDM mode format B

Frame
(Frame Length = 256-bits)
Channel
(Channel Length = 32-bits)

SCK ~ ~ ~ ~ ~

WS ~ Pulse width is 1 SCK period

~ or 1 channel length
~ ~ ~

SD CH7 CH0 ~ CH1 ~ ~ CH6 ~ CH7 ~ CH0

31.4 Clocking Polarity and Delay Options

The I2S block supports configurable clock polarity and delay options to alleviate any timing issues in the system involving
PCB signal propagation delays, and delays associated with internal device signal routing.
When the I2S Tx block operates in the slave mode, the tx_sck and tx_ws signals are input signals to the PSoC 6 MCU, and
the tx_sdo output signal is transmitted off the tx_sck falling edge. The tx_sdo signal is sampled by the external master device
Rx block on the subsequent tx_sck rising edge. Timing issues arise if the tx_sdo signal reaching the master side Rx block
does not meet the setup and hold time requirements for input data on the master side. The I2S Tx block in the PSoC 6 MCU
has an option to advance the serial data transmission by 0.5 SCK cycles when the B_CLOCK_INV bit in the I2S_TX_CTL
register is set. This feature can be used if there are timing issues while operating the I2S Tx block in slave mode.
Similarly, when the I2S Rx block operates in the master mode, the rx_sck and rx_ws signals are output signals from the
PSoC 6 MCU, and the rx_sdi signal is transmitted by the external master device on the falling edge of rx_sck. The PSoC I2S
Rx block samples the rx_sdi signal on the subsequent rx_sck rising edge. Timing issues arise if the rx_sdi signal reaching the
PSoC block does not meet the setup and hold time requirements for input data. The I2S Rx block has an option to delay the
serial data capture by 0.5 SCK cycles when the B_CLOCK_INV bit in the I2S_RX_CTL register is set. This feature can be
used if there are timing issues while operating the I2S Rx block in master mode.
In addition to these clock delay options, there is also an option to invert the outgoing bit clock (sck) in master mode by setting
the SCKO_POL bit in the I2S_TX_CTL and I2S_RX_CTL registers. Similarly, in the slave mode, there is an option to invert
the incoming bit clock (sck) by setting the SCKI_POL bit in the I2S_TX_CTL and I2S_RX_CTL registers.
Refer to the registers TRM for detailed description of the B_CLOCK_INV, SCKI_POL, and SCKO_POL register
configurations.

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 Inter-IC Sound Bus

31.5 Interfacing with Audio Codecs

The I2S block in the PSoC 6 MCU interfaces with an audio codec device based on the choice of codec device and the end
application requirements. Some scenarios and the connection diagrams are as follows:
■ Codecs with separate ws and sck signals for the Rx and Tx directions: To interface with these codecs, the connections
between the PSoC I2S block and the codec device will be as shown in Figure 31-1 where the PSoC I2S Tx signals
(tx_sck, tx_ws, tx_sdo) connect to the codec Rx signals, and the PSoC I2S Rx signals (rx_sck, rx_ws, rx_sdi) connect to
the codec Tx signals. The direction of sck (tx_sck, rx_sck) and ws (tx_ws, rx_ws) signals depends on which device is the
master and which device is the slave.
■ Codecs with common ws and sck signals for both Rx and Tx directions: There are two possible configurations to interface
these codecs with the PSoC 6 MCU as shown in Figure 31-5. In both configurations, the sck signals (tx_sck, rx_sck,
codec_sck) are shorted externally. The same goes for the ws signal connections as well (tx_ws, rx_ws, codec_ws).
Ensure that only one block is driving the sck and ws lines. So when the codec acts as the slave device, the PSoC I2S Rx
block should be in the master mode, and the PSoC I2S Tx block should be in the slave mode (or PSoC I2S Rx as slave
and PSoC I2S Tx as master). When the codec acts as the master device, both the PSoC I2S Rx and PSoC I2S Tx blocks
should be in slave mode.
Figure 31-5. Interfacing with Codecs having Common ws and sck Signals
PSoC PSoC

2
IS I2 S
tx_sck tx_sck
2
I2 S IS
tx_ws tx_ws Transmitter
Transmitter
(Slave) (Slave)
codec_rx_sdi tx_sdo codec_rx_sdi tx_sdo
Codec Codec
(Tx Slave, (Tx Master,
Rx Slave) codec_sck rx_sck Rx Master) codec_sck rx_sck

codec_ws I2 S codec_ws rx_ws I2 S

rx_ws Receiver
Receiver
(Master) (Slave)
codec_tx_sdo rx_sdi codec_tx_sdo rx_sdi

31.6 Clocking Features

The I2S unit has three clock inputs.

Table 31-2. Clock Inputs

Signal DESCRIPTION
System clock. This clock is used for the AHB slave Interface, control, status, and interrupt registers, and also
clk_sys_i2s
clocks the DMA trigger control logic.
I2S internal clock. This clock is used for I2S transmitter (Tx)/receiver (Rx) blocks; it is asynchronous with the
clk_audio_i2s clk_sys_i2s. This clock is connected to the CLK_HF[1] high-frequency clock in the device. Refer to the
Clocking System chapter on page 242 for more details on high frequency clocks.
I2S external clock. This clock is provided from an external I2S bus host through a port pin. It is used in place
clk_i2s_if
of the clk_audio_i2s clock to synchronize I2S data to the clock used by the external I2S bus host.

Figure 31-6 shows the clocking divider structure in the I2S block. In the master mode, the sck and ws signals are generated
either using the clk_audio_i2s internal clock or the clk_i2s_if external clock. Refer to the PSoC 61 datasheet/PSoC 62
datasheet for the port pin assignment of clk_i2s_if clock. The CLOCK_SEL bit in the I2S_CLOCK_CTL register controls the
selection between internal and external clocks.

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 Inter-IC Sound Bus

Figure 31-6. Clocking Divider Structure

clk_audio_i2s
SCK signal to Tx,
(CLK_HF[1])
Rx blocks
CLOCK_DIV
(MCLK_SOC / 8)
(1st stage divider) MCLK_SOC 2nd stage divider
clk_i2s_if
Divider range: 1 to 64 (Divider value fixed at 8)

CLOCK_SEL bit in
I2S_CLOCK_CTL register

There are two stages of clock dividers in the I2S block as follows.
■ The first stage clock divider is used to generate the internal I2S master clock (MCLK_SOC). The input clock to the first
stage divider is either clk_audio_i2s or clk_i2s_if. The first stage clock divider is configured using the CLOCK_DIV bits in
I2S_CLOCK_CTL register. Divider values from 1 to 64 are supported.
■ The second stage clock divider is used to generate the sck signals. The input clock is the output from the first stage clock
divider. This divider value is fixed at ‘8’ (FTX_SCK = FRX_SCK = FMCLK_SOC/8). The word select (ws) signal frequency
depends on the sck frequency, and the configured channel length value.
When in slave mode, the internal clock (MCLK_SOC) frequency should still be eight times the frequency of the input serial
clock. You must choose the appropriate clock source and the CLOCK_DIV divider value to guarantee this condition is met in
the slave mode of operation. Usually, when the PSoC I2S block operates in the slave mode, the host sends a master clock
which is an integral multiple of the sampling rate. This master clock can be routed to the clk_i2s_if port pin. The CLOCK_DIV
divider value can then be adjusted to ensure that the MCLK_SOC is eight times the input SCK frequency.
Table 31-3 gives an example of the clock divider settings for operating the I2S block at the standard sampling rates in the
standard I2S format. Note that the first stage divider values in the table are the register field values – the actual divider values
are one more than the configured register values as explained in the clock divider section. Refer to the PSoC 61 datasheet/
PSoC 62 datasheet for details on maximum values of SCK frequency, and the output sampling rates.

Table 31-3. I2S Divider Values for Standard Audio Sampling Rates in Standard I2S Format
SCK CLK_HF1 (CLK_HF[1])/SCK Second Stage
Sampling Rate WORD_LEN CLK_CLOCK_DIV
(2*WORD_LEN*SR) (or clk_i2s_if) (Total Divider Divider
(SR) (kHz) (bits) (First Divider)
(MHz) (MHz) Ratio) (Fixed at 8)
8 32 0.512 96 11
16 32 1.024 48 5
49.152
32 32 2.048 24 2 8
48 32 3.072 16 1
44.1 32 2.8224 45.1584 32 3

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 Inter-IC Sound Bus

31.7 FIFO Buffer and DMA pointers. This register can be used for debug purposes. The
I2S Tx FIFO read pointer is updated whenever the data is
Support transferred from the Tx FIFO to the internal transmit buffer.
Tx FIFO write pointer is updated whenever the data is
The I2S block has two FIFO buffers - one each for the Tx written to the I2S_TX_FIFO_WR register, either through the
block and Rx block, respectively. The ordering format of the CPU or the DMA controller.
channel data in both Tx and Rx FIFOs depends on the
configured digital audio format. This ordering format should For Tx FIFO data writes using the CPU, the hardware can
be considered when writing to the Tx FIFO or reading from be used to trigger an interrupt event for any of the FIFO
the Rx FIFO. In the standard I2S and LJ digital audio conditions such as TX_TRIGGER, TX_NOT_FULL, and
formats, the ordering of the data is (L, R, L, R, L, ...) where L TX_EMPTY. As part of the interrupt handler, the CPU can
refers to the left channel data and R refers to the right write to the I2S_TX_FIFO_WR register. The recommended
channel data. In the TDM format with the number of active method is to write (256 - TRIGGER_LEVEL) words to the
channels set to four, the data order will be (CH0, CH1, CH2, I2S_TX_FIFO_WR register every time the TX_TRIGGER
CH3, CH0, CH1, CH2, CH3, CH0, .....). If the number of interrupt event is triggered. In addition, interrupt events can
active channels is set to eight, the cycle will repeat after be generated for FIFO overflow/underflow conditions.
CH0–CH7 data.
For DMA-based Tx data transfers, the I2S Tx DMA trigger
I2S Tx FIFO: The I2S Tx block has a hardware FIFO of signal (tr_i2s_tx_req) can be enabled by writing ‘1’ to the
depth 256 elements where each element is 32-bit wide. In TX_REQ_EN bit in I2S_TR_CTL register. The trigger signal
addition to this 256-element FIFO, the I2S block has an output will become high whenever the Tx FIFO has less
internal transmit buffer that can store four 32-bit data to be entries than that configured in the TRIGGER_LEVEL field.
transmitted. This four-element buffer is used as an The DMA channel can be configured to transfer up to (256 -
intermediary to hold data to be transferred on the I2S bus, TRIGGER_LEVEL) words from the applicable source
and is not exposed to the AHB BUS interface. address (such as Flash and SRAM regions). The destination
address of the DMA should always be the
The TX FIFO can be paused by setting the TX_PAUSE bit in I2S_TX_FIFO_WR register address, with the destination
I2S_CMD. When the TX_PAUSE bit is set, the data sent address increment feature disabled in the DMA channel
over I2S is “0”, instead of TX FIFO data. To resume normal configuration. This FIFO address increment logic is handled
operation, the TX_PAUSE bit must be cleared. internally to adjust the write pointer, and the DMA should not
The I2S_TX_FIFO_CTL register is used for FIFO control increment the destination address. For more details on DMA
operations. The TRIGGER_LEVEL bits in the channel configuration, refer to the DMA Controller
I2S_TX_FIFO_CTL register can be used to generate a (DW) chapter on page 91.
transmit trigger event when the Tx FIFO has less entries The data in the I2S_TX_FIFO is always right-aligned. The
than the value configured in the TRIGGER_LEVEL bits. I2S_TX_FIFO_WR format for different word length
The FIFO freeze operation can be enabled by setting the configurations is provided in Figure 31-7.
FREEZE bit in the I2S_TX_FIFO_CTL register. When the
FREEZE bit is set and the Tx block is operational
(TX_START bit in I2S_CMD is set), hardware reads from the
Tx FIFO do not remove the FIFO entries. Also, the Tx FIFO
read pointer will not be advanced. Any writes to the
I2S_TX_FIFO register will increment the Tx FIFO write
pointer; when the Tx FIFO becomes full, the internal write
pointer stops incrementing. The freeze operation may be
used for firmware debug purposes. This operation is not
intended for normal operation. To return to normal operation
after using the freeze operation, the I2S must be reset by
clearing the TX_ENABLED bit in the I2S_CTL register, and
then setting the bit again.
The CLEAR bit in the I2S_TX_FIFO_CTL register is used to
clear the Tx FIFO by resetting the read/write pointers
associated with the FIFO. Write accesses to the Tx FIFO
using the I2S_TX_FIFO_WR or I2S_TX_FIFO_WR_SILENT
registers are not allowed while the CLEAR bit is set.
The I2S_TX_FIFO_STATUS register provides FIFO status
information. This includes number of used entries in the Tx
FIFO and the current values of the Tx FIFO read/write

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Figure 31-7. I2S_TX_FIFO_WR Register Format for Different Word Lengths

write data format of I2S_TX_FIFO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 24-bit mode
fixed "0" 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 20-bit mode
fixed "0" 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 18-bit mode
fixed "0" 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 16-bit mode
fixed "0" 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I2S Rx FIFO: The I2S Rx block has a hardware FIFO of from the I2S_RX_FIFO_RD register, either through the CPU
depth 256 elements where each element is 32-bit wide. In or the DMA controller. For debug purposes, the
addition to this 256-element FIFO, the I2S block has an I2S_RX_FIFO_RD_SILENT register is available, which
internal receive buffer that can store four 32-bit data to be always returns the top element of the Rx FIFO without
received. This four-element buffer is used as an updating the read pointer.
intermediary to hold data received on the I2S bus, and is not
For Rx FIFO data reads using the CPU, the hardware can
exposed to the AHB BUS interface.
be used to trigger an interrupt event for any of the FIFO
The I2S_RX_FIFO_CTL register is used for FIFO control conditions such as RX_TRIGGER, RX_NOT_EMPTY, and
operations. The TRIGGER_LEVEL bits in the RX_FULL. As part of the interrupt handler, the CPU can
I2S_RX_FIFO_CTL register is used to generate a receive read from the I2S_RX_FIFO_RD register. The
trigger event when the Rx FIFO has more entries than the recommended method is to read (TRIGGER_LEVEL + 1)
value configured in the TRIGGER_LEVEL bits. In the words from the I2S_RX_FIFO_RD register every time the
standard I2S/LJ format, the TRIGGER_LEVEL bits can be RX_TRIGGER interrupt event is triggered. In addition,
configured up to the allowed maximum value of 253. In the interrupt events can be generated for FIFO overflow/
TDM format, the maximum value of TRIGGER_LEVEL is underflow conditions.
[254–CH_NR) where CH_NR is the number of active
For DMA-based Rx data transfers, the I2S Rx DMA trigger
channels in the TDM frame.
signal (tr_i2s_rx_req) can be enabled by writing ‘1’ to the
The FIFO freeze operation can be enabled by setting the RX_REQ_EN bit in the I2S_TR_CTL register. The trigger
FREEZE bit in the I2S_RX_FIFO_CTL register. When the signal output will become high whenever the Rx FIFO has
FREEZE bit is set and the Rx block is operational more entries than that configured in the TRIGGER_LEVEL
(RX_START bit in the I2S_CMD register is set), hardware field. The DMA channel can be configured to transfer up to
will not write to the Rx FIFO. Also, the Rx FIFO write pointer (TRIGGER_LEVEL + 1) words to the applicable destination
will not be advanced. Any reads from the I2S_RX_FIFO address (such as SRAM regions). The source address of
register will increment the Rx FIFO read pointer; when the the DMA should always be the I2S_RX_FIFO_RD register
Rx FIFO becomes empty, the internal read pointer stops address, with the source address increment feature
incrementing. The freeze operation may be used for disabled in the DMA channel configuration. This FIFO
firmware debug purposes. This operation is not intended for address increment logic is handled internally to adjust the
normal operation. To return to normal operation after using read pointer, and the DMA should not increment the source
the freeze operation, the I2S must be reset by clearing the address. For more details on DMA channel configuration,
RX_ENABLED bit in the I2S_CTL register and then setting refer to the DMA Controller (DW) chapter on page 91.
the bit again.
The data in the I2S_RX_FIFO is always right aligned. The
The CLEAR bit in I2S_RX_FIFO_CTL register is used to I2S_RX_FIFO_RD format for different word length
clear the Rx FIFO by resetting the read/write pointers configurations is provided in Figure 31-8. Note that the
associated with the FIFO. Read accesses from the Rx FIFO unused most significant bits are either set as ‘0’ or sign-bit
using the I2S_RX_FIFO_RD or I2S_RX_FIFO_RD_SILENT extended depending on the BIT_EXTENSION bit in the
registers are not allowed while the CLEAR bit is set. I2S_RX_CTL register.
The I2S_RX_FIFO_STATUS register provides FIFO status
information. This includes number of used entries in the Rx
FIFO and the current values of the Rx FIFO read/write
pointers. This register can be used for debug purposes. The
I2S Rx FIFO write pointer is updated whenever the data is
transferred to the Rx FIFO from the internal receive buffer.
Rx FIFO read pointer is updated whenever the data is read

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 Inter-IC Sound Bus

Figure 31-8. I2S_RX_FIFO_RD Register Format for Different Word Lengths

read data format of I2S_RX_FIFO

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 24-bit mode
not Bit extension fixed "0" 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit extension "1" "1" "1" "1" "1" "1" "1" "1" "1" 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
"0" "0" "0" "0" "0" "0" "0" "0" "0" 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 20-bit mode
not Bit extension fixed "0" 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Bit extension "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
"0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 18-bit mode
not Bit extension fixed "0" 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit extension "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
"0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSb LSb
Word Length = 16-bit mode
not Bit extension fixed "0" 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit extension "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
"0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

31.8 Interrupt Support

The I2S block has one interrupt output signal that goes to the interrupt controller in the CPU. Refer to the Interrupts chapter on
page 56 for details on the vector number of the I2S interrupt and the procedure to configure the interrupt priority, vector
address, and enabling/disabling. The I2S interrupt can be triggered under any of the following events - TX_TRIGGER,
TX_NOT_FULL, TX_EMPTY, TX_OVERFLOW, TX_UNDERFLOW, TX_WD, RX_TRIGGER, RX_NOT_EMPTY, RX_FULL,
RX_OVERFLOW, RX_UNDERFLOW, or RX_WD. Each of the interrupt events can be individually enabled/disabled to
generate an interrupt condition. The I2S_INTR_MASK register is used to enable the required events by writing ‘1’ to the
corresponding bit. Irrespective of the INTR_MASK settings, if any of the events occur, the corresponding event status bit will
be set by the hardware in the I2S_INTR register. The I2S_INTR_MASKED register is the bitwise AND of the
I2S_INTR_MASK and I2S_INTR registers. The final I2S interrupt signal is the logical OR of all the bits in the
I2S_INTR_MASKED register. So only those events that are enabled in the I2S_INTR_MASK register are propagated as
interrupt events to the interrupt controller. Interrupts can also be triggered in software by writing to the corresponding bits in
I2S_INTR_SET register. Figure 31-9 illustrates the interrupt signal generation.
Figure 31-9. Interrupt Signal Generation

HW event for an interrupt INTR.XXX

D Q
OR AND
INTR_SET.XXX
INTR_I2S_MASK.XXX OR Interrupt_I2S

Other interrupt signals

(INTR_I2S & INTR_I2S_MASK)

In the interrupt service routine (ISR), the I2S_INTR_MASKED register should be read to know the events that triggered the
interrupt event. Multiple events can trigger the interrupt because the final interrupt signal is the logical OR output of the
events. The ISR should do the tasks corresponding to each interrupt event that was triggered. At the end of the ISR, the value
read in the I2S_INTR_MASKED register earlier should be written to the I2S_INTR register to clear the bits whose interrupt
events were processed in the ISR. Unless the bits are not cleared by writing ‘1’ to the I2S_INTR register, the interrupt signal
will always be high. A dummy read of the I2S_INTR register should be done for the earlier register write to take effect.

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 Inter-IC Sound Bus

31.9 Watchdog Timer

The Tx and Rx blocks have independent watchdog timers, which can be used to generate an interrupt event if the Word
Select (WS) input is idle for more than the configured time period. This feature is available only in the slave mode of operation
where the external master drives the WS input lines (tx_ws, rx_ws). This feature can be used to detect any signal
transmission issues, master device issues, or if the master has halted communication. If the master drives the same word
select signal to both the tx_ws and rx_ws lines, then only one of the watchdog timers can be enabled to cause the interrupt
event. Although the following explanation covers Tx watchdog, the same explanation applies to Rx watchdog as well.
To enable the Tx watchdog timer feature, WD_EN bit in the I2S_TX_CTL register should be set. The watchdog timer reload
value (32-bit timer) is configured by writing to the I2S_TX_WATCHDOG register. A value of zero written to the
I2S_TX_WATCHDOG register will also disable the watchdog timer. Figure 31-10 illustrates the watchdog behavior when the
timer is enabled. The timer runs off the CLK_PERI system clock. Refer to the Clocking System chapter on page 242 for
details on generation of CLK_PERI. The timer starts running when WD_EN and TX_START bits are set. The timer reload
happens either on a rising edge event on tx_ws input signal, or when the timer values reaches zero. When the timer value
reaches zero, the TX_WD interrupt event is generated. The TX_WD bit in the I2S_INTR_MASK register should be set to
enable interrupt generation by the watchdog timer interrupt event. The interrupt event can be cleared by writing ‘1’ to the
TX_WD bit in the I2S_INTR register.
Figure 31-10. Watchdog Timer Working
tx_ws (input to PSoC 6 MCU)
(or rx_ws)
Reloads watchdog timer Reloads watchdog timer
watchdog timer for tx on rising edge of tx_ws when timer value is 0.
(or rx)
(or rx_ws) Interrupt event generated
I2S_TX_WATCHDOG
(or I2S_RX_WATCHDOG)

Timer Value

0
time Interrupt event
Interrupt event of the
cleared in software
wachdog occurs
Interrupt Event (TX_WD)
(or RX_WD)

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 440
 32. PDM-PCM Converter

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PDM-PCM unit accepts a stereo or mono serial data stream (pulse modulated 1-bit stream) coming from external digital
PDM microphones. The PDM-PCM converter consists of a fifth order cascaded integrator comb (CIC) filter followed by a
decimator, and a final stage high-pass filter. This block simplifies the conversion process by exposing the different
configuration settings as registers, which you can program to meet the application needs. The entire PDM-PCM conversion
process is handled in hardware; the PCM output data streaming can be done using the DMA controller thus freeing up the
CPU bandwidth from performing periodic audio streaming activities.

32.1 Features
■ Supports Mono/Stereo mode pulse density modulation (PDM) to pulse code modulation (PCM) conversion
■ Accepts 1-bit PDM input and can generate 16-, 18-, 20-, or 24-bit PCM digital data output
■ Configurable PDM microphone clock frequency
■ Ability to generate standard audio sampling rates by adjusting the decimation rate and clock divider values
■ Digital volume control: Programmable gain amplifier (PGA) control from –12 dB to +10.5 dB in 1.5-dB steps
■ Smooth PGA and soft-mute control
■ Hardware receive buffer: 24-bit wide, 255-element FIFO with support for DMA controller-based data transfer
■ Optional high-pass filter to remove DC and low-frequency noise

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 441
 PDM-PCM Converter

32.2 Architecture
Figure 32-1. Block Diagram

PSoC

CPU Data Wire/ SRAM

DMA

AHB bus
clk
data PDM Microphone
(Right)
L/R Select GND

PDM-PCM Converter PDM_CKO

clk
PDM Microphone
PDM_DATA (Left)
data
Audio subsystem L/R Select VDD

Figure 32-1 shows the block diagram of the PDM-PCM converter. Refer to the PSoC 61 datasheet/PSoC 62 datasheet for
information on port pin assignments of the PDM block signals, electrical specifications, and the interrupt vector number.

32.2.1 Enable/Disable Converter

The PDM-PCM converter can be powered ON or OFF by using the ENABLED bit in the PDM_CTL register. The block can be
turned OFF when not used to save power. When the block is powered off by writing ‘0’ to the ENABLED bit, the non-retention
registers lose their current values. Refer to the registers TRM to know which registers are retention and non-retention type.
When the block is enabled again, the non-retention registers are reset to their default values. User firmware should ensure
that all non-retention registers are configured as required after the ENABLED bit is set, and before the PDM-PCM conversion
is started by setting the STREAM_EN bit in the PDM_CMD register. See Operating Procedure on page 448 for the
recommended procedure to configure this PDM-PCM converter before starting the PDM-PCM conversion.

32.2.2 Clocking Features

The block uses the CLK_HF[1] root high-frequency clock for performing the PDM-PCM conversion process. Refer to the
Clocking System chapter on page 242 for details on selecting the clock source for CLK_HF[1], and configuring the divider
registers to generate CLK_HF[1].
Figure 32-2. PDM-PCM Clocking Dividers

CLK_CLOCK_DIV MCLKQ_CLOCK_DIV CKO_CLOCK_DIV

CLK_HF[1] (1st stage divider) PDM_CLK (2nd stage divider) MCLKQ (3rd stage divider) PDM_CKO
To external PDM
Divider range: 1 to 4 Divider range: 1 to 4 Divider range: 2 to 16
Microphone

Figure 32-2 shows the clock divider structure in the block. The block has three stages of clock dividers to generate the clock
(PDM_CKO), which goes to the external PDM microphone clock input.
1. The first stage clock divider (CLK_CLOCK_DIV field in the PDM_CLOCK_CTL register) is used to generate the actual
clock signal (PDM_CLK) that goes to the PDM-PCM converter. The input is CLK_HF[1]; the CLK_CLOCK_DIV can be a
value between 0 and 3 (divider value between 1 and 4).
fPDM_CLK = fCLK-HF[1] / (CLK_CLOCK_DIV + 1)
2. The second stage clock divider (MCLKQ_CLOCK_DIV field in the PDM_CLOCK_CTL register) is used to generate the
internal master clock and can take a value between 0 and 3 (divider value between 1 and 4). The input clock is pdm_clk
and the output of the divider is MCLKQ.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 442
 PDM-PCM Converter

fMCLKQ = fPDM_CLK / (MCLKQ_CLOCK_DIV + 1)

3. The third stage clock divider (CKO_CLOCK_DIV field in the PDM_CLOCK_CTL register) is used to generate the clock
that goes to the PDM microphone clock (PDM_CKO) through the output pin of the PSoC 6 MCU. The input clock is
MCLKQ. The divider register can be between 1 and 15 (divider value between 2 and 16).
fPDM_CKO = fMCLKQ / (CKO_CLOCK_DIV + 1), if CKO_CLOCK_DIV 1
fPDM_CKO = fMCLKQ / 2, if CKO_CLOCK_DIV = 0

32.2.3 Over-Sampling Ratio

Over-sampling ratio (OSR) is the ratio between the frequency of the PDM microphone clock (fPDM_CKO) and the output PCM
sampling rate frequency (fS). The OSR is determined by the SINC_RATE bits in the PDM_CLOCK_CTL register. The relation
is as follows.
OSR = fPDM_CKO / fS = 2 x SINC_RATE

Table 32-1 gives an example of the PDM clock divider and SINC_RATE register configurations to generate the PCM output at
standard sampling rates. Note that the PDM divider values in the table are the register field values – the actual divider values
are one more than the configured register values as explained in the clock divider section. Refer to the PSoC 61 datasheet/
PSoC 62 datasheet for details on maximum values of PDM_CKO frequency, PDM_CLK frequency, and the output sampling
rates.

Table 32-1. PDM Clock Divider Values for Standard Audio Sampling Rates
(CLK_HF[1])/ MCLKQ_CLOCK
Sampling PDM_CKO CKO_CLOCK_
SINC_RATE CLK_HF1 (PDM_CKO) CLK_CLOCK_DIV _DIV
Rate (SR) (=2*SINC_RATE*SR) DIV
(= OSR/2) (MHz) (Total Divider (First Divider) (Second
(kHz) (MHz) (Third Divider)
Ratio) Divider)
8 32 0.512 96 1 3 11
16 32 1.024 48 1 3 5
49.152
32 32 2.048 24 0 3 5
48 32 3.072 16 0 1 7
44.1 32 2.8224 45.1584 32 0 1 7

There are various methods to generate the CLK_HF[1] register settings for the different operation modes are given
frequencies listed in the table depending on the clocking in Table 32-2. The table also lists the invalid register
options available on the device. Refer to the Clocking settings, which you must not use in the firmware.
System chapter on page 242 for details on the clocking
options available in the device, including the clock sources
and PLL/FLL circuitry. For example, an external crystal
oscillator (ECO) can be used in conjunction with a phase-
locked loop (PLL) to generate the CLK_HF[1] at the desired
frequency of 49.152 MHz or 45.1584 MHz.
One possible combination of PLL divider values to generate
the 49.152 MHz frequency from a 17.2032 MHz ECO are:
REFERENCE_DIV = 7, FEEDBACK_DIV = 100,
OUTPUT_DIV = 5. One possible combination of PLL divider
values to generate the 45.1584 MHz frequency from a
17.2032 MHz ECO are: REFERENCE_DIV = 8,
FEEDBACK_DIV = 105, OUTPUT_DIV = 5.

32.2.4 Mono/Stereo Microphone Support

The PDM-PCM converter supports mono-left, mono-right,
stereo, and swapped stereo modes of operation. The
operation mode is controlled by the PDM_CH_SET and
SWAP_LR bits in the PDM_MODE_CTL register. The

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 PDM-PCM Converter

Table 32-2. Operation Mode Register Settings

Register Setting Operation Mode
PCM_CH_SET = 0, SWAP_LR = 0 or 1 Recording OFF
Mono-Left recording mode. Only the left microphone channel is sampled on the rising
PCM_CH_SET = 1, SWAP_LR = 0
edge of PDM_CKO. FIFO buffer contains only left channel data.
Mono-Right recording mode. Only the right microphone channel is sampled on the falling
PCM_CH_SET = 2, SWAP_LR = 1
edge of PDM_CKO. FIFO buffer contains only right channel data.
Stereo recording mode. The right microphone channel is sampled on the falling edge of
PCM_CH_SET = 3, SWAP_LR = 0 PDM_CKO and left channel on rising edge. FIFO buffer contains data in L/R format (left
channel followed by right channel)
Swapped Stereo recording mode. The right microphone channel is sampled on the rising
PCM_CH_SET = 3, SWAP_LR = 1 edge of PDM_CKO and left channel on falling edge. FIFO buffer contains data in L/R for-
mat (left channel followed by right channel)
PCM_CH_SET = 1, SWAP_LR = 1 or Invalid setting (not supported). Do not operate the PDM-PCM converter in these configu-
PCM_CH_SET = 2, SWAP_LR = 0 ration settings.

Figure 32-3 shows the timing diagrams for the different operating modes.
Figure 32-3. PDM Mono/Stereo Timing
Mono left mode (PCM_CH_SET = 1, SWAP_LR = 0)

PDM_CKO

PDM_DATA L L L

Mono right mode (PCM_CH_SET = 2, SWAP_LR = 1)

PDM_CKO

PDM_DATA R R R

Stereo mode (PCM_CH_SET = 3, SWAP_LR = 0)

PDM_CKO

PDM_DATA L R L R L R

Swapped Stereo mode (PCM_CH_SET = 3, SWAP_LR = 1)

PDM_CKO

PDM_DATA R L R L R L

To alleviate uncertain board delay impact on PDM_IN setup different PDM microphone manufacturers. The SWAP_LR
and hold timing constraints, the PDM-PCM provides bit in the PDM-PCM converter ensures that you can adjust
CKO_DELAY bits in the PDM_MODE_CTL register to add the sampling logic according to the microphone datasheet
extra delay for the PDM_CKO path to internal sampler. recommendations. Refer to the PDM microphone
CKO_DELAY can be a value between 0 and 7. A value of ‘0’ manufacturer datasheet for the exact timing details. Also, in
implies that internal sampling of PDM data is advanced by stereo mode, use the same manufacturer for both the left/
three PDM_CLK clock cycles for the PDM_CKO transition. right PDM microphones to ensure the timing behavior is
A value of ‘7’ implies that internal sampling of PDM data is uniform for both channels.
delayed by four PDM_CLK clock cycles for the PDM_CKO
transition. Refer to the registers TRM for details on the
meaning of different CKO_DELAY values.
Note: Variations have been observed in the
recommendation for left/right sampling logic among the

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 PDM-PCM Converter

32.2.5 Hardware FIFO Buffers and DMA For DMA-based data transfers, the DMA trigger signal
(tr_pdm_rx_req) can be enabled by writing ‘1’ to the
Controller Support RX_REQ_EN bit in the PDM_TR_CTL register. The trigger
The PDM-PCM converter has a hardware FIFO depth of signal output will become high whenever the Rx FIFO has
255 elements where each element is 24-bit wide. more entries than that configured in the TRIGGER_LEVEL
field. Refer to the Trigger Multiplexer Block chapter on
The PDM_RX_FIFO_CTL register is used for FIFO control page 294 for details on how to connect the DMA trigger
operations. Refer to the register description in the registers signal to a particular DMA channel. The DMA channel can
TRM for more details. The TRIGGER_LEVEL field in the be configured to transfer up to (TRIGGER_LEVEL + 1)
PDM_RX_FIFO_CTL register is used to generate a receive words to the applicable destination address (such as SRAM
trigger event (interrupt event, DMA trigger signal) when the regions). The source address of the DMA should always be
Rx FIFO has more entries than the value configured in the the PDM_RX_FIFO_RD register address, with the source
TRIGGER_LEVEL field. The TRIGGER_LEVEL field can be address increment feature disabled in the DMA channel
configured up to 254 in the mono microphone recording configuration. This FIFO address increment logic is handled
mode and up to 253 in the stereo microphone recording internally to adjust the read pointer, and the DMA should not
mode. increment the source address. For more details on DMA
The FIFO freeze operation can be enabled by setting the channel configuration, refer to the DMA Controller
FREEZE bit in the PDM_RX_FIFO_CTL register. When the (DW) chapter on page 91.
FREEZE bit is set and the Rx block is operational The successive data read from the PDM_RX_FIFO_RD
(STREAM_EN bit in the PDM_CMD register is set), follows the Left 1/Right 1/Left 2/Right 2/… format in stereo
hardware will not write to the Rx FIFO. Also, the Rx FIFO and swapped stereo modes of operation. For mono left and
write pointer will not be advanced. Any reads from the mono right recording modes, the data read from FIFO
PDM_RX_FIFO_RD register will increment the Rx FIFO contains either the left channel data (mono left mode) or the
read pointer; when the Rx FIFO becomes empty, the internal right channel data (mono right mode).
read pointer stops incrementing. The freeze operation may
be used for firmware debug purposes. This operation is not The data in the PDM_RX_FIFO_RD is always right-aligned.
intended for normal operation. To return to normal operation The PDM_TX_FIFO_RD format for different word length
after using the freeze operation, the PDM-PCM must be configurations is provided in Figure 32-4. Note that the
reset by clearing the ENABLED bit in PDM_CTL register, unused most significant bits are either set as ‘0’ or sign-bit
and then setting the bit again. extended depending on the BIT_EXTENSION field setting in
the PDM_DATA_CTL register.
The CLEAR bit in the PDM_RX_FIFO_CTL register is used
to clear the Rx FIFO by resetting the read/write pointers
associated with the FIFO. Read accesses from the Rx FIFO
using PDM_RX_FIFO_RD or PDM_RX_FIFO_RD_SILENT
registers are not allowed while the CLEAR bit is set.
The PDM_RX_FIFO_STATUS register provides FIFO status
information. This includes number of used entries in the Rx
FIFO and the current values of the Rx FIFO read/write
pointers. This register can be used for debug purposes. The
Rx FIFO write pointer is updated whenever the data is
transferred to the Rx FIFO from the internal receive buffer.
Rx FIFO read pointer is updated whenever the data is read
from the PDM_RX_FIFO_RD register, either through the
CPU or the DMA controller. For debug purposes, the
PDM_RX_FIFO_RD_SILENT register is available, which
always returns the top element of the Rx FIFO without
updating the read pointer.
For Rx FIFO data reads using the CPU, the hardware can
be used to trigger an interrupt event for any of the FIFO
conditions such as RX_TRIGGER and RX_NOT_EMPTY.
As part of the interrupt handler, the CPU can read from the
PDM_RX_FIFO_RD register. The recommended method is
to read (TRIGGER_LEVEL + 1) words from the
PDM_RX_FIFO_RD register every time the RX_TRIGGER
interrupt event is triggered. In addition, interrupt events can
be generated for FIFO overflow and underflow conditions.

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 PDM-PCM Converter

Figure 32-4. FIFO Register Structure

read data format of PDM_RX_FIFO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WORD_LEN = 24-bit mode MSb LSb
BIT_EXTENSION = 0 fixed "0" 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BIT_EXTENSION = 1 "1" "1" "1" "1" "1" "1" "1" "1" "1" 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Sign Bit Extension)
"0" "0" "0" "0" "0" "0" "0" "0" "0" 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WORD_LEN = 20-bit mode MSb LSb

BIT_EXTENSION = 0 fixed "0" 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

BIT_EXTENSION = 1 "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" "1" 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
(Sign Bit Extension) "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" "0" 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

32.2.6 Interrupt Support

The block has one output signal (interrupt_pdm) that goes to the interrupt controller in the CPU. Refer to the PSoC 61
datasheet/PSoC 62 datasheet for details on the vector number of the PDM-PCM interrupt. Refer to the Interrupts chapter on
page 56 for the procedure to configure the interrupt priority, vector address, and enabling/disabling.
The PDM interrupt can be triggered under any of the following events – RX_TRIGGER, RX_NOT_EMPTY, RX_OVERFLOW,
or RX_UNDERFLOW. Table 32-3 lists the trigger conditions and details of these events.

Table 32-3. Interrupt Event Trigger Condition

Interrupt Event Trigger Condition
The PDM Rx FIFO has more entries than the value specified in the TRIGGER_LEVEL field in the PDM_RX-
RX_TRIGGER _FIFO_CTL register. At least (TRIGGER_LEVEL + 1) words can be read from the PDM_RX_FIFO_RD reg-
ister in the interrupt service routine.
RX_NOT_EMPTY The PDM Rx FIFO has at least one word that can be read from the PDM_RX_FIFO_RD register.
The PDM Rx FIFO content is overwritten by the PDM-PCM converter due to the number of unread words
exceeding the 256 word buffer capacity. The output PCM data after the overflow condition is discarded and
RX_OVERFLOW not transferred to the FIFO. This event can be used to detect bandwidth constraints in the end application
due to DMA or the interrupt used for data transfer not getting the required priority for executing the data
transfers.
Attempt to read from an empty PDM Rx FIFO. This can happen due to incorrect configuration of the DMA or
RX_UNDERFLOW
the interrupt service routine code used to do the data transfer.

Each of the interrupt events can be individually enabled or disabled to generate the interrupt condition. The
PDM_INTR_MASK register is used to enable the required events by writing ‘1’ to the corresponding bit.
Irrespective of the INTR_MASK settings, if any event occurs, the corresponding event status bit will be set by the hardware in
the PDM_INTR register. The PDM_INTR_MASKED register is the bitwise AND of the PDM_INTR_MASK and PDM_INTR
registers. The final PDM interrupt signal is the logical OR of all the bits in the PDM_INTR_MASKED register. So only those
events that are enabled in the PDM_INTR_MASK register are propagated as interrupt events to the interrupt controller.
Interrupt events can also be triggered in software by writing to the corresponding bits in PDM_INTR_SET register.
Figure 32-5 illustrates the interrupt signal generation from the PDM-PCM block as explained above. Only the RX_TRIGGER
interrupt generation is highlighted in the figure; the remaining interrupt events also follow the same generation logic.

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 PDM-PCM Converter

Figure 32-5. PDM Interrupt Signal Generation

PDM_INTR_MASKED.RX_TRIGGER
(Register bit)
PDM_INTR.RX_TRIGGER
RX_TRIGGER
(Register bit)
(Hardware event signal)
OR AND interrupt_pdm
PDM_INTR_MASK.RX_TRIGGER (To interrupt controller)
PDM_INTR_SET.RX_TRIGGER OR
(Register bit)
(Register bit, Software triggered event)

Other interrupt Trigger events

(RX_OVERFLOW etc)
(PDM_INTR & PDM_INTR_MASK) PDM_INTR_MASKED.xxx
(Register bits)

In the interrupt service routine (ISR) corresponding to the configured to a value between 64 sample periods and 512
interrupt vector number of interrupt_pdm, the sample periods using the S_CYCLES bits in the
PDM_INTR_MASKED register should be read to know the PDM_MODE_CTL register. So the STEP_SEL and
events that triggered the interrupt event. Multiple events can S_CYCLES bit settings together determine the rate at which
trigger the interrupt because the final interrupt signal is the PGA gain or the soft mute transitions take effect.
logical OR output of the events. The ISR should do the tasks
corresponding to each interrupt event that was triggered. At 32.2.9 Soft Mute
the end of the ISR, the value read in the
PDM_INTR_MASKED register earlier should be written to The PDM-PCM contains a built-in software-controlled mute
the PDM_INTR register to clear the bits whose interrupt function that digitally attenuates signals to imperceptible
events were processed in the ISR. A dummy read of the levels or zero. When mute function is enabled by setting the
PDM_INTR register should be done for the earlier register SOFT_MUTE bit in the PDM_CTL register, the
write to PDM_INTR to take effect. corresponding PCM output is decreased from current level
to mute state through predefined granular gain step per time
All of the interrupt event bits in PDM_INTR register will constant transition. The STEP_SEL bit setting determines
continue to indicate the event condition regardless of the the gain step and the S_CYCLES bits determine the time
true state until that bit is cleared (for example, when set, the constant. During soft-mute, the block is still ON and the
RX_OVERFLOW bit will continue to indicate an PCM data streaming is operational; the DMA or CPU-based
OVERFLOW state until the RX_OVERFLOW bit is cleared data transfer also happens as usual. Only the PCM output
regardless of the true state of the FIFO. A mere FIFO read level is muted. When mute function is disabled by setting
of the FIFO will not clear the RX_OVERFLOW bit.). Unless SOFT_MUTE = 0, the mute function is OFF and the PDM-
the PDM_INTR bits that are used to generate the interrupt PCM returns to normal operation where output signal level
are not cleared by writing ‘1’ to the PDM_INTR bits, the goes up to normal with current PGA gain.
interrupt signal will always be high.
32.2.10 Word Length and Sign Bit
32.2.7 Digital Volume Gain
Extension
The PDM-PCM converter supports independent digital
volume control on the left/right channels with a range from – The PCM output word length can be configured for either
12.5 dB to +10.5 dB in steps of 1.5 dB. It is programmed by 16-bits, 18-bits, 20-bits, or 24-bits using WORD_LEN bits in
configuring the PGA_R and PGA_L bits in the PDM_CTL the PDM_DATA_CTL register. Irrespective of the word
register. PGA gain may be changed on the fly during normal length setting, the PCM output is always read from the FIFO
operation, or as a one-time setting before starting the PDM- data buffer register (PDM_RX_FIFO_RD) as a 32-bit value.
PCM conversion process. The unused most significant bits in the 32-bit value can
either be sign extended or extended by ‘0’ by using the
BIT_EXTENSION bit in the PDM_DATA_CTL register.
32.2.8 Smooth Gain Transition
To reduce zipper or clip noise during on-the-fly gain 32.2.11 High-Pass Filter
transition or during soft mute operation, a built-in volume
smoother is implemented with fine gain steps and fine time The PDM-PCM converter has a final stage high-pass filter
steps that enable soft ramp up or ramp down of the volume (HPF) that blocks DC offset and low-frequency noise in
levels. Two fine gain options of 0.13 dB and 0.26 dB step signal band. The HPF is enabled when the HPF_EN_N bit in
sizes are available. The fine gain is set by the STEP_SEL the PDM_MODE_CTL register is zero, and disabled when
bit in the PDM_CTL register. In addition to the fine gain the HPF_EN_N bit is 1.
steps, a time step is available for the fine gain change in
terms of the number of sample cycles. The time step can be

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 PDM-PCM Converter

The filter response for HPF is characterized as: 4. Configure the Rx FIFO trigger level setting by writing to
–1 the TRIGGER_LEVEL bits in the PDM_RX_FIFO_CTL
1–z register. The CLEAR and FREEZE bits in PDM_RX_FI-
H  z  = -----------------------------------------------------------
– HPF_GAIN – 1
-
1 – 1 – 2 z FO_CTL are not set for normal operation.
5. Configure the events that must generate the interrupt by
The HPF operates at the final PCM output sampling rate.
setting the corresponding bits in the PDM_INTR_MASK
HPF_GAIN is a 4-bit gain configuration setting in the
register, and clearing the remaining bits.
PDM_MODE_CTL register. In default mode, HPF_GAIN =
0xB, so the HPF can be formulated by polynomial: 6. Configure the interrupt PDM interrupt vector and enable
the interrupt vector. See the Interrupts chapter on
–1
1–z page 56 for details.
H  z  = -----------------------------------
–1
-
1 – 0.99951z 7. If a DMA-based data transfer is required, connect the
PDM DMA trigger signal (tr_pdm_rx_req) to the trigger
The HPF_GAIN setting can be tuned to adjust HPF cutoff input of the required DMA channel. See the Trigger Mul-
corner frequency for better system configuration. tiplexer Block chapter on page 294 for details on how to
connect to the DMA channel trigger input. Configure the
32.2.12 Enable/Disable Streaming DMA channel as required - the source address of the
DMA descriptor is PDM_RX_FIFO_RD register with the
The PDM-PCM conversion process can be dynamically source address increment feature disabled and the
enabled/disabled by using the STREAM_EN bit in the source data length is word type (32-bits). The DMA
PDM_CMD register. channel can be used to transfer (TRIGGER_LEVEL + 1)
words from the PDM_RX_FIFO_RD register whenever
32.2.13 Power Modes the trigger signal becomes high. The destination address
configuration depends on the application requirements.
The PDM-PCM can operate in Active and Sleep CPU See the DMA Controller (DW) chapter on page 91 for
modes while in LP or ULP system power modes. It is not details on DMA channel configuration.
operational in system Deep Sleep or Hibernate power
modes. When the device transitions from Deep Sleep/ 8. Enable the DMA trigger signal generation by setting the
Hibernate power modes to the LP/ULP power modes, the RX_REQ_EN bit in the PDM_TR_CTL register.
non-retention registers lose their previous configuration
values. So the non-retention registers must be appropriately 32.3.2 Interrupt Service Routine (ISR)
configured before enabling the PDM-PCM again for LP/ULP Configuration
mode operation. One option is to store the non-retention
register values in SRAM before entering Deep Sleep/ The code for the PDM interrupt service routine should have
Hibernate modes. When returning to the LP/ULP modes, the the following flow:
SRAM values can be copied to the registers after enabling 1. The events that triggered the interrupt can be found by
the PDM-PCM by setting the ENABLED bit in the PDM_CTL reading the PDM_INTR_MASKED register in the ISR. All
register. Refer to the registers TRM to identify the non- the bits that are set causes the interrupt event. The reg-
retention registers for the PDM. ister value should also be in a variable “var”.
2. For each of the event bits that are set in PDM_IN-
32.3 Operating Procedure TR_MASKED, appropriate application level tasks can be
executed. For example, the RX_TRIGGER event can be
used for CPU-based data transfers if a DMA-based data
32.3.1 Initial Configuration transfer is not used. DMA transfers should use the tr_pd-
m_rx_req trigger signal (by setting the RX_REQ_EN bit
The sequence of steps for initial configuration of the PDM-
in the PDM_TR_CTL register). The DMA trigger should
PCM converter before starting the conversion process is as
not use the RX_TRIGGER interrupt event to reduce
follows:
CPU usage for data transfer. The RX_OVERFLOW
1. Configure the clock dividers and decimation rate in the event can be used to take appropriate counter measures
PDM_CLOCK_CTL register. This register configuration such as giving higher priority to PDM-PCM DMA chan-
should be done before enabling the PDM-PCM con- nel. The RX_UNDERFLOW event typically indicates
verter. If the ENABLED bit in the PDM_CTL register is wrong data transfer logic in the application – either in the
set, it should be cleared before changing the clock con- CPU-based data transfer code or in the DMA channel
figuration. configuration used to transfer data.
2. Enable the block; set the PGA gain and fine gain step 3. After the event conditions have been processed, the
setting as required by writing to the PDM_CTL register. “var” value read from PDM_INTR_MASKED should be
3. Configure the PDM_MODE_CTL and PDM_DATA_CTL written to the PDM_INTR register to clear the events that
registers as required. are set in the register. Due to the buffered write logic, the

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 PDM-PCM Converter

PDM_INTR register should also be read after the write

process to ensure the write process is completed in the
slower peripheral clock domain.

32.3.3 Enabling / Disabling Streaming

The PDM-PCM conversion process starts after the
STREAM_EN bit is set in the PDM_CMD register.
Depending on the application needs, the streaming can be
dynamically started and stopped using the STREAM_EN bit.
Clear the Rx FIFO before starting the streaming process to
reset the read/write pointers and FIFO state. The procedure
to clear the FIFO is to write a ‘1’ to the CLEAR bit in
PDM_RX_FIFO_CTL followed by writing a ‘0’ to the CLEAR
bit. When the CLEAR bit is set, all the data entries in the Rx
FIFO are cleared by resetting the internal read/write
pointers. Read accesses to the PDM_RX_FIFO_RD and
PDM_RX_FIFO_RD_SILENT registers are prohibited when
the CLEAR bit is 1. Therefore, the CLEAR bit should be
cleared before starting the streaming operation.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 449
 33. Universal Serial Bus (USB) Device Mode

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU USB block can act as a USB device that communicates with a USB host. The USB block is available as a
fixed-function digital block in the PSoC 6 MCU. It supports full-speed communication (12 Mbps) and is designed to be compli-
ant with the USB Specification Revision 2.0. USB devices can be designed for plug-and-play applications with the host and
also support hot swapping. This chapter details the PSoC 6 MCU USB block and transfer modes. For details about the USB
specification, see the USB Implementers Forum website.

33.1 Features
The USB in the PSoC 6 MCU has the following features:
■ Complies with USB Specification 2.0
■ Supports full-speed peripheral device operation with a signaling bit rate of 12 Mbps
■ Supports eight data endpoints and one control endpoint
■ Provides shared 512-byte buffer for data endpoints
■ Provides dedicated 8-byte memory for control endpoint (EP0)
■ Supports four types of transfers – bulk, interrupt, isochronous, and control
■ Supports bus- and self-powered configurations
■ Enables USB suspend mode for low power
■ Supports three types of logical transfer modes:
❐ No DMA mode (Mode 1)
❐ Manual DMA mode (Mode 2)
❐ Automatic DMA mode (Mode 3)
■ Supports maximum packet size of 512 bytes using Mode 1 and Mode 2, and maximum packet size of 1023 bytes for iso-
chronous transfer using Mode 3
■ Provides integrated 22- USB termination resistors on D+ and D– lines, and 1.5-k pull-up resistor on the D+ line
■ Supports USB 2.0 Link Power Management (LPM)
■ Can be configured using the USB Device Configurator available with the ModusToolbox software

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 450
 Universal Serial Bus (USB) Device Mode

33.2 Architecture
Figure 33-1 illustrates the device architecture of the USB block in PSoC 6 MCUs. It consists of the USB Physical Layer (USB
PHY), Serial Interface Engine (SIE), and the local 512-byte memory buffer.
Figure 33-1. USB Device Block Diagram
USB Block

Arbiter
CPU/DMA CPU/DMA
Interface Subsystem
512 Bytes Memory
SRAM Interface
Arbiter
Logic

SIE
Interface

SIE

USB PHY

D+ D- VBUS

33.2.1 USB Physical Layer (USB PHY) 33.2.3 Arbiter

The USB PHY allows physical layer communication with the The Arbiter handles access of the SRAM memory by the
USB host through the D+, D–, and VBUS pins. It handles endpoints. The SRAM memory can be accessed by the
the differential mode communication with the host, VBUS CPU, DMA, or SIE. The arbiter handles the arbitration
detection, and monitoring events such as SE0 on the USB between the CPU, DMA, and SIE. The arbiter consists of the
bus. following blocks:
■ SIE Interface Module
33.2.2 Serial Interface Engine (SIE) ■ CPU/DMA Interface
The SIE handles the decoding and creating of data and con- ■ Memory Interface
trol packets during transmit and receive. It decodes the USB
■ Arbiter Logic
bit streams into USB packets during receive, and creates
USB bit streams during transmit. The following are the fea- The arbiter registers are used to handle the endpoint config-
tures of the SIE: urations, read address, and write address for the endpoints.
■ Conforms to USB Specification 2.0 It also configures the logical transfer type required for each
endpoint.
■ Supports one device address
■ Supports eight data endpoints and one control endpoint 33.2.3.1 SIE Interface Module
■ Supports interrupt trigger events for each endpoint This module handles all the transactions with the SIE. The
■ Integrates an 8-byte buffer in the control endpoint SIE reads data from the SRAM memory and transmits to the
host. Similarly, it writes the data received from the host to
The registers for the SIE are mainly used to configure the the SRAM memory. These requests are registered in the
data endpoint operations and the control endpoint data buf- SIE Interface module and are handled by this module.
fers. This block also controls the interrupt events available
for each endpoint.

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 Universal Serial Bus (USB) Device Mode

33.2.3.2 CPU/DMA Interface Block accuracy of ±0.25%. In the PSoC 6 MCU, CLK_HF3 is the
clock source. The USB device block also requires a 100-kHz
This module handles all transactions with the CPU and peripheral clock for USB bus reset timing. The required USB
DMA. The CPU requests for reads and writes to the SRAM clock can be generated using one of the following clocking
memory for each endpoint. These requests are registered in schemes:
this interface and are handled by the block. When the DMA
is configured, this interface is responsible for all transactions ■ IMO (trimmed with USB) -> PLL -> CLK_HF3
between the DMA and USB. The block supports the DMA ■ ECO (with the required accuracy) -> FLL -> CLK_HF3
request line for each data endpoint. The behavior of the ■ ECO (with the required accuracy) -> PLL -> CLK_HF3
DMA depends on the type of logical transfer mode config-
ured in the configuration register. ■ Use external clock (EXTCLK) with the required accuracy

33.2.3.3 Memory Interface 33.3.2 USB PHY

The memory interface is used to control the interface The USB includes the transmitter and receiver (transceiver),
between the USB and SRAM memory unit. The maximum which corresponds to the USB PHY. Figure 33-2 shows the
memory size supported is 512 bytes organized as 256 × 16- PHY architecture. The USB PHY also includes the pull-up
bit memory unit. This is a dedicated memory for the USB. resistor on the D+ line to identify the device as full-speed
The memory access can be requested by the SIE or by the type to the host. The PHY integrates the 22- series termi-
CPU/DMA. The SIE Interface block and the CPU/DMA Inter- nation resistors on the USB line. The signal between the
face block handle these requests. USB device and the host is a differential signal. The receiver
receives the differential signal from the host and converts it
33.2.3.4 Arbiter Logic to a single-ended signal for processing by the SIE. The
transmitter converts the single-ended signal from the SIE to
This is the main block of the arbiter. It is responsible for arbi- the differential signal, and transmits it to the host. The differ-
trations for all the transactions that happen in the arbiter. It ential signal is given to the upstream devices at a nominal
arbitrates the CPU, DMA, and SIE access to the memory voltage range of 0 V to 3.3 V.
unit and the registers. This block also handles memory man-
agement, which is either ‘Manual’ or ‘Automatic’. In Manual
memory management, the read and write address manipu-
33.3.2.1 Power Scheme
lations are done by the firmware. In Automatic management, The USB PHY is powered by the VBUS power pad of the
all the memory handling is done by the block itself. This PSoC 6 MCU. The VBUS pad can be driven either by the
block takes care of the buffer size allocation. It also handles host VBUS (bus-powered) or an external power supply (self-
common memory area. This block also handles the interrupt powered).
requests for each endpoint.
The USB PHY needs a nominal voltage of 3.3 V for its com-
munication with the host.
33.3 Operation
33.3.1 USB Clocking Scheme
The USB device block should be clocked at 48 MHz with an
Figure 33-2. USB PHY Architecture

Bus (Host) powered

VDDUSB or Self Powered

PSoC 6 MCU GPIO Mode

USB D+ Pull Up
Logic
Enable Logic

1.5 K
ten 22  D+
td Transmitter Upstream
dpi Logic D- Host/Hub
dmi
22 
rd
dpo Receiver
dmo Logic
rse0

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 Universal Serial Bus (USB) Device Mode

33.3.2.2 VBUS Detection and the response when a sub PID other than the LPM
token is received from the host.
USB devices can either be bus-powered (power sourced
from the host) or self-powered (power sourced from an ■ The LPM_STAT register stores the values of the Best
external power supply). The VDDUSB power pad pin pow- Effort Service Latency (BESL) and the remote wakeup
ers the USB PHY and USB I/Os (D+ and D– pins). The pres- feature as sent by the host. The firmware should read
ence of VBUS can be detected using the following steps: this register on the LPM interrupt event and enter the
1. Enable the interrupt on VDDUSB power pad. For this appropriate low-power mode (Deep Sleep or Sleep)
write ‘1’ to the VDDIO_ACTIVE[5] bit of VDD_IN- based on the BESL value from the host.
TR_MASK register.
2. VDDIO_ACTIVE[5] bit of the supply detection interrupt 33.3.3 Endpoints
register (VDD_INTR) is set to ‘1’ whenever a change to The SIE and arbiter support eight data endpoints (EP1 to
supply is detected. Clear the interrupt cause by writing EP8) and one control endpoint (EP0). The data endpoints
‘1’ to the bitfield. share the SRAM memory area of 512 bytes. The endpoint
3. Check the status of the VDD_ACTIVE[5] bit of the exter- memory management can be either manual or automatic.
nal power supply detection register (VDD_ACTIVE). The The endpoints are configured for direction and other config-
uration using the SIE and arbiter registers. The endpoint
bit is set to ‘1’ when there is supply and ‘0’ when there is
read address and write address registers are accessed
no supply. through the arbiter.

33.3.2.3 USB D+ Pin Pull-up Enable Logic The endpoints can be individually made active. In the Auto
Management mode, the register EP_ACTIVE is written to
When a USB device is self-powered, the USB specification control the active state of the endpoint. The endpoint activa-
warrants that the device enable the pull-up resistor on its D+ tion cannot be dynamically changed during runtime. In Man-
pin to identify itself as a full-speed device to the host. When ual Memory Management mode, the firmware decides the
the host VBUS is removed, the device should disable the memory allocation, so it is not required to specify the active
pull-up resistor on the D+ line to not back power the host. endpoints. The EP_ACTIVE register is ignored during the
The USB PHY includes an internal 1.5-k pull-up resistor on manual memory management mode. The EP_TYPE regis-
the D+ line to indicate to the host that the PSoC 6 MCU is a ter is used to control the transfer direction (IN, OUT) for the
full-speed device. The pull-up resistor can be enabled or endpoints. The control endpoint has separate eight bytes for
disabled by configuring the DP_UP_EN bit in the its data (EP0_DR registers).
USBLPM_POWER_CTRL register.
33.3.4 Transfer Types
33.3.2.4 Transmitter and Receiver Logic
The PSoC 6 MCU USB supports full-speed transfers and is
The transceiver block transmits and receives USB differen- compliant with the USB 2.0 specification. It supports four
tial signals with an upstream device, and includes the USB types of transfers:
D+ pull-up resistor used to maintain an idle state on the bus.
Output data is differentially transmitted to upstream devices ■ Interrupt Transfer
at a nominal voltage of 3.3 V. The differential inputs ■ Bulk Transfer
received from upstream devices are converted into single- ■ Isochronous Transfer
ended data and sent to the core logic at a nominal voltage of
1.8 V. The D+ and D– pins are terminated with 22- resis- ■ Control Transfer
tors to meet the USB impedance specification. For further details about these transfers, refer to the USB
2.0 specification.
33.3.2.5 GPIO Mode Logic
The D+ and D– pins can be used either as GPIO pins or 33.3.5 Interrupt Sources
USB I/O pins. This is controlled by the IOMODE bit of the
USBDEV_USBIO_CR1 register. This bit should be set HIGH The USB device block generates 14 interrupts to the CPU.
for GPIO functionality and LOW for USB operation. These interrupts are mapped to three general-purpose
interrupt lines – INTR_LO, INTR_MED, and INTR_HI. Each
of these three interrupt lines has an associated status
33.3.2.6 Link Power Management (LPM) register, which identifies the cause of the interrupt event.
The USB PHY supports link power management (LPM), These are the USBLPM_INTR_CAUSE_LO,
which is similar to the suspend mode, but has transitional USBLPM_INTR_CAUSE_MED, and
latencies in tens of microseconds between power states, USBLPM_INTR_CAUSE_HI registers. The routing of these
compared to the greater than 20 ms latency associated with interrupts is controlled by the USBLPM_INTR_LVL_SEL
suspend/resume modes. For more details on LPM, refer to register fields.
the USB 2.0 specification. The following features are sup- The following events generate an interrupt on one of the
ported for LPM. three interrupt lines:
■ The LPM_CTL register should be configured to enable/ ■ USB start of frame (SOF) event
disable LPM, type of response when LPM is enabled,

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 Universal Serial Bus (USB) Device Mode

■ USB bus reset event ■ Successful completion of an IN/OUT transfer

■ Eight data endpoint (EP1 – EP8) interrupt events ■ NAK-ed IN/OUT transaction if the corresponding
■ Control endpoint (EP0) interrupt event NAK_INT_EN bit in the SIE_EPx_CR0 register is set
■ Link power management (LPM) event ■ When there is an error in the transaction, the
ERR_IN_TXN bit in the SIE_EPx_CR0 register is set
■ Resume event
and interrupt is generated.
■ Arbiter Interrupt event
■ If the STALL bit in SIE_EPx_CR0 is set, then stall events
can generate interrupts. This stall event can occur if an
33.3.5.1 USB Start of Frame (SOF) Event OUT packet is received for an endpoint whose mode bits
The SOF interrupt is generated upon receiving an SOF in SIE_EPx_CR0 are set to ACK_OUT or if an IN packet
packet from the USB host. The SOF interrupt is enabled is received with mode bits set to ACK_IN.
using the SOF_INTR_MASK bitfield in the USBLPM_IN-
TR_SIE_MASK register. 33.3.5.4 Control Endpoint Interrupt Event
■ The SOF interrupt status is reflected in the SOF_INTR
The interrupt event corresponding to the control endpoint
status bit in the USBLPM_INTR_SIE status register. (EP0) is generated under the following events:
■ The SOF interrupt status is also available in the ■ Successful completion of an IN/OUT transfer
SOF_INTR_MASKED bit of the
USBLPM_INTR_SIE_MASKED register – this bit is the ■ When a SETUP packet is received on the control end-
logical AND of the corresponding SOF bits in the point
USBLPM_INTR_SIE_MASK register and the The EP0 interrupt is setup using the EP0_INTR_SET bit of
USBLPM_INTR_SIE register. the USBLPM_INTR_SIE_SET register.
■ If there is no SOF interrupt for 3 ms, the USB device
goes into SUSPEND state.
33.3.5.5 Link Power Management (LPM)
Event
33.3.5.2 USB Bus Reset Event Generated whenever the LPM token packet is received. The
The USB bus reset interrupt is generated when a USB bus LPM interrupt is enabled by setting the LPM_INTR_MASK
reset condition occurs. The bus reset interrupt is enabled by bit in the USBLPM_INTR_SIE_MASK register. The LPM
setting the BUS_RESET_INTR_MASK bit in the interrupt status is reflected in the LPM_INTR status bit in the
USBLPM_INTR_SIE_MASK register. USBLPM_INTR_SIE status register.
■ The bus reset interrupt status is reflected in the The LPM interrupt status is also available in the LPM_IN-
TR_MASKED bit of the USBLPM_INTR_SIE_MASKED reg-
BUS_RESET_INTR bit in the USBLPM_INTR_SIE sta-
ister; this bit is the logical AND of the corresponding LPM
tus register. bits in the USBLPM_INTR_SIE_MASK and USBLPM_IN-
■ The bus reset interrupt status is also available in the TR_SIE registers.
BUS_RESET_INTR_MASKED bit of the The firmware needs to read the USBLPM_LPM_STAT reg-
USBLPM_INTR_SIE_MASKED register – this bit is the ister to read the BESL remote wakeup values and appropri-
logical AND of the corresponding bus reset bits in the ately enter the desired low-power mode. Enter the low-
USBLPM_INTR_SIE_MASK register and the power mode in the main code. The exit from LPM is identical
USBLPM_INTR_SIE register. to the resume event wakeup in the case of suspend mode.
■ The SIE logic triggers the counter to start running on the
divided version of CLK_PERI when an SE0 condition is
33.3.5.6 RESUME Interrupt
detected on the USB bus. When the counter reaches the The RESUME interrupt is asserted by the USB block when it
count value configured in the USBDEV_BUS_RST_CNT detects ‘0’ on the DP pad. The RESUME interrupt is enabled
register, the bus reset interrupt is triggered. Typically, by setting the RESUME_INTR_MASK bitfield of the
divided CLK_PERI is set to 100 kHz and USB- USBLPM_INTR_SIE_MASK register.
DEV_BUS_RST_CNT is set to ‘10’. ■ The RESUME interrupt status is reflected in the
RESUME_INTR status bit in the USBLPM_INTR_SIE
33.3.5.3 Data Endpoint Interrupt Events status register.
These are eight interrupt events corresponding to each data ■ The RESUME interrupt status is also available in the
endpoint (EP1-EP8). Each of the endpoint interrupt events RESUME_INTR_MASKED bit of the USBLPM_IN-
can be enabled/disabled by using the corresponding bit in TR_SIE_MASKED register – this bit is the logical AND of
the USBDEV_SIE_EP_INT_EN register. The interrupt sta- the corresponding RESUME bits in the USBLPM_IN-
tus of each endpoint can be known by reading the USB- TR_SIE_MASK register and the USBLPM_INTR_SIE
DEV_SIE_EP_INT_SR status register. An endpoint whose register.
interrupt is enabled can trigger the interrupt on the following
events: The RESUME interrupt is an Active mode interrupt and not
available in Deep Sleep or Hibernate mode.

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 Universal Serial Bus (USB) Device Mode

33.3.5.7 Arbiter Interrupt Event an IN token is received for that endpoint, it cannot
use the common buffer area, hence resulting in an
The arbiter interrupt can arise from five possible sources. overflow of data. The possible causes of this buffer
Each interrupt source is logically ANDed with its corre-
overflow can be incorrect programming of either the
sponding ENABLE bit and the results are logically ORed to
result in a single arbiter interrupt event. DMA transfer descriptor transfer size or the USB-
DEV_BUF_SIZE register.
The arbiter interrupt event can arise under any of the follow-
ing five scenarios: ❐ In an OUT endpoint, the dedicated buffer can over-
flow if two OUT transactions occur consecutively.
■ DMA Grant
The data from the previous transaction is still present
■ IN Buffer Full in the common area and the current ongoing trans-
■ Buffer Overflow action fills up the OUT endpoint’s dedicated buffer
■ Buffer Underflow space and overflows. The possible causes of this
overflow can be the overall DMA bandwidth con-
■ DMA Termin straint due to other DMA transactions or reduced
size of the dedicated OUT buffer size.
DMA Grant
■ Common area data overflow
This event is applicable in Mode 2 or Mode 3. (See Logical
❐ In an IN endpoint, the common area overflow occurs
Transfer Modes on page 456 for details on DMA modes).
This event is triggered when the DMA controller pulses the when the DMA transfer writes a larger number of
Burstend signal corresponding to that endpoint, for which a bytes than the space available in the common area.
DMA request had been raised to the DMA controller earlier. This situation may arise due to incorrect
The request may have been either a manual DMA request programming of either the DMA transfer descriptor
or an automatic arbiter DMA request. A common grant sta- transfer size or the USBDEV_DMA_THRESH and
tus exists for both modes of requests. This grant status indi- USBDEV_DMA_THRESH_MSB registers.
cates completion of the DMA transaction. This status
❐ In an OUT endpoint, the common area overflow
indication can be used by firmware to determine when the
next manual DMA request can be raised. Multiple requests occurs when the data written to the common area
raised for the same endpoint before the DMA grant status is has not yet been read and new data overwrites the
set will be dropped by the block. Only the first of multiple existing data.
requests will be transmitted to DMA controller.
Buffer Underflow
IN Buffer Full
This event is applicable only in the Cut Through mode
This event status can occur in any of the DMA modes (Mode (Mode 3). This underflow condition can occur only for an IN
1, 2, or 3) and is applicable only for IN endpoints. endpoint. The underflow condition can occur either in the
dedicated buffer space or common buffer space. The under-
■ Store and Forward Mode (Modes 1 and 2): This status is
flow condition on the dedicated buffer space can either be
set when the entire packet data is transferred to the local due to the reduced dedicated IN buffer size or DMA band-
memory. The check is that data written for the particular width constraint. The underflow condition can occur on the
endpoint is equal to the programmed byte count for that common buffer space due to DMA bandwidth constraint
endpoint in the USBDEV_SIE_EPx_CNT0 and USB- and/or lower DMA channel priority.
DEV_SIE_EPx_CNT1 registers.
■ Cut Through Mode (Mode 3): In this mode, the IN buffer DMA Termin
full status is set when the IN endpoint’s dedicated buffer This status is set when USBDEV generates a dma_termin
is filled with the packet data. The size of this buffer is signal to indicate the total programmed/ received bytes that
determined by the value programmed in bits [3:0] of the are written/read by the DMA controller. This status indication
USBDEV_BUF_SIZE register. This status indication can can be used by the firmware to reprogram the IN/OUT end-
be used to determine when the mode value in the USB- point for the next transfer. For an OUT endpoint, this indi-
DEV_SIE_EPx_CR0 register can be programmed to cates that the OUT packet data is available in the system
acknowledge an IN token for that endpoint. memory for further processing by the application.

Buffer Overflow 33.3.6 DMA Support

This event status is active only in the Cut Through Mode Each of the eight data endpoints has one DMA channel
(Mode 3). The following conditions can cause this bit to be available to transfer data between the endpoint buffer and
set: the SRAM memory. The USB generates the DMA request
signals (usb.dma_req[7:0]) to the respective DMA channels
■ Data overflow on the endpoint dedicated buffer space
to initiate the data transfer for the endpoint. This goes to the
❐ In an IN endpoint, the dedicated buffer can overflow Trigger Group 13 multiplexer as input triggers that can be
if the DMA transfer writes a larger number of bytes routed to one of the trigger inputs of the DMA block. The
than the space available in the dedicated buffer. Until Burstend signals from the DMA channel to the correspond-

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 Universal Serial Bus (USB) Device Mode

ing endpoint is routed using the Trigger Group 9 multiplexer. and from the SRAM memory unit for each endpoint). It does
For more details, see the DMA Controller (DW) chapter on not represent the transfer methods between the device and
page 91 and Trigger Multiplexer Block chapter on page 294. the host (the transfer types specified in the USB 2.0 specifi-
cation).
The USB supports two basic types of transfer modes:
33.4 Logical Transfer Modes
■ Store and Forward mode
The USB block in PSoC 6 MCUs supports two types of logi- ❐ Manual Memory Management with No DMA Access
cal transfers. The logical transfers can be configured using
(Mode 1)
the register setting for each endpoint. Any of the logical
transfer methods can be adapted to support the three types ❐ Manual Memory Management with Manual DMA
of data transfers (Interrupt, Bulk, and Isochronous) men- Access (Mode 2)
tioned in the USB 2.0 specification. The control transfer is ■ Cut Through mode
mandatory in any USB device.
❐ Automatic Memory Management with Automatic
The logical transfer mode is a combination of memory man-
DMA Access (Mode 3)
agement and DMA configurations. The logical transfer
modes are related to the data transfer within the USB (to Table 33-1 gives a comparison of the two transfer modes.

Table 33-1. USB Transfer Modes

Feature Store and Forward Mode Cut Through Mode
SRAM Memory Usage Requires more memory Requires less memory
SRAM Memory Manage-
Manual Auto
ment
Each endpoint is allocated a lesser share of memory auto-
512 bytes of SRAM shared between endpoints. matically by the block. The remaining memory is available
SRAM Memory Sharing
Sharing is done by firmware. as “common area.” This common area is used during the
transfer.
Memory filled with data only when SRAM IN command is
Entire packet present in SRAM memory before received. Data is given to host when enough data is avail-
IN Command
the IN command is received. able (based on DMA configuration). Does not wait for the
entire data to be filled.
Waits only for enough bytes (depends on DMA configura-
Entire packet is written to SRAM memory on OUT
tion) to be written in SRAM memory. When enough bytes
OUT Command command. After entire data is available, it is cop-
are present, it is immediately copied from SRAM memory to
ied from SRAM memory to the USB device.
the USB device.
Data is transferred when all bytes are written to Data is transferred when enough bytes are available. It
Transfer of Data
the memory. does not wait for the entire data to be filled.
No DMA mode
Types Based on DMA Only Auto DMA mode
Manual DMA mode
Supported Transfer Types Ideal for interrupt and bulk transfers Ideal for Isochronous transfer

Every endpoint has a set of registers that need to be handled during the modes of operation, as detailed in Table 33-2.

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 Universal Serial Bus (USB) Device Mode

Table 33-2. Endpoint Registers

Register Comment Content Usage
Endpoint Write This register indicates the SRAM location to which the data in
USBDEV_ARB_RWx_WA Address of the SRAM
Address Register the data register is to be written.
Endpoint Read This register indicates the SRAM location from which the data
USBDEV_ARB_RWx_RA Address of the SRAM
Address Register must be read and stored to the data register.
Data register is read/written to perform any transaction.
IN command: Data written to the data register is copied to the
SRAM location specified by the WA register. After write, the
WA value is automatically incremented to point to the next
Endpoint Data Regis- memory location.
USBDEV_ARB_RWx_DR 8-Bit Data
ter OUT command: Data available in the SRAM location pointed
by the USBDEV_ARB_RWx_RA register is read and stored to
the DR. When the DR is read, the value of USBDEV_ARB_R-
Wx_RA is automatically incremented to point to the next
SRAM memory location that must be read.
Holds the number of bytes that can be transferred.
IN command: Holds the number of bytes to be transferred to
host.
USBDEV_SIE_EPx-
Endpoint Byte Count OUT command: Holds the maximum number of bytes that
_CNT0 and USB- Number of Bytes
Register can be received. The firmware programs the maximum num-
DEV_SIE_EPx_CNT1
ber of bytes that can be received for that endpoint. The SIE
updates the register with the number of bytes received for the
endpoint.
Controls how the USB device responds to the USB traffic and
“Mode” bits in USB-
Mode Values Response to the Host the USB host. Some examples of modes are ACK, NAK, and
DEV_SIE_EPx_CR0
STALL.

In Manual memory management, the endpoint read and endpoint write address registers are updated by the firmware. So the
memory allocation can be done by the user. The memory allocation decides which endpoints are active; that is, you can
decide to share the 512 bytes for all the eight endpoints or a lesser number of endpoints.
In Automatic memory management, the endpoint read and endpoint write address registers are updated by the USB block.
The block assigns memory to the endpoints that are activated using the USBDEV_EP_ACTIVE register. The size of memory
allocated depends on the value in the USBDEV_BUF_SIZE register. The remaining memory, after allocation, is called the
common area memory and is used for data transfer.
In all of these modes, either the 8-bit endpoint data register or the 16-bit endpoint data register can be used to read/write to
the endpoint buffer. While transferring data to the 16-bit data registers, ensure that the corresponding SRAM memory
address locations are also 16-bit aligned.
In the following text, the algorithm for the IN and OUT transaction for each mode is discussed. An IN transaction is when the
data is read by the USB host (for example, PC). An OUT transaction is when the data is written by the USB host to the USB
device. The choice of using the DMA and memory management can be configured using the USBDEV_ARB_EPx_CFG reg-
ister.

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 Universal Serial Bus (USB) Device Mode

33.4.1 Manual Memory Management with No DMA Access

All operations in this mode are controlled by the CPU and works in a store-and-forward operation mode. An entire packet is
transferred to the memory and a mode bit (such as ACK IN or ACK OUT) is set by the CPU. The SIE responds appropriately
to an IN/OUT token received from the host. All memory space management is handled by the CPU.
Figure 33-3. No DMA Access IN Transaction Figure 33-4. No DMA Access OUT Transaction
Set Base address to WA Set Base address to WA

Set Packet size in the Endpoint byte Set Packet size in the Endpoint byte
count register count register

Set mode in CR0 register

Write to data to Endpoint Data
Register

Wait

No Is OUT Responds automatically

Token Received? with ACK
No Is all data written
to SRAM
Yes
Data received from host
Yes Written to SRAM location WA
WA++
Write to RA register(= initial WA
register)

Is all data
No written to
Set mode in CR0 register SRAM?

Yes

SIE sets mode to NAK. Updates byte count with

Wait actual no. of data received abd sets the data valid
No Is IN bit
Token Received? Responds SIE Data
Automatically Interrupt
With ACK Generated
Yes Write RA value (= initial WA value)
Data register is
Read by the CPU, RA++ is
USB block reads Data stored at RA
automatically done
and transmit to Host.
RA++ USB block reads data at RA
location and writes to data register

No Is all data Is all data

Transmitted? No
Read from
Interrupt SRAM?
Generated
Yes
Yes

Set the mode as NAK for the last End

byte in transfer. Status bit set by
the block

33.4.2 Manual Memory Management with DMA Access

This mode is similar to the No DMA Access except that write/read of packets is performed by the DMA. A DMA request for an
endpoint is generated by setting the DMA_CFG bit in the USBDEV_ARB_EPx_CFG register. When the DMA service is
granted and is done (DMA_GNT), an arbiter interrupt can be programmed to occur. The transfer is done using a single DMA
cycle or multiple DMA cycles. After completion of every DMA cycle, the arbiter interrupt (DMA_GNT) is generated. Similarly,
when all the data bytes (programmed in byte count) are written to the memory, the arbiter interrupt occurs and the IN_BUF_-
FULL bit is set.

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 Universal Serial Bus (USB) Device Mode

Figure 33-5 and Figure 33-6 show the flow charts for manual DMA IN and OUT transactions respectively.
Figure 33-5. Manual DMA IN Transaction
Write WA register
(based on required memory allocation)

Set Packet size in the Endpoint byte

count register

Set the DMA request in

USBDEV_ARB_EPx_CFG register

Value automatically written to

DMA writes data to Endpoint Data the SRAM specified by WA
Register
WA++

Is all data
No written
to SRAM

Yes

Write to RA register(= initial WA

register)

Set mode in CR0 register

Wait
No
Is IN
Token Received? Responds
Automatically
With ACK
Yes

USB block reads Data stored at

RA and transmit to Host.
RA++

No Is all data
Transmitted?
Interrupt
Generated
Yes

Set the mode as NAK for the last

byte in transfer. Status bit set by
the block

End

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 Universal Serial Bus (USB) Device Mode

Figure 33-6. Manual DMA OUT Transaction remaining memory (256 bytes) is left as common area and
is common for all endpoints.
Write WA register
(based on the required memory allocation) In this mode, the memory requirement is less and it is suit-
able for full-speed isochronous transfers up to 1023 bytes.
When an IN command is sent by the host, the device
Set Packet size in the Endpoint byte
count register responds with the data present in the dedicated memory
area for that endpoint. It simultaneously issues a DMA
request for more data for that EP. This data fills up the com-
Set mode in CR0 register mon area. The device does not wait for the entire packet of
data to be available. It waits only for the (USBDEV_DMA_-
THRES_MSB, USBDEV_DMA_THRES) number of data
available in the SRAM memory and begins the transfer from
Wait
the common area.
No Is OUT Responds automatically with
Token Received? ACK Similarly, when an OUT command is received, the data for
the OUT endpoint is written to the common area. When
Yes some data (greater than USBDEV_DMA_THRES_MSB,
USBDEV_DMA_THRES) is available in the common area,
Data received from host
Written to SRAM location WA
the arbiter block initiates a DMA request and the data is
WA++ immediately written to the device. The device does not wait
for the common area to be filled.
This mode requires configuration of the
USBDEV_DMA_THRES and
Is all data
No written to USBDEV_DMA_THRES_MSB registers to hold the number
SRAM? of bytes that can be transferred in one DMA transfer (32
bytes). Similarly, the burst count of the DMA should always
Yes be equal to the value set in the USBDEV_DMA_THRES
registers. Apart from the DMA configuration, this mode also
SIE sets mode to NAK. Updates byte count with
actual no. of data received abd sets the data valid needs the configuration of the USBDEV_BUF_SIZE for the
bit IN and the OUT buffers and the USBDEV_EP_ACTIVE and
SIE Data the USBDEV_EP_TYPE registers.
Interrupt
Generated Each DMA channel has two descriptors and both of them
Write RA value (= initial WA value)
are used in this mode. Each descriptor is considered as a
data chunk of 32 bytes and it executes according to the trig-
ger mechanism. The descriptors are chained and hence 64
Configure DMA request bytes can be transferred without firmware interaction. When
Data register is DMA Grant Arbiter
Read by the CPU, RA++ is Interrupted generated
both descriptors complete the endpoint DMA done interrupt
automatically done and the DMA error interrupt triggers (due to the lack of data
USB block reads data at RA to transfer). The descriptors are updated to advance the
location and writes to data register
source SRAM (IN endpoint) or destination SRAM (OUT end-
point) pointer locations and then enabled again. This
No sequence continues till all data is transferred.
The steps for IN and OUT transactions using automatic
Is all data
Read from DMA mode are shown in Figure 33-7 and Figure 33-8.
SRAM?

Yes

End

33.4.3 Automatic DMA Mode

This is the Automatic memory management mode with auto
DMA access. The CPU programs the initial buffer size
requirement for IN/OUT packets and informs the arbiter
block of the endpoint configuration details for the particular
application. The block then controls memory partitioning and
handling of all memory pointers. During memory allocation,
each active IN endpoint (set by the USBDEV_EP_ACTIVE
and USBDEV_EP_TYPE registers) is allocated a small
amount of memory configured using the USBDEV_BUF_-
SIZE register (32 bytes for each of the eight endpoints). The

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 460
 Universal Serial Bus (USB) Device Mode

Figure 33-7. IN Transaction using Automatic DMA Mode

Set Packet size in the Endpoint byte
count register

Set IN_DATA_RDY for the endpoint in

ARB_EP1_CFG register

This memory location is very limited. The

memory location is filled initially to make sure
the host does not stall when an IN command is Block automatically raises
sent. When an IN command is received the interrupt for DMA
PHUB initiates the copy of data from device to
common area. This initialization would take
Data automatically read and
some time. The data in the end point buffer is
transmitted until the data is copied to the written to SRAM pointed by WA.
common area DMA writes to Data register WA++

No Is the endpoint
Buffer full?
IN_BUF_FULL Interrupt
generated

Yes

Update mode value in the Mode

register

Wait

No Is IN Command
received?

Block automatically sends the

ACK (Configured as Mode
Yes value)

Is the complete
Yes data available No
in the memory

SIE reads data from SRAM (specified Raise a DMA Request

by location RA) and transmits to host

RA++
SIE reads data from SRAM (specified
by location RA) and transmits to host
In the mean time, the PHUB
initiates the transaction. The
Is all data RA++ data from the device is copied to
No
in buffer No the common area. The data
transmitted? from the USB is written to the
SRAM by the DMA
Yes Is all data
in buffer
transmitted?
Set the data valid bits
Yes
Wait

End Is data in Common Area> No

(DMA THRES, DMA THRES MSB)

The process is Yes

continued till all
the data is Initiate PHUB
transferred transfer

Block transfer data available

in Common Area

Set the data valid bits

End

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 461
 Universal Serial Bus (USB) Device Mode

Figure 33-8. OUT Transaction using Automatic DMA Mode

Write maximum bytes to Byte Count register

Program the Mode register for the

endpoint

Wait
No Is OUT
Token Received?

Yes

The DMA writes the received data to the

SRAM in location specified by WA

WA++
No

Is data in
SRAM>(DMA_THRES,DMA_TH
RES_MSB)?

Yes
DMA request is Data in the Data register is read
The process is raised and given to the USB device by
continued till all the DMA. RA is incremented
the data is transferred automatically
USB Block writes the data from
SRAM to the Data register

No

Is all data
from SRAM
copied to device?

Yes

Set the data valid

bits

End

33.4.4 Control Endpoint Logical Transfer

The control endpoint has a special logical transfer mode. It does not share the 512 bytes of memory. Instead, it has a dedi-
cated 8-byte register buffer (USBDEV_EP0_DRx registers). The IN and OUT transaction for the control endpoint is detailed in
the following figures.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 462
 Universal Serial Bus (USB) Device Mode

Figure 33-9. Control Endpoint IN Transaction Figure 33-10. Control Endpoint OUT Transaction
Set the mode bits to ACK Program the mode bits for
the IN token ACK_OUT

No Is SETUP No Is SETUP
token received? token received?

Yes Yes

The block ACKs it The block ACKs it

Generates Interrupt and sets the bit in EP0_CR

Generates Interrupt and sets the bit in EP0_CR register to
register to indicate that SETUP token was received
indicate that SETUP token was received

Read the data valid bit in

Read the status bit and data valid EP0_CNT
bit

No
Is Data Valid?
No
Is Data Valid?

Yes
Yes
Read the EP0_DRx register to find the
type of request
Read the EP0_DRx register to find the
type of request

Update the mode bits to ACK an

OUT token
Copy the required data to the EP0_DRx
registers

Set the data valid bit and the mode bits. No Is OUT
Also update the byte count value Token Received?

Yes

The block stores the received byte to the

No Is IN EP0_DRx registers and ACK the received
Token Received? byte

Yes
Interrupt generated
The block transmits the data from the
EP0_DRx registers

Read the status and data valid bits

The block sets the mode value to NAK all

further IN tokens

Is data No
Valid?
Block generates interrupt on receiving
ACK from host and sets the IN byte
received bit Yes

Set the mode bit to NAK all OUT tokens

till all bytes have been received

No Are all bytes

transferred? No Are all bytes
transferred?

Yes
Yes
End
End

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 463
 Universal Serial Bus (USB) Device Mode

33.5 USB Power Modes

The USB supports two modes of operation:
■ Active mode: In this mode, the USB is powered up and clocks are turned on.
■ Low-power (Deep Sleep) mode: In this mode, all clocks except the low-frequency clock are turned off.
Before entering low-power mode, the firmware should enable the GPIO interrupt (falling edge interrupt) on the D+ pin. The
USB suspend mode can be determined by monitoring the SOF interrupt; this means, if there is no SOF interrupt from the USB
for more than 3 ms, the USB goes into suspend mode and the block can be put into low-power mode by the firmware.
If there is any activity on the USB bus, D+ will be pulled low, which will cause a CPU interrupt. This interrupt can be used to
wake up the USB device.

33.6 USB Device Registers

Name Description
USBDEV_EP0_DR Control endpoint EP0 data register
USBDEV_CR0 USB control 0 register
USBDEV_CR1 USB control 1 register
USBDEV_SIE_EP_INT_EN USB SIE data endpoint interrupt enable register
USBDEV_SIE_EP_INT_SR USB SIE data endpoint interrupt status
USBDEV_SIE_EPx_CNT0 Non-control endpoint count register
USBDEV_SIE_EPx_CNT1 Non-control endpoint count register
USBDEV_SIE_EPx_CR0 Non-control endpoint's control register
USBDEV_USBIO_CR0 USBIO control 0 register
USBDEV_USBIO_CR2 USBIO control 2 register
USBDEV_USBIO_CR1 USBIO control 1 register
USBDEV_DYN_RECONFIG USB dynamic reconfiguration register
USBDEV_SOF0 Start of frame register
USBDEV_SOF1 Start of frame register
USBDEV_OSCLK_DR0 Oscillator lock data register 0
USBDEV_OSCLK_DR1 Oscillator lock data register 1
USBDEV_EP0_CR Endpoint0 control register
USBDEV_EP0_CNT Endpoint0 count register
Endpoint write address value register. Pointer value increments by 1 when
USBDEV_ARB_RWx_WA
accessed by CPU/debugger
USBDEV_ARB_RWx_WA_MSB Endpoint write address value register
Endpoint read address value register. Pointer value increments by 1 when
USBDEV_ARB_RWx_RA
accessed by CPU/debugger
USBDEV_ARB_RWx_RA_MSB Endpoint read address value register
USBDEV_ARB_RWx_DR Endpoint data register
USBDEV_BUF_SIZE Dedicated endpoint buffer size register
USBDEV_EP_ACTIVE Endpoint active indication register
USBDEV_EP_TYPE Endpoint type (IN/OUT) indication register
USBDEV_ARB_EPx_CFG Endpoint configuration register
USBDEV_ARB_EPx_INT_EN Endpoint interrupt enable register
USBDEV_ARB_EPx_SR Endpoint interrupt enable register
USBDEV_ARB_CFG Arbiter configuration register
USBDEV_USB_CLK_EN USB block clock enable register

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 Universal Serial Bus (USB) Device Mode

Name Description
USBDEV_ARB_INT_EN Arbiter interrupt enable register
USBDEV_ARB_INT_SR Arbiter interrupt status register
USBDEV_CWA Common area write address register
USBDEV_CWA_MSB Endpoint read address value register
USBDEV_DMA_THRES DMA burst / threshold configuration register
USBDEV_DMA_THRES_MSB DMA burst / threshold configuration register
USBDEV_BUS_RST_CNT Bus reset count register
USBDEV_MEM_DATA Data register
USBDEV_SOF16 Start of frame register
USBDEV_OSCLK_DR16 Oscillator lock data register
Endpoint write address value register. Pointer value increments by 2 when
USBDEV_ARB_RWx_WA16
accessed by CPU/debugger
Endpoint read address value register. Pointer value increments by 2 when
USBDEV_ARB_RWx_RA16
accessed by CPU/debugger
USBDEV_ARB_RWx_DR16 Endpoint data register
USBDEV_DMA_THRES16 DMA burst / threshold configuration register
USBLPM_POWER_CTL Power control register
USBLPM_USBIO_CTL USB IO control register
USBLPM_FLOW_CTL Flow control register
USBLPM_LPM_CTL LPM control register
USBLPM_LPM_STAT LPM status register
USBLPM_INTR_SIE USB SOF, BUS RESET, and EP0 interrupt status register
USBLPM_INTR_SIE_SET USB SOF, BUS RESET, and EP0 interrupt set register
USBLPM_INTR_SIE_MASK USB SOF, BUS RESET, and EP0 interrupt mask register
USBLPM_INTR_SIE_MASKED USB SOF, BUS RESET, and EP0 interrupt masked register
USBLPM_INTR_LVL_SEL Select interrupt level for each interrupt source register
USBLPM_INTR_CAUSE_HI High-priority interrupt cause register
USBLPM_INTR_CAUSE_MED Medium-priority interrupt cause register
USBLPM_INTR_CAUSE_LO Low-priority interrupt cause register

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 34. Universal Serial Bus (USB) Host

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The USB subsystem in PSoC 6 MCUs can be configured to function as a USB host. The USB host in the PSoC 6 MCU sup-
ports both full-speed (12 Mbps) and low-speed (1.5 Mbps) devices and is designed to be complaint with the USB Specifica-
tion Revision 2.0. This chapter details the PSoC 6 MCU USB and its operations. For details about the USB specification, refer
to the USB Implementers Forum website.

34.1 Features
The USB host in the PSoC 6 MCU has the following features:
■ Automatic detection of device connection or disconnection
■ Automatic detection of full-speed or low-speed transfer
■ Supports USB bus reset function
■ Supports IN, OUT, SETUP. and SOF tokens
■ Supports Bulk, Control, Interrupt, and Isochronous transfer
■ Automatic detection of handshake packet for OUT token and automatic sending of handshake packet for IN token (exclud-
ing STALL)
■ Supports a maximum packet length of up to 256 bytes
■ Supports action against errors (CRC error, toggle error, and timeout)

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 466
 Universal Serial Bus (USB) Host

34.2 Architecture
Figure 34-1. USB Host Block Diagram

Interrupt Interrupt
Signals Control Control / Status Registers
Block

Endpoint Block

Endpoint 1
VDDUSB

USB PHY
Registers
FFs x2
USB Clock Clock Host
(48 MHz) Control Controller D+
System Clock Block FIFO Control Unit
(at least 13 MHz) D-
Endpoint 2
Registers

FFs x2
DREQ
DREQ Control
FIFO Control
Signals

34.2.1 USB Physical Layer (USB PHY) be mapped to any of the three interrupt lines. Each of these
three interrupt lines has a status register to identify the
The USB includes the transmitter and receiver (transceiver), interrupt source. These are the
which corresponds to the USB PHY. This module allows USBHOST_INTR_USBHOST_CAUSE_LO,
physical layer communication with the USB device through USBHOST_INTR_USBHOST_CAUSE_MED, and
the D+, D–, and VDDUSB pins. It handles differential mode USBHOST_INTR_USBHOST_CAUSE_HI,
communication with the device. The USB PHY also includes USBHOST_INTR_USBHOST_EP_CAUSE_LO,
pull-down resistors on the D+ and D– lines. Differential USBHOST_INTR_USBHOST_EP_CAUSE_MED and
signaling is used between the USB host and the device. The USBHOST_INTR_USBHOST_EP_CAUSE_HI registers.
host controller unit receives the differential signal from the
device and converts it to a single-ended signal. While
transmitting, the host controller unit converts the single-
34.2.4 Endpoint n (n=1, 2)
ended signal to the differential signal, and transmits it to the The USB host has two endpoints. The maximum buffer size
device. The differential signal is at a nominal voltage range of endpoint 1 is 256 bytes and that of endpoint 2 is 64 bytes.
of 0 V to 3.3 V. The endpoint buffers are used to send and receive data. If
endpoint 1 is used as the transmitter, endpoint 2 must be
34.2.2 Clock Control Block used as the receiver and vice-versa. The DIR bit of the
USBHOST_HOST_EPn_CTL (n=1, 2) register is used to
This block controls the gated clocks – system clock and configure the endpoint as an IN buffer (DIR=0) or OUT buf-
USB clock. The USB host requires a clock frequency of fer (DIR=1).
48 MHz. USB host compliance requires a clock source with
an accuracy of ±0.25 percent. One way of doing this is to
use Clk_HF[3] sourced from an highly accurate ECO. The
34.2.5 DMA Request (DREQ) Control
PLL can be used to generate the required 48-MHz clock The USB host supports data transfer using DMA. DMA
from the ECO. Refer to the Clocking System chapter on operation is enabled by configuring the USB-
page 242 for details on generation of clock required for USB HOST_HOST_DMA_ENBL register. There are two DMA
operation. transfer modes: Automatic data transfer mode and packet
transfer mode. The DMAE bit of the USB-
34.2.3 Interrupt Control Block HOST_HOST_EPn_CTL (n=1, 2) register is used to set the
mode of DMA transfer. The Host Endpoint Block register
This block controls the interrupts associated with USB host (USBHOST_HOST_EPn_BLK; n=1, 2) sets the total num-
operations. The USB host block has three general-purpose ber of bytes for DMA transfer.
interrupt signals: USBHOST_INTR_USBHOST_LO,
USBHOST_INTR_USBHOST_MED, and
USBHOST_INTR_USBHOST_HI. There are 11 interrupt
trigger events associated with USB host operation that can

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 Universal Serial Bus (USB) Host

34.3 USB Host Operations

To operate the USB as a host, the following settings are required:
■ Enable the pull-down resistors on both D+ and D– pins. To enable the pull-down resistors, set the DP_DOWN_EN bit and
DM_DOWN_EN bit of the power control register (USBLPM_POWER_CTL) to ‘1’.
■ Set both the HOST and ENABLE bits of the Host Control 0 register (USBHOST_HOST_CTL0) to ‘1’.
■ Set the USTP bit of the Host Control 1 register (USBHOST_HOST_CTL1) to ‘0’.
■ Supply the operating clock for USB (48 MHz ± 0.25%). In the PSoC 6 MCU, CLK_HF3 is the clock source. The required
USB clock can be generated using one of the following clocking schemes:
❐ IMO (trimmed with USB) -> PLL -> CLK_HF3
❐ ECO (with the required accuracy) -> PLL -> CLK_HF3
❐ Use external clock (EXTCLK) with the required accuracy.

34.3.1 Detecting Device Connection

When an external USB device is not connected, both the D+ and D– pins are set to logic LOW by the pull-down resistors. In
the unconnected state, CSTAT bit of the USBHOST_HOST_STATUS register is '0' and the TMODE bit is undefined. If an
external USB device is connected, then the CSTAT bit is set to '1'.
When a device is detected, the CNNIRQ bit of the Interrupt USB host (USBHOST_INTR_USBHOST) register is set to '1'. A
device can be detected either by the method of interrupt or by polling. If '1' is set to the CNNIRQM bit of the Interrupt USB
host (USBHOST_INTR_USBHOST_MASK) register, a device connection interrupt occurs. To clear this interrupt, write '1' to
the CNNIRQ bit of USBHOST_INTR_USBHOST register. When detecting a device connection by polling, set the CNNIRQM
bit of the USBHOST_INTR_USBHOST_MASK register to '0' and check when the CNNIRQ bit of
USBHOST_INTR_USBHOST changes to '1'.
Figure 34-2. Device Connection

USB DP
USB DM
CSTAT bit of 2.5us or more
HOST_STATUS

34.3.2 Obtaining Transfer Speed of the USB Device

To obtain the possible transfer speed of the remote USB device after detecting a connection, check the value of the TMODE
bit of the USBHOST_HOST_STATUS register. The following shows the relationships between the transfer speed and the
value of the TMODE bit of USBHOST_HOST_STATUS.
■ If TMODE=1, then the device is a full-speed device
■ If TMODE=0, then the device is a low-speed device
Figure 34-3 shows the flow chart for device connection detection and obtaining the transfer speed.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 468
 Universal Serial Bus (USB) Host

Figure 34-3. Device Connection and Transfer Speed Detection Flow Chart
START

Enable pull down resistors on D+ and D -

POWER_CTL.DP_DOWN_EN=1
POWER_CTL.DM_DOWN_EN=1

Enable Host operation

HOST_CTL0.HOST=1
HOST_CTL0.ENABLE=1

Enable USB Host Clock and release the reset for USB host
HOST_CTL1.USTP=0
HOST_CTL1.RST=0

No
If
INTR_USBHOST.CNNIRQ=1

Yes

If No
HOST_STATUS.TMODE=1

Yes

USB device is Full speed USB device is Low speed

HOST_CTL1.CLKSEL=0 HOST_CTL1.CLKSEL=1

END

34.3.3 USB Bus Reset

The USB bus is reset by sending SE0 for 10 ms or more if the URST bit of the USBHOST_HOST_STATUS register is set to
'1'. After the USB bus is reset, the URST bit of HOST_STATUS is set to '0', and the URIRQ bit of
USBHOST_INTR_USBHOST is set to '1'. If the URIRQM bit of the USBHOST_INTR_USBHOST_MASK register is then set
to '1', an interrupt occurs. To clear this interrupt, write '1' to the URIRQ bit of USBHOST_INTR_USBHOST.
Figure 34-4 shows the timing diagram for USB bus reset.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 469
 Universal Serial Bus (USB) Host

Figure 34-4. Device Reset Timing Diagram

Pin D+ 10 ms or more

Pin D-

URST bit of
USBHOST_HOST_STATUS

CSTAT bit of
USBHOST_HOST_STATUS

URIRQ bit of
USBHOST_INTR_USBHOST

CNNIRQ bit of
USBHOST_INTR_USBHOST

Write ‫ ﺶ‬to the URST bit of 2.5 µs or more

USBHOST_HOST_STATUS

34.3.4 USB Packets

Exchange of information between the host and the device takes place in the form of packets, which are always initiated by the
host. There are three types of USB packets:
■ Token
■ Data
■ Handshake
The following sections explain about the settings required to initiate the packets by the PSoC 6 MCU USB host.

34.3.4.1 Token Packet

Endpoint 1 and Endpoint 2 buffers are used to send and receive data. If the DIR bit of the USBHOST_HOST_EP1_CTL
register is '1', the Endpoint 1 buffer is an OUT buffer. If the DIR bit of the USBHOST_HOST_EP2_CTL register is '0', then the
Endpoint 2 buffer is an IN buffer. Both the endpoints should never be configured as an OUT buffer or IN buffer
simultaneously, which implies that if Endpoint 1 is an OUT buffer then Endpoint 2 must be an IN buffer and vice-versa.
Use the following settings to process a token packet:
IN Token
1. Set the BFINI bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers to '1'.
2. Set the DIR bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers. Note that if Endpoint 1 is
an OUT buffer then Endpoint 2 must be an IN buffer and vice-versa.
3. Set the BFINI bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers to ‘0’.
4. Specify the target address in the USBHOST_HOST_ADDR register.
5. Specify the maximum number of bytes for the packet in the PKSn (n = 1, 2) bit field.
6. Specify the target endpoint, token (IN token), and toggle data in the USBHOST_HOST_TOKEN register.
7. Check if the token transfer is complete; the CMPIRQ bit will be set to ‘1’. To clear this interrupt, write ‘1’ to the CMPIRQ bit
of the USBHOST_INTR_USBHOST register. Note that the interrupt is triggered only if the CMPIRQM bit of the
USBHOST_INTR_USBHOST_MASK register is ‘1’.
8. Check for token packet transfer errors using the USBHOST_HOST_ERR register. Handle the errors, if any, appropriately.
9. Read the EPnDRQ (n = 1 or 2) bit of the USBHOST_INTR_HOST_EP register. A value of ‘1’ indicates that the packet
transfer ended normally. Clear the EPnDRQ bit by writing ‘1’.

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 Universal Serial Bus (USB) Host

10. Read data received from USBHOST_HOST_EPn_RWn_DR register (n =1, 2).

OUT and SETUP Tokens
1. Set the BFINI bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers to ‘1’.
2. Set the DIR bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers. Note that if Endpoint 1 is
an OUT buffer then Endpoint 2 must be an IN buffer and vice-versa.
3. Set the BFINI bit of the USBHOST_HOST_EP1_CTL and USBHOST_HOST_EP2_CTL registers to ‘0’.
4. Specify the target address in the USBHOST_HOST_ADDR register.
5. Specify the maximum number of bytes for the packet in the PKSn (n = 1, 2) bit field.
6. Write the data to be sent to the Endpoint n (n = 1 or 2) buffer. Use USBHOST_HOST_EPn_WR1_DR for 1-byte data and
USBHOST_HOST_EPn_WR2_DR for 2-byte data. Also, set the EPnDRQ (n = 1 or 2) bit of the USBHOST_IN-
TR_HOST_EP register as ‘1’.
7. Specify the target endpoint, token (OUT token), and toggle data in the USBHOST_HOST_TOKEN register.
8. Check if the token transfer is complete; the CMPIRQ bit will be set to ‘1’. To clear this interrupt, write ‘1’ to the CMPIRQ bit
of the USBHOST_INTR_USBHOST register. Note that the interrupt is triggered only if the CMPIRQM bit of the USB-
HOST_INTR_USBHOST_MASK register is ‘1’.
9. Check for token packet transfer errors using the USBHOST_HOST_ERR register. Handle the errors, if any, appropriately.
The USB PHY sends a token packet in the order of sync, token, address, endpoint, CRC5, and EOP based on the specified
token; however, sync, CRC5, and EOP are sent automatically. After one packet is sent, the CMPIRQ bit of the
USBHOST_INTR_USBHOST register is set to ‘1’. The TKNEN bit of the USBHOST_HOST_TOKEN register is set to ‘000’. At
this time, if the CMPIRQM bit of USBHOST_INTR_USBHOST_MASK register is '1', an interrupt occurs. To clear this
interrupt, write '1' to the CMPIRQ bit of the USBHOST_INTR_USBHOST register.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 471
 Universal Serial Bus (USB) Host

Figure 34-5. IN Token Flow Chart Figure 34-6. SETUP/OUT Token Flow Chart

START START

Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1'

Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’. Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘1'
Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0' Set DIR bit HOST_EP1_CTL and HOST_EP2_CTL to ‘1’ or ‘0’.
Set the BFINI bit of HOST_EP1_CTL and HOST_EP2_CTL to ‘0'

Specify the target address in

HOST_ADDR
Specify the target address in
HOST_ADDR
Configure the packet size for the endpoints using
the
HOST_EPn_CTL (n=1,2) registers

Configure the packet size for the endpoints using

HOST_TOKEN settings ( specify Toggle data, Endpoint) the
HOST_TOKEN.TKNEN = 0x02 HOST_EPn_CTL (n=1,2) registers

Write data to HOST_EPn_RWn_DR

No (n= 1,2)

INTR_USBHOST.CMPIRQ=1?
Check for token transfer
completion
Set INTR_HOST_EP.EPnDRQ=1
Yes (n=1,2)

Is SOF Lost HOST_TOKEN settings ( specify Toggle data, Endpoint)

HOST_ERR.LSTSOF=1? HOST_TOKEN.TKNEN = 0x01 for Setup Token
Yes HOST_TOKEN.TKNEN = 0x03 for Out Token
Yes
No

Check for Time out error

HOST_ERR.TOUT=1? No
INTR_USBHOST.CMPIRQ=1?
Yes Check for token transfer
No completion

Check for toggle error Yes

HOST_ERR.TGERR=1?
Yes
Is SOF Lost Yes
No HOST_ERR.LSTSOF=1?

No
Check for Handshake error
HOST_ERR.HS=00? Yes
Check for Time out error
Yes HOST_ERR.TOUT=1?
No

Error Processing No
No
Is Check for toggle error Yes
INTR_HOST_EP.EPnDRQ=1 HOST_ERR.TGERR=1?

No
Yes

Read received data from Check for Handshake error Yes

HOST_EPn_RWn_DR HOST_ERR.HS=00?
Register (n=1,2)

Error
No Processing

INTR_HOST_EP.EPnDRQ = 0 END

END

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 472
 Universal Serial Bus (USB) Host

When issuing an SOF token, specify the EOF time in the Host EOF Setup (USBHOST_HOST_EOF) register and the frame
number in the Host Frame Setup (USBHOST_HOST_FRAME) register respectively. Then, specify an SOF token code in the
TKNEN bit of the USBHOST_HOST_TOKEN register. After sync, SOF token, frame number, CRC5, and EOP are sent, the
SOFBUSY bit of the USBHOST_HOST_STATUS register is set to ‘1’, and the USBHOST_HOST_FRAME register is
incremented by one. The CMPIRQ bit of the USBHOST_INTR_USBHOST register is also set to ‘1’, causing the TKNEN bit of
the USBHOST_HOST_TOKEN register to be cleared to ‘000’. To clear a token completion interrupt, write ‘1’ to the CMPIRQ
bit of the Host Interrupt (USBHOST_HIRQ) register.
An SOF is automatically sent every 1 ms while the SOFBUSY bit of the USBHOST_HOST_STATUS register is ‘1’.
Figure 34-7 depicts steps to send an SOF token
Figure 34-7. SOF Token Flow Chart

START

HOST_FRAME Setting

HOST_EOF Setting

HOST_TOKEN setting

No
INTR_USBHOST.CMPIRQ=1?

Yes
Yes
HOST_ERR.LSTSOF=1?

No Error
Processing
END

The conditions (SOF stop conditions) to set the SOFBUSY bit of the USBHOST_HOST_STATUS register to ‘0’ are as fol-
lows:
■ Writing 0 to the SOFBUSY bit of USBHOST_HOST_STATUS
■ Resetting the USB bus
■ Writing 1 to the SUSP bit of USBHOST_HOST_STATUS
■ Disconnecting the USB device (when the CSTAT bit of USBHOST_HOST_STATUS is ‘0’)
The USBHOST_HOST_EOF register is used to prevent the SOF from being sent simultaneously with other tokens. If the
TKNEN bit of the USBHOST_HOST_TOKEN register is written within the time period specified by the
USBHOST_HOST_EOF register, the specified token is placed into the wait state. After the SOF is sent, the token in the wait
state is issued. The HOST_EOF Setup register specifies a 1-bit time as the time unit. When the EOF setting is shorter than
the 1-packet time, SOF may be sent doubly during execution of other tokens. In this case, the LSTSOF bit of the Host Error
Status (USBHOST_HOST_ERR) register is set to ‘1’ and SOF is not sent. If ‘1’ is set to the LSTSOF bit of the
USBHOST_HOST_ERR register, the value of the Host EOF Setup register must be increased.
Figure 34-8. SOF Timing
SOF SOF

EOF setting time EOF setting time

1 ms
EOF > 1-packet time

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 473
 Universal Serial Bus (USB) Host

34.3.4.2 Data Packet remented by one when a 1-bit transfer clock (12 MHz in full-
speed mode) is output. When the retry timer reaches 0, the
Follow these steps to send or receive a data packet after target token is sent, and processing ends. If a token retry
sending a token packet. occurs in the EOF area, the retry timer is stopped until SOF
■ Transmitting data (host to device) is sent. After SOF is sent, the retry timer restarts with the
value that is set when the timer stopped.
❐ Sync pattern is automatically sent.
❐ If the TGGL bit of USBHOST_HOST_TOKEN is 0, 34.3.6 Error Status
DATA0 is sent. If the TGGL bit is 1, DATA1 is sent.
❐ If the DIR bit of the USBHOST_HOST_EP1_CTL The USB host supports detection of the following types of
errors:
register is 1 (that is, if EP1 is an OUT endpoint),
select the Endpoint 1 buffer; otherwise, select the ■ Stuffing Error
Endpoint 2 buffer. Then, send all the target data. If 1 is written to six successive bits, 0 is inserted into one
❐ 16-bit CRC is automatically sent. bit. If 1 is successively detected in seven bits, it is
regarded as a Stuffing error, and the STUFF bit of the
❐ 2-bit EOP is automatically sent.
USBHOST_HOST_ERR register is set to 1. To clear this
❐ 1-bit J State is automatically sent. status, write ‘1’ to the STUFF bit.
■ Receiving data (device to host) ■ Toggle Error
❐ Receive sync. When sending an IN token, the Toggle Data field of a
❐ Receive toggle data, and compare it with the value of data packet is compared with the value of the TGGL bit
the TGGL bit of HOST_TOKEN. of the USBHOST_HOST_TOKEN register. If they do not
❐ If the toggle data matches the value of the TGGL bit, match, the TGERR bit of the USBHOST_HOST_ERR
check the DIR bit of HOST_EP1_CTL. If the DIR bit register is set to 1. To clear the TGERR bit, write ‘1’ to
is 1, select the Endpoint 2 buffer; otherwise, select the TGERR bit of the USBHOST_HOST_ERR register.
the Endpoint 1 buffer. Then, distribute the received ■ CRC Error
data to the respective buffers. When receiving an IN token, the data and CRC of the
❐ Verify the 16-bit CRC when EOF is received. received data packet are obtained with the CRC
polynomial G(X) = X16 + X15 + X2 + 1. If the remainder
34.3.4.3 Handshake Packet is not 0x800D, it means that a CRC error has occurred,
and the CRC bit of the USBHOST_HOST_ERR register
A handshake packet is used to notify the remote device of
is set to 1. To clear the CRC bit, write ‘1’ to the CRC bit
the status of the local device. A handshake packet sends
either one of ACK, NAK, and STALL from the receiving side of USBHOST_HOST_ERR. For more details, refer to the
when it is judged that the receiving side is ready to receive documentation: CRC in USB.
data normally. If the USB circuit receives a handshake ■ Time Out Error
packet, the type of the received handshake packet is set to
The TOUT bit of the USBHOST_HOST_ERR register is
the HS bit of the USBHOST_HOST_ERR register.
set and time out error is considered under any of the
following conditions:
34.3.5 Retry Function
❐ A data packet or handshake packet is not input in the
When a NAK or CRC error occurs at the end of a packet, if specified time
‘1’ is set to the RETRY bit of the Host Control 2
❐ SE0 is detected when receiving data
(USBHOST_HOST_CTL2) register, processing is retried
repeatedly for the period specified in the Host Retry Timer ❐ Stuffing error is detected
Setup (USBHOST_HOST_RTIMER) register. To clear the TOUT bit, write 0 to the TOUT bit of the
When an error other than STALL or device disconnection USBHOST_HOST_ERR register.
occurs, the target token is retried if the RETRY bit of ■ Receive Error
HOST_CTL2 is 1. The conditions to end retry processing
are as follows. The PKSn (n = 1, 2) bit of Endpoint Control register
(USBHOST_HOST_EPn_CTL; n=1, 2) indicates the
■ The RETRY bit of HOST_CTL2 is set to 0.
receiver packet size. When the received data exceeds
■ ‘0’ is detected in the retry timer. the specified receive packet size, the RERR bit of the
■ The interrupt flag is generated by SOF (SOFIRQ of USBHOST_HOST_ERR register is set to 1. To clear the
USBHOST_INTR_USBHOST = 1). RERR bit, write ‘1’ to the RERR bit of
■ ACK is detected. USBHOST_HOST_ERR.
■ A device disconnection is detected. ■ Lost SOF Error
The retry timer is activated when a token is sent while the When the LSTSOF bit of the USBHOST_HOST_ERR
RETRY bit of HOST_CTL2 is ‘1’. The retry time is then dec- register is set, it means that the SOF token cannot be

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 474
 Universal Serial Bus (USB) Host

sent because another token is in process. When this bit time, if the CMPIRQM bit of the
is ‘0’, it means that no lost SOF error is detected. USBHOST_INTR_USBHOST_MASK register is 1, an
interrupt occurs.
34.3.7 End of Packet (EOP) When a packet ends, the interrupt is generated when the
TKNEN bit of the USBHOST_HOST_TOKEN register is set
If a packet ends in the USB host, the CMPIRQ bit of the as ‘001’ (SETUP token), ‘010’ (IN token), ‘011’ (OUT token),
USBHOST_INTR_USBHOST register is set to 1. At this or ‘100’ (SOF token).
Figure 34-9. EOP Interrupt Timing Diagram (for IN/OUT/SETUP token)
Write data to the
TKNEN bit of
HOST_TOKEN Token Packet Data Packet Handshake Packet

J-ST Sync TKN ADR ENDP CRC5 EOP J-ST Sync TGGL DATA CRC16 EOP J-ST Sync ACK EOP J-ST

CMPIRQ bit of INTR_USBHOST

J-ST : J State
TKN : Token
ADR : Address
ENDP : Endpoint
TGGL : Toggle

Figure 34-10. EOP Interrupt Timing Diagram (for SOF token)

Write data to the TKNEN bit of HTOKEN.

J-ST Sync TKN FRAME CRC5 EOP J-ST

CMPIRQ bit
(HIRQ)

J-ST : J State
TKN : Token
FRAME : Frame Number

34.3.8 Interrupt Sources

The USB host generates 11 interrupts to the CPU. These interrupts are mapped to three general-purpose interrupt lines:
USBHOST_INTR_LO, USBHOST_INTR_MED, and USBHOST_INTR_HI. Each of these three interrupt lines has an
associated status register, which identifies the cause of the interrupt event. These are
USBHOST_INTR_USBHOST_CAUSE_LO, USBHOST_INTR_USBHOST_CAUSE_MED,
USBHOST_INTR_USBHOST_CAUSE_HI, USBHOST_INTR_HOST_EP_CAUSE_LO,
USBHOST_INTR_HOST_EP_CAUSE_MED, and USBHOST_INTR_HOST_EP_CAUSE_HI.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 475
 Universal Serial Bus (USB) Host

Figure 34-11. USB Host Interrupt Sources

Interrupt Control/Status Registers

CM4
Interrupt
Controller

URIRQ
CNNIRQ
SOFIRQ
DIRQ
INTR_HI CM0+
CMPIRQ Interrupt
INTR_MED
TCAN MUX
INTR_LO Controller
RWKIRQ
EP1DRQ
EP1SPK
EP2DRQ
EP2SPK

The following events generate an interrupt on one of the three interrupt lines:
■ Start-of-frame (SOF) event
SOF interrupt is generated when an SOF token is sent. The SOF interrupt is enabled by setting the SOFIRQM bit of the
USBHOST_INTR_USBHOST_MASK register. The status of the SOF interrupt is reflected in the SOFIRQ bit of the
USBHOST_INTR_USBHOST register.
■ Device connection and disconnection events
The CNNIRQ bit of the USBHOST_INTR_USBHOST register is set to ‘1’ when a device connection is detected. The
interrupt can be enabled by setting the CNNIRQM bit of the USBHOST_INTR_USBHOST_MASK register.
When a device is disconnected, an interrupt is generated if the DIRQM bitfield of USBHOST_INTR_USBHOST_MASK is
set to ‘1’. The status of the device disconnection is reflected in the DIRQ bit of the USBHOST_INTR_USBHOST register.
■ USB bus reset event
The URIRQ bit of the USBHOST_INTR_USBHOST register is set when the USB bus reset ends. An interrupt is generated
if the URIRQM bit of the USBHOST_INTR_USBHOST_MASK register is set to ‘1’.
■ Token completion event
When token (IN, OUT, or SETUP token) processing is complete, the CMPIRQ bit of the USBHOST_INTR_USBHOST
register is set. An interrupt is generated if the CMPIRQM bit is set to ‘1’.
■ Interrupt on resume event
The RWKIRQ bit of the USBHOST_INTR_USBHOST register is set when the host enters the resume state from suspend
state. The RWKIRQ bit is set under the following conditions:
❐ The SUSP bit of the USBHOST_HOST_STATUS register is set to ‘0’.
❐ The D+/D– pins are placed in the K-state.
❐ A device connection/disconnection is detected.
An interrupt is generated on a resume event if the RWKIRQM bit of the USBHOST_INTR_USBHOST_MASK register is
set to ‘1’.
■ Interrupt on token cancellation

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 476
 Universal Serial Bus (USB) Host

An interrupt is generated when a token send is canceled based on the setting of the CANCEL bit in the Host Control 2
register (USBHOST_HOST_CTL2). If the CANCEL bit is set and if the target token is written to the
USBHOST_HOST_TOKEN register in the EOF area (specified in the Host EOF Setup register), the token send is
canceled.
■ Endpoint interrupts
The USB host has two endpoints: Endpoint1 and Endpoint2. Each endpoint can generate two interrupts. When the packet
transfer of an endpoint ends normally, the EPnDRQ (n=1or 2) bit of the USBHOST_INTR_HOST_EP register is set to ‘1’.
An interrupt can be triggered if the EPnDRQM (n=1or 2) bit of the USBHOST_INTR_HOST_EP_MASK register is set to
‘1’. If the packet size does not match the packet size specified in the PKS bit of the HOST_EPn_CTL (n=1 or 2) register,
the EPnSPK (n=1or 2) bit of the USBHOST_INTR_HOST_EP register is set. An interrupt can be configured by setting the
EPnSPKM (n=1or 2) bit of the USBHOST_INTR_HOST_EP_MASK register.

34.3.9 DMA Transfer Function

Data handled by the USB host can be transferred via DMA between the send/receive buffer and the internal RAM. There are
two modes of DMA transfer:
■ Packet transfer mode
■ Automatic buffer transfer mode

34.3.9.1 Packet Transfer Mode

The packet transfer mode transfers each packet according to the configured data size in DMA. This transfer mode can access
each buffer of the endpoints.
In the packet transfer mode the OUT direction transfer (host to device) involves the following sequence of steps:
1. After the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register is set and the interrupt handling is entered,
configure the DMA register settings relevant to the number of transfers and block size corresponding to the data size to be
transferred in the next OUT packet; then, enable DMA to start the transfer.
2. After the DMA transfer, clear the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register and the interrupt
cause flag of DMAC, and return from the interrupt handling.
Figure 34-12. Packet Transfer Mode: OUT Direction
OUT packet OUT packet

Host Device OUT DATA0 OUT DATA1

DM_EPnDRQ
E bit is set by
Device Host ACK software ACK
DM_EPnDRQ
DMA is
E bit is
configured and
cleared by Generate the Genarate the
enabled.
software interrupt of DMAC interrupt of DMAC
DMAE bit 0

EPnDRQ bit EPnDRQ bit

DM_EPnDRQE bit is cleared is cleared
(n=1 or 2) by software by software

EPnDRQ bit
(n=1 or 2)
CMPIRQ is set to CMPIRQ is set to
Write the data to the 1 1
HOST_EPn_RW1_DR or Write the data to the
HOST_Epn_RW2_DR by DMAC HOST_EPn_RW1_DR or
OUT token is HOST_Epn_RW2_DR by DMAC OUT token is
(DATA0)
issued (DATA1) issued

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 477
 Universal Serial Bus (USB) Host

Figure 34-13. Packet Transfer Mode: IN Direction

IN packet IN packet

Host Device IN ACK IN ACK

DATA
Device Host DATA1
0

Generate the Generate the

interrupt of DMAC interrupt of DMAC
DMAE bit 0

DM_EPnDRQE
bit 1 EPnDRQ bit EPnDRQ bit
(n=1 or 2) is cleared is cleared
by software by software
EPnDRQ bit
(n=1 or 2)

Read the data from the

Read the data from the HOST_EPn_RW1_DR or
DMA is configured and DMA is HOST_EPn_RW1_DR or HOST_Epn_RW2_DR by DMAC
enabled. HOST_Epn_RW2_DR by DMAC
(DATA1)
After that, IN token is issued (DATA0)
DMA is configured and DMA is
enabled.
After that, IN token is issued

The data transfer in the IN direction (device to host) involves the following sequence of steps:
1. After the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register is set and the interrupt handling is entered,
check the transfer data size.
2. Configure the DMA register setting relevant to the number of transfers and block size corresponding to the transfer data
size, and then enable DMA to start the transfer.
3. After the transfer, clear the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register and the interrupt source
flag of DMAC, and return from the interrupt handling.

34.3.9.2 Automatic Data Transfer Mode

Automatic data transfer mode is enabled by setting the DMAE bit of the USBHOST_HOST_EPn_CTL register (n=1 or 2).
When the EPnDRQ bit (n=1 or 2) of the USBHOST_INTR_HOST_EP register is set while DMAE is enabled, the DMA request
is automatically cleared when the data size corresponding to PKSn (n = 1, 2) bits of the USBHOST_HOST_EPn_CTL register
(n=1 or 2) has been transferred. Later, the same sequence is repeated until the data size configured in the DMA is reached.
In this mode, configuration by software is not required. Thus, this mode can transfer data automatically by a single setting. It
can also transfer even bytes; to transfer odd bytes, a software transfer sequence is required.
The data transfer in the OUT direction (host to device) must be processed in the following sequence:
1. Configure the DMA register setting relevant to the number of transfers and block size corresponding to the total data size,
and then enable DMA to start the transfer.
2. Set the packet size and total number of bytes for DMA transfer to PKS bits of the USBHOST_HOST_EPn_CTL (n=1 or 2)
register and BLK_NUM bits of the USBHOST_HOST_EPn_BLK (n=1 or 2) register, respectively.
3. Enable DMAE bit of the USBHOST_HOST_EPn_CTL (n=1 or 2) register and EPnDRQE bit of the Host DMA Enable
(USBHOST_HOST_DMA_ENBL) (n=1 or 2) register.
4. After the transfer, reconfigure the DMAC using an interrupt generated by the DMA controller, and clear the flag to return
from interrupt handling.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 478
 Universal Serial Bus (USB) Host

Figure 34-14. Automatic Data Transfer Mode: OUT Direction

OUT token is OUT token is
issued issued
OUT packet Last OUT packet

Host Device OUT DATA0 OUT DATA1

Device Host ACK ACK

DMAE bit DMA is configured EPnDRQ bit is

and DMA is cleared
enabled. automatically
DM_EPnDRQE
bit EPnDRQ bit
(n=1 or 2) cleared
automatically
EPnDRQ bit
(n=1 or 2)
CMPIRQ is set to
1
Write the data to the
HOST_EPn_RW1_DR or CMPIRQ is set to
HOST_Epn_RW2_DR by DMAC 1
(DATA0) Write the rest data to the
HOST_EPn_RW1_DR or
HOST_Epn_RW2_DR by DMAC
(DATA1)

To transfer the odd bytes of data via DMA, write the last byte of data by software transfer.
Figure 34-15. Odd Bytes Transfer in the OUT Direction
15 87 0

0x22 0x11
(byte 2) (byte 1)

0x44 0x33
(byte 4) (byte 3) DMA Transfer (Write)

0x66 0x55
(byte 6) (byte 5)

0x88 0x77
(byte 8) (byte 7)

0x99 Write the data to the

(byte 9) HOST_Epn_RW1_DR by software

Endpoint n Buffer

The data transfer in the IN direction (device to host) must be processed in the following sequence:
1. Configure the DMA register setting relevant to the number of transfers and block size corresponding to the total data size,
and then enable DMA to start the transfer.
2. Enable DMAE bit of the USBHOST_HOST_EPn_CTL (n = 1 or 2) register and EPnDRQE bit of the
USBHOST_HOST_DMA_ENBL (n = 1 or 2) register.
3. After the transfer, reconfigure the DMA controller using an interrupt generated by the DMAC and clear the flag to return
from interrupt handling.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 479
 Universal Serial Bus (USB) Host

Figure 34-16. Automatic Data Transfer Mode: IN Direction

IN packet IN packet

Host Device IN ACK IN ACK

Device Host DATA0 DATA1

Generate the interrupt Genarate the interrupt

of DMAC of DMAC
DMAE bit 0

DM_EPnDRQE bit
1 EPnDRQ bit is EPnDRQ bit is
(n=1 or 2)
cleared by cleared by
software software
EPnDRQ bit
(n=1 or 2)

Read the data from the

Read the data from the HOST_EPn_RW1_DR or
DMA is configured and DMA is enabled. HOST_EPn_RW1_DR or HOST_Epn_RW2_DR by DMAC
After that, IN token is issued HOST_Epn_RW2_DR by DMAC (DATA1)
(DATA0)

DMA is configured and DMA is enabled.

After that, IN token is issued

Figure 34-17. Odd Bytes Transfer in the IN Direction

Transfer the last data by software Transfer all of the data by DMA

Endpoint n Buffer Endpoint n Buffer

15 87 0 15 87 0
0x22 0x11 0x22 0x11
DMA Transfer (Read)

DMA Transfer (Read)

(byte 2) (byte 1) (byte 2) (byte 1)
0x44 0x33 0x44 0x33
(byte 4) (byte 3) (byte 4) (byte 3)
0x66 0x55 0x66 0x55
(byte 6) (byte 5) (byte 6) (byte 5)
0x88 0x77 0x88 0x77
(byte 8) (byte 7) (byte 8) (byte 7)
0x99 Undefined 0x99
(byte 9) (byte 9)

Read the data to the The data is discarded

HOST_EPn_RW1_DR by software

To transfer the data size corresponding to odd number of bytes via DMA, either of the following methods can be used:
■ Use the software transfer only for the last data, and read the low-order byte (HOST_EPn_RW1_DR: n=1 or 2).
■ Transfer all the data + 1 byte via DMA, and discard the last data after an endian conversion.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 480
 Universal Serial Bus (USB) Host

34.3.10 Suspend and Resume Operations

The USB host supports suspend and resume operations.

34.3.10.1 Suspend Operation

If the SUSP bit of the USBHOST_HOST_STATUS register is set, the following procedure is performed, and the USB circuit is
placed in the suspend state.
■ The USB bus is placed in the high-impedance state.
■ All circuit blocks with no clock required are stopped.

34.3.10.2 Resume Operation

The USB bus changes from the suspend state to the resume state to start processing when one of the following conditions is
satisfied.
■ SUSP bit of the USBHOST_HOST_STATUS register is set to ‘0’.
■ The D+ or D– pin is placed in the K-state mode by the device.
■ A device disconnection is detected.
■ A device connection is detected.
The host can start issuing tokens when RWKIRQ bit of the USBHOST_INTR_USBHOST register is set to ‘1’.

34.3.11 Device Disconnection

The device disconnection timer starts when both the D+ and D– pins are set to LOW. If both D+ and D– remain at LOW for
2.5 µs or more, the device is considered to be disconnected. This then sets the CSTAT bit of the USBHOST_HOST_STATUS
register as ‘0’ and the DIRQ bit of the USBHOST_INTR_USBHOST register as ‘1’. At this time, if the DIRQM bit of the
USBHOST_INTR_USBHOST_MASK register is 1, an interrupt occurs. To clear this interrupt, write '1' to the DIRQ bit of the
USBHOST_INTR_USBHOST register.
If the USB bus is reset, the device is considered to be disconnected. In this case, the CSTAT bit of the
USBHOST_HOST_STATUS register is set to ‘0’, but the DIRQ bit of the USBHOST_INTR_USBHOST register is not set to 1.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 481
 Universal Serial Bus (USB) Host

34.4 USB Host Registers

Name Description
USBHOST_HOST_CTL0 Host control 0 register
USBHOST_HOST_CTL1 Host control 1 register
USBHOST_HOST_CTL2 Host control 2 register
USBHOST_HOST_ERR Host error status register
USBHOST_HOST_STATUS Host status register
USBHOST_HOST_FCOMP Host SOF interrupt frame compare register
USBHOST_HOST_RTIMER Host retry timer setup register
USBHOST_HOST_ADDR Host address register
USBHOST_HOST_EOF Host EOF setup register
USBHOST_HOST_FRAME Host frame setup register
USBHOST_HOST_TOKEN Host token endpoint register
USBHOST_HOST_EP1_CTL Host endpoint 1 control register
USBHOST_HOST_EP1_STATUS Host endpoint 1 status register
USBHOST_HOST_EP1_RW1_DR Host endpoint 1 data 1-byte register
USBHOST_HOST_EP1_RW2_DR Host endpoint 1 data 2-byte register
USBHOST_HOST_EP2_CTL Host endpoint 2 control register
USBHOST_HOST_EP2_STATUS Host endpoint 2 status register
USBHOST_HOST_EP2_RW1_DR Host endpoint 2 data 1-byte register
USBHOST_HOST_EP2_RW2_DR Host endpoint 2 data 2-byte register
USBHOST_HOST_LVL1_SEL Host interrupt level 1 selection register
USBHOST_HOST_LVL2_SEL Host interrupt level 2 selection register
USBHOST_INTR_USBHOST_CAUSE_HI Interrupt USB host cause high register
USBHOST_INTR_USBHOST_CAUSE_MED Interrupt USB host cause medium register
USBHOST_INTR_USBHOST_CAUSE_LO Interrupt USB host cause low register
USBHOST_INTR_HOST_EP_CAUSE_HI Interrupt USB host endpoint cause high register
USBHOST_INTR_HOST_EP_CAUSE_MED Interrupt USB host endpoint cause medium register
USBHOST_INTR_HOST_EP_CAUSE_LO Interrupt USB host endpoint cause low register
USBHOST_INTR_USBHOST Interrupt USB host register
USBHOST_INTR_USBHOST_SET Interrupt USB host set register
USBHOST_INTR_USBHOST_MASK Interrupt USB host mask register
USBHOST_INTR_USBHOST_MASKED Interrupt USB host masked register
USBHOST_INTR_HOST_EP Interrupt USB host endpoint register
USBHOST_INTR_HOST_EP_SET Interrupt USB host endpoint set register
USBHOST_INTR_HOST_EP_MASK Interrupt USB host endpoint mask register
USBHOST_INTR_HOST_EP_MASKED Interrupt USB host endpoint masked register
USBHOST_HOST_DMA_ENBL Host DMA enable register
USBHOST_HOST_EP1_BLK Host endpoint 1 block register
USBHOST_HOST_EP2_BLK Host endpoint 2 block register

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 482
 35. LCD Direct Drive

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU Liquid Crystal Display (LCD) drive system is a highly configurable peripheral that allows the device to
directly drive STN and TN segment LCDs.

35.1 Features
The PSoC 6 MCU LCD segment drive block has the following features:
■ Supports up to 61 segments and 8 commons
■ Supports Type A (standard) and Type B (low-power) drive waveforms
■ Any GPIO can be configured as a common or segment
■ Supports five drive methods:
❐ Digital correlation
❐ PWM at 1/2 bias
❐ PWM at 1/3 bias
❐ PWM at 1/4 bias
■ Ability to drive 3-V displays from 1.8 V VDD in Digital Correlation mode
■ Operates in Active, Sleep, and Deep Sleep modes
■ Digital contrast control

35.2 Architecture
35.2.1 LCD Segment Drive Overview
A segmented LCD panel has the liquid crystal material between two sets of electrodes and various polarization and reflector
layers. The two electrodes of an individual segment are called commons (COM) or backplanes and segment electrodes
(SEG). From an electrical perspective, an LCD segment can be considered as a capacitive load; the COM/SEG electrodes
can be considered as the rows and columns in a matrix of segments. The opacity of an LCD segment is controlled by varying
the root-mean-square (RMS) voltage across the corresponding COM/SEG pair.
The following terms/voltages are used in this chapter to describe LCD drive:
■ VRMSOFF: The voltage that the LCD driver can realize on segments that are intended to be off.
■ VRMSON: The voltage that the LCD driver can realize on segments that are intended to be on.

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 LCD Direct Drive

■ Discrimination Ratio (D): The ratio of VRMSON and VRMSOFF that the LCD driver can realize. This depends on the type of
waveforms applied to the LCD panel. Higher discrimination ratio results in higher contrast.
Liquid crystal material does not tolerate long term exposure to DC voltage. Therefore, any waveforms applied to the panel
must produce a 0-V DC component on every segment (on or off). Typically, LCD drivers apply waveforms to the COM and
SEG electrodes that are generated by switching between multiple voltages. The following terms are used to define these
waveforms:
■ Duty: A driver is said to operate in 1/M duty when it drives ‘M’ number of COM electrodes. Each COM electrode is effec-
tively driven 1/M of the time.
■ Bias: A driver is said to use 1/B bias when its waveforms use voltage steps of (1/B) × VDRV. VDRV is the highest drive
voltage in the system (equals VDD). The PSoC 6 MCU supports 1/2, 1/3, and 1/4 biases in PWM drive modes.
■ Frame: A frame is the length of time required to drive all the segments. During a frame, the driver cycles through the com-
mons in sequence. All segments receive 0-V DC (but non-zero RMS voltage) when measured over the entire frame.
The PSoC 6 MCU supports two different types of drive waveforms in all drive modes. These are:
■ Type-A Waveform: In this type of waveform, the driver structures a frame into M sub-frames. ‘M’ is the number of COM
electrodes. Each COM is addressed only once during a frame. For example, COM[i] is addressed in sub-frame i.
■ Type-B Waveform: The driver structures a frame into 2M sub-frames. The two sub-frames are inverses of each other.
Each COM is addressed twice during a frame. For example, COM[i] is addressed in sub-frames i and M+i. Type-B wave-
forms are slightly more power efficient because it contains fewer transitions per frame.

35.2.2 Drive Modes

The PSoC 6 MCU supports the following drive modes.
■ PWM drive at 1/2 bias
■ PWM drive at 1/3 bias
■ PWM drive at 1/4 bias with high-frequency clock input
■ Digital correlation

35.2.2.1 PWM Drive

In PWM drive mode, multi-voltage drive signals are generated using a PWM output signal together with the intrinsic resis-
tance and capacitance of the LCD. Figure 35-1 illustrates this.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 484
 LCD Direct Drive

Figure 35-1. PWM Drive (at 1/3 Bias)

GPIO Output Impedance ITO Panel Resistance LCD Segment
Capacitance

PWM Generator
COM

VPWM VLCD

PWM Generator

SEG

VPWM

VDDD

0
t
VLCD

VDDDD

2/3 VDDD

1/3 VDDD

0
t

The output waveform of the drive electronics is a PWM waveform. With the Indium Tin Oxide (ITO) panel resistance and the
segment capacitance to filter the PWM, the voltage across the LCD segment is an analog voltage, as shown in Figure 35-1.
This figure illustrates the generation of a 1/3 bias waveform (four commons and voltage steps of VDD/3). See the Clocking
System chapter on page 242 for details.
The PWM is derived from either CLK_LF (32 kHz, low-speed operation) or CLK_PERI (high-speed operation). See the Clock-
ing System chapter on page 242 for more details of peripheral and low-frequency clocks. The filtered analog voltage across
the LCD segments typically runs at low frequency for segment LCD driving.
Figure 35-2 and Figure 35-3 illustrate the Type A and Type B waveforms for COM and SEG electrodes for 1/2 bias and 1/4
duty. Only COM0/COM1 and SEG0/SEG1 are drawn for demonstration purpose. Similarly, Figure 35-4 and Figure 35-5 illus-
trate the Type A and Type B waveforms for COM and SEG electrodes for 1/3 bias and 1/4 duty.

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 LCD Direct Drive

Figure 35-2. PWM1/2 Type-A Waveform Example

One frame of Type A waveform
(addresses all segments once)

VDD
COM0 1/2 VDD

VDD

COM1 1/2 VDD

VDD

SEG0 1/2 VDD

VDD
SEG1 1/2 VDD

0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
Segment On:
0 VRMS = 0.661 VDD
COM0 -SEG0
-VDD

VDD

COM0 -SEG1 0 Segment Off:

VRMS = 0.433 VDD
-VDD

VDD

COM1 -SEG0 0
Segment On:
VRMS = 0.661 VDD
-VDD

VDD
COM1 -SEG1 0 Segment Off:
VRMS = 0.433 VDD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.661/0.433 = 1.527

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 LCD Direct Drive

Figure 35-3. PWM1/2 Type-B Waveform Example

One frame of Type B waveform
(addresses all segments twice)

VDD
COM0 1/2 V DD

VDD

COM1 1/2 V DD

VDD

SEG0 1/2 V DD

VDD
SEG1 1/2 V DD

0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
COM0 -SEG0 Segment On:
0 VRMS = 0.661 VDD
-VDD

VDD
COM0 -SEG1 0 Segment Off:
VRMS = 0.433 VDD
-VDD

VDD
COM1 -SEG0 Segment On:
0
VRMS = 0.661 VDD
-VDD

VDD
COM1 -SEG1 Segment Off:
0
VRMS = 0.433 VDD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.661/0.433 = 1.527

Segment is Off

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 LCD Direct Drive

Figure 35-4. PWM1/3 Type-A Waveform Example

One Frame‫ﺶ‬of Type A Waveform

(addresses all segments once)

VDD
COM0 2/3 V DD
1/3 V DD
0

VDD
2/3 V DD
COM1
1/3 V DD
0

VDD
2/3 V DD
SEG0
1/3 V DD
0

VDD
SEG1 2/3 V DD
1/3 V DD
0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
Segment On:
COM0 -SEG0
0 VRMS = 0.577 V DD

-VDD

VDD
COM0 -SEG1 0 Segment Off:
VRMS = 0.333 V DD
-VDD

VDD
COM1 -SEG0 Segment On:
0
VRMS = 0.577 V DD
-VDD

VDD

COM1 -SEG1 0 Segment Off:

VRMS = 0.333 V DD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.577/0.333 = 1.732

Segment is Off

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 LCD Direct Drive

Figure 35-5. PWM1/3 Type-B Waveform Example

One Frame‫ﺶ‬of Type B Waveform

(addresses all segments twice)

VDD
COM0 2/3 V DD
1/3 V DD
0

VDD
2/3 V DD
COM1
1/3 V DD
0

VDD
2/3 V DD
SEG0
1/3 V DD
0

VDD
SEG1 2/3 V DD
1/3 V DD
0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
Segment On:
COM0 -SEG0 0 VRMS = 0.577 V DD

-VDD

VDD
COM0 -SEG1 0 Segment Off:
VRMS = 0.333 V DD
-VDD

VDD

COM1 -SEG0 0 Segment On:

VRMS = 0.577 V DD
-VDD

VDD

COM1 -SEG1 0 Segment Off:

VRMS = 0.333 V DD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.577/0.333 = 1.732

Segment is Off

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 LCD Direct Drive

The effective RMS voltage for ON and OFF segments can be calculated easily using these equations:

V 2
2B – 2 + 2M – 1  V
RMS  OFF  = ----------------------------------------------------x ------------
DRV
2M  B 
Equation 35-1

V 2
2B + 2  M – 1   V
RMS  ON  = --------------------------------------x ------------
DRV
2M  B 
Equation 35-2
Where B is the bias and M is the duty (number of COMs).
For example, if the number of COMs is four, the resulting discrimination ratios (D) for 1/2 and 1/3 biases are 1.528 and 1.732,
respectively. 1/3 bias offers better discrimination ratio in two and three COM drives also. Therefore, 1/3 bias offers better con-
trast than 1/2 bias and is recommended for most applications. 1/4 bias is available only in high-speed operation of the LCD.
They offer better discrimination ratio especially when used with high COM designs (more than four COMs).
When the low-speed operation of LCD is used, the PWM signal is derived from the 32-kHz CLK_LF. To drive a low-capaci-
tance display with acceptable ripple and rise/fall times using a 32-kHz PWM, additional external series resistances of 100 k-
1 M should be used. External resistors are not required for PWM frequencies greater than ~1 MHz. The ideal PWM fre-
quency depends on the capacitance of the display and the internal ITO resistance of the ITO routing traces.
The 1/2 bias mode has the advantage that PWM is only required on the COM signals; the SEG signals use only logic levels,
as shown in Figure 35-2 and Figure 35-3.

35.2.2.2 Digital Correlation

The digital correlation mode, instead of generating bias voltages between the rails, takes advantage of the characteristic of
LCDs that the contrast of LCD segments is determined by the RMS voltage across the segments. In this approach, the cor-
relation coefficient between any given pair of COM and SEG signals determines whether the corresponding LCD segment is
on or off. Thus, by doubling the base drive frequency of the COM signals in their inactive sub-frame intervals, the phase rela-
tionship of the COM and SEG drive signals can be varied to turn segments on and off. This is different from varying the DC
levels of the signals as in the PWM drive approach. Figure 35-8 and Figure 35-9 are example waveforms that illustrate the
principles of operation.

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 LCD Direct Drive

Figure 35-6. Digital Correlation Type-A Waveform

One Frame‫ﺶ‬of Type A Waveform
(addresses all segments once)

VDD
COM0

VDD
COM1

VDD
SEG0

VDD
SEG1

0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
Segment On:
COM0 -SEG0 0 VRMS = 0.791 V DD
-VDD

VDD
COM0 -SEG1 0 Segment Off:
VRMS = 0.612 V DD
-VDD

VDD
COM1 -SEG0 Segment On:
0
VRMS = 0.791 V DD
-VDD

VDD

COM1 -SEG1 0 Segment Off:

VRMS = 0.612 V DD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.791/0.612 = 1.291

Segment is Off

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 LCD Direct Drive

Figure 35-7. Digital Correlation Type-B Waveform

One Frame‫ﺶ‬of Type B Waveform

(addresses all segments twice)

VDD
COM0

VDD

COM1

VDD

SEG0

VDD
SEG1

0
t0 t1 t2 t3

One Frame

COM / SEG is selected

COM / SEG is not selected

Resulting voltage across segments

(VDC = 0)

VDD
Segment On:
COM0 -SEG0 0 VRMS = 0.791 V DD

-VDD

VDD
COM0 -SEG1 0 Segment Off:
VRMS = 0.612 V DD
-VDD

VDD
COM1 -SEG0 Segment On:
0
VRMS = 0.791 V DD
-VDD

VDD

COM1 -SEG1 0 Segment Off:

VRMS = 0.612 V DD
-VDD
t0 t1 t2 t3

Discrimination ratio:
Segment is On D = 0.791/0.612 = 1.291

Segment is Off

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 LCD Direct Drive

The RMS voltage applied to on and off segments can be calculated as follows:
V
M – 1
RMS  OFF  = ------------------x  V DD 
2M
V
2 + M – 1
RMS  ON  = ----------------------------x  V DD 
2M

Where B is the bias and M is the duty (number of COMs). This leads to a discrimination ratio (D) of 1.291 for four COMs.
Digital correlation mode also has the ability to drive 3-V displays from 1.8-V VDD.

35.2.3 Recommended Usage of Drive Modes

The PWM drive mode has higher discrimination ratios compared to the digital correlation mode, as explained in 35.2.2.1
PWM Drive and 35.2.2.2 Digital Correlation. Therefore, the contrast in digital correlation method is lower than PWM method
but digital correlation has lower power consumption because its waveforms toggle at low frequencies.
The digital correlation mode creates reduced, but acceptable contrast on TN displays, but no noticeable difference in contrast
or viewing angle on higher contrast STN displays. Because each mode has strengths and weaknesses, recommended usage
is as follows.

Table 35-1. Recommended Usage of Drive Modes

Display Type Deep Sleep Mode Sleep/Active Mode Notes
Four COM TN Firmware must switch between LCD drive modes before going to deep
Digital correlation PWM 1/3 bias
Glass sleep or waking up.
Four COM STN
Digital correlation No contrast advantage for PWM drive with STN glass.
Glass
Supported only in the high-speed LCD mode. The low-speed CLK_LF is
Eight COM, STN Not supported PWM 1/4 bias
not fast enough to make the PWM work at high multiplex ratios.

35.2.4 Digital Contrast Control

In all drive modes, digital contrast control can be used to change the contrast level of the segments. This method reduces
contrast by reducing the driving time of the segments. This is done by inserting a ‘Dead-Time’ interval after each frame.
During dead time, all COM and SEG signals are driven to a logic 1 state. The dead time can be controlled in fine resolution.
Figure 35-8 illustrates the dead-time contrast control method for 1/3 bias and 1/4 duty implementation.
Figure 35-8. Dead-Time Contrast Control
Two Frames of of Type A Waveform with Dead-time
(Example for 1/4th Duty and 1/3rd bias)

VDD
COM0 2/3 VDD
1/3 VDD
0

VDD
COM1 2/3 VDD
1/3 VDD
0

VDD
2/3 VDD
SEG0
1/3 VDD
0

VDD
SEG1 2/3 VDD
1/3 VDD
0
t0 t1 t2 t3 dt t0 t1 t2 t3 dt

Dead-Time

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 LCD Direct Drive

35.3 PSoC 6 MCU Segment LCD Direct Drive

Figure 35-9. Block Diagram of LCD Direct Drive System

High-Speed (HS)
LCD Master
High-Frequency Generator
Clock, CLK_PERI
HS COM Signals
AHB
AHB HS SEG Signals COM
interface Signals LCD com[0]
HSIO
HS Sub Frame Data LCD seg[0]
Active SEG Matrix
Power Domain Signals
Deep Sleep Multiplexer
Low-Speed (LS)
Power Domain LCD Master LCD com[1]
Generator
Sub Frame HSIO
LS COM Signals Data LCD seg[1] Matrix
Low Frequency LS SEG Signals LCD
Clock, CLK_LF Pin
(32 kHz) Logic
LS Sub Frame Data
LCD Mode
Select
(HS/LS)
Config & Control
Registers

Display Data [0]

LCD com[n]
Display
Display Display Data [1]
Data
Data HSIO
LCD seg[n] Matrix
Registers
Display Data [n]

The LCD controller block contains two generators, one with 35.3.1 High-Speed and Low-Speed
a high-speed clock source CLK_PERI and the other with a
Master Generators
low-speed clock source (32 kHz) derived from the CLK_LF.
These are called high-speed LCD master generator and The high-speed and low-speed master generators are simi-
low-speed LCD master generator, respectively. Both the lar to each other. The only exception is that the high-speed
generators support PWM and digital correlation drive version has larger frequency dividers to generate the frame
modes. PWM drive mode with low-speed generator requires and sub-frame periods. The high-speed generator is in the
external resistors, as explained in PWM Drive on page 484. active power domain and the low-speed generator is in the
Deep Sleep power domain. A single set of configuration reg-
The multiplexer selects one of these two generator outputs
isters is provided to control both high-speed and low-speed
to drive LCD, as configured by the firmware. The LCD pin
blocks. Each master generator has the following features
logic block routes the COM and SEG outputs from the gen-
and characteristics:
erators to the corresponding I/O matrices. Any GPIO can be
used as either COM or SEG. This configurable pin assign- ■ Register bit configuring the block for either Type A or
ment for COM or SEG is implemented in GPIO and I/O Type B drive waveforms (LCD_MODE bit in LCD0_-
matrix; see High-Speed I/O Matrix. These two generators CONTROL register).
share the same configuration registers. These memory ■ Register bits to select the number of COMs (COM_NUM
mapped I/O registers are connected to the system bus field in LCD0_CONTROL register).
(AHB) using an AHB interface. ■ Operating mode configuration bits enabled to select one
The LCD controller works in three device power modes: of the following:
Active, Sleep, and Deep Sleep. High-speed operation is ❐ Digital correlation
supported in Active and Sleep modes. Low-speed operation ❐ PWM 1/2 bias
is supported in Active, Sleep, and Deep Sleep modes. The
LCD controller is unpowered in Hibernate mode. ❐ PWM 1/3 bias

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 LCD Direct Drive

❐ PWM 1/4 bias (not supported in low-speed genera- ration and control register. The LCD pin logic uses the sub-
tor) frame signal from the multiplexer to choose the display data.
❐ Off/disabled. Typically, one of the two generators will This pin logic will be replicated for each LCD pin.
be configured to be Off
OP_MODE and BIAS fields in LCD0_CONTROL bits 35.3.3 Display Data Registers
select the drive mode. Each LCD segment pin is part of an LCD port with its own
■ A counter to generate the sub-frame timing. The SUB- display data register, LCD0_DATAx. The device has eight
FR_DIV field in the LCD0_DIVIDER register determines such LCD ports. Note that these ports are not real pin ports
the duration of each sub-frame. If the divide value written but the ports/connections available in the LCD hardware for
into this counter is C, the sub-frame period is 4 × (C+1). mapping the segments to commons. Each LCD segment
The low-speed generator has an 8-bit counter. This configured is considered as a pin in these LCD ports. The
counter generates a maximum half sub-frame period of LCD0_DATAxx registers are 32-bit wide and store the ON/
8 ms from the 32-kHz CLK_LF. The high-speed genera- OFF data for all SEG-COM combination enabled in the
tor has a 16-bit counter. design. For example, LCD0_DATA0x holds SEG-COM data
■ A counter to generate the dead time period. These for COM0 to COM3 and LCD0_DATA1x holds SEG-COM
counters have the same number of bits as the sub-frame data for COM4 to COM7. The bits [4i+3:4i] (where ‘i’ is the
period counters and use the same clocks. DEAD_DIV pin number) of each LCD0_DATAxx register represent the
field in the LCD0_DIVIDER register controls the dead ON/OFF data for Pin[i], as shown in Table 35-2. The
time period. LCD0_DATAxx register should be programmed according to
the display data of each frame. The display data registers
are Memory Mapped I/O (MMIO) and accessed through the
35.3.2 Multiplexer and LCD Pin Logic AHB slave interface. See the PSoC 61 datasheet/PSoC 62
The multiplexer selects the output signals of either high- datasheet for the pin connections.
speed or low-speed master generator blocks and feeds it to
the LCD pin logic. This selection is controlled by the configu-

Table 35-2. SEG-COM Mapping Example of LCD0_DATA00 Register (each SEG is a pin of the LCD port)
BITS[31:28] = PIN_7[3:0] BITS[27:24] = PIN_6[3:0]
PIN_7-COM3 PIN_7-COM2 PIN_7-COM1 PIN_7-COM0 PIN_6-COM3 PIN_6-COM2 PIN_6-COM1 PIN_6-COM0
BITS[23:20] = PIN_5[3:0] BITS[19:16] = PIN_4[3:0]
PIN_5-COM3 PIN_5-COM2 PIN_5-COM1 PIN_5-COM0 PIN_4-COM3 PIN_4-COM2 PIN_4-COM1 PIN_4-COM0
BITS[15:12] = PIN_3[3:0] BITS[11:8] = PIN_2[3:0]
PIN_3-COM3 PIN_3-COM2 PIN_3-COM1 PIN_3-COM0 PIN_2-COM3 PIN_2-COM2 PIN_2-COM1 PIN_2-COM0
BITS[7:3] = PIN_1[3:0] BITS[3:0] = PIN_0[3:0]
PIN_1-COM3 PIN_1-COM2 PIN_1-COM1 PIN_1-COM0 PIN_0-COM3 PIN_0-COM2 PIN_0-COM1 PIN_0-COM0

35.4 Register List

Table 35-3. LCD Direct Drive Register List
Register Name Description
LCD0_ID This register includes the information of LCD controller ID and revision number
LCD0_DIVIDER This register controls the sub-frame and dead-time period
LCD0_CONTROL This register is used to configure high-speed and low-speed generators
LCD0_DATA0x LCD port pin data register for COM0 to COM3
LCD0_DATA1x LCD port pin data register for COM4 to COM7

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 495
 Section E: Analog Subsystem

This section encompasses the following chapters:

■ Analog Reference Block chapter on page 497
■ Low-Power Comparator chapter on page 501
■ SAR ADC chapter on page 506
■ Temperature Sensor chapter on page 520
■ CapSense chapter on page 524

Top Level Architecture

Figure E-1. Analog System Block Diagram
Peripheral clock (PCLK)

2x Smart I/O Ports

I/O Subsystem: Up to 102 GPIOs (including 6 OVT), 128-TQFP Package
Peripheral Interconnect (MMIO, PPU)

Programmable Analog

SAR ADC 12 bit

SARMUX

Temperature
Sensor
Boundary Scan

Color Key:
Power Modes and
Domains

System LP/ULP Mode

CPUs Active/Sleep

System
DeepSleep Mode

System
Hibernate Mode

Backup
Domain

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 496
 36. Analog Reference Block

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The Analog Reference block (AREF) generates highly accurate reference voltage and currents needed by the programmable
analog subsystem (PASS) and CapSense (CSD) blocks.

36.1 Features
■ Provides accurate bandgap references for PASS and CSD subsystems
■ 1.2-V voltage reference (VREF) generator
■ Option to output alternate voltage references routed from SRSS or from an external pin
■ Zero dependency to absolute temperature (IZTAT) flat current reference generation, which is independent of temperature
variations
■ Option to generate IZTAT from SRSS generated current reference

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 Analog Reference Block

36.2 Architecture
Figure 36-1. AREF Block Diagram

Analog Reference (AREF) block

PASS_AREF_AREF_CTRL.
IZTAT_SEL

External reference
input pin (VREF) or
SRSS Current Reference Scale (x4) bypass capacitor for
(250 nA) Current IZTAT To SAR ADC

MUX
internal reference
Mirror and CapSense
IZTAT IZTAT
Generator 1 uA

PASS_AREF_AREF_CTRL. SAR Reference

AREF_MODE (SARREF)
Bandgap VREFBG 1.2 V
Reference
Low Pass VREF To SAR ADC

MUX
To
Filter VREF
SAR ADC
VDDA/2 Buffer VDDA
SRSS Voltage Reference (0.8 V) Core

Low Pass VREF

External (off-chip) reference from a pin Filter To CapSense Block
AREF_EXT_VREF

PASS_AREF_AREF_CTRL.
VREF_SEL

Figure 36-1 shows the architecture of the Analog Reference (AREF) block. It consists of a bandgap reference circuit, which generates 1.2 V voltage reference (VREFBG). Options
for the voltage reference include 0.8 V reference from the SRSS block and an external reference from a dedicated pin (see the PSoC 61 datasheet/PSoC 62 datasheet for pin
number). Application use cases of the selected voltage reference (VREF) include setting the reference SAR ADC, and CapSense blocks.

The AREF block also generates zero-temperature coefficient IZTAT reference current (1 µA), which remains stable over temperature. The other option for IZTAT reference is the
1 µA current derived from the 250-nA reference current from SRSS. Selected IZTAT reference current is used in SAR ADC, and CapSense blocks.
Current mirror circuits are used to generate multiple current references to drive to different analog blocks.
The following sections explain the configurations in detail.

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 Analog Reference Block

36.2.1 Bandgap Reference Block

The AREF block contains a local bandgap reference generator, which has tighter accuracy, temperature stability, and lower
noise than the SRSS bandgap reference. The bandgap reference block provides a temperature stable voltage (VREFBG). See
the device datasheet to know the accuracy of VREFBG.

The AREF block is enabled by writing ‘1’ into the ENABLED bit of the PASS_AREF_AREF_CTRL register.

36.2.2 VREF Reference Voltage Selection Multiplexer Options

The multiplexer in AREF is used to select the sources for the output voltage reference. The following options are available for
selection using VREF_SEL bits of the PASS_AREF_AREF_CTRL register.

Table 36-1. Reference Voltage Multiplexer Options

VREF_SEL[1:0] Description
Routes the VREF from SRSS (0.8 V)
00 (SRSS)

01 (LOCAL) Routes locally generated bandgap reference (1.2V)

02 (EXTERNAL) Routes the reference from the external pin – AREF_EXT_VREFa
a. The AREF_EXT_VREF pin is different from the VREF pin. VREF pin is used by SAR ADC to take the reference directly bypassing the reference voltage from
AREF.

36.2.3 Zero Dependency To Absolute Temperature Current Generator (IZTAT)

The IZTAT current generator uses the output of the selected reference voltage (VREF) to generate a precise current reference,
which has a low variation over temperature.

Table 36-2. IZTAT Reference

IZTAT Reference Outputs Value
IZTAT 1 µA

36.2.3.1 IZTAT Selection Multiplexer Options

IZTAT output current can be derived from the SRSS reference current (250 nA) or the reference current from the local IZTAT
generator. The selection is made using IZTAT_SEL bit of the PASS_AREF_AREF_CTRL register.

Table 36-3. IZTAT Multiplexer Options

IZTAT_SEL Description
Uses SRSS current reference
0 (SRSS)

1 (LOCAL) Uses locally generated reference current

36.2.4 Startup Modes

AREF supports two startup modes, which provide a trade-off between wakeup time and noise performance when transitioning
from the Deep Sleep to Active power mode. This is selected using the AREF_MODE bit of the PASS_AREF_AREF_CTRL
register. The FAST_START mode enables faster wakeup, but with higher noise levels. Firmware can switch to NORMAL
mode after the FAST_START settling time to achieve better noise performance.

Table 36-4. Startup Modes

AREF_MODE Description
0 (NORMAL) Normal startup mode
1 (FAST_START) Fast startup mode

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 499
 Analog Reference Block

36.3 Registers
Table 36-5. List of AREF Registers
Register Comment Features
PASS_AREF_AREF_CTRL AREF control register Reference selection, startup time, and low-power mode.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 500
 37. Low-Power Comparator

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

PSoC 6 MCUs have two Low-Power comparators, which can perform fast analog signal comparison of internal and external
analog signals in all system power modes. Low-Power comparator output can be inspected by the CPU, used as an interrupt/
wakeup source to the CPU when in CPU Sleep mode, used as a wakeup source to system resources when in System Deep
Sleep or Hibernate mode, or fed to GPIO or trigger multiplexer (see Trigger Multiplexer Block chapter on page 294) as an
asynchronous or synchronous signal (level or pulse).

37.1 Features
The PSoC 6 MCU comparators have the following features:
■ Configurable input pins
■ Programmable power and speed
■ Ultra low-power mode support
■ Each comparator features a one-sided hysteresis option
■ Rising edge, falling edge, combined rising and falling edge detection at the comparator output
■ Local reference voltage generation
■ Wakeup source from low-power modes

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 Low-Power Comparator

37.2 Architecture
Figure 37-1 shows the block diagram for the Low-Power comparator.
Figure 37-1. Low-Power Comparator Block Diagram

Low Power Comparator Block

MMIO

Part of I/O Analog Sub-Section AHB

Interface AHB
system Registers

Routing
Switches Comparator0
inp0 edge + pulse dsi_comp0
IP0 + Sync (To HSIOM or trigger

Sync
Sync
P0A P0B AP0 BP0 multiplexer)
inn0
IN0 -
P1A P1B AN0 BN0 VN0
out0

out_wk0
Edge
Comparator1 Detector
inp1
IP1 + Interrupt to
P2A P2B AP1 BP1 combine &
CPU
inn1 mask
IN1 - Subsystem
P3A P3B AN1 BN1 VN1
out_wk1

AA_SL AA_SR

BB_SL BB_SR Edge

Detector
Routing out1
AMUXBUS A

AMUXBUS B

Switches To MMIO

edge + pulse dsi_comp1

V REF (0.45 V -0.75 V)
Sync (To HSIOM or trigger
multiplexer)

Wake up signals to
System Resources Sub-System

The following sections describe the operation of the PSoC 6 uses the AMUXBUS for the connection. See the I/O
MCU Low-Power comparator, including input configuration, System chapter on page 261 for more details on connecting
power and speed modes, output and interrupt configuration, the GPIO to AMUXBUS A/B or setting up the GPIO for
hysteresis, and wakeup from low-power modes. comparator input.
Refer to the LPCOMP_CMP0_SW, LPCOMP_CMP1_SW,
37.2.1 Input Configuration LPCOMP_CMP0_SW_CLEAR, and
Low-Power comparators can operate with the following input LPCOMP_CMP1_SW_CLEAR registers in the registers
options: TRM to understand how to control the internal routing
switches shown in Figure 37-1.
■ Compare two voltages from external pins.
■ Compare a voltage from an external pin against an If the inverting input of a comparator is routed to a local
internally generated analog-signal (through AMUXBUS). voltage reference, the LPREF_EN bit in the
LPCOMP_CONFIG register must be set to enable the
■ Compare two internal voltages through AMUXBUS-A/ voltage reference.
AMUXBUS-B.
■ Compare internal and external signals with a locally- 37.2.2 Output and Interrupt Configuration
generated reference voltage. Note that this voltage is not
a precision reference and can vary from 0.45 V–0.75 V. Both Comparator0 and Comparator1 have hardware outputs
available at dedicated pins. See the PSoC 61 datasheet/
See the PSoC 61 datasheet/PSoC 62 datasheet for detailed
PSoC 62 datasheet for the location of comparator output
specifications of the Low-Power comparator.
pins.
Note that AMUXBUS connections are not available in Deep
Sleep and Hibernate modes. If Deep Sleep or Hibernate
operation is required, the Low-Power comparator must be Firmware readout of Comparator0 and Comparator1 outputs
connected to the dedicated pins. This restriction also are available at the OUT0 and OUT1 bits of the
includes routing of any internally-generated signal, which LPCOMP_STATUS register (Table 37-1). The output of each

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 Low-Power Comparator

comparator is connected to a corresponding edge detector interrupt. Alternatively, COMP0_MASK bit and
block. This block determines the edge that triggers the COMP1_MASK bit of the LPCOMP_INTR_MASK register
interrupt. The edge selection and interrupt enable is can be used to mask the Comparator0 and Comparator1
configured using the INTTYPE0 and INTTYPE1 bitfields in interrupts to the CPU. Only the masked interrupts will be
the LPCOMP_CMP0_CTRL and LPCOMP_CMP1_CTRL serviced by the CPU. After the interrupt is processed, the
registers for Comparator0 and Comparator1, respectively. interrupt should be cleared by writing a ‘1’ to the COMP0
Using the INTTYPE0 and INTTYPE1 bits, the interrupt type and COMP1 bits of the LPCOMP_INTR register in firmware.
can be selected to disabled, rising edge, falling edge, or If the interrupt to the CPU is not cleared, it stays active
both edges, as described in Table 37-1. regardless of the next compare events and interrupts the
CPU continuously. Refer to the Interrupts chapter on
Each comparator’s output can also be routed directly to a
page 56 for details.
GPIO pin through the HSIOM. See the I/O System chapter
on page 261 for more details. LPCOMP_INTR_SET register bits [1:0] can be used to
assert an interrupt for firmware debugging.
During an edge event, the comparator will trigger an
interrupt. The interrupt request is registered in the COMP0 In Deep Sleep mode, the wakeup interrupt controller (WIC)
bit and COMP1 bit of the LPCOMP_INTR register for can be activated by a comparator edge event, which then
Comparator0 and Comparator1, respectively. Both wakes up the CPU. Similarly in Hibernate mode, the
Comparator0 and Comparator1 share a common interrupt LPCOMP can wake up the system resources sub-system.
signal output (see Figure 37-1), which is a logical OR of the Thus, the LPCOMP has the capability to monitor a specified
two interrupts and mapped as the Low-Power comparator signal in low-power modes. See the Power Supply and
block’s interrupt in the CPU NVIC. Refer to the Monitoring chapter on page 218 and the Device Power
Interrupts chapter on page 56 for details. If both the Modes chapter on page 225 for more details.
comparators are used in a design, the COMP0 and COMP1
bits of the LPCOMP_INTR register must be read in the
interrupt service routine to know which one triggered the

Table 37-1. Output and Interrupt Configuration

Register[Bit_Pos] Bit_Name Description
LPCOMP_STATUS[0] OUT0 Current/Instantaneous output value of Comparator0
LPCOMP_STATUS[16] OUT1 Current/Instantaneous output value of Comparator1
Sets on which edge Comparator0 will trigger an IRQ
00: Disabled
LPCOMP_CMP0_CTRL[7:6] INTTYPE0 01: Rising Edge
10: Falling Edge
11: Both rising and falling edges
Sets on which edge Comparator1 will trigger an IRQ
00: Disabled
LPCOMP_CMP1_CTRL[7:6] INTTYPE1 01: Rising Edge
10: Falling Edge
11: Both rising and falling edges
Comparator0 Interrupt: hardware sets this interrupt when Comparator0 triggers. Write
LPCOMP_INTR[0] COMP0
a '1' to clear the interrupt
Comparator1 Interrupt: hardware sets this interrupt when Comparator1 triggers. Write
LPCOMP_INTR[1] COMP1
a '1' to clear the interrupt
LPCOMP_INTR_SET[0] COMP0 Write a '1' to trigger the software interrupt for Comparator0
LPCOMP_INTR_SET[1] COMP1 Write a 1 to trigger the software interrupt for Comparator1

37.2.3 Power Mode and Speed Configuration

The Low-Power comparators can operate in three power modes:
■ Normal
■ Low-power
■ Ultra low-power

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 Low-Power Comparator

The power or speed setting for Comparator0 is configured using the MODE0 bitfield of the LPCOMP_CMP0_CTRL register.
Similarly, the power or speed setting for Comparator1 is configured using the MODE1 bitfield of the LPCOMP_CMP1_CTRL
register. The power consumption and response time vary depending on the selected power mode; power consumption is
highest in fast mode and lowest in ultra-low-power mode, response time is fastest in fast mode and slowest in ultra-low-power
mode. Refer to the PSoC 61 datasheet/PSoC 62 datasheet for specifications for the response time and power consumption
for various power settings.
The comparators can also be enabled or disabled using these bitfields, as described in Table 37-2.
Note: The output of the comparator may glitch when the power mode is changed while comparator is enabled. To avoid this,
disable the comparator before changing the power mode.

Table 37-2. Comparator Power Mode Selection Bits

Register[Bit_Pos] Bit_Name Description
Compartor0 power mode selection
00: Off
01: Ultra low-power operating mode. This mode must be used when the device is in
LPCOMP_CMP0_CTRL[1:0] MODE0 Deep Sleep or Hibernate mode.
10: Low-power operating mode
11: Normal, full-speed, full-power operating mode
See the datasheet for electrical specifications in each power mode.
Compartor1 power mode selection
00: Off
01: Ultra low-power operating mode. This mode must be used when the device is in
LPCOMP_CMP1_CTRL[1:0] MODE1 Deep Sleep or Hibernate mode.
10: Low-power operating mode
11: Normal, full-speed, full-power operating mode
See the datasheet for electrical specifications in each power mode.

Additionally, the entire Low-Power comparator system can be enabled or disabled globally using the LPCOMP_CONFIG[31]
bit. See the registers TRM for details of these bitfields.

37.2.4 Hysteresis
For applications that compare signals close to each other and slow changing signals, hysteresis helps to avoid oscillations at
the comparator output when the signals are noisy. For such applications, a fixed hysteresis may be enabled in the comparator
block. See the PSoC 61 datasheet/PSoC 62 datasheet for the hysteresis voltage range.
The hysteresis level is enabled/disabled by using the HYST0 and HYST1 bitfields in the LPCOMP_CMP0_CTRL and
LPCOMP_CMP1_CTRL registers for Comparator0 and Comparator1, as described in Table 37-3.

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 Low-Power Comparator

Table 37-3. Hysteresis Control Bits

Register[Bit_Pos] Bit_Name Description
Enable/Disable hysteresis to Comparator0
1: Enable Hysteresis
LPCOMP_CMP0_CTRL[5] HYST0
0: Disable Hysteresis
See the datasheet for hysteresis voltage range.
Enable/Disable hysteresis to Comparator1
1: Enable Hysteresis
LPCOMP_CMP1_CTRL[5] HYST1
0: Disable Hysteresis
See the datasheet for hysteresis voltage range.

37.2.5 Wakeup from Low-Power Modes

The comparator is operational in the device’s low-power modes, including Sleep, Deep Sleep, and Hibernate modes. The
comparator output can wake the device from Sleep and Deep Sleep modes. The comparator output can generate interrupts in
Deep Sleep mode when enabled in the LPCOMP_CONFIG register, the INTTYPEx bits in the LPCOMP_CMPx_CTRL
register should not be set to disabled, and the INTR_MASKx bit should be set in the LPCOMP_INTR_MASK register for the
corresponding comparator to wake the device from low-power modes. Comparisons involving AMUXBUS connections are not
available in Deep Sleep and Hibernate modes. Moreover, if the comparator is required in Deep Sleep or Hibernate modes,
then it must be configured into Ultra Low-Power mode before the device is put into Deep Sleep or Hibernate mode.
In the Deep Sleep and Hibernate power modes, a compare event on either Comparator0 or Comparator1 output will generate
a wakeup interrupt. The INTTYPEx bits in the LPCOMP_CONFIG register should be properly configured. The mask bits in the
LPCOMP_INTR_MASK register is used to select whether one or both of the comparator’s interrupt is serviced by the CPU.
See the Device Power Modes chapter on page 225 for more details.

37.2.6 Comparator Clock

The comparator uses the system main clock SYSCLK as the clock for interrupt and output synchronization. See the Clocking
System chapter on page 242 for more details.

37.3 Register List

Table 37-4. Low-Power Comparator Register Summary

Register Function
LPCOMP_CONFIG LPCOMP global configuration register
LPCOMP_INTR LPCOMP interrupt register
LPCOMP_INTR_SET LPCOMP interrupt set register
LPCOMP_INTR_MASK LPCOMP interrupt request mask register
LPCOMP_INTR_MASKED LPCOMP masked interrupt output register
LPCOMP_STATUS Output status register
LPCOMP_CMP0_CTRL Comparator0 configuration register
LPCOMP_CMP1_CTRL Comparator1 configuration
LPCOMP_CMP0_SW Comparator0 switch control
LPCOMP_CMP1_SW Comparator1 switch control
LPCOMP_CMP0_SW_CLEAR Comparator0 switch control clear
LPCOMP_CMP1_SW_CLEAR Comparator1 switch control clear

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 505
 38. SAR ADC

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

The PSoC 6 MCU has a 12-bit successive approximation register analog-to-digital converter (SAR ADC). The 12-bit, 1-Msps
SAR ADC is designed for applications that require moderate resolution and high data rate.

38.1 Features
■ Maximum sample rate of 1 Msps
■ Sixteen individually configurable logical channels that can scan eleven unique input channels. Each channel has the fol-
lowing features:
❐ Input from eight dedicated pins (eight single-ended mode or four differential inputs) or internal signals (AMUXBUS or
temperature sensor)
❐ Each channel may choose one of the four programmable acquisition times to compensate for external factors (such as
high input impedance sources with long settling times)
❐ Single-ended or differential measurement
❐ Averaging and accumulation
❐ Double-buffered results
■ Result may be left- or right-aligned, or may be represented in 16-bit sign extended
■ Scan can be triggered by firmware, trigger from other peripherals or pins
❐ One-shot – periodic or continuous mode
■ Hardware averaging support
❐ First order accumulate
❐ Supports 2, 4, 8, 16, 32, 64, 128, and 256 samples (powers of 2)
■ Selectable voltage references
❐ Internal VDDA and VDDA/2 references
❐ Internal 1.2-V reference with buffer
❐ External reference
■ Interrupt generation
❐ End of scan
❐ Saturation detect and over-range (configurable) detect for every channel
❐ Scan results overflow
❐ Collision detect

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 SAR ADC

38.2 Architecture
Figure 38-1. Block Diagram
External Reference or Bypass Capacitor
VREF Buffer
for Internal Reference
1.2V from AREF
Pin 0 VDDA
VDDA / 2
Pin 1
Pin 2
SAR_CTRL
Pin 3
Pins of SARMUX Port
Pin 4
VREF
Pin 5 VPLUS SAR_CHAN_WORK_UPDATED SAR_CHAN_RESULT_UPDATED
Accumulate /

SARMUX
Pin 6 Average /
SAR ADC SAR_CHAN_WORK0 SAR_CHAN_RESULT0
Pin 7 VMINUS Align / to to
Sign extend SAR_CHAN_WORK15 SAR_CHAN_RESULT15

Working Data Registers Conversion Result Registers

SARBUS0
SARBUS connects to
SAR_RANGE_COND
CTBm outputs SARBUS1
Saturation Range Detect SAR_RANGE_THRES
Connects to internal Temp Detect <,=,>
Temperature Sensor VSSA_KELVIN SAR_INTR_MASK
range_intr SAR_INTR_MASKED
SAR_INTR
saturate_intr
eos /
collision / sar_interrupt (to NVIC)
overflow_int
Hardware trigger from
other peripherals tr_sar_out
such as TCPWM
(used to start tr_sar_in Hardware trigger to other peripherals
Control Registers (occurs at end of sample (eos)
conversion)
SAR_CTRL
SAR_SAMPLE_CTRL Status Registers
SAR_SAMPLE_TIME01 SARSEQ SAR_STAT
SAR_SAMPLE_TIME23 SAR_AVG_STAT
SAR_CHAN_EN
SAR_CHAN_CONFIG0 to SAR_CHAN_CONFIG15
SAR_START_CTRL

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 SAR ADC

Figure 38-1 shows the simplified block diagram of PSoC 6 To get a single-ended conversion with 12 bits, you must con-
MCU SAR ADC system, with important registers shown in nect VREF to the negative input of the SAR ADC; then, the
blue. Preceding the SAR ADC is the SARMUX, which can input range can be from 0 to 2 × VREF.
route external pins and internal signals (AMUXBUS A/
AMUXBUS B or temperature sensor output) to the internal Note that temperature sensor can only be used in single-
channels of SAR ADC. The sequencer controller (SARSEQ) ended mode.
is used to control SARMUX and SAR ADC to do an auto-
matic scan on all enabled channels without CPU interven- 38.2.1.2 Input Range
tion. SARSEQ also performs pre-processing such as
All inputs should be in the range of VSSA to VDDA. Input volt-
averaging and accumulating the output data.
age range is also limited by VREF. If voltage on negative
The result from each channel is double-buffered and a com- input is Vn and the ADC reference is VREF, the range on the
plete scan may be configured to generate an interrupt at the positive input is Vn ± VREF. This criterion applies for both
end of the scan. The sequencer may also be configured to single-ended and differential modes. In single-ended mode,
flag overflow, collision, and saturation errors that can be Vn is connected to VSSA, VREF or an external input.
configured to assert an interrupt.
Note that Vn ± VREF should be in the range of VSSA to VDDA.
For example, if negative input is connected to VSSA, the
38.2.1 SAR ADC Core range on the positive input is 0 to VREF, not –VREF to VREF.
This is because the signal cannot go below VSSA. Only half
The PSoC 6 MCU SAR ADC core is a 12-bit SAR ADC. The
of the ADC range is usable because the positive input signal
maximum sample rate for this ADC is 1 Msps. The SAR
cannot swing below VSS, which effectively only generates
ADC core has the following features:
an 11-bit result.
■ Fully differential architecture; also supports single-ended
mode
■ 12-bit resolution
■ Four programmable acquisition times
■ Seven programmable power levels
■ Supports single and continuous conversion mode
SAR_CTRL register contains the bitfields that control the
operation of SAR ADC core. See the registers TRM for more
details of this register.

38.2.1.1 Single-ended and Differential Modes

The PSoC 6 MCU SAR ADC can operate in single-ended
and differential modes. Differential or single-ended mode
can be configured using the DIFFERENTIAL_EN bitfield in
the channel configuration register, SAR_CHAN_CONFIGx,
where x is the channel number (0–15).
SAR ADC gives full range output (0 to 4095) for differential
inputs in the range of –VREF to +VREF.

Note: The precise value of the input range in the differential

mode is –VREF to (+VREF – (VREF/2047)). The positive input
range is limited by the resolution of the ADC.
The single-ended mode options of negative input include
VSSA, VREF, or an external input from P1, P3, P5, or P7 pins
of SARMUX. See the PSoC 61 datasheet/PSoC 62 data-
sheet for the exact location of SARMUX pins. This mode is
configured by the NEG_SEL bitfield in the global configura-
tion register SAR_CTRL. When VMINUS is connected to
these SARMUX pins, the single-ended mode is equivalent
to differential mode. However, when the odd pin of each dif-
ferential pair is connected to the common alternate ground,
these conversions are 11-bit because measured signal
value cannot go below ground.

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 SAR ADC

Figure 38-2. Input Range

Single Ended Single Ended Differential
VMINUS = VSSA VMINUS = VREF

2 x VDD
5

Unusable Unusable Unusable

4 4 4
Range Range Range
VDD = 3.3 VDD = 3.3 VDD = 3.3
3 3 3 Usable

VREF = V DD
Usable Range
Usable
Range

VREF = V DD / 2
Range

VREF = V DD
2 2 2

VREF = V DD / 2
-Vin

VREF = 1.2
-Vin
-Vin

VREF = V DD / 2
1 1 1

VREF = V DD

VREF = 1.2
VREF = 1.2

0 0 0

-1 -1 -1
Unusable
Unusable Unusable Range
Range Range
-2 -2 -2

-VDD

38.2.1.3 Result Data Format

Result data format is configurable from two aspects:
■ Signed/unsigned
■ Left/right alignment
When the result is considered signed, the most significant bit of the conversion is used for sign extension to 16 bits with MSb.
For an unsigned conversion, the result is zero extended to 16-bits. The sample value can be either right-aligned or left-
aligned within the 16 bits of the result register. By default, data is right-aligned in data[11:0], with sign extension to 16 bits, if
required. Left-alignment will cause lower significant bits to be made zero.
Result data format can be controlled by DIFFERENTIAL_SIGNED, SINGLE_ENDED_SIGNED, and LEFT_ALIGN bitfields in
the SAR_SAMPLE_CTRL register.
The result data format can be shown as follows.

Table 38-1. Result Data Format

Signed/ Result Register

Alignment
Unsigned 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Right Unsigned – – – – 11 10 9 8 7 6 5 4 3 2 1 0
Right Signed 11 11 11 11 11 10 9 8 7 6 5 4 3 2 1 0
Left – 11 10 9 8 7 6 5 4 3 2 1 0 – – – –

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 SAR ADC

38.2.1.4 Negative Input Selection

The negative input connection choice affects the voltage range and effective resolution (Table 38-2). In single-ended mode,
negative input of the SAR ADC can be connected to VSSA, VREF, or P1, P3, P5, or P7 pins of SARMUX. Vx is the common

Table 38-2. Negative Input Selection Comparison

Single-ended/Differential Signed/Unsigned VMINUS VPLUS Range Result Register
+VREF 0x7FF
Single-ended N/Aa VSSA
VSSA = 0 0x000
+2 × VREF 0xFFF
Single-ended Unsigned VREF VREF 0x800
VSSA = 0 0
+2 × VREF 0x7FF
Single-ended Signed VREF VREF 0x000
VSSA = 0 0x800
Vx + VREF 0xFFF
Single-ended Unsigned Vxb Vx 0x800
Vx – VREF 0
Vx + VREF 0x7FF
Single-ended Signed Vx Vx 0x000
Vx – VREF 0x800
Vx + VREF 0xFFF
Differential Unsigned Vx Vx 0x800
Vx – VREF 0
Vx + VREF 0x7FF
Differential Signed Vx Vx 0x000
Vx – VREF 0x800
a. For single-ended mode with VMINUS connected to VSSA, conversions are effectively 11-bit because voltages cannot swing below VSSA on any PSoC 6 MCU
pin. Because of this, the global configuration bit SINGLE_ENDED_SIGNED (SAR_SAMPLE_CTRL[2]) will be ignored and the result is always (0x000-0x7FF).
b. Vx is the differential input common mode voltage.

mode voltage.
Note that single-ended conversions with VMINUS connected to the pins with SARMUX connectivity are electrically equivalent
to differential mode. However, when the odd pin of each differential pair is connected to the common alternate ground, these
conversions are 11-bit because measured signal value (SARMUX.vplus) cannot go below ground.

38.2.1.5 Acquisition Time

Acquisition time is the time taken by sample and hold (S/H) circuit inside SAR ADC to settle. After acquisition time, the input
signal source is disconnected from the SARADC core, and the output of the S/H circuit will be used for conversion. Each
channel can select one from four acquisition time options, from 4 to 1023 SAR clock cycles defined in global configuration
registers SAR_SAMPLE_TIME01 and SAR_SAMPLE_TIME23. These two registers contain four programmable sample
times ST0, ST1, ST2, and ST3. One of these four sample times can be selected for a particular channel by configuring the
SAMPLE_TIME_SEL bitfield in the respective SAR_CHAN_CONFIGx register.

PSoC 6 MCU: CY8C6xx8, CY8C6xxA Architecture TRM, Document No. 002-24529 Rev. *I 510
 SAR ADC

Figure 38-3. Acquisition Time

½ LSB
Inside PSoC 6
Signal
Source
RSRC RSW2 RSW1
VCSH ADC Core
SWACQ
DC CSHOLD

tACQ

SWACQ

ADC
Clocks

Acquisition Resolution + 2 Clocks

Time 4 Clocks 12bits + 2 = 14 Clocks

Minimum 12-Bit Conversion Time 18 Clocks

The acquisition time should be sufficient to charge the internal hold capacitor of the ADC through the resistance of the routing
path, as shown in Figure 38-3. The recommended value of acquisition time is:
Tacq >= 9 × (Rsrc + Rmux + Racqsw) × Csh
Where:
■ Rsrc = Source resistance
■ Rmux = SARMUX switch resistance
■ Racqsw = Sample and hold switch
■ Rmux + Racqsw ~= 1000 ohms
■ Csh ~= 10pF
This depends on the routing path (see Analog Routing on page 513 for details).

38.2.1.6 SAR ADC Clock

Note: The maximum SAR ADC clock frequency may be limited to less than 18 MHz by the PSoC 61 datasheet/PSoC 62
datasheet specification for sample rate maximum.
SAR ADC clock frequency must be between 1.8 MHz and 18 MHz, which comes from the peripheral clock (CLK_PERI) in the
system resources subsystem (SRSS). See the Clocking System chapter on page 242 to know how to configure the peripheral
clock.

38.2.1.7 SAR ADC Timing

As Figure 38-4 shows, an ADC conversion with the minimum acquisition time of four clocks requires 18 clocks to complete.
Note that the minimum acquisition time of four clock cycles at 36 MHz is based on the minimum acquisition time supported by
the SAR block (RSW1 and CSHOLD in Figure 38-3 on page 511), which is 97 ns.

Total clock cycles for valid output are equal to:

4 clock cycles for sampling input (minimum acquisition time set by SAR_SAMPLE_TIME01 or SAR_SAMPLE_TIME23)
+ 12 clock cycle conversions (with 12-bit resolution)
+ 1 clock for EOF output signal
+ 1 clock for continuous conversion mode and Auto-zero
=18 clock cycles.

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 SAR ADC

Figure 38-4. SAR ADC Timing

SARADC CLK

trigger

SOC

sample

18 clock cycles

State * SAMPLE G S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 F SAMPLE G S12 S11S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 F SAMPLE

EOC

Next

Data_out Data Data

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 SAR ADC

38.2.2 SARMUX
SARMUX is an analog dedicated programmable multiplexer. The main features of SARMUX are:
■ Controlled by sequencer controller block (SARSEQ) or firmware
■ Internal temperature sensor
■ Multiple inputs:
❐ Analog signals from pins (port 2)
❐ Temperature sensor output (settling time for the temperature sensor is about 1 µs)
❐ AMUXBUS A/AMUXBUS B

38.2.2.1 Analog Routing

SARMUX has many switches that may be controlled by SARSEQ block (sequencer controller) or firmware. Different control
methods have different control capability on the switches. Figure 38-5 shows the SARMUX switches. See the PSoC 61 data-
sheet/PSoC 62 datasheet for the exact location of SARMUX pins.
Figure 38-5. SARMUX Switches

Pin 0
MUX_FW_P0_VMINUS MUX_FW_P0_VPLUS

Pin 1
MUX_FW_P1_VMINUS MUX_FW_P1_VPLUS

Pin 2
MUX_FW_P2_VMINUS MUX_FW_P2_VPLUS

Pin 3
MUX_FW_P3_VMINUS MUX_FW_P3_VPLUS
Pins of SARMUX Port
Pin 4
MUX_FW_P4_VMINUS MUX_FW_P4_VPLUS

Pin 5
MUX_FW_P5_VMINUS MUX_FW_P5_VPLUS

Pin 6
MUX_FW_P6_VMINUS MUX_FW_P6_VPLUS

Pin 7
MUX_FW_P7_VMINUS MUX_FW_P7_VPLUS

AMUXBUS connects to AMUXBUS A

other pins / analog MUX_FW_AMUXBUSA_VMINUS MUX_FW_AMUXBUSA_VPLUS
peripherals
AMUXBUS B
MUX_FW_AMUXBUSB_VMINUS MUX_FW_AMUXBUSB_VPLUS

MUX_FW_TEMP_VPLUS

VSSA_KELVIN
MUX_FW_VSSA_VMINUS

Enable
VPLUS
Temp Temperature VSSA
Sensor SAR ADC
VMINUS

SARMUX

Sequencer control: In the sequencer control mode, the SARMUX switches are controlled by the SARSEQ block. After con-
figuring each channel’s analog routing, it enables multi-channel, automatic scan in a round-robin fashion, without CPU inter-
vention. Not every switch in analog routing can be controlled by the sequencer, as Figure 38-5 shows.

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 SAR ADC

SAR_MUX_SWITCH_SQ_CTRL register can be used to enable/disable SARSEQ control of SARMUX switches. See section
19.3.4 SARSEQ for more details of sequencer control.
Firmware control: In firmware control, registers are written by the firmware to connect required signals to VPLUS/VMINUS
terminals before starting the scan. Firmware can control every switch in SARMUX, as Figure 38-5 shows. However, firmware
control needs continuous CPU intervention for multi-channel scans. The SAR_MUX_SWITCH0 register can be used by the
firmware to control SARMUX switches. Note that additional register writes may be required to connect blocks outside the
SARMUX.
The PSoC 6 MCU analog interconnection is very flexible. SAR ADC can be connected to multiple inputs via SARMUX, includ-
ing both external pins and internal signals. It can also connect to non-SARMUX ports through AMUXBUS A/AMUXBUS B, at
the expense of scanning performance (more parasitic coupling, longer RC time to settle).

Input from SARMUX Port

In this mode, sequencer and firmware control are possible. In addition to SARMUX switch configuration, the GPIOs must be
configured properly to connect to SARMUX. See the I/O System chapter on page 261 for more details.

Input from Other Pins through AMUXBUS

Two pins that do not support SARMUX connectivity can be connected to SAR ADC as a differential pair. Additional switches
are required to connect these two pins to AMUXBUS A and AMUXBUS B, and then connect AMUXBUS A and AMUXBUS B
to the SAR ADC. See the I/O System chapter on page 261 for details of AMUXBUS connections.
The additional switches reduce the scanning performance (more parasitic coupling, longer RC time to settle). This is not rec-
ommended for external signals; the dedicated SARMUX port should be used, if possible. Moreover, sequencer control may
not be available if more than one AMUXBUS channel is required.

Input from Temperature Sensor

On-chip temperature sensor can be used to measure the device temperature. See the Temperature Sensor chapter on
page 520 for more details of this block. For temperature sensors, differential conversions are not available (conversion result
is undefined), thus always use it in singled-ended mode. Temperature sensor can be routed to positive input of SAR ADC
using a switch that can be controlled by the sequencer, or firmware. Setting the MUX_FW_TEMP_VPLUS bit in the
SAR_MUX_SWITCH0 register can enable the temperature sensor and connect its output to VPLUS of SAR ADC; clearing this
bit will disable temperature sensor by cutting off its bias current.

38.2.3 SARREF
The main features of the SAR reference block (SARREF) are:
■ Reference options: VDDA, VDDA/2, 1.2-V bandgap, and external reference
■ Reference buffer and bypass capacitor to enhance internal reference drive capability

38.2.3.1 Reference Options

SARREF generates VDDA and VDDA/2 voltages. In addition, it can take in a 1.2-V bandgap reference from AREF (see the
Analog Reference Block chapter on page 497 for details) or an external VREF connected to a dedicated pin (see the PSoC 61
datasheet/PSoC 62 datasheet for details). External VREF value should be between 1-V and VDDA.

The external VREF pin is also used to bypass the internal references. The VREF_SEL bitfield in the SAR_CTRL register can be
used to select which one of these references is connected to the SAR ADC.

38.2.3.2 Reference Buffer and Bypass Capacitors

The internal references, 1.2 V from bandgap and VDDA/2, are buffered with the reference buffer. This reference may be routed
to the external VREF pin where a capacitor can be used to filter noise that may exist on the reference.
The VREF_BYP_CAP_EN bitfield in the SAR_CTRL register can be used to enable the bypass capacitor. REFBUF_EN and
PWR_CTRL_VREF bitfields in the same register can be used to enable the buffer, and select one of seven available power
levels of the reference buffer respectively.

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 SAR ADC

SAR performance varies with the mode of reference and the VDDA supply.
Table 38-3. Reference Modes
Maximum SAR ADC
Reference Mode Maximum Sample Rate
Clock Frequency
External Reference 18 MHz 1 Msps
Internal reference without bypass capacitor 1.8 MHz 100 ksps
Internal reference with bypass capacitor 18 MHz 1 Msps
VDDA as reference 18 MHz 1 Msps

Reference buffer startup time varies with different bypass capacitor size. Table 38-4 lists two common values for the bypass
capacitor and its startup time specification. If reference selection is changed between scans or when scanning after device
low-power modes in which the ADC is not active (see the Device Power Modes chapter on page 225), make sure the refer-
ence buffer is settled before the SAR ADC starts sampling.
Table 38-4. Bypass Capacitor Values vs Startup Time
Capacitor Value Startup Time
Internal reference with bypass capacitor (50 nF) 120 µs
Internal reference with bypass capacitor (100 nF) 210 µs
Internal reference without bypass capacitor 10 µs

38.2.3.3 Input Range versus Reference ❐ One of four programmable acquisition times
❐ Result averaging and accumulation
All inputs should be between VSSA and VDDA. The ADCs
input range is limited by VREF selection. If negative input is ■ Scan triggering
Vn and the ADC reference is VREF, the range on the positive ❐ One-shot, periodic, or continuous mode
input is Vn ± VREF. These criteria applies for both single- ❐ Triggered by any digital signal or input from GPIO pin
ended and differential modes as long as both negative and ❐ Triggered by internal block
positive inputs stay within VSSA to VDDA. ❐ Software triggered
■ Hardware averaging support
38.2.4 SARSEQ ❐ First order accumulate
SARSEQ is a dedicated control block that automatically ❐ 2, 4, 8, 16, 32, 64, 128, or 256 samples averaging
sequences the input mux from one channel to the next while (powers of 2)
placing the result in an array of registers, one per channel. ❐ Results in 16-bit representation
SARSEQ has the following functions:
■ Double buffering of output data
■ Controls SARMUX analog routing automatically without
CPU intervention ❐ Left or right adjusted results

■ Controls SAR ADC core such as selecting acquisition ❐ Results in working register and result register
times ■ Interrupt generation
■ Receives data from SAR ADC and pre-process (aver- ❐ Finished scan conversion
age, range detect) ❐ Channel saturation detection
■ Results are double-buffered; therefore, the CPU can ❐ Range (configurable) detection
safely read the results of the last scan while the next
❐ Scan results overflow
scan is in progress.
❐ Collision detect
The features of SARSEQ are:
■ Sixteen channels can be individually enabled as an 38.2.4.1 Channel Configuration
automatic scan without CPU intervention that can scan
The SAR_CHAN_CONFIGx register contains the following
eleven unique input channels
bitfields, which control the behavior of respective channels
■ Each channel has the following features: during a SARSEQ scan:
❐ Single-ended or differential mode ■ POS_PORT_ADDR and POS_PIN_ADDR select the
❐ Input from external pin or internal signal (AMUXBUS/ connection to VPLUS terminal of the ADC
temperature sensor)

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 SAR ADC

■ NEG_ADDR_EN, NEG_PORT_ADDR, and kable range detect interrupt (RANGE_INTR). The following
NEG_PIN_ADDR select the connection to VMINUS termi- conditions can be selected:
nal of the ADC 0: result < RANGE_LOW (below the range)
■ SAMPLE_TIME_SEL selects the acquisition time for the
channel 1: RANGE_LOW  result < RANGE_HIGH (inside the
range)
■ AVG_EN enables the hardware averaging feature
■ DIFFERENTIAL_EN selects single-ended/differential 2: RANGE_HIGH  result (above the range)
mode 3: result < RANGE_LOW || RANGE_HIGH  result (outside
SAR_CHAN_EN contains the enable bits that can be used range)
to include or exclude a channel for the next SARSEQ scan. See Range Detection Interrupts on page 517 for details.

38.2.4.2 Averaging 38.2.4.4 Double Buffer

The SARSEQ block has a 20-bit accumulator and shift reg- Double buffering is used so that firmware can read the
ister to implement averaging. Averaging is performed after results of a complete scan while the next scan is in prog-
sign extension. The SAR_SAMPLE_CTRL register controls ress. The SAR ADC results are written to a set of working
the global averaging settings. registers until the scan is complete, at which time the data is
Each channel configuration register (SAR_CHAN_CONFIG) copied to a second set of registers where the data can be
has an enable bit (AVG_EN) to enable averaging. read by your application. This action allows sufficient time
for the firmware to read the previous scan before the pres-
The AVG_CNT bitfield in the SAR_SMAPLE_CTRL register ent scan is completed. All input channels are double buff-
specifies the number of accumulated samples (N) according ered with 16 registers.
to the formula:
SAR_CHAN_WORKx registers contain the working data
N=2^(AVG_CNT+1) N range = [2..256] and SAR_CHAN_RESULTx contain the buffered results of
the channels. The SAR_CHAN_WORK_UPDATED and
For example, if AVG_CNT = 3, then N = 16.
SAR_CHAN_RESULT_UPDATED registers can be used to
Because the conversion result is 12-bit and the maximum track if the working data and the result value of a channel is
value of N is 256 (left shift 8 bits), the 20-bit accumulator will updated.
never overflow.
The AVG_SHIFT bitfield in the SAR_SAMPLE_CTRL regis- 38.2.5 SAR Interrupts
ter is used to shift the accumulated result to get the aver- SAR ADC can generate interrupts on these events:
aged value. If this bit is set, the SAR sequencer performs
■ End of Scan – When scanning is complete for all the
sign extension and then accumulation. The accumulated
enabled channels.
result is then shifted right AVG_CNT + 1 bits to get the aver-
aged result. ■ Overflow – When the result register is updated before
the previous result is read.
The AVG_MODE bitfield in the SAR_SAMPLE_CTRL can
■ Collision – When a new trigger is received while the SAR
be used to select between accumulate-and-dump and inter-
ADC is still processing the previous trigger.
leaved averaging modes. If a channel is configured for accu-
mulate-and-dump averaging, the SARSEQ will take N ■ Range Detection – When the channel result meets the
consecutive samples of the specified channel before moving threshold value.
to the next channel. In the interleaved mode, one sample is ■ Saturation Detection – When the channel result is equal
taken per channel and averaged over several scans. to the minimum or maximum value.

38.2.4.3 Range Detection This section describes each interrupt in detail. These inter-
rupts have an interrupt mask in the SAR_INTR_MASK reg-
The SARSEQ supports range detection to allow automatic ister. By making the interrupt mask low, the corresponding
detection of result values compared to two programmable interrupt source is ignored. The SAR interrupt is generated if
thresholds without CPU involvement. Range detection is the interrupt mask bit is high and the corresponding interrupt
defined by the SAR_RANGE_THRES register. The source is pending.
RANGE_LOW field in the SAR_RANGE_THRES register
When servicing an interrupt, the interrupt service routine
defines the lower threshold and RANGE_HIGH field defines
(ISR) can clear the interrupt source by writing a ‘1’ to the
the upper threshold of the range.
corresponding interrupt bit in the SAR_RANGE_INTR regis-
The RANGE_COND bitfield in the SAR_RANGE_COND ter, after reading the data.
register define the condition that triggers a channel mas-

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 SAR ADC

The SAR_INTR_MASKED register is the logical AND set the collision interrupt, which is intended for debug and
between the interrupts sources and the interrupt mask. This verification.
register provides a convenient way for the firmware to deter-
mine the source of the interrupt. 38.2.5.4 Range Detection Interrupts
For verification and debug purposes, a set bit (such as Range detection interrupt flag can be set after averaging,
EOS_SET in the SAR_INTR_SET register) is used to trigger alignment, and sign extension (if applicable). This means it
each interrupt. This action allows the firmware to generate is not required to wait for the entire scan to complete to
an interrupt without the actual event occurring. determine whether a channel conversion is over-range. The
threshold values need to have the same data format as the
38.2.5.1 End-of-Scan Interrupt (EOS_INTR) result data.
After completing a scan, the end-of-scan interrupt Range detection interrupt for a specified channel can be
(EOS_INTR) is raised. Firmware should clear this interrupt masked by setting the SAR_RANGE_INTR_MASK register
after picking up the data from the RESULT registers. specified bit to ‘0’. Register SAR_RANGE_INTR_MASKED
reflects a bitwise AND between the interrupt request and
EOS_INTR can be masked by making the EOS_MASK bit 0
mask registers. If the value is not zero, then the SAR inter-
in the SAR_INTR_MASK register. EOS_MASKED bit of the
rupt signal to the NVIC is high.
SAR_INTR_MASKED register is the logic AND of the inter-
rupt flags and the interrupt masks. Writing a ‘1’ to EOS_SET SAR_RANGE_INTR_SET can be used for debug/verifica-
bit in SAR_INTR_SET register can set the EOS_INTR, tion. Write a ‘1’ to set the corresponding bit in the interrupt
which is intended for debug and verification. request register; when read, this register reflects the inter-
rupt request register.
38.2.5.2 Overflow Interrupt
There is a range detect interrupt for each channel
If a new scan completes and the hardware tries to set the (RANGE_INTR and INJ_RANGE_INTR).
EOS_INTR and EOS_INTR is still high (firmware does not
clear it fast enough), then an overflow interrupt (OVER- 38.2.5.5 Saturate Detection Interrupts
FLOW_INTR) is generated by the hardware. This usually
The saturation detection is always applied to every conver-
means that the firmware is unable to read the previous
sion. This feature detects if a sample value is equal to the
results before the current scan completes. In this case, the
minimum or maximum value and sets a maskable interrupt
old data is overwritten.
flag for the corresponding channel. This action allows the
OVERFLOW_INTR can be masked by making the OVER- firmware to take action, such as discarding the result, when
FLOW_MASK bit 0 in SAR_INTR_MASK register. OVER- the SAR ADC saturates. The sample value is tested right
FLOW_MASKED bit of SAR_INTR_MASKED register is the after conversion, before averaging. This means that the
logic AND of the interrupt flags and the interrupt masks, interrupt is set while the averaged result in the data register
which are for firmware convenience. Writing a ‘1’ to the is not equal to the minimum or maximum.
OVERFLOW_SET bit in SAR_INTR_SET register can set
Saturation interrupt flag is set immediately to enable a fast
OVERFLOW_INTR, which is intended for debug and verifi-
response to saturation, before the full scan and averaging.
cation.
Saturation detection interrupt for specified channel can be
masked by setting the SAR_SATURATE_INTR_MASK reg-
38.2.5.3 Collision Interrupt
ister specified bit to ‘0’. SAR_SATURATE_INTR_MASKED
It is possible that a new trigger is generated while the register reflects a bit-wise AND between the interrupt
SARSEQ is still busy with the scan started by the previous request and mask registers. If the value is not zero, then the
trigger. Therefore, the scan for the new trigger is delayed SAR interrupt signal to the NVIC is high.
until after the ongoing scan is completed. It is important to
SAR_SARTURATE_INTR_SET can be used for debug/veri-
notify the firmware that the new sample is invalid. This is
fication. Write a ‘1’ to set the corresponding bit in the inter-
done through the collision interrupt, which is raised any time
rupt request register; when read, this register reflects the
a new trigger, other than the continuous trigger, is received.
interrupt request register.
The collision interrupt for the firmware trigger (FW_COLLI-
SION_INTR) allows the firmware to identify which trigger 38.2.5.6 Interrupt Cause Overview
collided with an ongoing scan.
INTR_CAUSE register contains an overview of all the pend-
The collision interrupts can be masked by making the corre- ing SAR interrupts. It allows the ISR to determine the cause
sponding bit ‘0’ in the SAR_INTR_MASK register. The corre- of the interrupt. The register consists of a mirror copy of
sponding bit in the SAR_INTR_MASKED register is the logic SAR_INTR_MASKED. In addition, it has two bits that aggre-
AND of the interrupt flags and the interrupt masks. Writing a gate the range and saturate detection interrupts of all chan-
‘1’ to the corresponding bit in SAR_INTR_SET register can nels. It includes a logical OR of all the bits in

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 SAR ADC

RANGE_INTR_MASKED and SATURATE_INTR_MASKED

registers (does not include INJ_RANGE_INTR and INJ_-
SATURATE_INTR).

38.2.6 Trigger
A scan can be triggered in the following ways:
■ A firmware or one-shot trigger is generated when the
firmware writes to the FW_TRIGGER bit of the
SAR_START_CTRL register. After the scan is com-
pleted, the SARSEQ clears the FW_TRIGGER bit and
goes back to idle mode waiting for the next trigger. The
FW_TRIGGER bit is cleared immediately after the SAR
is disabled.
■ Trigger from other peripherals through the trigger multi-
plexer (see the Trigger Multiplexer Block chapter on
page 294 for more details).
■ A continuous trigger is activated by setting the CONTIN-
UOUS bit in SAR_SAMPLE_CTRL register. In this
mode, after completing a scan the SARSEQ starts the
next scan immediately; therefore, the SARSEQ is
always BUSY. As a result, all other triggers are essen-
tially ignored. Note that FW_TRIGGER will still get
cleared by hardware on the next completion.
For firmware continuous trigger, it takes only one SAR ADC
clock cycle before the sequencer tells the SAR ADC to start
sampling (provided the sequencer is idle).

38.2.7 SAR ADC Status

The current SAR status can be observed through the BUSY
and CUR_CHAN fields in the SAR_STATUS register. The
BUSY bit is high whenever the SAR is busy sampling or
converting a channel; the CUR_CHAN bits indicate the
number of the current channel being sampled.
SW_VREF_NEG bit indicates the current switch status,
including register controls, of the switch in the SAR ADC
that shorts NEG with VREF input.

The CUR_AVG_ACCU and CUR_AVG_CNT fields in the

SAR_AVG_STAT register indicate the current averaging
accumulator contents and the current sample counter value
for averaging (counts down).
The SAR_MUX_SWITCH_STATUS register gives the cur-
rent switch status of MUX_SWITCH0 register. These status
registers help to debug SAR behavior.

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 SAR ADC

38.3 Registers
Name Description
SAR_CTRL Global configuration register. Analog control register
SAR_SAMPLE_CTRL Global configuration register. Sample control register
SAR_SAMPLE_TIME01 Global configuration register. Sample time specification ST0 and ST1
SAR_SAMPLE_TIME23 Global configuration register. Sample time specification ST2 and ST3
SAR_RANGE_THRES Global range detect threshold register
SAR_RANGE_COND Global range detect mode register
SAR_CHAN_EN Enable bits for the channels
SAR_START_CTRL Start control register (firmware trigger)
SAR_CHAN_CONFIGx Channel configuration register. There are 16 such registers with x = 0 to 15
SAR_CHAN_WORKx Channel working data register. There are 16 such registers with x = 0 to 15
SAR_CHAN_RESULTx Channel result data register. There are 16 such registers with x = 0 to 15
SAR_CHAN_WORK_UPDATED Channel working data register: updated bits
SAR_CHAN_RESULT_UPDATED Channel result data register: updated bits
SAR_STATUS Current status of internal SAR registers (for debug)
SAR_AVG_STAT Current averaging status (for debug)
SAR_INTR Interrupt request register
SAR_INTR_SET Interrupt set request register
SAR_INTR_MASK Interrupt mask register
SAR_INTR_MASKED Interrupt masked request register
SAR_SATURATE_INTR Saturate interrupt request register
SAR_SATURATE_INTR_SET Saturate interrupt set request register
SAR_SATURATE_INTR_MASK Saturate interrupt mask register
SAR_SATURATE_INTR_MASKED Saturate interrupt masked request register
SAR_RANGE_INTR Range detect interrupt request register
SAR_RANGE_INTR_SET Range detect interrupt set request register
SAR_RANGE_INTR_MASK Range detect interrupt mask register
SAR_RANGE_INTR_MASKED Range interrupt masked request register
SAR_INTR_CAUSE Interrupt cause register
SAR_MUX_SWITCH0 SARMUX firmware switch controls
SAR_MUX_SWITCH_CLEAR0 SARMUX firmware switch control clear
SAR_MUX_SWITCH_SQ_CTRL SARMUX switch sequencer control
SAR_MUX_SWITCH_STATUS SARMUX switch status

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 39. Temperature Sensor

This PSoC 6 MCU technical reference manual (TRM) provides comprehensive and detailed information about the
functions of the PSoC 6 MCU device hardware. It is divided into two books: architecture TRM and registers TRM. The
TRM is not recommended for those new to the PSoC 6 MCU, nor as a guide for developing PSoC 6 MCU applications.
Use these documents instead:
■ PSoC 61 datasheet, PSoC 62 datasheet
■ Peripheral Driver Library (PDL) documentation
■ Application notes
■ Code examples

PSoC 6 MCUs have an on-chip temperature sensor that is used to measure the internal die temperature. The sensor consists
of a transistor connected in diode configuration.

39.1 Features
■ Measures device temperature
■ Voltage output can be internally connected to SAR ADC for digital readout
■ Factory calibrated parameters

39.2 Architecture
The temperature sensor consists of a single bipolar junction transistor (BJT) in the form of a diode. The transistor is biased
using a reference current IREF from the analog reference block (see the Analog Reference Block chapter on page 497 for
more details). Its base-to-emitter voltage (VBE) has a strong dependence on temperature at a constant collector current and
zero collector-base voltage. This property is used to calculate the die temperature by measuring the VBE of the transistor
using the SAR ADC, as shown in Figure 39-1.

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 Temperature Sensor

Figure 39-1. Temperature Sensing Mechanism

Current from Analog
Reference Block

IREF
SAR_MUX_SWITCH0.MUX
_FW_TEMP_VPLUS

vplus
Temperature
Sensor
SAR ADC CPU
12 bit
vminus

SARMUX
vssa_kelvin
1.2 V

Vssa Vssa

The analog output from the sensor (VBE) is measured using the SAR ADC. Die temperature in °C can be calculated from the
ADC results as given in the following equation:
10
Temp =  A  SAR out + 2  B  + T adjust
Equation 39-1
■ Temp is the slope compensated temperature in °C represented as Q16.16 fixed point number format.
■ ‘A’ is the 16-bit multiplier constant. The value of A is determined using the PSoC 6 MCU characterization data of two point
slope calculation. It is calculated as given in the following equation.

100C –  – 40C 
A =  signed int   2  -------------------------------------------------------- 
16
  SAR 100C – SAR – 40C  Equation 39-2

Where,
SAR100C = ADC counts at 100 °C
SAR–40C = ADC counts at –40 °C
Constant ‘A’ is stored in a register SFLASH_SAR_TEMP_MULTIPLIER. See the registers TRM for more details.
■ ‘B’ is the 16-bit offset value. The value of B is determined on a per die basis by taking care of all the process variations
and the actual bias current (IREF) present in the chip. It is calculated as given in the following equation.

 6  A  SAR 100C 
B =  unsigned int   2 x100C –  --------------------------------
- 
  2
10
 Equation 39-3

Where,
SAR100C = ADC counts at 100 °C
Constant ‘B’ is stored in a register SFLASH_SAR_TEMP_OFFSET. See the registers TRM for more details.
■ Tadjust is the slope correction factor in °C. The temperature sensor is corrected for dual slopes using the slope correction
factor. It is evaluated based on the result obtained without slope correction, which is given by the following equation:

10
T initial =  A  SAR OUT + 2  B
Equation 39-4
If Tinitial is greater than the center value (15 °C), then Tadjust is given by the following equation.

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 Temperature Sensor

0.5C
T adjust =  -----------------------------------   100C  2 – T initial 
16
 100C – 15C  Equation 39-5
If Tinitial is less than center value, then Tadjust is given by the following equation.

0.5C
T adjust =  --------------------------------   40C  2 + T initial 
16
 40C + 15C  Equation 39-6
Figure 39-2. Temperature Error Compensation
Temperature
Error
Compensation curve
0.5 °C
Tadjust
0 °C

-0.5 °C
Sensor Error Curve

Actual Temperature
-40 °C 15 °C 100 °C

Note: A and B are 16-bit constants stored in flash during factory calibration. These constants are valid only with a specific
SAR ADC configuration. See 39.3 SAR ADC Configuration for Measurement for details.

39.3 SAR ADC Configuration for Measurement

The temperature sensor is routed to the SAR ADC for measurement. Configure the SAR ADC channel to connect to the
temperature sensor by writing ‘1’ to the MUX_FW_TEMP_VPLUS bit of the SAR_MUX_SWITCH0 register. This also routes
the reference current to the sensor. Note that if the SAR sequencer is used, the SAR_MUX_SWITCH_SQ_CTRL register also
needs to be written. Configure the selected channel to a single-ended mode with negative input connected to VSS.

Use the following SAR ADC parameters:

1. 12-bit resolution
2. Internal 1.2-V VREF
3. Right-aligned result
4. 100 ksps sample rate (for best performance)
5. Averaging can be enabled to reduce the noise. However, averaging count, averaging shift, and averaging mode should be
set so as to get a 12-bit result after averaging.
For details about the SAR ADC parameters and its configuration, see the SAR ADC chapter on page 506.

39.4 Algorithm
1. Get the digital output from the SAR ADC.
2. Fetch ‘A’ from SFLASH_SAR_TEMP_MULTIPLIER and ‘B’ from SFLASH_SAR_TEMP_OFFSET.
3. Calculate the die temperature using the following equation:
10
Temp =  A  SAR OUT + 2  B  + T ADJUST

For example, let A = 0xBC4B and B = 0x65B4. Assume that the output of SAR ADC (VBE) is 0x595 at a given tempera-
ture. Firmware does the following calculations:
a. Multiply A and VBE: 0xBC4B × 0x595 = (–17333)10 × (1429)10 = (–24768857)10
b. Multiply B and 1024: 0x65B4 × 0x400 = (26036)10 × (1024)10 = (26660864)10
c. Add the result of steps 1 and 2 to get Tinitial: (–24768857)10 + (26660864)10 = (1892007)10 = 0x1CDEA7

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 Temperature Sensor

d. Calculate Tadjust using Tinitial value: Tinitial is the upper 16 bits multiplied by 216, that is, 0x1C00 = (1835008)10. It is
greater than 15°C (0x1C - upper 16 bits). Use Equation 4 to calculate Tadjust. It comes to 0x6B1D = (27421)10
e. Add Tadjust to Tinitial: (1892007)10 + (27421)10 = (1919428)10 = 0x1D49C4
f. The integer part of temperature is the upper 16 bits = 0x001D = (29)10
g. The decimal part of temperature is the lower 16 bits = 0x4B13 = (0.18884)10
h. Combining the result of steps f and g, Temp = 29.18884 °C ~ 29.2°C

39.5 Registers
Name Description
SFLASH_SAR_TEMP_MULTIPLIER Multiplier constant 'A' as defined in Equation 39-1.
SFLASH_SAR_TEMP_OFFSET Constant 'B' as defined in Equation 39-1.

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 40. CapSense

The CapSense system can measure the self-capacitance of an electrode or the mutual capacitance between a pair of
electrodes. In addition to capacitive sensing, the CapSense system can function as an ADC to measure voltage on any GPIO
pin that supports the CapSense functionality.
The CapSense touch sensing method in PSoC 6 MCUs, which senses self-capacitance, is known as CapSense Sigma Delta
(CSD). Similarly, the mutual-capacitance sensing method is known as CapSense Cross-point (CSX). The CSD and CSX
touch sensing methods provide the industry’s best-in-class signal-to-noise ratio (SNR), high touch sensitivity, low-power
operation, and superior EMI performance.
CapSense touch sensing is a combination of hardware and firmware techniques. Therefore, use the CapSense component
provided by the ModusToolbox IDE to implement CapSense designs. See the PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details.

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