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TOPIC:

Computer Organization and Architecture

Timing and Control, Instruction Cycle, Interrupt

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 Timing and Control
• The timing for all register in computer is controlled by a master
clock generator.
• Control signals are generated in the control unit and provide
control inputs for the multiplexers, common bus, processor
registers, and accumulator.
• Two major types of control organizations:
-Hardwired Control
- Microprogrammed Control
• Hardwired control is implemented with gates, flip-flops,
decoders, and other digital circuits.
• In microprogrammed control, control information is stored in
control memory, and any required change or modification can
be done by updating the microprogram in the control memory.
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 Hardwired Control unit of basic Computer
.

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 Instruction Cycle
• A program residing in the memory unit of computer consists of
a sequence of instructions.
• The program is executed in the computer by going through a
cycle for each instruction.
• Each instruction cycle is subdivided into sequence of subcycles
of phases.
– 1. Fetch an instruction from memory
– 2. Decode the instruction
– 3. Read the effective address from memory if the information has an
indirect address.
– 4. Execute the instruction
• Upon completion of step 4, control goes back to step 1 to fetch, decode and
execute the next instruction.
• This process continues indefinitely unless a HALT instruction is encountered.
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 Example of Control Timing Signals
. At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC🡨0

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 Fetch and Decode
• Initially program counter PC is loaded with the address of first
instruction in the program. And sequence counter (SC) is
cleared to 0.
• After each clock pulse, SC is incremented by 1.
• The micro operations for the fetch and decode phase can be
specified by following register transfer statement.

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 Cont…
.

• Place the content

of PC onto the bus
by making the bus
selection inputs
S2 S1 S0=010.

• Transfer the
content of the bus
to AR.

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 Determine the Type of Instruction
• During time T3, the control unit determines the type of instruction that
was just read from the memory.

• Purpose is to determine the type of instruction by control unit whether it is

i. Memory Reference Instruction
ii. Register Reference Instruction
iii. I/O Instruction

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 Determine the Type of
Instruction- Flow Chart

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Memory reference instruction
 Memory reference instruction

• Memory reference instructions are those commands or instructions

which are in the custom to generate a reference to the memory and
approval to a program to have an approach to the commanded
information and that states as to from where the data is cache
continually. These instructions are known as Memory Reference
Instructions.
• There are seven memory reference instructions which are as follows &
AND
• The AND instruction implements the AND logic operation on the bit
collection from the register and the memory word that is determined by
the effective address. The result of this operation is moved back to the
register.
ADD
• The ADD instruction adds the content of the memory word that is
denoted by the effective address to the value of the register.
LDA

The LDA instruction shares the memory word denoted by the

effective address to the register.

STA
STA saves the content of the register into the memory word that
is defined by the effective address. The output is next used to
the common bus and the data input is linked to the bus. It
needed only one micro-operation.
 Memory reference
instruction
BUN
The Branch Unconditionally (BUN) instruction can send the instruction that is
determined by the effective address. They understand that the address of the next
instruction to be performed is held by the PC and it should be incremented by one
to receive the address of the next instruction in the sequence. If the control needs
to implement multiple instructions that are not next in the sequence, it can
execute the BUN instruction.
BSA
BSA stands for Branch and Save return Address. These instructions can branch a part
of the program (known as subroutine or procedure). When this instruction is
performed, BSA will store the address of the next instruction from the PC into a
memory location that is determined by the effective address.
ISZ
The Increment if Zero (ISZ) instruction increments the word determined by effective
address. If the incremented cost is zero, thus PC is incremented by 1. A negative
value is saved in the memory word through the programmer. It can influence the
zero value after getting incremented repeatedly. Thus, the PC is incremented and
the next instruction is skipped.
 1. AND to AC

⚫ This is an instruction that performs the AND logic

operation on pair of bits in AC and the Memory word
specified by effective address.
⚫ The result of the operation is transferred to AC.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6

 2. ADD to AC

⚫ This instruction adds the content of memory word

specified by effective address to the value to AC.
⚫ The sum is transferred to AC and the output carry Cout
is transferred to the E (extended AC) flip-flop.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6

 3. LDA : Load to Ac

⚫ This instruction transferred the content of memory

word specified by effective address to the AC.

⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6

 4. STA : Store AC

⚫ This instruction store the content of AC in to the

memory word specified by effective address .
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 5

 5. BUN: Branch
Unconditionally

⚫ This instruction transfers the program to the

instruction specified by the effective address. PC holds
the address of instruction to be read from memory in
the next instruction cycle.
⚫ It allows the programmer to specify an instruction out
of sequence.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 5

 6. BSA: Branch and Save
return Address

⚫ This instruction is useful for branching to a portion of

the program called a subroutine or procedure.
⚫ 1st it stores the address of next instruction in sequence
into memory location specified by effective address.
Then effective address plus one is transferred to PC to
serve the address of next instruction.
⚫ The microoperation performed this operation are:

⚫ Total time cycle = 6

 Control Flowchart
6. BSA:
 7. INZ: Increment
and Skip if Zero

⚫ This instruction increments the word specified by the

effective address, and if increment value is equal to
zero, PC is incremented by 1.

⚫ The microoperation performed this operation are:

⚫ Total time cycle = 7

Input-Output and Interrupt
 Introduction
⚫ A Computer can serve no useful purpose unless it
communicates with the external environment.
⚫ Instructions and data stored in memory must come from some
input device.
⚫ Computational results must be transmitted to user through
some output device.
⚫ Commercial computers include many types of input and output
devices.
⚫ To demonstrate the most basic requirements for input and
output communication, we will use as a illustration a terminal
unit with a keyboard and printer.
 Input-Output
Configuration

⚫ The terminal sends and receives serial information.

⚫ Each quantity of information has eight bits of an
alphanumeric code.
⚫ The serial information from the keyboard is shifted
into the input register INPR.
⚫ The serial information for printer is stored in output
register OUTR.
⚫ These two registers communicate with
communication interface serially and with the AC in
parallel.
Input-Output
Configuration
 Input-Output Flags

1 bit input flag FGI is a control flip-flop. The flag bit is 1 when new information
is available in input device and cleared to zero when accepted by computer.
Flag is used to synchronize the timing rate difference between input device
and computer.
Initially FGI is set to 0. when a key is struck in the keyboard, an 8-bit
alphanumeric code is shifted in to INPR and the input flag FGI is set to 1.

The output register OUTR works similarly but the direction of information flow
is reversed.
Initially, the output flag FGO is set to 1.
Computer checks FGO, and if it is 1, the information from AC is transferred in
a parallel to OUTR and FGO is cleared to 0.
 Input-Output
Instructions.
⚫ For this type of information I=1, and
D7 (i.e. IR(12-14)=111)
⚫ For basic Computer only 6 input-output instruction.
 Program Interrupt
⚫ An alternative to the programmed controlled procedure is
to let the external device inform the computer when it is
ready for the transfer.
⚫ In the meantime computer can be busy with other tasks.
⚫ This type of transfer use the interrupt facility. While
computer is running the program, it does not check the
flags, however when a flag is set then computer receives an
interrupt.
⚫ The interrupt enable flip-flop IEN can be set and cleared
with two instructions.
⚫ When IEN is cleared to zero (with IOF instruction), the
flag can not interrupt the computer.
⚫ When IEN is cleared to 1 (with ION instruction), the
computer can be interrupted.
Flowchart of
Interrupt cycle
Interrupt E.g.

M[0] <- PC
PC <-M[1]
 Interrupt cycle

⚫ Here the modified fetch and decode phase of interrupt

cycles as follow:
Thank You

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 Question Practice

1. How many flip flops are required to design

Mod-82.
2. A 4-bit serial-in-parallel-out shift register is
initially set to 1011. The data 1110 is applied
to the input. List the sequence of states after
each shift for 3 clock cycles. Illustrate the
same using a timing diagram.

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 Question Practice

3. A computer uses a memory unit with 65536 words of 32 bits each. A binary
instruction code is stored in one word of memory. The instruction has four
parts: an indirect bit, an operation code, a register code part to specify one
of 1024 registers and an address part.
(i). How many bits are there in the operation code, the register part, indirect bit
and the address part?
(ii). Draw an instruction word format and indicate the number of bits in each
part. •Memory unit with word size 65536, So number of address bits = 16
Resister 1024, Register code 10 bits.
Indirect bit 1 bit.
So, operation code = (32-10-16-1)=5 bits
•
Total 32 bits.
1 5 10 16
I Opcode Register Address

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4. A 4-bit shift register circuit configured for right-shift operation is shown in
the figure below. Given that the present state of the shift register is 1110,
then how many clock cycles are required to again reach the state 1110. List
the sequence of states of the four flip-flops after each shift. Illustrate the
same with a timing diagram.
5. An instruction at address 021 in the basic computer has an address part
equal to 083 (all numbers are in hexadecimal). The memory word at
address 083 contains the operand C73A and the content of AC
(Accumulator) is B239. Determine the contents of the registers at the end
of the execute phase: PC (Program Counter), AR (Address Register), AC and
IR (Instruction Register). Implement the problem using following operation
codes (Hexadecimal code):
i) AND (0083)
ii) CMA (7200)
iii) INC (7800)
iv) BUN (4520)
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Ans. 5
Step 1

PC AR DR AC IR
Initial 021 083 C73A B239 0083
AND
CMA
INC
BUN

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Ans. 5

PC AR DR AC IR
Initial 021 083 C73A B239 0083
AND 022 083 --- 8238 0083
CMA 022 083 ---- 4DC6 7200
INC 022 083 ---- B23A 7800
BUN 083 083 B239 4520

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6. JK Flip Flop and Discuss Race around condition. Master Slave Flip Flop.
7. Serial and Parallel transmission. 4 bit SIPO and PISO
8. Design a MOD counter which will count up to 1011 and restart from 0000
when we give clear to T or J-K flip-flop.
9. Instruction cycle
10. Interrupt cycle
11. Hardwired control unit
12. Instruction format
13. Common bus system

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Ans. 5

PC AR AC IR
Initial 021 083 B239 0083
AND 022 083 8238 0083
CMA 022 083 4DC6 7200

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Ans. 5

PC AR AC IR
Initial 021 083 B239 0083
AND 022 083 8238 0083
CMA 022 083 4DC6 7200

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