CIT-244 ELECTRONICS-II

4.1 Define sequential logic circuits.

A sequential circuit is a logical circuit, where the output depends on the present value of the input signal
as well as the sequence of past inputs. A sequential circuit is a combination of combinational circuit and
a storage element.
4.2 What is the difference between flip flop and latch?
The main difference between latches and flip-flops is in the method used for changing their state.
Whenever a multivibrator is enabled at transitional edge of a square-wave signal, we call it a flip-flop. If
a multivibrator is level triggered, it is called a latch.
4.3 Name the types of flip flops.
• RS Flip Flop
• D Flip Flop
• JK Flip Flop
• T Flip Flop
4.4 Describe RS flip flop.
A RS-flipflop is the simplest possible memory element. It is constructed by feeding the outputs of two
NOR or NAND gates back to the other NOR or NAND gates input.
4.5 What is meant by active low and active high latch?
An active low SR latch is a type of latch which is SET when S = 0 and RESET when R = 0. It is typically
designed by using NAND gates.
An active high SR latch is a type of latch which is SET when S = 1 and RESET when R = 1. It is typically
designed by using NOR gates.
4.6 Draw the circuit of active low RS latch.

4.7 Draw the truth table of active low RS latch.

4.8 Draw the circuit of active high RS latch.

4.9 Draw the truth table of active high RS latch.

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4.10 What is meant by reset condition in a flip flop?

If 𝑄𝑄 = 0 𝑎𝑎𝑎𝑎𝑎𝑎 𝑄𝑄� = 1 of a flip flop then this condition is called reset.
4.11 What is meant by set condition in a flip flop?
If 𝑄𝑄 = 1 𝑎𝑎𝑎𝑎𝑎𝑎 𝑄𝑄� = 0 of a flip flop then this condition is called set.
4.12 What do you mean by clock pulse?
A clock pulse is a time varying voltage signal applied to control the operation (triggering) of a flip flop
4.13 Describe D-flip flop.
The D flip flop ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1. The
Delay flip-flop is designed using a gated SR flip-flop with an inverter connected between the inputs
allowing for a single input D.
4.14 Draw the logic diagram of D flip flop?

4.15 Describe one-bit delay in D flip flop?

D Flip Flop is also called a delay flip flop because when the input data is provided to the D flip-flop, the
output follows the input data delay by one clock pulse. It is used to delay the change of state of its output
signal (Q) until the next rising edge of a clock timing input signal occurs.
4.16 Draw truth table of D flip flop.

4.17 Name the types of flip flop triggering.

• Level triggering
• Edge triggering
4.18 Differentiate between level and edge triggering.
In level triggering the circuit will become active when the gating or clock pulse is on a particular level low
or high. In edge triggering, the circuit becomes active at negative or positive edge of the clock signal.
4.19 Name the types of edge triggered flip flops.
• Negative edge triggering
• Positive edge triggering
4.20 Define low-level and high-level triggered flip flop.
In low-level triggered flip flop, the circuit is active when the clock signal is low and in high-level triggered
flip flop, the circuit is active when the clock signal is high.
4.21 Define negative edge and positive edge triggering.

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If the circuit is positive edge triggered, it will take input at exactly the time in which the clock signal goes
from low to high. Similarly, input is taken at exactly the time in which the clock signal goes from high to
low in negative edge triggering.
4.22 Describe JK-flip flop?
JK flip Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop
circuit. Both the S and the R inputs have now been replaced by two inputs called the J and K inputs,
respectively.
4.23 Draw the logic diagram of JK flip flop?

4.24 Draw truth table of JK flip flop.

4.25 How is a JK flip flop different from RS flip flop in its basic operation?
In J-K flip flop when both inputs are HIGH, the output toggles i.e. it changes from high to low and low to
high periodically when both the inputs are 1. For an SR flip flop, however, when both the inputs are HIGH,
we encounter an invalid state, which is not present for a JK flip flop.
4.26 What is toggle mode of JK flip flop?
In J-K flip flop when both inputs are HIGH, the output changes from high to low and low to high
periodically. It is called toggle mode of JK flip flop.
4.27 Define JK master slave flip flop?
The basic JK flip flop can be improved further by adding a second JK flip-flop to its output that is activated
on the complementary clock signal to produce a “Master-Slave JK flip flop”.
4.28 Define T-type flip flop.
The T or "toggle" flip-flop changes its output on each clock edge, giving an output, which is half the
frequency of the signal to the T input. The J input and K input of the JK flip flop are connected together
and provided with the T input.
4.29 What are synchronous inputs?
The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs
because they have an effect on the outputs (Q and not-Q) with the clock signal transitions.
4.30 What are asynchronous inputs?
Th extra inputs of a flip flop that can set or reset the flip-flop regardless of the status of the clock signal
are called asynchronous inputs. Typically, they’re called preset and clear inputs.
4.31 Enlist the applications of flip flops.

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• Storing data
• Shifting data
• Frequency division
• Counting pulses
4.32 Describe frequency division function of flip flop.
When the pulse waveform is applied to the clock input of a J-K flip-flop that is connected to toggle, the
frequency of the clock is divided by of the clock input. If more flip-flops are joined together, further division
of the clock frequency can be achieved.
4.33 What is multivibrator?
A multivibrator circuit is nothing but a switching circuit. It generates non-sinusoidal waves such as Square
waves, Rectangular waves and Saw tooth waves etc.
4.34 Define astable multivibrator.
An astable multivibrator has no stable states and therefore changes back and forth (oscillates) between
two unstable states without any external triggering.
4.35 Define bistable multivibrator.
A Bistable Multivibrator has two stable states. The circuit stays in any one of the two stable states. It
continues in that state, unless an external trigger pulse is given.
4.36 Define monostable multivibrator.
Monostable multivibrator has only ONE stable state, and produce a single output pulse when it is triggered
externally. It only returns back to their first original and stable state after a period of time determined by
the time constant of the RC circuit.
4.37 How is the rise and fall time of a pulse measured?
Rise time is typically measured from 10% to 90% of the maximum value. Conversely, fall time is the
measurement of the time it takes for the pulse to move from 90% to 10% of the maximum value.
4.38 What is meant by propagation delay?
The propagation delay of the flip flops means a small delay occurs between the clock edge and the flip
flop output, Q, becoming valid.
4.39 What is pulse width?
The pulse width is a measure of the elapsed time between the rising and falling edges of a single pulse
of electrical signals.
4.40 Define set up time of a flip flop.
Setup time is the required time duration that the input data MUST be stable before the triggering-edge of
the clock.
4.41 Define hold time of flip flop.
Hold time is the required duration that the input data MUST be stable after the triggering edge of the
clock.
4.42 How is the output pulse width set in IC type one shot?
An external resistor and capacitor connected are used to set up the 555 timer as a one-shot. The pulse
width of the output is determined by the time constant of R and C according to the following formula:
tW =1.1 RC.
4.43 Write two applications of 555 timer IC.
555 timer IC applications include: oscillators, pulse generation, pulse width modulation etc.