STEP BY STEP

JAIRAJ
Design Verification
MIRASHI

2 3
Synthesis
Place and Route

4 5
1 Specification

Mask
Static Timing
Analysis 6
Fabrication Preparation

9 8
System Physical
Integration Packaging Verification

12 11 10 7
Testing
1 Specification
IN THE SPECIFICATION STAGE, THE
REQUIREMENTS FOR THE ASIC ARE DEFINED.
THIS INCLUDES FUNCTIONALITY,
PERFORMANCE, POWER CONSUMPTION, AND
OTHER KEY PARAMETERS. THE SYSTEM
ARCHITECT AND THE CUSTOMER WORK ON
DEFINING THE SPECIFICATION.
2 Design
IN THE DESIGN STAGE, THE DIGITAL OR ANALOG
CIRCUIT DESIGN IS CREATED USING COMPUTER-AIDED
DESIGN (CAD) TOOLS. THE DIGITAL DESIGN ENGINEER
WORKS ON THE LOGICAL DESIGN OF THE CIRCUITS,
WHILE THE ANALOG DESIGN ENGINEER WORKS ON
THE DESIGN OF THE ANALOG AND MIXED-SIGNAL
CIRCUITS. THE DESIGN PROCESS INVOLVES VERIFYING
THE FUNCTIONALITY, TIMING, POWER CONSUMPTION,
AND OTHER PERFORMANCE METRICS OF THE CIRCUIT
USING SIMULATION TOOLS.
3 Verification
IN THE VERIFICATION STAGE, ENGINEERS USE
SIMULATION AND OTHER TOOLS TO ENSURE THAT
THE DESIGN WORKS CORRECTLY AND MEETS THE
SPECIFICATIONS. VERIFICATION ENGINEERS WORK
ON TESTING THE DESIGN AT DIFFERENT LEVELS OF
ABSTRACTION, INCLUDING FUNCTIONAL, TIMING, AND
POWER. THEY USE VARIOUS TECHNIQUES SUCH AS
SIMULATION, FORMAL VERIFICATION, AND
EMULATION TO ENSURE THAT THE DESIGN IS
CORRECT AND ROBUST.
4 Synthesis
IN THE SYNTHESIS STAGE, THE DESIGN IS
TRANSLATED INTO A NETLIST, WHICH IS A LIST OF
LOGIC GATES AND THEIR CONNECTIONS. THIS
NETLIST IS OPTIMIZED FOR AREA, TIMING, AND
POWER USING SYNTHESIS TOOLS. THE SYNTHESIS
ENGINEER WORKS ON OPTIMIZING THE DESIGN FOR
PERFORMANCE AND AREA.
5 Place and Route
IN THE PLACE AND ROUTE STAGE, THE NETLIST IS
MAPPED ONTO A PHYSICAL LAYOUT OF THE ASIC.
THIS INVOLVES PLACING THE CELLS AND ROUTING
THE WIRES BETWEEN THEM. THE PLACE AND
ROUTE ENGINEER WORKS ON OPTIMIZING THE
PLACEMENT AND ROUTING FOR TIMING, AREA, AND
POWER.
6 Static Timing Analysis
IN THE STATIC TIMING ANALYSIS STAGE, THE TIMING
OF THE DESIGN IS ANALYZED TO ENSURE THAT IT
MEETS THE TIMING REQUIREMENTS. THE STATIC
TIMING ANALYSIS ENGINEER WORKS ON
ANALYZING THE TIMING OF THE DESIGN AND
ENSURING THAT IT MEETS THE TIMING
CONSTRAINTS.
7 Physical Verification
IN THE PHYSICAL VERIFICATION STAGE, THE
PHYSICAL LAYOUT OF THE ASIC IS VERIFIED TO
ENSURE THAT IT IS CORRECT AND MEETS THE
DESIGN RULES. THIS INVOLVES CHECKING FOR
DESIGN RULE VIOLATIONS, SUCH AS MINIMUM
SPACING AND MINIMUM WIDTH VIOLATIONS. THE
PHYSICAL VERIFICATION ENGINEER WORKS ON
ENSURING THAT THE LAYOUT IS CORRECT AND CAN
BE MANUFACTURED.
8 Mask Preparation
IN THE MASK PREPARATION STAGE, THE PHYSICAL LAYOUT
IS USED TO CREATE THE MASK SET, WHICH IS A SET OF
PATTERNS THAT WILL BE USED TO CREATE THE ACTUAL
CIRCUIT ON THE SILICON WAFER. THE MASK PREPARATION
ENGINEER WORKS ON CREATING THE CORRECT PATTERN
FOR EACH LAYER OF THE CHIP. THIS INVOLVES
CONVERTING THE LAYOUT INTO A SET OF
PHOTOLITHOGRAPHY MASKS, WHICH ARE USED TO PATTERN
THE SILICON WAFER. THE MASK PREPARATION ENGINEER
NEEDS TO ENSURE THAT THE MASKS ARE CORRECTLY
ALIGNED AND THAT THE PATTERNS ARE OPTIMIZED FOR
THE PROCESS TECHNOLOGY.
9 Fabrication
IN THE FABRICATION STAGE, THE MASK SET IS USED
TO CREATE THE ASIC ON THE SILICON WAFER. THE
FABRICATION PROCESS INVOLVES SEVERAL STEPS,
SUCH AS PHOTOLITHOGRAPHY, DEPOSITION, ETCHING,
AND IMPLANTATION. THE FABRICATION ENGINEER
WORKS ON THE PROCESS OF CREATING THE
DIFFERENT LAYERS OF THE ASIC USING THESE
TECHNIQUES. THE FABRICATION PROCESS IS HIGHLY
AUTOMATED AND REQUIRES A CLEAN-ROOM
ENVIRONMENT TO ENSURE THE QUALITY AND
RELIABILITY OF THE ASIC.
10 Testing
IN THE TESTING STAGE, THE ASIC IS TESTED TO
ENSURE THAT IT WORKS CORRECTLY AND MEETS
THE SPECIFICATIONS. TESTING ENGINEERS WORK
ON DEVELOPING TEST PLANS AND TEST PATTERNS
TO VERIFY THE FUNCTIONALITY AND
PERFORMANCE OF THE ASIC. THEY USE VARIOUS
TECHNIQUES SUCH AS AUTOMATIC TEST EQUIPMENT
(ATE), SCAN CHAINS, AND BUILT-IN SELF-TEST
(BIST) TO TEST THE ASIC. THE TESTING PROCESS IS
CRITICAL TO ENSURING THE QUALITY AND
RELIABILITY OF THE ASIC.
11 Packaging
IN THE PACKAGING STAGE, THE ASIC IS ENCAPSULATED
IN A PACKAGE THAT PROVIDES ELECTRICAL
CONNECTIONS TO THE OUTSIDE WORLD AND PROTECTS
THE ASIC FROM ENVIRONMENTAL FACTORS SUCH AS
MOISTURE, TEMPERATURE, AND PHYSICAL DAMAGE. THE
PACKAGING ENGINEER WORKS ON SELECTING THE
APPROPRIATE PACKAGE FOR THE ASIC AND DESIGNING
THE LAYOUT OF THE PACKAGE. THE PACKAGING
PROCESS ALSO INVOLVES TESTING THE ASIC AFTER IT
IS PACKAGED TO ENSURE THAT IT STILL WORKS
CORRECTLY.
12 System Integration
IN THE SYSTEM INTEGRATION STAGE, THE ASIC IS
INTEGRATED INTO THE LARGER SYSTEM IN WHICH IT
WILL BE USED. THIS INVOLVES DESIGNING THE BOARD
OR SYSTEM THAT THE ASIC WILL BE MOUNTED ON, AS
WELL AS WRITING THE SOFTWARE THAT WILL RUN
ON THE SYSTEM. SYSTEM INTEGRATION ENGINEERS
WORK ON INTEGRATING THE ASIC INTO THE LARGER
SYSTEM, TESTING ITS FUNCTIONALITY, AND OPTIMIZING
ITS PERFORMANCE IN THE SYSTEM.