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Question Bank DSD III Sem

The document contains 13 questions related to modeling digital circuits in Verilog HDL. The questions cover topics such as modeling combinational and sequential circuits using gate level, dataflow, structural and behavioral modeling. It also includes questions on modeling counters, registers, RAM blocks and finite state machines. The questions ask to write testbenches to verify the functionality and performance parameters of the designed circuits.

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66 views4 pages

Question Bank DSD III Sem

The document contains 13 questions related to modeling digital circuits in Verilog HDL. The questions cover topics such as modeling combinational and sequential circuits using gate level, dataflow, structural and behavioral modeling. It also includes questions on modeling counters, registers, RAM blocks and finite state machines. The questions ask to write testbenches to verify the functionality and performance parameters of the designed circuits.

Uploaded by

asymtodegaming0501
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Question bank Digital System Design

Q1 Model following Combinational Circuits in Verilog HDL using gate primitives.


1. Full adder using Gates
2. Full subtractor
3. Half subtractor
4. 4:2 Encoder, 8:3 Encoder
5. 2:4 Decoder, 3:8 Decoder
6. 2:1 Mux, 4:1 Mux, 8: 1 Mux and 16:1 Mux
7. 1:2, 1:4, 1:8, 1:16 Demux
8. Ripple Carry Adder 4 bit

Write a test bench to test the above circuits by calculating the critical path delay of the circuit in
Vivado tool chain. Calculate the LUT count.

Q2 Model following Combinational Circuits in Verilog HDL using data flow Modeling
1. Full adder using equation
2. Full subtractor
3. Half subtractor
4. 4:2 Encoder, 8:3 Encoder
5. 2:4 Decoder, 3:8 Decoder
6. 2:1 Mux, 4:1 Mux, 8: 1 Mux and 16:1 Mux
7. 1:2, 1:4, 1:8, 1:16 Demux
Write a test bench to test the above circuits by calculating the critical path delay of the circuit in
Vivado tool chain. Calculate the LUT count. Use $monitor or $display in test bench to
demonstrate the results in console window

Q3 Model following Combinational Circuits in Verilog HDL using structural Modeling


1. Full adder using Gates
2. Full adder using two half adders
3. Full subtractor
4. Half subtractor
5. 4:2 Encoder, 8:3 Encoder
6. 2:4 Decoder, 3:8 Decoder
7. 2:1 Mux, 4:1 Mux, 8: 1 Mux and 16:1 Mux
8. 1:2, 1:4, 1:8, 1:16 Demux
9. Model 16 bit Adders. write a self check test bench to test these designs
a. Ripple Carry Adder 16 bit
b. Carry Look ahead adder 16 bit
c. Carry Select adder 16 bit
10. Model the following multiplier circuits. Write a self check test bench to test these designs.
(Find power dissipation for these multipliers)
a. 8 bit unsigned parallel multiplier
b. 8 bit signed multiplier
11. 8 bit adder using operators
12. 8 bit signed and unsigned multiplier using operators

Write a test bench to test the above circuits by calculating the critical path delay of the circuit in
Vivado tool chain. Calculate the LUT count. Calculate the power dissipation and compare the
performance parameters of 16 bit ripple carry adder, carry look ahead adder and carry select
adder. Use $monitor or $display in test bench to demonstrate the results in console window

Q5 Model following Circuits in Verilog HDL using behavioral Modeling

1. Full adder
2. Full subtractor
3. Half subtractor
4. 4:2 Encoder, 8:3 Encoder
5. Priority Encoder 8:3
6. 2:4 Decoder, 3:8 Decoder
7. 2:1 Mux, 4:1 Mux, 8: 1 Mux and 16:1 Mux
8. 1:2, 1:4, 1:8, 1:16 Demux
9. 8 bit adder using operators
10. 8 bit signed and unsigned multiplier using operators
11. Flip Flops with synchronous reset: D, Jk, T, JK master Slave, SR- test this circuit using a
test bench with clock frequency 10 KHz. (Negative edge triggered Clock)
i. Use If Else Statement
ii. Use Case Statement
12. Flip Flops with asynchronous reset: D, Jk, T, JK master Slave, SR- test this circuit using
a test bench with clock frequency 10 KHz. (Positive edge triggered Clock)
a. Use If Else Statement
b. Use Case Statement

13. 4 bit Counters with synchronous reset: Up counter , Down counter, Up - Down Counter,
Loadable counter Up - Down counter. (Negative edge triggered Clock)
14. 4 bit Counters with asynchronous reset: Up counter , Down counter, Up - Down Counter,
Loadable counter Up - Down counter. (Positive edge triggered Clock)
15. 4 bit Counters with asynchronous reset: Up counter , Down counter, Up - Down Counter,
Loadable counter Up - Down counter. (Positive edge triggered Clock)
16. 4 bit Counters with synchronous reset: Up counter , Down counter, Up - Down Counter,
Loadable counter Up - Down counter. (Positive edge triggered Clock)

Write a test bench to test the above circuits by calculating the critical path delay of the circuit in
Vivado tool chain. Calculate the LUT count. For Sequential circuits show the post
implementation timing simulation results.
Demonstrate the synchronous and asynchronous behavior of sequential circuits given above
using following test conditions.
- Activate reset for first 3 clock cycles, deactivate reset for next 10 clock cycles.
- After 10 clock cycles, again activate reset for 3 clock cycles. While doing this make sure
that if the circuit is positive edge triggered then reset should be activated at the negative
edge of the clock. Similarly if the circuit is negative edge triggered then the reset should
be activated at the positive edge of the clock.

Q6.A. Design a 4 bit Magnitude Comparator using Gates


B. Design a 8 bit Magnitude Comparator using Behavior modeling
Use $monitor or $display in test bench to demonstrate the results in console window

Q7. Design structural model and behavioral model for


-SISO, Discuss use of blocking and non blocking assignment to design SISO
- PIPO
- PISO
-SIPO

Test the above circuit using a suitable test bench. Assume clk frequency as 10 KHz.
Use $monitor or $display to demonstrate the results in console window

Q8 Design a 8 bit universal Shif Register. Test the circuit using suitable test bench

Q9 Design a 4 bit Mod -10 Counter using Verilog HDL

Q10 Design an Arbitrary counter that counts the following sequence

0, 2, 4, 5, 7, 0, 2, 4........
Write a test bench to test this design.

Q11. Model a verilog code to instantiate a 1 KB Block RAM on FPGA. Test the circuit using a
suitable test bench. Demonstrate the Memory read and write operations for single port and dual
port RAM.

Assume 20 Bytes data, to be written, is stored in the text file in the binary format. Write a test
bench to read this text file. Store the data in the first 20 locations of RAM. After successfully
storing the data, read the data back from the RAM and store it in the new text file.
Use $monitor or $display to demonstrate the results in console window
Q12 Model a sequence detector using verilog HDL for the following sequences
- 101010
- 111000
- 110011
Part a. Overlapping allowed
Part b. Overlapping not allowed
Part c. Model using Moore Machine
Part d. Model using Melay Machine

Q13. Demonstrate all Verilog Operators using suitable program.


Refer https://www.asic-world.com/verilog/operators2.html
1. Arithmetic Operators
2. Relational Operators
3. Equality Operators
4. Logical Operators
5. Bit-wise Operators
6. Reduction Operators
7. Shift Operators
8. Concatenation Operator
9. Replication Operator
10. Conditional Operators

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