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4 Jtag

The document discusses JTAG (Joint Test Action Group) testing. Some key points: 1) JTAG was originally intended for boundary scan testing to test connections between chips on a board. 2) Engineers later realized JTAG could also be used to test internal chip structures during testing. 3) JTAG uses standard protocols and allows test structures to be reused, providing advantages for testing.

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Jai Kiran R
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31 views10 pages

4 Jtag

The document discusses JTAG (Joint Test Action Group) testing. Some key points: 1) JTAG was originally intended for boundary scan testing to test connections between chips on a board. 2) Engineers later realized JTAG could also be used to test internal chip structures during testing. 3) JTAG uses standard protocols and allows test structures to be reused, providing advantages for testing.

Uploaded by

Jai Kiran R
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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By

Vamsy

JTAG
JTAG on Board

• Image You buy some 3 chips


and assembled on board
• You manager asks to test the
board and chips
JTAG
• The original motivation of JTAG usage is
Boundary scan testing
• This enables the testing on the
interconnections between devices that
are mounted on a circuit board.
• DFT Engineers realized that it need not
be limited to boundary but also can be
used to gain access on internal structure
during test.
• The main advantage of this design is it
can be reused and standard protocols.
JTAG I/O’s:
JTAG MODULE SAMPLE BLOCK:
Boundary scan
It gives the ability to gain the control on the I/O’s at the
boundary of chip
INPUT
BOUNDARY
SCAN CELL:

• It has 2 FF’s : capture/scan


FF and output FF.
• It also have 2 control
signals : Mode and ShiftDR
• 2 clock pins : ClockDR and
UpdateDR
• It supports 4 operations
ShiftDR = 1 , data
Mode = 0 , normal from Last scan cell to
operation of BSC , next scan cell for BS
data from PI to circuit operation using Clock
making BSC DR. This mode is not
transparent related to core scan
chain operation.
OPERATIONS
OF BSC: Mode = 1 , Update
operation , Load data
Shift DR =0 , data
from Scan FF to
captures at capture
Output FF to system
FF from PI, captures
logic, applying the
the test response
test patterns to
system logic
TAP Controller

• It is commonly used in block in


on chip testing
• It is at the heart of complete
JTAG network
• Understanding thoroughly
about TAP is essential for DFT
Engineers
• Abbreviation of TAP
• It is part of 1149.1 IEEE
standard
• It is 16 states FSM
JTAG NETWORK COMPLETE:

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