Project Report On PWM Generator using Verilog Submitted in the partial fulfilment of the requirements for the award of the degree of Bachelor of Technology (Hons.) in VLSI Design By Ashish Satpathy (2021 UGEC027) Mohit Singh (2021UGEC029) Nikhil Priyadarshi (2021UGEC030) Jay Prakash Kumar (2021UGEC031) Ashish Satpathy (2021UGEC032) Department of Electronics and Communication Engineering NATIONAL INSTITUTE OF TECHNOLOGY, JAMSHEDPUR JSHARKHAND-831014, INDIA November 2023TABLE OF CONTENTS PROJECT DETAILS VERILOG CODE BLOCK DIAGRAM RESULTS AND DISCUSSIONS CONCLUSION 12 3-6PROJECT DETAILS 1, Introduction: The Verilog PWM Generator with Variable Duty Cycle project focuses on designing and implementing a Pulse Width Modulation (PWM) generator using Verilog. This project builds upon a previous endeavor that involved a VHDL code for a PWM. generator. In this iteration, the focus is on Verilog, providing an alternative and versatile solution, 2. Project Objective: The primary goal of this project is to create a 10MHz PWM signal with a variable duty cycle. The duty cycle adjustment is facilitated through the integration of two debounced push buttons. One button increments the duty cycle by 10%, while the other button decreases it by 10%. 3. Features: PWM Signal Generation: The project generates a PWM signal with a frequency of 10MHz. Variable Duty Cycle: Users can dynamically adjust the duty cycle of the PWM signal Push Button Control: Two debounced push buttons facilitate duty cyele adjustment, Increment/Decrement: One button increases the duty cycle by 10%, and the other decreases it by 10%. 4. Implementation Details: Verilog Code: The core of the project lies in the Verilog code, which orchestrates the PWM signal generation and duty cycle control. Debouncing Mechanism: The push buttons are debounced to ensure reliable and stable input for duty eycle adjustment. Frequency Configuration: The PWM signal is configured to operate at a frequency of 10MHY, providing a balance between resolution and practicality. Variable Duty Cycle Logic: The Verilog code incorporates logic for adjusting the duty cycle based on user input.5. Components: FPGA Board: The Verilog PWM generator can be implemented on a suitable FPGA development board Push Buttons: Two push buttons are utilized for duty cycle control, Display (Optional): A display module can be added to visualize the current duty cycle. 6. Working Principle: Upon power-up, the system initializes with a default duty cycle. Users can press the increment button to raise the duty cycle or the decrement button to lower it The Verilog code processes the button inputs and adjusts the duty eycle accordingly. The PWM signal is output at a frequency of 10MHz with the updated duty cycle. 7. Applications: Motor Control: PWM signals are widely used in motor control applications to regulate speed. LED Brightness Control: The variable duty cycle can be employed to control the brightness of LEDs. Audio Systems: PWM is utilized in audio systems for amplification and modulation. 8. Conclusion: The Verilog PWM Generator with Variable Duty Cycle project demonstrates the flexibility and utility of Verilog in designing digital systems. By integrating debounced push buttons for duty cycle control, the project offers a practical solution for applications requiring dynamic PWM signal modulation. 9, Future Enhancements: Integration with External Devi Explore interfacing the PWM generator with external devices for real-world applications Advanced Control Mechanisms: Implement more sophisticated control mechanisms for duty cycle adjustment. Optimization: Fine-tune the Verilog code for efficiency and resource utilization,VERILOG CODE Verilog code for PWM generator with variable duty cycle: module PWM_Generator_Verilog C lk, // 100MEZz clock input inerease_duty, // input to increase 10% duty eyele decrease_duty, // input to decrease 10% duty cycle PWM_OUT // 10MHz PWM output signal ‘ input clk; input increase_duty; input decrease_duty; ‘output PWM_OUT; wire slow_elk_enable; // slow clock enable signal for debouncing FFs reg[27:0] counter_debounce=0;// counter for creating slow clock enable signa wire tmp1,tmp2,duty_ine;// temporary flip-flop signals for debouncing the increasing button wire tmp3,tmp4,duty_deey// temporary flip-flop signals for debouncing the decreasing button reg[3:0] counter_ PWM=| reg[3:0] DUTY_CYCLE- counter for creating 10Mhz PWM signal initial duty cycle is 50% Debouncing 2 buttons for inc/dec duty cycle Firstly generate slow clock enable for debouncing flip-flop (4Hz) always @(posedge clk) begin counter_debounce <= counter_debounce + 1; {f(counter_debounce>=25000000) then for running on FPGA -- comment when running simulation (counter_debounce>=1) for running simulation ~ omment when running on FPGAcounter_debounce <= 0; end assign slow_clk_enable = counter_debounce == 25000000 71:0; for running on FPGA .- comment when running simulation assign slow_clk_enable = counter_debounce == 1 1:0; for running simulation -- comment when running on FPGA debouncing FFs for increasing button DFF_PWM PWM_DEFI(clk,slow_clk_enable,increase_duty,tmp1); DFF_PWM PWM_DFF2(clk,slow_clk_enable,tmp1, tmp2); assign duty_inc= tmp1 & (~ tmp2) & slow_clk_enable; debouncing FFs for decreasing button DFF_PWM PWM_DFF3(clk,slow_clk_enable,decrease_duty, tmp3); DFF_PWM PWM_DFF4(clk,slow_clk_enable,tmp3, tmp4); assign duty_dec = tmp3 & (~ tmp4) & slow_clk_enable; vary the duty cycle using the debounced buttons above always @(posedge clk) begin if(duty_ine~-1 && DUTY_CYCLE <9) DUTY_CYCLE <= DUTY_CYCLE + 13// increase duty cycle by 10% else if(duty_dec—=1 && DUTY_CYCLE>=1) DUTY_CYCLE <= DUTY_CYCLE - Iy//deerease duty eyele by 10% end Create 10MHz PWM signal with variable duty cycle controlled by 2 buttons Iways @(posedge clk) begin counter_PWM <= counter_PWM + 1; if(counter_PWM>=9) counter_PWM <= 0; end assign PWM_OUT = counter_PWM < DUTY_CYCLE ? 1:0; endmoduleDebouncing DFFs for push buttons on FPGA module DFF_PWM(clk,en,D,Q); input clk,en,D; output reg Q; always @(posedge clk) begin if(ex=1) // slow clock enable signal QD; end endmodule Verilog Testbench code for PWM generator: “timescale Ins / Ips module th_PWM_Generator_Verilog; Inputs reg elk; reg increase_duty; reg decrease_duty; 1/ Outputs wire PWM_OUT; Instantiate the PWM Generator with variable duty cyele in Verilog PWM_Generator_Verilog PWM_Generator_Unit( sclk(elk), increase_duty(inerease_duty), sdecrease_duty(decrease_duty), -PWM_OUT(PWM_OUT) /| Create 100Mhz clock initial begin clk= 05 forever #5 elk = ~elk; end initial begin increase_duty = 0; decrease_duty = 0; #100;inerease_duty = 1; #1003// increase duty cycle by 10% increase_duty = 0; #100; increase_duty = 1; #100;// increase duty cycle by 10% inerease_duty = 0; #100; inerease_duty = 1; #1005// increase duty cycle by 10% increase_duty = 0; #100; decrease_duty = 1; #1003//decrease duty cycle by 10% decrease_duty = #100; decrease_duty = 1; #100;//decrease duty cycle by 10% ase_duty = dec #100; decrease_duty = 1; #100;//decrease duty cycle by 10% decrease_duty = end endmoduleBLOCK DIAGRAM Figure 1 Block diagram of PWMUPPM generator.RESULTS AND DISCUSSIONS Simulation waveforms generated by varying clock pulse and varying duty eycles: me Nob SBOE CE PRY ~ ForeCONCLUSION A PWM (Pulse Width Modulation) generator implemented in Verilog is a digital module designed to produce a waveform with variable duty eycle, The Verilog code for a PWM generator typically includes the following key components: Clock and Reset: The module is usually synchronized with a clock signal (clk), ensuring that the PWM waveform is generated at a regular interval. Input Signals: Relevant input signals may include a duty cycle control input, which determines the percentage of time the PWM signal is in the high state. Counter: A counter is often used to divide the clock cycles and determine the PWM signal period. The counter inerements on each clock cycle and resets when the desired period is reached. Comparator: The comparator compares the current count value with a threshold to decide when to set the PWM signal high or low. The threshold is determined by the duty eycle control input. Output: The PWM output is typically driven by the comparator's decision. When the counter value is below the threshold, the output is high; otherwise, it's low. This module increments a counter on each clock cycle and compares it to the duty cycle threshold. The output is high when the counter is less than the duty cycle and low otherwise, creating a PWM waveform. The counter resets on reaching its maximum value to complete one period.