Egyptian Russian University

Faculty of Artificial Intelligence

Sheet 4: Combinational Logic Circuits

1) Consider the flowing circuit. Derive the truth table

2) Implement the following Boolean Equation

__
Z = (a  b) + c • a

3) Show how to implement the function f ( w1 , w2 , w3 ) =  m (0,2,3,4,5,7 ) using a 3 x 8 binary decoder and
an OR gate. Write the VHDL code
4) Show how to implement the function f ( w1 , w2 , w3 ) =  m (1,2,3,5,6) using a 3 x 8 binary decoder and
an OR gate. Write the VHDL code
___ ___ ___ ___
5) Consider the function f = w1 w3 + w2 w3 + w1 w2 . Use the truth table to derive a circuit for f that uses a 2-
to-1 multiplexer
6) Find the truth table, and Boolean expressions for a digital circuit that counts the number of 1’s in a 4-bit
word code . Develop a VHDL behavior and structure model. Simulate the model
7) A two-out-of-five detector. The device receives an input a 5-bit parallel word. The output is a logic 1 for any
code word the has exactly two 1’s in it and a logic 0 otherwise. Find the truth table, logic diagram, and
Develop a behavior VHDL model. Simulate the model
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8) A parallel even-parity detector. The input is a 4-bit word code. The output is logic 1 if the number of 1’s is
even, and 0 if the number of 1’s is odd. Find the truth table, logic diagram, and Develop a behavior and
structural VHDL model. Simulate the model

9) Consider the following truth table. Find the truth table, and Boolean expressions. Develop a structure VHDL
model. Simulate the model
X2 X1 X0 F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

10) For the following circuit. Deduce the Boolean equations. Develop a behavioral and structure VHDL models
.

11) 3 x 8 decoder using two 2 x 4 decoder shown in the following figure. Find the structure VHDL model.
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12) Implement the following Boolean algebra function by

a) MUX 4 x 1 b) MUX 8 x 1
c) Decoder d) memory
F1 = ( 2,4,6,8,9 ) F2= ( 3,6,4,8,E,F )
13) Implement a full-adder circuit with
a) MUX b) decoder c) memory

14) For the following circuit. Deduce the Boolean equation. Develop a behavioral and structure VHDL
models.

F ( A, B , C , D ) =  (0,1,3,4,8,9,15)

15) From 32x4 memory Show how to get :

a) 64x4 memory b) 128x4 memory c) 32x8 memory d) 64x8 memory
16) Analyze the multiplexers network given in the following figure
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17) Show the tree of 2 x 1 multiplexers implementing the expression:

__ __ __ __ __ __ __
F ( A, B, C , D ) = A B + A B C + B C D + AB D + B CD
18) Analyze the network shown in the following figure and design a gate network using AND, OR, XOR, and
XNOR gates that implements the same function. (hint : Z=1 if the inputs to the decoder and the
multiplexer are identical.)

19) Implement the following Boolean equation:

b) F = (0,3,5,7,8) using
a) decoder
b) inverted decoder
20) Implement the following Boolean equation:
F = (0,3,5,7,8) using
a) 4 x 1 multiplexer
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b) 8 x 1 multiplexer
21) Implement the following Boolean equation:
F =  (2,5,8,7,8) using
a) 4 x 1 multiplexer
b) 8 x 1 multiplexer

22) Implement the following Boolean equation:

a) F =  (0,3,5,7,8) using decoder
23) Implement the following Boolean equation:
F =  (0,3,5,7,8) using
a) 4 x 1 multiplexer
b) 8 x 1 multiplexer
24) Implement a circuit that converts a binary number (4-bits) to its BCD using a 4-bit adder.
25) For the following figure
a) Find the Boolean Equation
b) Find the Truth Table

c) For the following waveforms of the input signals a,b, and c, find the waveforms at w,y, and z
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26) Implement a circuit that performs

a) A+B ,
b) A-B
where A and B are two 4-bit binary variables.
27) Implement a circuit that performs A+B and A-B
a) where A and B are two 4-bit binary variables.
28) Implement 2 x 4 decoder using elementary logic gates
29) Implement a 5 x 32 decoder using 3 x 8 decoder
30) Implement a 4 x 16 decoder using 2 x 4 decoder
31) Implement a 4 x 16 decoder using 3 x 8 decoder.
32) Implement a 4 x 1 multiplexer using elementary logic gates
33) Implement a 8 x 1 multiplexer using 4 x 1 multiplexer
34) Implement a 16 x 1 multiplexer using 8 x 1 multiplexer.
35) Implement a 16 x 1 multiplexer using 4 x 1 multiplexer.
36) Given F =  (0,1,2,3,4,8,9,12,13) . Implement F
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a) using 4 x 6 decoder
b) using 4 x 1 multiplexer and 8 x 1 multiplexer
37) F1 =  (0,1,2,3), and F2 =  (3,5,7 ) . Implement F1 and F2 using
a) PLA
b) PAL
c) ROM
38) Using a PLA, implement a system that converts from BCD-to-excess-3-code
39) Using a PLA, implement a system that produce the square of a BCD digit. The output should be in binary
representation
40) The following figure illustrates a simple CPU circuit that processes two 4-bit binary variables A and B (4-
bits). It contains and:
o four 4-bit registers
o two 4x1 multiplexers
o one 2x4 decoder
o ALU
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S8 S7 S6 Operation type
0 0 0 Binary addition
0 0 1 Binary subtraction
0 1 0 Binary multiplication
0 1 1 Binary division
1 0 0 OR
1 0 1 AND
1 1 0 XOR
1 1 1 XNOR

If the contents of the registers are:

A = (10)10 B = (9)10 C = (15)10 D = (13)10

a) Find the type and the operands for the operation corresponding of the controls given in the following table

Type and Contents of

Y S S S S S S S S S operand of registers after
8 7 6 5 4 3 2 1 0 the operation
operation MB A B CD
R
1 0 1 1 1 0 0 0 1 1
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0 0 1 0 1 0 1 1 1 0
1 1 0 1 0 1 0 0 0 0

b) Find the controls for the following operations listed in following table

S8 S S S S S S S S Type and operand of the

7 6 5 4 3 2 1 0 operation
A–B D
A or B C
A xor D MBR

41) Find following

a) Truth Table for full adders
b) Boolean Equation for Full adder
c) Implement the full adder using decoder
d) For the following waveforms for the input signals A, B, and Ci, find the waveforms of S and Co
42) If a= (27)10 and b=(33)10, find the value of the following :
a) Z1 = a  b
b) Z2 = a + b
c) Z3 = a • b
Express the results in binary and decimal systems
43) Find following
a) Truth Table for 1-bit comparators
b) Boolean Equation for 1-bit comparators
c) Implement the Full adder using decoder
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d) For the following waveforms for the input signals A, and B, find the waveforms of L, E and G

44) Implement 4x1 multiplexer using 3-state buffer

45) Implement 8x2 bidirectional RAM using 3-state buffer