Digital Logic Design and Computer Architecture 1

Module: 04
Design of Sequential Logic
Motivation:
Sequential elements, latches and flip flops dissipate power when there is switching in their internal
capacitance. This may happen with every clock transition/pulse into the sequential element.
Sometimes the sequential elements need to change their state, but sometimes they retain their state
and their output remains the same, before and after the clock pulse. This leads to unnecessary
dissipation of power due to clock transition. If flip flops are designed in such a way that they are
able to gate the clock with respective to their own internal data path, only to use the clock when
needed, power dissipation can be brought down.

Syllabus:
Lecture Content Duration Self-Study
no (Hrs)
(Hr)
1 Concepts of Flip Flops: SR, D Truth tables and 1 2
Excitation Tables
J-K Flip Flop, T Flip Flop with Truth table and
2 1 2
Excitation Table, Race around condition
Master Slave J- K Flip Flops, Flip-flop conversion
3 1 2
Counters: Design of Asynchronous and synchronous
4 1 2
counters
Modulus of L1, L2, L3 counters
5 1 2
UP-Down Counters
6 1 2
Shift Registers: SISO, SIPO, PIPO, PISO
7 1 2
Universal Shift Register
8 1 2
Ring and Twisted ring/Johnson Counter
9 1 2

Learning Objective:
Learners shall be able to:
1. To explain the concept of Latch.
2. To explain the concept of flip-flops like SR, D, J-K and T with truth tables and excitation tables.
3. To compare latch and flip-flop.
4. To design synchronous and asynchronous counters.
Module 04: Design of Sequential Circuit 2

5. To understand the working of shift registers.

Theoretical Background:
Digital electronics is classified into combinational logic and sequential logic. Combinational logic
output depends on the inputs levels, whereas sequential logic output depends on stored levels and
also the input levels. The memory elements are devices capable of storing binary info. The binary
information stored in the memory elements at any given time defines the state of the sequential
circuit. The input and the present state of the memory element determine the output. Memory
elements next state is also a function of external inputs and present state. A sequential circuit is
specified by a time sequence of inputs, outputs, and internal states. Examples of sequential circuits
are Flip-Flops, latches, counters, registers, and time state generators.
"Flip-flop" is the common name given to two-state devices which offer basic memory for sequential
logic operations. Flip-flops are heavily used for digital data storage and transfer and are commonly
used in banks called "registers" for the storage of binary numerical data.
Latches are flip-flops for which the timing of the output changes is not controlled. For a latch, the
output essentially responds immediately to changes on the input lines (and possibly the presence of
a clock pulse). A flip-flop is designed to change its output at the edge of a controlling clock signal.

Key Definitions:

Flip Flop: Flip-flop is the common name given to two-state devices which offer basic memory for
sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and are
commonly used in banks called "registers" for the storage of binary numerical data.

Latch: Latches are flip-flops for which the timing of the output changes is not controlled. For a
latch, the output essentially responds immediately to changes on the input lines (and possibly the
presence of a clock pulse).

Excitation Table: An excitation table shows the minimum inputs that are necessary to generate a
particular next state (in other words, to "excite" it to the next state) when the current state is known.
They are similar to truth tables and state tables, but rearrange the data so that the current state and
next state are next to each other on the left-hand side of the table, and the inputs needed to make
that state change happen are shown on the right side of the table.

Race around Condition: For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q
 Digital Logic Design and Computer Architecture 3

output will toggle as long as CLK is high, which makes the output of the flip-flop unstable or
uncertain. This problem is called race around condition in J-K flip-flop.

Asynchronous Counter: A digital counter in which all the flip-flop are not triggered
simultaneously.

DOWN Counter: A counter in which the count decreases with every clock pulse.

Synchronous Counter: A digital counter in which all the F/F are clocked simultaneously.

Left Shift Register: A shift register in which data gets shifted in the left direction in response to
clock pulses.

Right Shift Register: A shift register in which data gets shifted in the right direction in response to
clock pulses.

SR Flip Flop: SR flip-flop is basically a one-bit memory bistable device that has two inputs, one
which will “SET” the device (meaning the output = “1”), and is labelled S and one which will
“RESET” the device (meaning the output = “0”), labelled R.

JK Flip Flop: The JK flip flop is basically a gated SR flip-flop with the addition of a clock input
circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and
R are equal to logic level “1”.

Master-Slave JK Flip Flop: The master-slave flip-flop eliminates all the timing problems by using
two SR flip-flops connected together in a series configuration. One flip-flop acts as the “Master”
circuit, which triggers on the leading edge of the clock pulse while the other acts as the “Slave”
circuit, which triggers on the falling edge of the clock pulse. This results in the two sections, the
master section and the slave section being enabled during opposite half-cycles of the clock signal.

Course Content:
Lecture: 1

Introduction: SR latch
A Latch is a special type of logical circuit. The latches have low and high two stable states. Due to
Module 04: Design of Sequential Circuit 4

these states, latches also refer to as bistable-multivibrators. A latch is a storage device that holds
the data using the feedback lane. The latch stores 1 -bit until the device set to 1. The latch changes
the stored data and constantly trials the inputs when the enable input set to 1.
Based on the enable signal, the circuit works in two states. When the enable input is high, then both
the inputs are low, and when the enable input is low, both the inputs are high.
Types of Latches
There are various types of latches used in digital circuits which are as follows:
o SR Latch
o Gated S-R Latch
o D latch
o Gated D Latch
o JK Latch
o T Latch.
SR Latch
The SR latch is a special type of asynchronous device which works separately for control signals. It
depends on the S-states and R-inputs. The SR latch design by connecting two NOR gates with a
cross loop connection. The SR latch can also be designed using the NAND gate. Below are the
circuit diagram and the truth table of the SR latch.
Truth Table

S R Q Q'

0 0 latch Latch

0 1 0 1

1 0 1 0

1 1 0 0

Circuit Diagram
 Digital Logic Design and Computer Architecture 5

Gated SR Latch
A Gated SR Latch is a special type of SR Latch having three inputs, i.e., Set, Reset, and Enable. The
enable input must be active for the SET and RESET inputs to be effective.The ENABLE input of
gated SR Latch enables the operation of the SET and RESET inputs.This ENABLE input connects
with a switch. The Set-Reset inputs are enabled when this switch is on. Otherwise, all the changes
are ignored in the set and reset inputs. Below are the circuit diagram and the truth table of the
Gated SR latch.

Truth Table

Circuit Diagram
Module 04: Design of Sequential Circuit 6

Concepts of Flip Flops: SR, D Truth tables and Excitation Tables

Flip flops are an application of logic gates. A flip-flop circuit can remain in a binary state
indefinitely (as long as power is delivered to the circuit) until directed by an input signal to switch
states.
S-R flip-flop stands for SET-RESET flip-flops.
The SET-RESET flip-flop consists of two NOR gates and also two NAND gates.
These flip-flops are also called S-R Latch.
The design of these flip flops also includes two inputs, called the SET [S] and RESET [R]. There are
also two outputs, Q and Q'.
 Digital Logic Design and Computer Architecture 7

Clocked S-R Flip-Flop

The operation of a basic flip-flop can be modified by providing an additional control input that
determines when the state of the circuit is to be changed.
The limitation with a S-R flip-flop using NOR and NAND gate is the invalid state. This problem can
be overcome by using a stable SR flip-flop that can change outputs when certain invalid states are
met, regardless of the condition of either the Set or the Reset inputs.
Module 04: Design of Sequential Circuit 8

A clock pulse is given to the inputs of the AND Gate. If the value of the clock pulse is '0', the
outputs of both the AND Gates remain '0'.

D Flip-Flop
D flip-flop is a slight modification of clocked SR flip-flop.

From the above figure, you can see that the D input is connected to the S input and the complement
of the D input is connected to the R input.
When the value of CP is '1' (HIGH), the flip-flop moves to the SET state if it is '0' (LOW), the flip-
flop switches to the CLEAR state.
 Digital Logic Design and Computer Architecture 9

Let’s check the take away from this lecture

1) Latch is a device with ___________
a) One stable state
b) Two stable state
c) Three stable state
d) Infinite stable states
2) The SR latch consists of ___________
a) 1 input
b) 2 inputs
c) 3 inputs
d) 4 inputs
3) Why latches are called memory devices?
a) It has capability to stare 8 bits of data
b) It has internal memory of 4 bit
c) It can store one bit of data
d) It can store infinite amount of data
4) A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
a) AND or OR gates
b) XOR or XNOR gates
c) NOR or NAND gates
d) AND or NOR gates
5) In S-R flip-flop, if Q = 0 the output is said to be ___________
a) Set
b) Reset
c) Previous state
d) Current state
6) Which of the following is correct for a gated D-type flip-flop?
a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b) The output complement follows the input when enabled
c) Only one of the inputs can be HIGH at a time
d) The output toggles if one of the inputs is held HIGH
Module 04: Design of Sequential Circuit 10

Exercise
Q.1 Define Latch.
Q.2 Explain why latches are used as memory devices.
Q.3 Write the truth table for SR latch
Q.4 Define Flip flop
Q.5 Write the truth table for D flip flop

Learning from this lecture: Learners will be able to understand the concept of flip flops and the
working of SR and D Flip Flops.

Lecture: 2

J-K Flip Flop with Truth table and Excitation Table

J-K flip-flop can be considered as a modification of the S-R flip-flop.
The main difference is that the intermediate state is more refined and precise than that of an S-R
flip-flop.
 Digital Logic Design and Computer Architecture 11

The characteristics of inputs 'J' and 'K' is same as the 'S' and 'R' inputs of the S-R flip-flop.
J stands for SET, and 'K' stands for CLEAR.
When both the inputs J and K have a HIGH state, the flip-flop switches to the complement state, so,
for a value of Q = 1, it switches to Q=0, and for a value of Q = 0, it switches to Q=1.

T Flip Flop with Truth table and Excitation Table, Race around condition
T Flip-Flop
T flip-flop is a much simpler version of the J-K flip-flop.
Module 04: Design of Sequential Circuit 12

Both the J and K inputs are connected and are also called as a single input J-K Flip-flop.
Triggering of Flip-Flops
The state of the flip-flop is changed by a momentary change in the input signal. This momentary
change is known as Trigger, and the transition it causes is said to triggering the flip-flop.
Pulses trigger clocked flip-flops.
A pulse start from the initial value of '0', goes momentarily to '1', and after a short while, returns to
its initial '0' value.
A clock pulse is either positive or negative.
A positive clock source remains at '0' during the interval between pulses and goes to 1 during the
occurrence of a pulse.
The pulse goes through two signal transition: from '0' to '1' and return from '1' to '0'.
 Digital Logic Design and Computer Architecture 13

Definition of clock pulse transition:

The positive transition is defined as a positive edge and the negative transition as a negative edge.

Race around Condition

The following are the two cases where race around condition occurs:
1. When the S and R inputs of a SR flip flop is at logical 1, then the output becomes unstable and it is
known as race condition.
2. For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as long
as CLK is high, which makes the output of the flip-flop unstable or uncertain. This problem is called
race around condition in J-K flip-flop. This problem (Race Around Condition) can be avoided by
ensuring that the clock input is at logic “1” only for a very short time. This introduced the concept
of Master Slave JK flip flop.

Let’s check the take away from this lecture

1) When both inputs of a J-K flip-flop cycle, the output will ___________
a) Be invalid
b) Change
c) Not change
d) Toggle
2) The characteristic of J-K flip-flop is similar to _____________
a) S-R flip-flop
b) D flip-flop
c) T flip-flop
Module 04: Design of Sequential Circuit 14

d) Gated T flip-flop
3) How is a J-K flip-flop made to toggle?
a) J = 0, K = 0
b) J = 1, K = 0
c) J = 0, K = 1
d) J = 1, K = 1
4) Which of the following flip-flops is free from the race around the problem?
a) T flip-flop
b) SR flip-flop
c) Master-Slave Flip-flop
d) D flip-flop
5) Which of the following is not a sequential circuit?
a) Flip flop
b) Counter
c) Logical gate
d) Shift register
6) The T FF is called
a) delay flip-flop
b) trigger flip-flop
c) falling flip-flop
d) none of the above.

Exercise
Q.1 Define JK Flip Flop.
Q.2 Write the truth table for JK Flip Flop.
Q.3 State how JK Flip Flop is similar to SR Flip Flop.
Q.4 Define Race around condition.
Q.5 Write the truth table for T Flip Flop.
Q.6 Why is T Flip Flop called trigger Flip Flop?

Learning from this lecture: Learners will be able to understand the working of J-K Flip Flop, T Flip
Flop and the occurrence of race around condition.

Lecture: 3

Master Slave J- K Flip Flops, Timing Diagram

 Digital Logic Design and Computer Architecture 15

Master Slave J- K Flip Flop

The Master-Slave Flip-Flop is basically a combination of two JK flip-flops connected together in a
series configuration. Out of these, one acts as the “master” and the other as a “slave”. The output
from the master flip flop is connected to the two inputs of the slave flip flop whose output is fed
back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to
clock pulse in such a way that the inverted clock pulse is given to the slave flip-flop. In other words
if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if CP=1 for master flip flop then it
becomes 0 for slave flip flop.

Working of a master slave flip flop –

1. When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect the state of
the system. The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.
2. Firstly the master flip flop is positive level triggered and the slave flip flop is negative level
triggered, so the master responds before the slave.
3. If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave and the
clock forces the slave to reset, thus the slave copies the master.
4. If J=1 and K=0, the high Q output of the master goes to the J input of the slave and the
Negative transition of the clock sets the slave, copying the master.
5. If J=1 and K=1, it toggles on the positive transition of the clock and thus the slave toggles on
the negative transition of the clock.
6. If J=0 and K=0, the flip flop is disabled and Q remains unchanged.

Timing Diagram of a Master flip flop

Module 04: Design of Sequential Circuit 16

1. When the Clock pulse is high the output of master is high and remains high till the clock is
low because the state is stored.
2. Now the output of master becomes low when the clock pulse becomes high again and
remains low until the clock becomes high again.
3. Thus toggling takes place for a clock cycle.
4. When the clock pulse is high, the master is operational but not the slave thus the output of
the slave remains low till the clock remains high.
5. When the clock is low, the slave becomes operational and remains high until the clock again
becomes low.
6. Toggling takes place during the whole process since the output is changing once in a cycle.
This makes the Master-Slave J-K flip flop a Synchronous device as it only passes data with the
timing of the clock signal.

Flip-flop conversion
For the conversion of one flip flop to another, a combinational circuit has to be designed first. If a JK
Flip Flop is required, the inputs are given to the combinational circuit and the output of the
combinational circuit is connected to the inputs of the actual flip flop. Thus, the output of the actual
flip flop is the output of the required flip flop. In this section, the following flip flop conversions
will be explained.
• SR Flip Flop to JK Flip Flop
• JK Flip Flop to SR Flip Flop
• SR Flip Flop to D Flip Flop
• D Flip Flop to SR Flip Flop
• JK Flip Flop to T Flip Flop
• JK Flip Flop to D Flip Flop
 Digital Logic Design and Computer Architecture 17

• D Flip Flop to JK Flip Flop

SR Flip Flop to JK Flip Flop

As told earlier, J and K will be given as external inputs to S and R. As shown in the logic diagram
below, S and R will be the outputs of the combinational circuit.
The truth tables for the flip flop conversion are given below. The present state is represented by Qp
and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J, K and
Qp, the corresponding Qp+1 states are found. Qp+1 simply suggests the future values to be
obtained by the JK flip flop after the value of Qp. The table is then completed by writing the values
of S and R required to get each Qp+1 from the corresponding Qp. That is, the values of S and R that
are required to change the state of the flip flop from Qp to Qp+1 are written.

JK Flip Flop to SR Flip Flop

This will be the reverse process of the above explained conversion. S and R will be the external
inputs to J and K. As shown in the logic diagram below, J and K will be the outputs of the
combinational circuit. Thus, the values of J and K have to be obtained in terms of S, R and Qp. The
logic diagram is shown below.
Module 04: Design of Sequential Circuit 18

A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and R, eight
combinations are made. For each combination, the corresponding Qp+1 outputs are found ut. The
outputs for the combinations of S=1 and R=1 are not permitted for an SR flip flop. Thus the outputs
are considered invalid and the J and K values are taken as “don’t cares”.

SR Flip Flop to D Flip Flop

As shown in the figure, S and R are the actual inputs of the flip flop and D is the external input of
the flip flop. The four combinations, the logic diagram, conversion table, and the K-map for S and R
in terms of D and Qp are shown below.

D Flip Flop to SR Flip Flop

D is the actual input of the flip flop and S and R are the external inputs. Eight possible combinations
are achieved from the external inputs S, R and Qp. But, since the combination of S=1 and R=1 are
invalid, the values of Qp+1 and D are considered as “don’t cares”. The logic diagram showing the
conversion from D to SR, and the K-map for D in terms of S, R and Qp are shown below.
 Digital Logic Design and Computer Architecture 19

JK Flip Flop to T Flip Flop

J and K are the actual inputs of the flip flop and T is taken as the external input for conversion. Four
combinations are produced with T and Qp. J and K are expressed in terms of T and Qp. The
conversion table, K-maps, and the logic diagram are given below.

JK Flip Flop to D Flip Flop

D is the external input and J and K are the actual inputs of the flip flop. D and Qp make four
combinations. J and K are expressed in terms of D and Qp. The four combination conversion table,
the K-maps for J and K in terms of D and Qp, and the logic diagram showing the conversion from
JK to D are given below.
Module 04: Design of Sequential Circuit 20

D Flip Flop to JK Flip Flop

In this conversion, D is the actual input to the flip flop and J and K are the external inputs. J, K and
Qp make eight possible combinations, as shown in the conversion table below. D is expressed in
terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram showing the
conversion from D to JK are given in the figure below.

Let’s check the take away from this lecture

1) Master slave flip flop is also referred to as?
a) Level triggered flip flop
b) Pulse triggered flip flop
c) Edge triggered flip flop
d) Edge-Level triggered flip flop
2) The S-R, J-K and D inputs are called ____________
a) Asynchronous inputs
b) Synchronous inputs
c) Bidirectional inputs
d) Unidirectional inputs
3) On a master-slave flip-flop, when is the master enabled?
a) when the gate is LOW
b) when the gate is HIGH
c) both of the above
d) neither of the above
4) Which of the following describes the operation of a positive edge-triggered D flip-flop?
a) If both inputs are HIGH, the output will toggle.
b) The output will follow the input on the leading edge of the clock.
c) When both inputs are LOW, an invalid state exists.
 Digital Logic Design and Computer Architecture 21

d) The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output
on the trailing edge of the clock.
5) On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
a) the clock pulse is LOW
b) the clock pulse is HIGH
c) the clock pulse transitions from LOW to HIGH
d) the clock pulse transitions from HIGH to LOW
6) The difference between a flip-flop & latch is ____________
a) Both are same
b) Flip-flop consist of an extra output
c) Latches has one input but flip-flop has two
d) Latch has two inputs but flip-flop has one

Exercise
Q.1 Explain the need for master-slave JK FF.
Q.2 Explain the working of master-slave JK FF.
Q.3 Draw the timing diagram of master-slave JK FF and explain?
Q.4 Write steps to convert from one flip flop to another.
Q.5 List down the different flip flop conversions.
Q.6 Explain D flip flop to JK flip flop conversion.

Learning from this lecture: Learners will be able to understand the working of Master J-K Flip Flop
and the process of different flip flop conversions.

Lecture: 4
Counters: Design of Asynchronous and Synchronous Counters

Sequential circuits are divided into two main types: synchronous and asynchronous. Their
classification depends on the timing of their signals.

Synchronous sequential circuits change their states and output values at discrete instants of time,
which are specified by the rising and falling edge of a free-running clock signal. The clock signal is
generally some form of square wave as shown in Figure 2 below.
Module 04: Design of Sequential Circuit 22

From the diagram you can see that the clock period is the time between successive transitions in the
same direction, that is, between two rising or two falling edges. State transitions in synchronous
sequential circuits are made to take place at times when the clock is making a transition from 0 to 1
(rising edge) or from 1 to 0 (falling edge). Between successive clock pulses there is no change in the
information stored in memory.

The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined
as the time during which the value of the clock signal is equal to 1. The ratio of the clock width and
clock period is referred to as the duty cycle. A clock signal is said to be active high if the state
changes occur at the clock's rising edge or during the clock width. Otherwise, the clock is said to be
active low. Synchronous sequential circuits are also known as clocked sequential circuits.

The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits
are binary cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for
the normal value and one for the complement value of the bit stored in it. Binary information can
enter a flip-flop in a variety of ways, a fact which give rise to the different types of flip-flops. For
information on the different types of basic flip-flop circuits and their logical properties, see the
previous tutorial on flip-flops.

In asynchronous sequential circuits, the transition from one state to another is initiated by the
change in the primary inputs; there is no external synchronisation. The memory commonly used in
asynchronous sequential circuits are time-delayed devices, usually implemented by feedback
among logic gates. Thus, asynchronous sequential circuits may be regarded as combinational
circuits with feedback. Because of the feedback among logic gates, asynchronous sequential circuits
may, at times, become unstable due to transient conditions. The instability problem imposes many
difficulties on the designer. Hence, they are not as commonly used as synchronous systems.

Combinational logic refers to circuits whose output is strictly depended on the present value of the
inputs. As soon as inputs are changed, the information about the previous inputs is lost, that is,
 Digital Logic Design and Computer Architecture 23

combinational logics circuits have no memory. In many applications, information regarding input
values at a certain instant of time is required at some future time. Although every digital system is
likely to have combinational circuits, most systems encountered in practice also include memory
elements, which require that the system be described in terms of sequential logic. Circuits whose
outputs depends not only on the present input value but also the past input value are known as
sequential logic circuits. The mathematical model of a sequential circuit is usually referred to as a
sequential machine.

A general block diagram of a sequential circuit is shown below in Figure 4.1.

Figure 6.1. Block Diagram of Sequential Circuit.

The diagram consists of combinational circuit to which memory elements are connected to form a
feedback path. The memory elements are devices capable of storing binary information within
them. The combinational part of the circuit receives two sets of input signals: one is primary
(coming from the circuit environment) and secondary (coming from memory elements). The
particular combination of secondary input variables at a given time is called the present state of the
circuit. The secondary input variables are also know as the state variables.

The block diagram shows that the external outputs in a sequential circuit are a function not only of
external inputs but also of the present state of the memory elements. The next state of the memory
elements is also a function of external inputs and the present state. Thus a sequential circuit is
specified by a time sequence of inputs, outputs, and internal states.

➢ Synchronous and Asynchronous Operation

Sequential circuits are divided into two main types: synchronous and asynchronous. Their
classification depends on the timing of their signals.

Synchronous sequential circuits change their states and output values at discrete instants of time,
which are specified by the rising and falling edge of a free-running clock signal. clock period is the
Module 04: Design of Sequential Circuit 24

time between successive transitions in the same direction, that is, between two rising or two falling
edges. State transitions in synchronous sequential circuits are made to take place at times when the
clock is making a transition from 0 to 1 (rising edge) or from 1 to 0 (falling edge). Between
successive clock pulses there is no change in the information stored in memory.

The reciprocal of the clock period is referred to as the clock frequency. The clock width is defined
as the time during which the value of the clock signal is equal to 1. The ratio of the clock width and
clock period is referred to as the duty cycle. A clock signal is said to be active high if the state
changes occur at the clock's rising edge or during the clock width. Otherwise, the clock is said to be
active low. Synchronous sequential circuits are also known as clocked sequential circuits.

The memory elements used in synchronous sequential circuits are usually flip-flops. These circuits
are binary cells capable of storing one bit of information. A flip-flop circuit has two outputs, one for
the normal value and one for the complement value of the bit stored in it. Binary information can
enter a flip-flop in a variety of ways, a fact which give rise to the different types of flip-flops. For
information on the different types of basic flip-flop circuits and their logical properties, see the
previous tutorial on flip-flops.

In asynchronous sequential circuits, the transition from one state to another is initiated by the
change in the primary inputs; there is no external synchronization. The memory commonly used in
asynchronous sequential circuits is time-delayed devices, usually implemented by feedback among
logic gates. Thus, asynchronous sequential circuits may be regarded as combinational circuits with
feedback. Because of the feedback among logic gates, asynchronous sequential circuits may, at
times, become unstable due to transient conditions. The instability problem imposes many
difficulties on the designer. Hence, they are not as commonly used as synchronous systems.

Let’s check the take away from this lecture

1) When is it important to use a three-state buffer?
a) When two or more outputs are connected to the same input
b) when all outputs are normally HIGH
c) When all outputs are normally LOW
d) When two or more outputs are connected to two or more inputs

2) The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that
is initially clear. What are the Q outputs after two clock pulses?

A. 0000
 Digital Logic Design and Computer Architecture 25

B. 0010

C. 1000

D. 1111

3) Which type of device may be used to interface a parallel data format with external equipment's
serial format?
A. key matrix

B. UART

C. memory chip

D. series in, parallel out

Exercise
Q.1 Define Asynchronous Counter.
Q.2 Define Synchronous Counter
Q.3 Difference between asynchronous and synchronous counter.

.
Learning from this lecture: Learners will be able to understand the concept of synchronous and
asynchronous counters.

Lecture: 5
Modulus of L1, L2, L3 Counters
➢ Finite State Machines: Notation
In this course, we represent sequential circuits as finite state machines.
A Finite State Machine (FSM) is a circuit that can exist in a finite number of states, usually a rather
small number. Finite State Machines with more than 32 states are rare.

The FSM has a memory that stores its state.

If the FSM has N states, then its memory can be implemented with P flip–flops where
2P–1 < N  2P

Typical values: 3 states 2 flip–flops

4 states 2 flip–flops
5 states 3 flip–flops
8 states 3 flip–flops
Module 04: Design of Sequential Circuit 26

Tools to describe finite states machines include

1) The state diagram

2) The state table

3) The transition table

State Diagram for a Sequence Detector

NOTE: We have five states, labeled “A”, “B”, “C”, “D”, and “E”.

We have labeled edges connecting the states. Each is labeled Input / Output.

This is a directed graph with labeled edges and loops.

➢ The main function of the state diagram for the FSM is to indicate what the next state will be
given the present state and input.
➢ Here the input is labeled X. Were the input two bits at a time, the input would be labeled as X 1
X0, with X1 the more significant bit.
➢ The labeling of the arcs between the states indicates that there is output associated with each
transition. Not all Finite State Machines have output associated with the transition. This one
does.
➢ This and all typical FSM represents a synchronous machine. Transitions between states and
production of output (if any) take place at a fixed phase of the clock, depending on the flip–flops
used to implement the circuit.
➢ Were we pressed to be more specific, we would associate the transitions with the rising edge of
the clock. This is usually an unnecessary detail.
➢ State Diagram for a Modulo–4 Counter
Here is the state diagram for a modulo–4 counter.
 Digital Logic Design and Computer Architecture 27

There is no input but the clock. It just counts clock pulses.

Note the direction of the arrows; this is an up–counter.

The state table is a tabular form of the state diagram. It is easier to work with.

Here is the state table for the sequence detector.

Present State Next State / Output

X=0 X=1
A A/0 B/0
B A/0 C/0
C D/0 C/0
D A/0 E/0
E A/0 C/1
Here is the state table for the modulo–4 counter.
Present State Next State
0 1
1 2
2 3
3 0
➢ Transition Tables
Transition tables are just state tables in which the labels have been replaced by binary numbers.
Often the labels are retained to facilitate translation to binary.
Here is the transition table for the sequence detector.

Present State Next State / Output

X=0 X=1
A = 000 000 / 0 001 / 0
B = 001 000 / 0 010 / 0
C = 010 011 / 0 010 / 0
Module 04: Design of Sequential Circuit 28

D = 011 000 / 0 100 / 0

E = 100 000 / 0 010 / 1
Here is the transition table for the modulo–4 counter. There is no output table.
Present State Next State
0=00 01
1=01 10
2=10 11
3=11 00
➢ Sample Circuit for Analysis

The analysis of such a circuit follows a fixed set of steps.

1) Determine the inputs and outputs of the circuit. Assign variables to represent these.
2) Characterize the inputs and outputs of the flip-flops. Show as Boolean expressions.
3) Construct the Next State and Output Tables.
4) Construct the State Diagram.
5) If possible, identify the circuit. There are no good rules for this step.

Step 1: Determine the inputs and outputs of the circuit.

The circuit has one input and one output, with one internal variable of interest.

The input is labeled as X.

The output is labeled as Z.
The internal line that is fed back into the flip–flop is labeled as Y.
NOTE: There is output associated with the input because we see the gate producing Z based on the
input X.
 Digital Logic Design and Computer Architecture 29

Step 2: Show the inputs and outputs as Boolean expressions.

Input: X
Output: Z=XY
Input to Flip–Flop: D = X +Y
Output of Flip–Flop: Y

Step 3: Construct the Next State and Output Tables

Here is the next state table.
X Q(t) = Y D=X+Y Q(t+1)
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1

We know the present state of the flip–flop; call it Y.

Given Y and X, the input, we can compute D. This determines the next state.

Here is the output table. It depends on the input and present state.

X Y = Q(t) Z
0 0 0
0 1 1
1 0 1
1 1 0

Step 3A: Construct the Next State / Output Table

Just combine the two tables into one table.
X Q(t) = Y D=X+Y Q(t+1) / Z
0 0 0 0/0
0 1 1 1/1
1 0 1 1/1
Module 04: Design of Sequential Circuit 30

1 1 1 1/0
We then put the table into a standard form that will lead to the state diagram.
Present State Next State/Output
X=0 X=1
0 0/0 1/1
1 1/1 1/0
We use this to build a state diagram. The two states are Q = 0 and Q = 1.
The outputs are associated with the transitions.

Step 4: Construct the State Diagram.

Here again is the state table with output.
Present State Next State/Output
X=0 X=1
0 0/0 1/1
1 1/1 1/0
Here is the state diagram.

Step 5: Identify the Circuit if Possible

This is often hard to do.
The key here is that the circuit stays in state 0 until the first 1 is input.
When the first 1 is input it goes to state 1 and stays there for all input.

We now characterize the output as a function of the input for each of the two states.

Input Q(T) Output

0 0 0 For Q(t) = 0, the output is X

1 0 1

0 1 1 For Q(t) = 1, the output is X.

 Digital Logic Design and Computer Architecture 31

1 1 0

It can be shown that this is a serial generator for a two’s–complement.

The binary integer is read from Least Significant Bit to Most Significant Bit.

Up to and including the first (least significant) 1, the input is copied.

After that it is complemented.

0001 1100 becomes 1110 0100

0010 1101 becomes 1101 0011. Try this, it works.

Design a Modulo–4 Counter

Step 1: Derive the state diagram and state table for the circuit.
Here is the state diagram. Note that it is quite simple and involves no input.

Here is the state table for the modulo–4 counter

Present State Next State

0 1
1 2
2 3
3 0
Step 2: Count the Number of States
Obviously, there are only four states, numbered 0 through 3.
Determine the number of flip–flops needed.

Solve 2P–1 < N  2P. If N = 4, we have P = 2 and 21 < 4  22.

We need two flip–flops for this design. Number them 1 and 0.

Their states will be Q1 and Q0 or Y1 and Y0, depending on the context.

Remember: 21 = 2, 22 = 4, 23 = 8, 24 = 16, 25 = 32, 26 = 64, 27 = 128, etc.

Step 3 Assign a unique P-bit binary number (state vector)

to each state.
Here P = 2, so we assign a unique 2–bit number to each state.
Module 04: Design of Sequential Circuit 32

For a number of reasons the first state, state 0, must be assigned Y1 = 0 and Y0 = 0.

For a counter, there is only one assignment that is not complete nonsense.

State 2-bit Vector

0 00
1 01
2 10
3 11

The 2–bit vectors are just the unsigned binary equivalent of the decimal state numbers.

Step 4 Derive the state transition table.

Present State Next State

0 00 01
1 01 10
2 10 11
3 11 00

Strictly speaking, we should have dropped the decimal labels in this step.

However, this representation is often useful for giving the binary numbers.

The state transition table tells us what the required next state will be
for each present state.

Step 5 Separate the state transition table into P tables, one for each flip-flop.
Here P = 2, so we need two tables.

Flip-Flop 1 Flip-Flop 0
Present State Next State Present State Next State
Y1 Y0 Y1( t+1 ) Y1 Y0 Y0( t+1 )
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 1
1 1 0 1 1 0

Each flip–flop is represented with the complete present state and its own next state.

Step 6 Decide on the types of flip-flops to use. When in doubt, use all JK’s.
Our design will use JK flip–flops.
For design work, it is important that we remember the excitation table.

Here it is.

Q( t ) Q( t+1 ) J K
0 0 0 d
0 1 1 d
1 0 d 1
1 1 d 0
 Digital Logic Design and Computer Architecture 33

Step 7 Derive the input table for each flip-flop using the excitation tables for the type.
Here is the table for flip–flop 1.
PS NS Input
Y1 Y0 Y1 J1 K1
00 0 0 d
01 1 1 d
10 1 d 0
11 0 d 1

Here is the table for flip–flop 0.

PS NS Input
Y1 Y0 Y0 J0 K0
00 1 1 d
01 0 d 1
10 1 1 d
11 0 d 1
Step 8 Derive the input equations for each flip-flop
I use a set of intuitive rules based on observation and not on formal methods.
1) If a column does not have a 0 in it, match it to the constant value 1.
If a column does not have a 1 in it, match it to the constant value 0.
2) If the column has both 0’s and 1’s in it, try to match it to a single variable, which must be part of
the present state. Only the 0’s and 1’s in a column must match the suggested function.
3) If every 0 and 1 in the column is a mismatch, match to the complement of a function or a
variable in the present state.
4) If all the above fails, try for simple combinations of the present state.
NOTE: The use of the complement of a state in step 3 is due to the fact that each flip–flop outputs
both its state and the complement of its state.

Step 9 Derive the input equations for each flip-flop

Here is the input table for Flip–Flop 1
PS NS Input
Y1 Y0 Y1 J1 K1
00 0 0 d
01 1 1 d
10 1 d 0
11 0 d 1
J1 = Y0 K1 = Y0

Here is the input table for Flip–Flop 0

PS NS Input
Y1 Y0 Y0 J0 K0
00 1 1 d
01 0 d 1
10 1 1 d
11 0 d 1
J0 = 1 K0 = 1

Step 9 Summarize the equations by writing them in one place.

Module 04: Design of Sequential Circuit 34

Here they are.

J1 = Y0 K 1 = Y0
J0 = 1 K0 = 1
For homework and tests, this is required so that I can easily find the answers.

Step 10 Draw the circuit diagram.

But note that each flip–flop has input J = K. This suggests a simplification.

Let’s check the take away from this lecture

1) Which pins need to be connected together on a 7493 to make a MOD-12 counter.

A. 12 to 1, 11 to 3, 9 to 2

B. 12 to 1, 11 to 3, 12 to 5

C. 12 to 1, 11 to 3, 8 to 2

D. 12 to 1, 11 to 3, 1 to 5

2) The terminal count of a modulus-11 binary counter is ________.

A. 1010

B. 1000

C. 1001

D. 1100

3) How many flip-flops are required to make a MOD-32 binary counter?

A. 3

B. 45

C. 5

D. 6

Exercise
Q.1 Define Module 4 Counter.
Q.2 Explain transitions table with example
Q.3 Explain ripple counter & Mod 11 Counter

.
 Digital Logic Design and Computer Architecture 35

Learning from this lecture: Learners will be able to understand the concept of working of
module 4 counter.

Lecture: 6
UP-DOWN Counter
An up-counter counts events in increasing order. A down-counter counts stuff in the decreasing
order. An up-down counter is a combination of an up-counter and a down-counter. It can count in
both directions, increasing as well as decreasing.

How to design a 2-bit synchronous up counter?

Step 1: Find the number of flip-flops and choose the type of flip-flop.

Since this is a 2-bit synchronous counter, we can deduce the following. There will be two flip-flops.
These flip-flops will have the same RST signal and the same CLK signal. We will be using the D
flip-flop to design this counter.

Step 2: Proceed according to the flip-flop chosen.

Since we are using the D flip-flop, the next step is to draw the truth table for the counter.

The counting should start from 1 and reset to 0 in the end. So the display would start with
displaying 1, 2, 3 and then 0.

Truth table for the 2-bit synchronous up counter

Here’s what the truth table will look like. Q represents the previous output, and Qn represents
the current output.

Q1 Q0 Qn1 Qn0

0 0 0 1

0 1 1 0

1 0 1 1

1 1 0 0

Another handy tip for designing synchronous counters using D flip-flop is that for the 1st flip-flop,
you have to connect the inverted output to the input directly. You don’t have to perform any extra
logical operation.
Module 04: Design of Sequential Circuit 36

So, in this case, we will calculate the equation for only Qn1 to be fed back to Q1. From the truth
table, using the shortcut we saw in our post on digital comparators, we get the following.

Qn1 is high when Q1 is low AND Q0 is high, OR Q1 is high AND Q0 is low. This gives us the
following equation

Qn1 =

The resulting circuit for the 2-bit synchronous up counter is as shown below.

How to design a 2-bit synchronous down counter?

Step 1: Find the number of flip-flops and choose the type of flip-flop.

Since this is a 2-bit synchronous counter, we have two flip-flops. These flip-flops will have the same
RST signal and the same CLK signal. We will be using the D flip-flop to design this counter.

Step 2: Proceed according to the flip-flop chosen.

We will now design the truth table for this counter. The counter should follow the sequence 0, 3, 2,
1, 0, 3, 2, 1.

Truth table for the 2-bit synchronous down counter

Q1 Q0 Qn1 Qn0

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 1

Hence, we can see that the equation that we will derive for Qn1 is the same as that for the up
counter. The only difference in the construction will be that in the 2-bit synchronous down counter, the
output will be taken from the inverted outputs of the flip-flop.
 Digital Logic Design and Computer Architecture 37

How to design a 3-bit synchronous up counter?

We will need three flip-flops. These three flip-flops are synchronous to the same clock input. They
will have the same reset signal as well. Since we are using the D flip-flop to construct this, we can
straightaway design the truth table.

The sequence will be 1, 2, 3, 4, 5, 6, 7, 0.

Q2 Q1 Q0 Qn2 Qn1 Qn0

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

We have our shortcut of connecting Qn0 to Q0 directly. For the inputs of the remaining two flip-
flops, we will solve the truth table using K-maps to derive the equations.
Module 04: Design of Sequential Circuit 38

Thus Qn1 =

And Qn2 =

Implementing the logic equations above , we get the following circuit for a 3-bit synchronous up
counter.
 Digital Logic Design and Computer Architecture 39

How to design a 3-bit synchronous down counter?

The circuit diagram for the 3-bit synchronous down counter is the same as that of the up counter. The
only difference is that instead of attaching the non-inverted outputs to the display port, we will
attach the inverted outputs.

How to design a 3-bit synchronous up-down counter?

An up-down counter is capable of counting in both incremental and decremental fashion. For a 3-bit
synchronous up-down counter, we need three flip-flops, with the same clock and reset inputs.

The way to achieve the ability to count in both the directions is by combining the designs for the up
and the down counters and using a switch to alternate between them.

We know that for the up and down counters, the design of the circuit is the same. The only
difference is that for the up counter the output is taken at the non-inverting output ports of the flip-
flops. Whereas, for the down counter, the output is taken at the inverting output ports of the flip-
flops.

So we have a total of 3+3 outputs. When we combine them, we get six outputs, and now we need
one switch input.

From our post on multiplexers, we know that we can use three 2:1 multiplexers connected via their
select lines. This would give us six inputs, one select line, and three outputs.

Perfect. That is exactly what we need.

Sure, we can’t expect your mind to jump straightaway to multiplexers. But remember that
multiplexers give you an option of choosing between multiple inputs. So it does an excellent job of
being a switch in digital electronics.
Module 04: Design of Sequential Circuit 40

The resulting circuit diagram of the up-down counter is shown below.

How to design a 4-bit synchronous up counter?

Since this is a 4-bit synchronous up counter, we will need four flip-flops. These flip-flops will have
the same RST signal and the same CLK signal. We will be using the D flip-flop to design this
counter.

We will start right away with the design of the truth table for this counter. The 4-bit synchronous up
counter should follow the sequence 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0.

Q3 Q2 Q1 Q0 Qn3 Qn2 Qn1 Qn0

0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 0

0 0 1 0 0 0 1 1

0 0 1 1 0 1 0 0

0 1 0 0 0 1 0 1

0 1 0 1 0 1 1 0

0 1 1 0 0 1 1 1

0 1 1 1 1 0 0 0

1 0 0 0 1 0 0 1

1 0 0 1 1 0 1 0

1 0 1 0 1 0 1 1
 Digital Logic Design and Computer Architecture 41

1 0 1 1 1 1 0 0

1 1 0 0 1 1 0 1

1 1 0 1 1 1 1 0

1 1 1 0 1 1 1 1

1 1 1 1 0 0 0 0

The input to the first flip-flop D0 will come directly from its own inverted output. We will use
Kmaps to find the logic equations for the remaining flip-flops.

Hence the input to the fourth flip-flop will have the following logic expression

Therefore from the Kmap, the input equation for the third flip-flop is
Module 04: Design of Sequential Circuit 42

And the equation for the for the second flip-flop is

From the above equations, we obtain the logic circuit for the 4-bit synchronous up counter below.

Let’s check the take away from this lecture

1) UP-DOWN counter is also known as ___________
a) Dual counter
b) Multi counter
c) Multimode counter
d) Two Counter
2) In DOWN-counter, each flip-flop is triggered by ___________
a) The output of the next flip-flop
 Digital Logic Design and Computer Architecture 43

b) The normal output of the preceding flip-flop

c) The clock pulse of the previous flip-flop
d) The inverted output of the preceding flip-flop
3) In 4-bit up-down counter, how many flip-flops are required?
a) 2
b) 3
c) 4
d) 5
Exercise
Q.1 Define Binary Counter
Q.2 Explain Up-Down Counter
Q.3 Explain 2 –bit Up-Down Counter

Learning from this lecture: Learners will be able to understand the concept of working of up-down
counter

Lecture:7
Shift Registers:
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They are a
group of flip-flops connected in a chain so that the output from one flip-flop becomes the input of
the next flip-flop. Most of the registers possess no characteristic internal sequence of states. All the
flip-flops are driven by a common clock, and all are set or reset simultaneously.

➢ Serial In - Serial Out Shift Registers

A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
operation of the circuit is as follows. The register is first cleared, forcing all four outputs to zero.
The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0).
During each clock pulse, one bit is transmitted from left to right. Assume a data word to be
1001. The least significant bit of the data has to be shifted through the register from FF0 to FF3.
Module 04: Design of Sequential Circuit 44

In order to get the data out of the register, they must be shifted out serially. This can be done
destructively or non-destructively. For destructive readout, the original data is lost and at the end
of the read cycle, all flip-flops are reset to zero.

To avoid the loss of data, an arrangement for a non-destructive reading can be done by adding two
AND gates, an OR gate and an inverter to the system. The construction of this circuit is shown
below.

The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be shifted
out of the register when the control line is LOW (ie READ). This is shown in the animation below.

➢ Serial In - Parallel Out Shift Registers

For this kind of register, data bits are entered serially in the same manner as discussed in the last
section. The difference is the way in which the data bits are taken out of the register. Once the
data are stored, each bit appears on its respective output line, and all bits are available
simultaneously. A construction of a four-bit serial in - parallel out register is shown below.
 Digital Logic Design and Computer Architecture 45

In the animation below, we can see how the four-bit binary number 1001 is shifted to the Q outputs
of the register.

➢ Parallel In - Serial Out Shift Registers

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-flops and
NAND gates for entering data (ie writing) to the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is the least
significant bit. To write data in, the mode control line is taken to LOW and the data is clocked in.
The data can be shifted when the mode control line is HIGH as SHIFT is active high. The register
performs right shift operation on the application of a clock pulse, as shown in the animation below.
Module 04: Design of Sequential Circuit 46

➢ Parallel In - Parallel Out Shift Registers

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a four-bit
parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is clocked, all
the data at the D inputs appear at the corresponding Q outputs simultaneously.

Let’s check the take away from this lecture

1) How much storage capacity does each stage in a shift register represent?
a) One bit
b) Two bits
c) Four bits
d) Eight bits

2) What is the function of a buffer circuit?

A. to provide an output that is inverted from that on the input

B. to provide an output that is equal to its input

C. to clean up the input

D. to clean up the output

3) Stepper motors have become popular in digital automation systems because ________.
A. of their low cost

B. they are driven by sequential digital signals

C. they can be used to provide repetitive mechanical movement

they are driven by sequential digital signals and can be used to provide repetitive
D.
mechanical movement
 Digital Logic Design and Computer Architecture 47

Exercise
Q.1 Define Shift Register
Q.2 Explain SIPO
Q.3 What is meant by the parallel load of a shift register
.

Learning from this lecture: Learners will be able to understand the concept of working of shift
register and its types

Lecture: 8

Universal Shift Register

A Universal shift register is a register which has both the right shift and left shift with parallel
load capabilities. Universal shift registers are used as memory elements in computers. A
Unidirectional shift register is capable of shifting in only one direction. A bidirectional shift
register is capable of shifting in both the directions. The Universal shift register is a combination
design of bidirectional shift register and a unidirectional shift register with parallel load
provision.
n-bit universal shift register –
A n-bit universal shift register consists of n flip-flops and n 4×1 multiplexers. All the n
multiplexers share the same select lines(S1 and S0)to select the mode in which the shift register
operates. The select inputs select the suitable input for the flip-flops.

Basic connections –
Module 04: Design of Sequential Circuit 48

1. The first input (zeroth pin of multiplexer) is connected to the output pin of the corresponding
flip-flop.
2. The second input (first pin of multiplexer) is connected to the output of the very-previous flip
flop which facilitates the right shift.
3. The third input (second pin of multiplexer) is connected to the output of the very-next flip-
flop which facilitates the left shift.
4. The fourth input (third pin of multiplexer) is connected to the individual bits of the input
data which facilitates parallel loading.
The working of the Universal shift register depends on the inputs given to the select lines.

The register operations performed for the various inputs of select lines are as follows:

S1 s0 Register operation

0 0 No changes

0 1 Shift right

1 0 Shift left

1 1 Parallel load

Let’s check the take away from this lecture

1) A sequence of equally spaced timing pulses may be easily generated by which type of counter
circuit?
a) Ring shift
b) Clock
c) Johnson
d) universal

2) A 4-bit shift register that receives 4 bits of parallel data will shift to the ________ by ________
position for each clock pulse.
a) Right, one
b) Right, two
 Digital Logic Design and Computer Architecture 49

c) Left, two
d) Left, one
3) An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the
time delay between the serial input and the Q3 output?
Ans: 26.67 ms

Exercise:
Q.1 Define Universal Shift Register?
Q.2 Which IC is used for universal shift register?
Q.3Explain working of universal shift register?

Learning from this lecture: Learners will be able to understand the concept of working of
Universal shift register and its working

Lecture: 9
Ring and Twisted ring counter

Ring counter is a type of counter composed of flip-flops connected into a shift register. It is of two
types:
1. Straight Ring Counter:
Straight ring counter is a type of ring counter in which the output of the last flip-flop is
connected to the input of the first flip-flip. It circulates a single ‘0’ or ‘1’ bit around the
ring.
Module 04: Design of Sequential Circuit 50

2. Twisted Ring Counter :

Twisted ring counter is a types of ring counter in which the complement of output of the last shift
register is connected to the input of the first register. It circulates a stream of 1s followed by 0s
around the ring.

Difference between Straight and Twisted Ring Counter:

STRAIGHT RING COUNTER TWISTED RING COUNTER

It connects the complement of output of the

It connects the output of the last shift
last shift register to the input of the first
register to the input of first shift register.
register.

It is known as One hot counter. It is known as Walking ring counter.

It circulates a single bit (0 or 1) around It circulates stream of 1 followed by stream of

the ring. 0.

PRESET is used in first shift register. PRESET is not used in twisted ring counter.

CLEAR is used for last (n-1) flip-flops. CLEAR is used for all flip-flips in it.

It is used in successive approximation

It is used in phase shift or function generator.
and stepper motor control.

Johnson Counter

Johnson counter also known as creeping counter, is an example of synchronous counter. In

Johnson counter, the complemented output of last flip flop is connected to input of first flip flop
 Digital Logic Design and Computer Architecture 51

and to implement n-bit Johnson counter we require n flip-flop.It is one of the most important type
of shift register counter. It is formed by the feedback of the output to its own input.Johnson
counter is a ring with an inversion.Another name of Johnson counter are:creeping counter,
twisted ring counter, walking counter, mobile counter and switch tail counter.

Total number of used and unused states in n-bit Johnson counter:

number of used states=2n
number of unused states=2n – 2*n
Example:
If n=4
4-bit Johnson counter
Initially, suppose all flip-flops are reset.

Truth Table:
Module 04: Design of Sequential Circuit 52

where,
CP is clock pulse and
Q1, Q2, Q3, Q4 are the states.

Question: Determine the total number of used and unused states in 4-bit Johnson counter.

Answer: Total number of used states= 2*n

= 2*4
=8
Total number of unused states= 2 n – 2*n
= 24-2*4
=8
Advantages of Johnson counter:
• The Johnson counter has same number of flip flop but it can count twice the number of
states the ring counter can count.
• It can be implemented using D and JK flip flop.
• Johnson ring counter is used to count the data in a continuous loop.
• Johnson counter is a self-decoding circuit.
Disadvantages of Johnson counter:
• Johnson counter doesn’t count in a binary sequence.
• In Johnson counter more number of states remain unutilized than the number of states
being utilized.
 Digital Logic Design and Computer Architecture 53

• The number of flip flops needed is one half the number of timing signals.
• It can be constructed for any number of timing sequence.
Applications of Johnson counter:
• Johnson counter is used as a synchronous decade counter or divider circuit.
• It is used in hardware logic design to create complicated Finite states machine. ex: ASIC
and FPGA design.
• The 3 stage Johnson counter is used as a 3 phase square wave generator which produces
1200 phase shift.
• It is used to divide the frequency of the clock signal by varying their feedback.

Let’s check the take away from this lecture

1) What is a transceiver circuit?

a) A buffer that transfers data from input to output
b) A buffer that transfers data from output to input
c) A buffer that can operate in both directions
d) A buffer that can operate in one direction

2) What is the preset condition for a ring shift counter?

a) All FFs set to 1
b) All FFs cleared to 0
c) A single 0, the rest 1
d) A single 1, the rest 0
3) To connect devices to a shared data bus is to use a ____________
a) Circulating gate
b) Transceiver
c) Bidirectional encoder
d) Strobed latch
4) Which of the following is true regarding ring and Johnson counter:
(A) ring counter has an inverted feedback path
(B) ring counter has fewer flip-flops but requires more decoding circuitry
(C) johnson counter has an inverted feedback path
(D) johnson counter has more flip-flops but less decoding circuitry
Module 04: Design of Sequential Circuit 54

Exercise:
Q.1 Define straight and twisted ring counter?
Q.2 Difference between straight and twisted ring counter
Q.3 Explain working of Straight ring counter?
Q.4 Define Johnson counters?
Q.5 Explain working of Johnson counters?

Learning from this lecture: Learners will be able to understand the concept of working of ring
and twisted ring/Johnson counter

Conclusion
The study of latches and flip flops explains the concept of latch and different flip flops and their use
in digital logic design. Also by studying counters and registers help to understand their real world
applications.

Short Answer Questions:

1. What is Flip-flop?
Ans) Flip-flop is the common name given to two-state devices which offer basic memory for
sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and are
commonly used in banks called "registers" for the storage of binary numerical data.

2. What is Latch?
Ans) Latches are flip-flops for which the timing of the output changes is not controlled. For a latch,
the output essentially responds immediately to changes on the input lines (and possibly the
presence of a clock pulse).

3. What is race around condition?

Ans) For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q output will toggle as
long as CLK is high, which makes the output of the flip-flop unstable or uncertain. This
problem is called race around condition in J-K flip-flop.

4. What is Excitation Table?

Ans) An excitation table shows the minimum inputs that are necessary to generate a particular next
state (in other words, to "excite" it to the next state) when the current state is known. They are
similar to truth tables and state tables, but rearrange the data so that the current state and next state
are next to each other on the left-hand side of the table, and the inputs needed to make that state
 Digital Logic Design and Computer Architecture 55

change happen are shown on the right side of the table.

5. What is SR flip flop?

Ans) SR flip-flop is basically a one-bit memory bistable device that has two inputs, one which will
“SET” the device (meaning the output = “1”), and is labelled S and one which will “RESET” the
device (meaning the output = “0”), labelled R.

6. What is JK flip flop?

Ans) The JK flip flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to
logic level “1”.

7. State the difference between latch and flip flop.

Ans) The difference between a latch and a flip-flop is that a latch is level-triggered (outputs can
change as soon as the inputs changes) and Flip-Flop is edge triggered (only changes state when a
control signal goes from high to low or low to high).

8. What is Counter?

Ans) Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal
applied. Counters are of two types.

• Asynchronous or ripple counters.

• Synchronous counters.

9. What is Up-Down Counter?

Ans) An up-down counter is a combination of an up-counter and a down-counter. It can count in
both directions, increasing as well as decreasing. Depending on the type of clock inputs

10. What is SIPO?

Ans) Is called as Serial-In Parallel-Out shift Register (SIPO) ,The circuit consists of four D flip-flops
which are connected. ... The output of the first flip flop is connected to the input of the next
flip flop and so on. All these flip-flops are synchronous with each other since the same clock
signal is applied to each flip flop.
Module 04: Design of Sequential Circuit 56

11. State the difference between Ring counter and Johnson Counter.
Ans) The difference between a ring counter and a Johnson counter is which output of the last stage
is fed back (Q or Q'). ... Recirculating a single 1 around a ring counter divides the input clock by a
factor equal to the number of stages. Whereas, a Johnson counter divides by a factor equal to twice
the number of stages.

Long Answer Questions:

1. Explain SR flip flop with excitation table and logic diagram.
Ans) (Refer the topic ‘SR flip flop’ under lecture 1).
2. Explain JK flip flop with excitation table and logic diagram.
Ans) (Refer the topic ‘JK flip flop’ under lecture 2).
3. Explain Master-Slave JK flip flop.
Ans) (Refer contents under lecture 3)
4. Convert SR flip flop to JK flip flop.
Ans) (Refer the topic ‘SR flip flop to JK flip flop’ under lecture 3)
5. Convert JK flip flop to D flip flop.
Ans) (Refer the topic ‘JK flip flop to D flip flop’ under lecture 3)
6. Explain Sequential circuit with diagram.
Ans) (Refer the topic under lecture 4).
7. Explain State Diagram for a Sequence Detector
Ans) (Refer the topic ‘Modulus of counter’ under lecture 5).
3. Explain different shift register in details with diagram.
Ans) (Refer contents under lecture 7)
4. Explain Universal shift register
Ans) (Refer contents under lecture 8)

Set of Questions for FA/IA/ESE

Q. 1) State the difference between latch and flip flop.
Q. 2) What is Excitation Table?
Q. 3) State the difference between Truth table and Excitation table.
Q. 4) What is race around condition?
Q. 5) Convert D flip flop to T flip flop.
Q. 6) Explain Master-Slave JK flip flop.
Q. 7) Convert SR flip flop to JK flip flop.
Q. 8) Explain SR flip flop with excitation table and logic diagram.
 Digital Logic Design and Computer Architecture 57

Q. 9) Explain JK flip flop with excitation table and logic diagram.

Q. 10) State the difference between straight ring and twisted ring counter
Q. 11) What is synchronous and asynchronous counter?
Q. 12) State the difference between 4 types of shift register.
Q. 13) what is Jonson counter?
Q. 14) Design 4 bit Up-down Counter.

References:
1) Modern Digital Electronics By R. P. Jain.
2) Digital Logic and Computer Design By M. Morris Mano.
3) Digital Principles and Applications By Donald p Leach, Albert Paul Malvino

Practice for Module-04

Q.1) Explain Master-Slave JK flip flop with timing diagram. (10 marks)
Q.2) Explain SR flip flop with excitation table and logic diagram. (10 marks)
Q.3) Convert SR flip flop to JK flip flop. (10 marks)

Q.4) Convert JK flip flop to D flip flop. (10 marks)

Q.5) Convert D flip flop to T flip flop. (5 marks)
Q.6) Explain 2 types of counters with clock signal diagram. (10 marks)
Q.7) Explain Universal shift register with excitation table and logic diagram. (10 marks)
Q.8) Write short notes on
i) sequence Generator (5 marks)
ii) module 4 counter (10 marks)

Self-assessment
Q.1) What is Flip flop? Define the role of flip flops as storage elements in digital logic design.
Q. 2) Explain the Excitation tables for each flip flop.
Q. 3) Describe the steps to convert from flip flop to another flip flop.
Q.4) What is counter Define the role of asynchronous and synchronous.
Q. 5) Explain the state tables for each shift register.
Q. 6) Describe the steps to convert from 2 bit to 4 bit up down counter.
Module 04: Design of Sequential Circuit 58

Self-evaluation
Name of
Student
Class
Roll No.
Subject
Module No.
S.No Tick
Your choice
1. Do you understand how flip flops can be used o Yes
as storage elements used in digital logic o No
design?
2. Do you understand the difference between flip o Yes
flop and latch? o No
3. Do you understand how to convert from one o Yes
flip flop to another? o No
4. Do you understand the working of Counters? o Yes
o No
5. Do you understand how shift registers work ? o Yes
o No
6. Do you understand module 4 ? o Yes, Completely.
o Partialy.
o No, Not at all.