MULTIPROCESSOR SYSTEMS

 A multiprocessor system is defined as "a system with more than one

processor", and, more precisely, "a number of central processing units linked
together to enable parallel processing to take place".
 The key objective of a multiprocessor is to boost a system's execution
speed.
 A multiprocessor has a memory system that is addressable by each
processor. As such, the memory system consists of one or more memory
modules whose address space is shared by all the processors.
 Based on the organization of the memory system, the multiprocessors can be
further divided into two groups,
1. Tightly Coupled
2. Loosely Coupled

Tightly Coupled Systems

 In a tightly coupled multiprocessor, a central memory system provides
the same access time for each processor.
 This type of central memory system is often called main memory,
shared memory, or global memory.
 The central memory system can be implemented either as one big
memory module or as a set of memory modules that can be accessed
in parallel by different processors.

Loosely Coupled Systems

 A loosely coupled multiprocessor design reduces memory contention
by the processors and makes the system more efficient.
  Memory contention refers to situations where many processors
request access to memory within a very short time interval, resulting
in unreasonable memory access delays.
 In addition to the central memory system, each processor might also
have a small cache memory. (A cache memory is a fast type of
memory that sits between the processor and the interconnection to
main memory in order to make the accessing faster.)
 These caches also help reduce memory contention and make the
system more efficient.
 In a loosely coupled multiprocessor, in order to reduce memory
contention the memory system is partitioned between the processors;
that is, a local memory is attached to each processor.
 Thus each processor can directly access its own local memory and all
the other processors' local memories. However, the access time to a
remote memory is much higher than to the local memory.

Interconnection Topologies

One of the first decisions that must be made when designing a multiprocessor
system is the type of interconnection network that will be used between the
processors and the shared memory.
The interconnection must be such that each processor is able to access all the
available memory space. When two or more processors are accessing memory at
the same time, they should all be able to receive the requested data.
Shared Bus: One commonly used interconnection is the shared bus (also called
common bus or single bus). The shared bus is the simplest and least expensive way
of connecting several processors to a set of memory modules. It allows
compatibility and provides ease of operation and high bandwidth.
Multiple Bus: In a multiple-bus architecture, multiple buses are physically
connected to components of the system. In this way, the performance and
reliability of the system are increased. Although the failure of a single bus line may
degrade system performance slightly, the whole system is prevented from going
down.
There are other topologies also like crossbar switch, hierarchy based etc.
 CO-PROCESSORS

 The general-purpose microprocessors have an upper limit of data-processing

capability and these general processors require complex programming to
perform any mathematical calculations.
 For any mathematical operations, processors use high-level language for
programming and a library of floating point objects has to be obtained from
the manufacturer.
 To increase the operating speed, several microprocessors are connected
together using a certain network topology. Then the system is called a
multiprocessor system.
 The simplest multiprocessors system consists of a microprocessor and a
Numeric Data Processor (NDP). The numeric data processor has an
independent math processing unit and it can do complex numeric
calculations very fast compared to the main processor.
 The most commonly used numeric processors are 8087.

8087 NUMERIC DATA PROCESSOR

 The 8087 was first released in 1980 by Intel and this can work with 8086,
8088, 80186 and 80188 processors.
 The 8087 Numeric Data Processor (NDP) is called a high-speed math co-
processor. This math co-processor is also known as Numeric Processor
Extension (NPX) or Numeric Data Processor (NDP) or Floating Unit Point
(FUP).
 The 8087 is available in 40-pin DIP packages in 5 MHz, 8 MHz, and 10
MHz versions and it is compatible with 8086 and higher-version processors.
  The purpose of 8087 was to speed up the computations involving floating
point calculations. Addition, subtraction, multiplication and division of
simple numbers is not the coprocessor’s job. It does all the calculations
involving floating point numbers like scientific calculations and algebraic
functions.
 This increases the overall speed and performance of the entire system.
 This coprocessor introduced about 60 new instructions available to the
programmer.
 All the mnemonics begin with “F” to differentiate them from the standard
8086 instructions. For e.g. in contrast to ADD/MUL, 8087 provide
FADD/FMUL.

ARCHITECTURE OF 8087

The internal structure of 8087 coprocessor is divided into two major sections:

1. Control Unit (CU)

2. Numerical Execution Unit (NEU)
CONTROL UNIT (CU)

 It interfaces coprocessor to the microprocessor system bus.

 It also synchronizes the operation of the coprocessor and the microprocessor.
This unit has a Control Word, Status Word and Data Buffer.
 If an instruction is ESC instruction, then coprocessor executes it. If not, then
the microprocessor executes.

NUMERIC EXECUTION UNIT (NEU)

 This unit is responsible for executing all coprocessor instructions.

 It has an 8 register stack that holds the operands for instructions and result of
instructions.
 The stack contains 8 registers that are 80-bits wide.
 Numeric data is transferred inside the coprocessor in two parts:
1. 64-bit mantissa bus
2. 16-bit exponent bus.
Registers of 8087

STATUS REGISTER

 Status Register tells the overall status of 8087 coprocessor.

 It is a 16-bit register.
 It is accessed by executing the FSTSW instruction.
 This instruction stores the contents of status register into memory.
 Once the status is stored in memory, the bit positions of the status register
can be examined.
Busy: It indicates that the coprocessor is busy executing the task.
Condition Codes (C0-C3): They indicate various conditions about the coprocessor.
Top of Stack: It indicates a register as top of stack register, out of the eight stack
registers.
Exception Flag: It is set if any of the exception flag bits (SF, PR, UF, OF, ZD, DN,
IO) are set.
Stack Fault: It is not available in 8087. It is active only in 80387 and above.
Precision: It indicates that the result has exceeded the selected precision.
Underflow: It tells if the result is too small to fit in a register.
Overflow: It tells if the result is too large to fit in a register.
Zero Divide: It indicates that you try to divide a non-zero value by zero.
Denormalized: It indicates that at least one of the operand is de-normalized.
Invalid Operation: It indicates an invalid operation. For e.g.: pushing more than
eight items onto the stack, attempting to pop an item off an empty stack or taking
the square root of a negative number.
CONTROL REGISTER
 Control Register controls the operating modes of 8087.
 It is also a 16-bit register.
 It performs rounding control and precision control.
 It is also used to do masking and unmasking of the exception bits that
correspond to the rightmost six bits of the status register. FLDCW
instruction is used to load the value into control register.

Rounding Control: It determines the type of rounding or truncating to be done.

00=Round to nearest or even
01=Round down towards minus infinity
10=Round up towards plus infinity
11=Chop or truncate towards zero

Precision Control: It sets the precision of the result.

00=Single precision (short)
01=Reserved
10=Double precision (long)
11=Extended precision (temporary)

Exception Masks: It determines that whether an error effects the exception bits in
the status register.
If it is one, then the corresponding error is ignored.
If it is zero and the corresponding error occurs, then it generates an interrupt,
and the corresponding bit in status register is set.
TAG WORD
 Tag Register is used to indicate the contents of each register in the stack.
 There are total 8 tags (Tag 0 to Tag 7) in this register and each tag uses 2
bits to represent a value.
 Therefore, it is a 16-bit register.

Tag Values: 00 = Valid 01 = Zero 10 = Invalid 11 = Empty

INSTRUCTION POINTER & DATA POINTER

 The IP and DP registers are used to hold the information (address of
instruction, op-code, operand address) about the last executed floating point
instruction.
 They contain the address of the currently executed instruction and the
corresponding data.
PIN DIAGRAM OF 8087 NDP
INTERFACING OF 8086 AND 8087
 Multiplexed address-data bus lines are connected directly from 8086 to
8087.
 The status lines and the queue status lines are connected directly from 8086
to 8087.
 The Request/Grant (RQ/GT0and RQ/GT1) signals of 8087 are connected to
RQ/GT0and RQ/GT1of 8086.
 BUSY signal of 8087 is connected to TEST pin of 8086.
Exception Handling
The 8087 detects six different types of exception conditions that occur during
instruction execution.
These will cause an interrupt if unmasked and interrupts are enabled.
1. INVALID OPERATION
2. OVERFLOW
3. ZERO DIVISOR
4. UNDERFLOW
5. DENORMALIZED OPERAND
6. INEXACT RESULT

Data Types
Internally, all data operands are converted to the 80-bit temporary real format.
There are 3 types.
1. Integer data type
2. Packed BCD data type
3. Real data type
 I/O PROCESSORS
 The Input Output Processor is a specialized processor which loads and stores
data into memory along with the execution of I/O instructions.
 It acts as an interface between the processor and the devices.
 It involves a sequence of events to execute I/O operations and then store the
results into the memory.

 I/O Processors handles all of the interactions between the I/O devices and
the microprocessor.
1. I/O Processors communicates with input and output devices through
separate address, data, and control lines.
2. This provides an independent pathway for the transfer of information
between external devices and internal memory.
3. Relieves the microprocessor of ‘I/O device chores’.

 Used to address the problem of direct transfer after executing the necessary
format conversion or other instructions
 In an IOP-based system, I/O devices can directly access the memory
without the intervention by the processor.
 When I/O is handled by IOP, microprocessor can perform some other
functions at the time of I/O transfer. This increases the system speed.
 8089 IOP is the most extensively processor used for I/O interfacing.
 The microprocessor is connected with the memory and input/output devices
and forms a microcomputer. The technique of connection between
input/output devices and a microprocessor is known as interfacing.
 8089 IO PROCESSOR

 The 8089 IOP is a high-performance processor which comes in 40-pin DIP.

 The 8089 instruction set is optimized for high speed, flexible and efficient
I/O handling.
 It can work with both 16-bit and 8-bit microprocessors with 16-bit and 8-bit
I/O peripherals.

Features of 8089
 An IOP can fetch and execute its own instructions.
 Instructions are specially designed for I/O processing.
 In addition to data transfer, 8089 can perform arithmetic and logic
operations, branches, searching and translation.
 IOP does all work involved in I/O transfer including device setup,
programmed I/O and DMA operation.
 IOP can transfer data from an 8-bit source to 16-bit destination and vice-
versa.
 Communication between IOP and CPU is through memory based control
blocks. CPU defines tasks in the control blocks to locate a program
sequence, called a channel program.
ARCHITECTURE OF 8089 IOP

 The 8089 IOP has two internal I/O channels.

 These two channels can be programmed independently to handle two
separate I/O tasks for the host processor.
 The ALU and the main control unit are shared by both the channels.
 The main control unit generates the control signals for the operation of the
I/O processor.
 The bus control unit generates handles all the bus activities.
PIN DIAGRAM OF 8089 IOP

CA channel attention signal of the I/O processor.

SEL the first CA received after reset informs the IOP through
the SEL line, whether it is a master or slave and starts
the initialization process.

DRQ2-DRQ1 DMA request input signals to the IOP. Here signals

 Indicate that a peripheral is ready to transfer/ receive data
using either channel-1 or channel-2.

SIMTR2-SIMTR1 Interrupt output signals from channel-1 and channel-2.

EXT2-EXT1 External terminate input signals for channel-1 and

channel-2.

Registers of 8089 IOP

• GA- Points to source
• GB- Points to destination
• GC- Used as base address of a 256 byte translation table.
• TP- Task pointer
• PP- Parameter pointer
• IX -Index Register
• BC- Byte Count
• MC- Mask Compare
• CC- Channel Control
• PSW-Program Status Word

Channel Control Word

• Function control- b15 & b14
• Translation mode- b13
• Synchronization control-b12 & b11
• Source/ Destination indicator – b10
• Lock control- b9
• Chaining control- b8
• Single transfer mode – b7
• Termination control – b0-b6
Interfacing of 8089 with 8086
 BUS ARBITRATION

 Bus Arbitration refers to the process by which the current bus master
accesses and then leaves the control of the bus and passes it to the another
bus requesting processor unit. The controller that has access to a bus at an
instance is known as Bus master.
 A conflict may arise if a number of controllers or processors try to access the
common bus at the same time, but access can be given to only one of those.
Only one processor or controller can be Bus master at the same point of
time.
 To resolve these conflicts, Bus Arbitration procedure is implemented to
coordinate the activities of all devices requesting memory transfers.
 The Bus Arbiter decides who would become current bus master.

There are two approaches to bus arbitration

1. Centralized bus arbitration – A single bus arbiter performs the required
arbitration.
2. Distributed bus arbitration – All devices participate in the selection of the next
bus master.

Methods of Centralized BUS Arbitration

There are three bus arbitration methods

(i) Daisy Chaining method

It is a simple and cheaper method where all the bus masters use the same line for
making bus requests. The bus grant signal serially propagates through each master
until it encounters the first one that is requesting access to the bus. This master
blocks the propagation of the bus grant signal, therefore any other requesting
module will not receive the grant signal and hence cannot access the bus.
During any bus cycle, the bus master may be any device – the processor or any
DMA controller unit, connected to the bus.

Advantages –
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a certain
maximum value.
Disadvantages–
 The value of priority assigned to a device is depends on the position of
master bus.
 Propagation delay is arises in this method.
 If one device fails then entire system will stop working.

(ii) Polling or Rotating Priority method –

In this, the controller is used to generate the address for the master (unique
priority), the number of address lines required depends on the number of masters
connected in the system. The controller generates a sequence of master address.
When the requesting master recognizes its address, it activates the busy line and
begins to use the bus.
Advantages –

 This method does not favor any particular device and processor.
 The method is also quite simple.
 If one device fails then entire system will not stop working.
Disadvantages –
 Adding bus masters is difficult as increases the number of address lines of
the circuit.

(iii) Fixed priority or Independent Request method –

In this, each master has a separate pair of bus request and bus grant lines and each
pair has a priority assigned to it.

The built-in priority decoder within the controller selects the highest priority
request and asserts the corresponding bus grant signal.

Advantages –
 This method generates fast response.

Disadvantages –
 Hardware cost is high as large no. of control lines are required.
Distributed BUS Arbitration
In this, all devices participate in the selection of the next bus master. Each device
on the bus is assigned a 4-bit identification number. The priority of the device will
be determined by the generated ID.
 8289 BUS ARBITER

 The Intel 8289 is a bus arbiter designed for Intel 8086/ 8087/ 8088/ 8089.
 The chip is supplied in 20-pin DIP package.
 The 8086 (and 8088) operate in maximum mode, so they are configured
primarily form multiprocessor or for working with coprocessors.
 Provides simple interface with 8288 Bus Controller

ARCHITECTURE OF 8289 BUS ARBITER

 The 8289 bus arbiter operates in conjunction with the 8288 bus controller to
interface the 8086.
PIN DIAGRAM OF 8289 BUS ARBITER

CRQLCK’ prevents the arbiter from surrendering the multimaster

system bus to any other bus arbiter requesting the bus
through the CBRQ input pin.

RESB Resident Bus. When RESB is high, the multi-master

system bus is requested. When RESB is put to low,
SYSB/ RESB input is ignored.

SYSB/RESB’ the arbiter requests the multi-master system bus in the

System/Resident Mode.
When SYSB/ RESB is high and allows the bus to be
surrendered when this pin is low.

ANYRQST Any Request. It is an active high input pin. An active

signal on ANYRQST would enable the multi-master
system bus to be handed over to an arbiter—even if it has
lower priority.

CRQLCK An active low on this input pin prevents the arbiter from
surrendering the multi-master system bus to any other
bus arbiter IC after being requested through CBRQ input
 pin.

INIT’ An active lo signal (= 0) on INIT input resets all bus

arbiters on the multi-master system bus. After
initialisation is over, no arbiter can use the said bus.

CBRQ Common Bus Request. an active condition on CBRQ

tells the arbiter of the presence of other lower priority
arbiters in the multi-master system bus.

BREQ Bus Request. BREQ is used in the parallel priority

resolving scheme which a particular arbiter activates to
request the use of multi-master system bus.

BPRN Bus Priority In. BPRN indicates that it is the highest

priority arbiter presently on the bus. If an arbiter loses its
BPRN active signal.

BPRO Bus Priority Out. BPRO is used in the serial priority

resolving scheme and it is daisy-chained to BPRN of the
just next lower priority arbiter.

BUSY When the particular arbiter has completed its job, it

releases the BUSY signal, thereby allowing the next
highest arbiter to seize the bus.

MODES OF 8289 BUS ARBITER

8289 bus arbiter provides support to two types of processors : 8089 I/O Processor
and 8086/8088. Thus 8289 supports two modes of operations:

(a) IOB (I/O Peripheral Bus) mode which permits the processor access to both I/O
peripheral bus and a multi-master system bus. When 8289 needs to communicate
with system memory, this is effected with the help of system memory bus.
(b) RESB (Resident Bus) mode which permits the processor to access to resident
bus and a multi-master system bus.

All devices residing on IOB are treated as I/O devices (including memory) and are
all addressed by I/O commands, the memory commands being handled by
multimaster system bus. A Resident Bus can also issue both memory and I/O
commands—but distinct from the multi-master system bus. The Resident Bus has
only one master.

When IOB = 0 , 8289 is in IOB mode and when RESB = 1, 8289 is in RESB mode.
When IOB =0 and RESB = 1, then 8089 interfaces with 8086 to a multi-master
system bus, a Resident Bus and an I/O Bus. Again, for IOB = 1 and RESB = 0,
8089 interfaces with 8086 to a multi-master system bus only.

PRIORITY RESOLVING METHODS

On a multi-master system bus, there may be several bus masters. The particular bus
master which is going to gain control of multi-master system bus is determined by
employing bus arbiters. Several techniques are there to resolve this priority
amongst bus masters. They are:
 Parallel Priority Resolving Technique.
 Serial Priority Resolving Technique.
 Rotating Priority Resolving Technique.