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Optical Computing on
Photonic Integrated Circuits

David Z. Pan
Dept. of Electrical and Computer Engineering
The University of Texas at Austin

1
Acknowledgment
t Prof. Ray T. Chen at UT Austin
t Graduate students at UT
› Zheng Zhao
› Zhoufeng Ying
› Chenghao Feng
› Shounak Dhar

t Sponsored by the DoD MURI (Multi-University

Research Initiative) Program at UT Austin

2
Optical Computing
t Early days: free-space, e.g., Fourier transform
› Large devices not friendly to scaling and integration
t Photonic integrated circuits (PICs) based on silicon-on-
insulator (SOI)
› CMOS-compatible process
› Monolithic integration of electronics and photonics

3
Optical Computing Components
t Micro-resonator based optical switches
› Can be implemented with micro-rings/micro-disks
λ through

drop

2x2 optical switch

Ideal transmission
Optical Computing Components
t Y-branch combiner vs. directional coupler
› Only one input will be light-on
k: coupling constant
In1 In1 Out
k
Out

In2
In2

Pout = 0.5 PIn1 Pout = k PIn1

Pout = 0.5 PIn2 Pout = (1-k) PIn2

Power efficiency factor = Pout/Pin

t Size of a Y-branch – very small
t Size of a coupler ≈ 2x micro-resonator switch
Outline

t Introduction
t Optical Adder Designs

t Optical Logic Synthesis

t Optical Neural Network

t Conclusion

6
 Directed Logic Based EO Computing
Architecture

All electrical SIMD Hybrid electrical-optical (EO) architecture

architecture • Light in, light out
• No OE/EO conversion in OLU
7
Building Blocks for Directed Logics

[Zamir+, IEEE Photonics Soc. Opt. Interconnects Conf. OI’2017]

8
 Schematic of Electrical and Optical
Full Adders

Signal Symbol Transitional signals Expression Transfer function

Addends !" , #" ‘Propagate’ $" $" = !" ⊕ #" '" = $" ( '")* + ,"
Carry, Sum '", -" ‘Generate’ ," ," = !" ( #" -" = '")* ⊕ $"

2M design for each-bit [Ying+, Opt. Lett’2018, Ying+ CLEO’2017]

9
 Electrical vs. Optical Full Adder

Electrical full
adder

Optical
full adder

Latency of Latency of optical

electrical full adder Reduced to full adder

T = Tp , g + Tepb ´ n Topb Tepb T = Tp , g + Tsw + Topb ´ n

Delay for Switch time of Optical propagation Electrical delay per

generating P and G modulators delay per bit bit
!",$ !%& !'"( !)"(
10
 Candidates for EO Modulators
Electrical
MZI Absorption Micro-ring Micro-disk
Modulator
~2,000×500
Footprint ~40×10 μm2 ~10×10 μm2 ~5×5 μm2
μm2
Wavelength- Multiple devices Multiple devices
Multiple devices Multiple devices
division with extra with extra
only only
multiplexing MUX/DEMUX MUX/DEMUX
Available in Available in Available in Available in
Industry
PDKs offered PDKs offered PDKs offered PDKs offered
maturity
by foundries by foundries by foundries by foundries
Insertion loss ~2.2 dB ~4.4 dB ~2.8 dB ~0.9 dB
Extinction ratio ~4.1 dB ~4.2 dB ~6.6 dB ~ 7.8 dB
Expected
energy ~750 fJ/bit ~20 fJ/bit ~50 fJ/bit ~1 fJ/bit
consumption
[Timurdogan+, Nat. Commun’ 2014, Pantouvaki+, JLT’2017] [Ying+, APL’18]
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Latency

!)')*+ = !",$ + !%& + !'"( × /

!",$ = 1223
!%& = 5023
!'"( = 0.623

!",$ Delay for generating P

and G
!%& Switch time of
modulators
!'"( Optical propagation
delay per bit
!)')*+ Total latency

12
Power Consumption Comparison
t Calculation is based on 32nm node library

13
2-bit Thermal Optical Adder Fabrication
and Measurement
[Ying+, Optics Letters 2018]

14
Experiment Results

15
AIM Chip
4 mm

2-bit full adder

2 mm
Testing area

4-bit full adder

The chip is under test

16
Outline

t Introduction
t Optical Adder Designs

t Optical Logic Synthesis

t Optical Neural Network

t Conclusion

17
 BDD Based Optical Implementation

t Data structure and direct implementation

f
b
a 1
a S
0
1 c CB PD
b λ S
0
CB S1

c
S optical CB combiner PD photodetector
switch
1

Binary decision diagram Optical direct implementation:

(BDD) each multi-parent BDD node
has a combiner

18
Problem with Direct Implementation
t Due to BDD’s single-path property, any
combiners have at most one light input
t Power is cut by half (-3dB)
f

a
abc = 101
b

1
Light stream to the lower/upper input port

Binary decision diagram

(BDD)
19
Our Proposed Techniques
t Our goal: to improve the worst-case network
optical power efficiency under a reasonable
overhead and computational budget
t Two key techniques are proposed
› Combiner elimination to avoid cascaded combiner
loss
› Coupler assignment to redistribute the power
resource
t Applicable to any BDD-based architecture
› Not restricted by specific types of optical switches

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Technique 1: Combiner Elimination
t Idea: avoid cascaded combiner loss
› e.g., for abc=101 b
1 1/4
f f a S0
0
1 c CB PD
λ S0
a a
CB S1
1/2
b
b
b 1
a S
0 1/3
c c c 1 c CB PD
λ S0
S1
1 1
S1

Greater combiner loss at the

terminal but not cascaded
Technique 2: Coupler Assignment
t Idea: redistribute the power with directional
couplers (DCs) instead of combiners
t Assign the coupling efficiency for each DC

b
1
a S
0 *1/3
1 1 c DC PD
λ S
0 1/3
CB S1 *2/3
1/2

22
 Optical Power Efficiency
[Zhao+, ASPDAC’18]
Optical Power Efficiency (dB)
Worst-case Terminal

Prev. work: [Wille+, ASPDAC’2015]

Average power efficiency ratio over prev.: 27.02 x
Average/greatest CPU time: 1.88s / 14.5s
 And-Invertor Graphs (AIG) Based Logic
Synthesis
Basic Gate Library

§ Basic gates: three categories based on E/O interfaces

§ And-Invertor Graphs (AIGs) based logic synthesis

[Ying+, Optics Express 2018]

24
AIG-Based Logic Synthesis

[Ying+, Optics Express 2018]

25
 AIG Optical Logic Examples
[Ying+, Optics
Express 2018]

!"# = (& + ()(* ⊕ , + -). Full adder For each bit:

/012 = /34 · (& ⊕ () + & · (

Elements in library Circuit size Redundancy Generality

BDD Only one Large Large Yes
AIG Many, scalable Small Small No*
 BDD vs. AIG Example
!"# = a ⊕ ' + ) ⊕ *
out

b b

BDD c

d d

1
BDD-based approach
output

O-OR

AIG E-XOR

E-XOR

with multi-
a b c d AIG-based
27 operand gates
Outline

t Introduction
t Optical Adder Designs

t Optical Logic Synthesis

t Optical Neural Network

t Conclusion

28
 Optical Neural Network (ONN)
t Potential to achieve ~0 energy and speed of light for inference
Mach-Zehnder interferometers (MZI) for SU(2) MZI array for unitary
Input Output
coupler coupler
ϕ

…
Transfer function: …

T2,1 T3,1…T3,2 Tn-1,1… Tn,1…

ith row Tn-1,n-2 Tn,n-1
Expand to Transfer function of
n-dim: jth row
an n-dim MZI array:
ith column jth column

Basic architecture for each MLP layer

W

SVD-decomposition
x … V* Σ U … actf … y
weight matrix to U Σ V*
Non-linear
Linear transform activation
(MZI array) (saturable absorber)
Shen et al. Nature Photonics (2017).
Proposed Co-design Method
t Software hardware co-design to reduce # of MZIs by co-
training weights with simpler hardware architecture
W = U Σ V*
[m x n]
Previous

x … V* Σ U … actf … y
Tree network (T)
[n x 1] [m x 1]
[n x n] [n x m] [m x m] w/ single-out MZI or
directional coupler
# of MZI ~ (n^2+m^2)/2

W TUΣ
[m x n]
1st subtree
architecture
Proposed

outputs
inputs
x … Σ U T … actf … y
2nd subtree
[n x 1] [m x 1]
[n x n] [n x n] [m x n]

# of MZI ~ n^2/2 3rd subtree

[Zhao+, ASPDAC 2019] 30

 Proposed Co-design Method
t Previous way t Proposed co-design
› Train W directly › T and Σ: Embed the device
› Use SVD-decomp to parameters in training
obtain U, Σ, V* › U: Add unitary regularization and
approximate the trained U with the
closest true unitary
Training Optical
variables Implementation Training Optical
SVD
decomp. variables Implementation
W V* Σ U =
T T
=
Σ Σ

U approx.
t Training (software) and (with reg.)
U
optical implementation
(hardware) is separate
t Training and implementation is
closely related
 Results
t Dataset: MNIST [Zhao+, ASPDAC 2019]
› Much less # of MZIs (e.g., 50%)
› Similar accuracy

# of MZI’s

Accuracy

ONN configuration:

32
Results
t Better resilience to phase noise due to less cascaded
components

Previous ONN Our ONN

[Zhao+, ASPDAC 2019]

33
Conclusion
t Optical computing with SOI-based PICs
› CMOS-compatible
› Applications such as large-bit carry-ripple adders
› General optical logic synthesis
› Specialized applications for optical neural network
t Still many challenges yet opportunities
› Optical power loss and noise
› Better devices and system integration
› Optical still bulky compared to CMOS
» Shall work together with CMOS
» New circuit/architecture (e.g., WDM) to scale
› Optical interconnect, memory (?)
34