Digital Fundamentals

CHAPTER 4
Boolean Algebra and Logic Simplification

Slide 1
Boolean Operations and Expressions

Slide 2
 Boolean Operations and Expressions

• Addition • Multiplication
0+0=0 0*0=0
0+1=1 0*1=0
1+0=1 1*0=0
1+1=1 1*1 =1

Slide 3
Laws and Rules of Boolean Algebra

Slide 4
 Laws Boolean Algebra

• Commutative Laws
• Associative Laws
• Distributive Law

Slide 5
 Laws of Boolean Algebra

• Commutative Law of Addition:

Slide 6
 Laws of Boolean Algebra

• Commutative Law of Multiplication:

Slide 7
 Laws of Boolean Algebra

• Associative Law of Addition:

Slide 8
 Laws of Boolean Algebra

• Associative Law of Multiplication:

Slide 9
 Laws of Boolean Algebra

• Distributive Law:
A(B + C) = AB + AC

Slide 10
Rules of Boolean Algebra

Slide 11
 Rules of Boolean Algebra

• Rule 1

OR Truth Table

Slide 12
 Rules of Boolean Algebra

• Rule 2

OR Truth Table

Slide 13
 Rules of Boolean Algebra

• Rule 3

AND Truth Table

Slide 14
 Rules of Boolean Algebra

• Rule 4

AND Truth Table

Slide 15
 Rules of Boolean Algebra

• Rule 5

OR Truth Table

Slide 16
 Rules of Boolean Algebra

• Rule 6

OR Truth Table

Slide 17
 Rules of Boolean Algebra

• Rule 7

AND Truth Table

Slide 18
 Rules of Boolean Algebra

• Rule 8

AND Truth Table

Slide 19
 Rules of Boolean Algebra

• Rule 9

Slide 20
 Rules of Boolean Algebra

• Rule 10: A + AB = A

AND Truth Table OR Truth Table

Slide 21
 Rules of Boolean Algebra

• Rule 11: A + AB = A + B

AND Truth Table OR Truth Table

Slide 22
 Rules of Boolean Algebra

• Rule 12: (A + B)(A + C) = A + BC

AND Truth Table OR Truth Table

Slide 23
DeMorgan’s Theorem

Slide 24
 DeMorgan’s Theorems

• Theorem 1
XY = X + Y

• Theorem 2
X + Y = XY
Remember:
“Break the bar,
change the sign”

Slide 25
Figure 4–16
A logic circuit showing the development of the Boolean expression for the output.

Slide 26
Figure 4–16
A logic circuit showing the development of the Boolean expression for the output.

Slide 27
Standard Forms of Boolean Expressions

Slide 28
 Standard Forms of Boolean Expressions

• The sum-of-product (SOP) form

• The product of sum (POS) form

Slide 29
Figure 4–18 Implementation of the SOP expression AB + BCD + AC.

Slide 30
Figure 4–19
This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.

Slide 31
Figure 4–19
This NAND/NAND implementation is equivalent to the AND/OR in Figure 4–18.

Slide 32
The Karnaugh Map

Slide 33
The Karnaugh Map

3-Variable Example
3-Variable Karnaugh Map

Slide 34
 The Karnaugh Map

4-Variable Karnaugh Map

4-Variable Example

Slide 35
Figure 4–23 Adjacent cells on a Karnaugh map are those that differ by only one
variable. Arrows point between adjacent cells.

Slide 36
Figure 4–24 Example of mapping a standard SOP expression.

Slide 37
Figure 4–25

Slide 38
Figure 4–28

Slide 39
Figure 4–29

Slide 40
Figure 4–30

Slide 41
Figure 4–31

Slide 42
Figure 4–32

Slide 43
Figure 4–33

Slide 44
Figure 4–34

Slide 45
Figure 4–35 Example of mapping directly from a truth table to a Karnaugh map.

Slide 46
Figure 4–36 Example of the use of “don’t care” conditions to simplify an expression.

Slide 47
Figure 4–37 Example of mapping a standard POS expression.

Slide 48
Figure 4–38

Slide 49
Figure 4–39

Slide 50
Figure 4–40

Slide 51
Figure 4–41

Slide 52
 The Karnaugh Map

5-Variable Karnaugh Mapping

Slide 53
Figure 4–43 Illustration of groupings of 1s in adjacent cells of a 5-variable map.

Slide 54
Figure 4–44

Slide 55
VHDL

Slide 56
Figure 4–45 A VHDL program for a 2-input AND gate.

Slide 57
 VHDL

• VHDL Operators • VHDL Elements

and entity
or architecture
not
nand
nor
xor
xnor

Slide 58
 VHDL

• Entity Structure

Example:

entity AND_Gate1 is
port(A,B:in bit:X:out bit);
end entity AND_Gate1

Slide 59
 VHDL

• Architecture

Example:

architecture LogicFunction of AND_Gate1 is

Slide 60
Figure 4–46

Slide 61
 Hardware Description Languages (HDL)

• Boolean Expressions in VHDL

Slide 62
Figure 4–47 Seven-segment display format showing arrangement of segments.

Slide 63
Figure 4–48 Display of decimal digits with a 7-segment device.

Slide 64
Figure 4–49 Arrangements of 7-segment LED displays.

Slide 65
Figure 4–50 Block diagram of 7-segment logic and display.

Slide 66
Figure 4–51 Karnaugh map minimization of the segment-a logic expression.

Slide 67
Figure 4–52
The minimum logic implementation for segment a of the 7-segment display.

Slide 68
Summary

Slide 69
Figure 4–54

Slide 70
Figure 4–55. What is the Boolean expression for each of the logic gates?

Slide 71
Figure 4–56. What is the Boolean expression for each of the logic gates?

Slide 72
Figure 4–58. Derive a standard SOP and standard POS expression for each truth table.

Slide 73
Figure 4–59.
Reduce the function in the truth table to its minimum SOP form by using a Karnaugh map.

Slide 74
Figure 4–62. Example 4-21. Related Problem answer.

Slide 75
Figure 4–63. Example 4-22. Related Problem answer.

Slide 76
Figure 4–64. Example 4-23. Related Problem answer.

Slide 77
Figure 4–65. Example 4-24. Related Problem answer.

Slide 78
Figure 4–66. Example 4-30. Related Problem answer.

Slide 79