Course Code: ECE1003 Course Title: Digital Logic Design TPC 3 2 3

Version No. 1.1

Course Pre-requisites/ None
Co-requisites/
anti-requisites (if any).
Objectives: 1. To learn various techniques for logic minimization.
2. To comprehend the concepts of various combinational
circuits.
3. To understand the concepts of various sequential circuits.
4. Helps student to carry out projects which contain digital
electronics modules.

CO's Mapping with PO's and PEO's

Course
Course Outcome Statement
Outcomes PO's / PEO's
Assimilate the knowledge of different types of number PO1, PO2, PO3,
CO1 systems and logically use them to perform binary PEO1
arithmetic
Design and Analyze combinational and sequential PO1, PO2, PO3,
CO2
circuits. PEO1, PEO2
PO1, PO2, PO3,
CO3 Design and analyze finite state machines
PEO1, PEO2
Design and realize combinational and sequential PO1, PO2, PO3,
CO4
circuits using programmable devices PEO1, PEO2
Assess different logic families that exist to realize PO1, PO2, PO3,
CO5 digital circuits and understand their operation and PEO1, PEO1
limitations
TOTAL HOURS OF
INSTRUCTIONS: 44

Module No. 1 Number Systems and Boolean 12 Hours

Algebra
Number systems and conversions, r’s and (r-1)’s compliment, binary signed and unsigned
numbers, binary arithmetic operations, weighted and non-weighted binary codes, logic gates
and universal gates, tri-state logic and don’t care logic, boolean algebra, SOP and POS
minimization, K-maps upto 4-variables.
Module No. 2 Combinational Logic Circuit 12 Hours
Design
Binary adder and subtractor, Ripple carry adders/subtractors and fast adders. Binary
decoders, encoders, multiplexers and de-multiplexers. Logic functions using decoders and
multiplexers. , Code converters, Magnitude comparator.
Module No. 3 Sequential Logic Circuit Design 13Hours
 Latches, Flip flops, Flip flop conversions, shift Registers, counters-synchronous and
asynchronous counters, ring and Johnson counters. Finite State Machine – design using
mealy and Moore state machines, Sequence detectors and generators design.
Module No. 4 Programmable Logic Devices 5 Hours
PROM, PLA, PAL, Comparison between PROM, PLA and PAL. Look-Up Tables (LUT)
design.
Module No. 5 Digital Integrated Circuits 6 Hours
Introduction to various logic families, Specifications – noise margin, propagation delay,
fan-in, fan-out. Comparison of logic families. Basic combination circuits design using
NMOS, PMOS and CMOS logic families.
Text Books.
1. M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition, Pearson Publishers, 2013.
2. Samir Palnitkar, ”Verilog HDL: A Guide to Digital Design and Synthesis” Prentice Hall,
2ndEdition, 2009.
3. R.P. Jain, “Modern Digital Electronics”, 4th edition,TMH.
References
1. M.Morris Mano, Charles R. Kime, Tom MartinLogic and Computer Design Fundamentals,
4thedition, Pearson Publishers.
2. C. H. Roth and L. L. Kinney, Fundamentals of Logic Design, 5th edition, Cengage Publishers
Mode of Evaluation Practice Tests-20%, Continuous Assessment Tests-60%, Practical
Assesment-20%

Class Tests - Cumulative for 16 Weeks 20%

Continuous Assessment Test-1 20%
Continuous Assessment Test-2 20%
Continuous Assessment Test-3 20%
Practical Assessment (Mini Project) 20%

Recommended by the Board 07.04.2019

of Studies on
Date of Approval by the Xxth Academic Council held on xx-xx-xxxx
Academic Council

List of Laboratory Experiments

1. Verification of Basic gates in behavioral, dataflow and gate-level modeling.

2. Verification of half adder & subtractor, full adder and subtractors.
3. Design and verification of 4-bit binary adder and subtractor.
4. Design and verification of 3x8 decoder and 8x3 priority encoder.
5. Design and verification of 4x1 MUX and 1x4 DeMUX.
6. Design and verification of 4-bit magnitude comparator.
7. Verification of latches and flip-flops.
8. Design and verification of 4-bit shift registers – SISO, SIPO, PISO and PIPO
9. Design and verification of 4-bit asynchronous up, down, up/down counter.
10. Design and verification of 4-bit synchronous up, down, up/down counter.
11. Design and verification of 4-bit ring and Johnson counters.