Computer

Organization
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Workbook

Electronics & Communication Engineering

GATE / PSUs

Aishwaria Vijay Ma’am

Computer Organization
PEN-Drive / G-Drive Course / VOD & Tablet Users

Workbook
EC

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GATE ACADEMY ®

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 GATE Syllabus
Machine instructions and addressing modes
ALU
Data-path and control unit
Instruction pipelining

Table of Contents
Sr. Chapter Pages

1. Addressing Modes …………………………………………………..…. 1

2. Control Unit ……………………………………….…..……………….…. 11

3. Pipelining ……………………………..………….….…………..…....…. 16
 Video Lecture Information
Sr. Lecture Name Duration

Lecture 01 Introduction + Basics of Computer Organization 0:55:05

Lecture 02 Registers 0:43:52

Lecture 03 Bus Arbitration 0:29:36

Lecture 04 Instructions 1:07:37

Lecture 05 Instruction Cycle 1:09:18

Lecture 06 Addressing Modes 0:55:05
Lecture 07 Miscellaneous Topics of Addressing Modes + Workbook Questions 0:58:08
Lecture 08 Workbook Questions 0:56:23
Lecture 09 Workbook Questions 0:41:53
Lecture 10 Introduction to CPU 0:43:27

Lecture 11 Microprogrammed Control Unit 0:57:13

Lecture 12 Input-Output Devices 0:50:20
Lecture 13 Modes of Data Transfer 0:53:44

Lecture 14 Direct Memory Access 0:32:38

Lecture 15 CPU + Workbook Questions 0:49:30

Lecture 16 Workbook Questions 0:32:36
Lecture 17 Parallel Processing & Pipelining 1:06:41
Lecture 18 Synchronous Pipelining (Part 1) 0:50:23

Lecture 19 Synchronous pipelining (Part 2) 0:53:13

Lecture 20 Instruction Pipeline 0:49:01

Lecture 21 Pipeline Hazards 0:38:44

Lecture 22 Workbook Questions 0:42:36
Lecture 23 Workbook Questions 0:12:55
 1 Addressing Modes

Classroom Practice Questions : Common Data for

Q.1 The content of the registers are R1 = 25 H, Questions 3 & 4

R2 = 30 H and R3 = 40 H . The following

Consider the following program segment for a
machine instructions are executed hypothetical CPU having three user registers R1, R2
PUSH { R1} and R3. [GATE 2004, IIT Delhi]
Instruction Operation Size
PUSH {R2} (in words)
MOV R1,5000 ; R1 ← Memory[5000] 2
PUSH {R3}
MOV R2,(R1) ; R 2 ← Memory[(R1)] 1
POP { R1} ADD R2,R3 ; R 2 ← R 2 + R3 1
MOV 6000, R2 ; Memory[6000] ← R2 2
POP {R2}
HALT ; Machine halts 1
POP {R3} Q.3 Consider that the memory is byte addressable
After execution, the content of registers with size 32 bits, and the program has been
R1 , R2 , R3 are loaded starting from memory location 1000
(decimal). If an interrupt occurs while the CPU
(A) R1 = 40 H , R2 = 30 H , R3 = 25 H has been halted after executing the HALT
(B) R1 = 25 H , R2 = 30 H , R3 = 40 H instruction, the return address (in decimal)
saved in the stack will be
(C) R1 = 30 H , R2 = 40 H , R3 = 25 H
(A) 1007 (B) 1020
(D) R1 = 40 H , R2 = 25 H , R3 = 30 H (C) 1024 (D) 1028
[GATE 2021, IIT Bombay] Q.4 Let the clock cycles required for various
Q.2 In absolute addressing mode operations be as follows : Register to/from
(A) the operand is inside the instruction memory transfer : 3 clock cycles, ADD with
(B) the address of the operand is inside the both operands in register : 1 clock cycle,
instruction. Instruction fetch and decode : 2 clock cycles
per word the total number of clock cycles
(C) the register containing the address of the
required to execute the program is
operand is specified inside the instruction.
(A) 29 (B) 24
(D) the location of the operand is implicit
(C) 23 (D) 20
[GATE 2002, IISc Bangalore]
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Computer Organization & Architecture [Workbook] 2 GATE ACADEMY®
Q.5 Which of the following is/are true of the auto- DEC R1 R1← R1–1 2
increment addressing mode? BNEZ 1004 Branch if non-zero 2
I. It is useful in creating self-relocating to the absolute
code. address
II. If it is included in an Instruction Set HALT Stop 1
Architecture, then an additional ALU is
Assume that the content of the memory
required for effective address calculation.
location 5000 is 10 and the content of the
III. The amount of increment depends on the
register R3 is 3000. The content of each of the
size of the data item accessed.
memory locations from 3000 to 3010 is 50.
(A) I only (B) II only The instruction sequence starts from the
(C) III only (D) II and III only memory location 1000. All the numbers are in
[GATE 2008, IISc Bangalore] decimal format. Assume that the memory is
Q.6 Consider the C struct defined below : byte addressable.
struct data After the execution of the program, the content
{ int marks [100]; of memory location 3010 is __.
char grade; [GATE 2021, IIT Bombay]
}; Q.8 A memory has 14-bits address bus. Then how
struct data student; many memory locations are there?
The base address of student is available in (A) 16 k (B) 16384
14
register R1. (C) 2 (D) All
The field student grade can be accessed Q.9 Memory is represented as?
efficiently using (A) A*B where A= no. of memory locations,
(A) Post-increment addressing mode, (R1) + B = no. of bits in each location
(B) Pre-decrement addressing mode, – (R1) (B) 2A*B where A = no. of address bits, B =
(C) Register direct addressing mode, R1 no. of bits in each location
(D) Index addressing mode, X (R1), where X (C) B*A where, B = no. of bits in each
is an offset represented in 2’S location, A = no. of memory locations
complement 16-bit representation. (D) Both A and B
[GATE 2017, IIT Roorkee] Q.10 Any instruction should have at least?
Q.7 Consider a computer system consisting of (A) 3 operands (B) 2 operands
registers R1, R2, R3 and MEMORY[X] (C) 1 operand (D) None
denotes the content at the memory location of Q.11 Which of the following addressing mode can
X. Assume memory is byte addressable. support relocation without any change in code
Size (instructions)?
Instruction Semantics
(bytes) (A) PC relative mode
MOV R1 R1← M[5000] 4 (B) Index register mode
(5000) (C) Base register mode
MOV R2 (R3) R2← M[R3] 4 (D) Direct mode
ADD R2,R1 R2←R1+R2 2 Q.12 Which of the following is included in the
architecture of computer?
MOV(R3) M[R3]← R2 4
1. Addressing modes, design of CPU
INC R3 R3← R3+1 2
2. Instruction set, data format
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GATE ACADEMY® 3 Addressing Modes
3. Secondary memory, operating system (i) How many bits are needed for opcode?
(A) 1 and 2 (B) 2 and 3 (ii) How many bits are left for address part of
(C) 1 and 3 (D) 1, 2 and 3 instruction?
Q.13 Consider the following statements : (iii) What is the maximum allowable size of
[ESE 2020] memory?
1. A computer will have a multiply Q.17 An instruction is stored at location 300 with its
instructions address field at location 301. The address field
2. Multiply instruction will be implemented has the value 640. A processor register
by a special multiply unit. contains the number 260. Evaluate the
Which of the following issues? effective address, if addressing mode is
(A) Both 1 and 2 are not architectural design 1. Direct
issues 2. Immediate
(B) Both 1 and 2 are not organizational issue 3. Relative
(C) 1 is an architectural design issue while 2 4. Register indirect
is an organizational issue Q.18 Consider a PC-relative mode type branch
(D) 1 is an organizational issue while 2 is an instruction. The instruction size is 4 bytes. This
architectural design instruction takes branch to a location 600. If
Q.14 A machine has a 32-bit architecture, with 1- the instruction has relative address value is
word long instructions. It has 64 registers each 160, then the starting address of instruction is
of which is 32 bits long. It needs to support 45 _______?
instructions, which have an immediate operand Q.19 Consider following sequence of instructions in
in addition to two register operands. Assuming which each instruction is of 4 bytes
that the immediate operand is an unsigned i
integer, the maximum value of the immediate
i+1
operand is _______?
i+2
[GATE 2014, ESE 2016]
i+3
Q.15 Consider a processor with 64 registers and an
instruction set of size twelve. Each instruction Assume that i+3 is branch instruction and it’s
has five distinct fields, namely, opcode, two target is instruction i. if branch instruction uses
source register identifiers, one destination PC-relative mode, then what should be the
register identifier and a twelve-bit immediate value of offset?
value. Each instruction must be stored in Q.20 Which addressing mode helps to access table
memory in a byte-aligned fashion. If a program data in memory efficiently?
has 100 instructions, the amount of memory (in (A) Indirect mode
byte) consumed by the program text is (B) Immediate mode
_______? (C) Auto increment or auto decrement
[GATE 2014, ESE 2016] (D) Index mode
Q.16 A digital computer has a memory unit with 32
Q.21 The addressing modes used for source operand
bits per word. The instruction set consists of
in the following instructions are respectively?
240 different operations. All the instructions
1. R1 ← #5
have an operation code part (opcode) and an
address part (allowed for only 1 address). Each 2. R1 ← M[5000]
instructions is stored in on word of memory. 3. R1 ← M[R2]
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Computer Organization & Architecture [Workbook] 4 GATE ACADEMY®
(A) Implied, direct, register Statement (II) : Programs are stored in the
(B) Implied, direct, register indirect same memory as data, which has a single
(C) Immediate, direct, register indirect interface with the CPU.
(D) Immediate, direct, register Codes :
Q.22 During branch instructing execution, value of (A) Both statement (I) and Statement (II) are
Program (PC) individually true and Statement (II) is the
(A) Always updated by Target Address correct explanation of Statement (I)
(B) Always remains same (B) Both Statement (I) and Statement (II) are
(C) Sometime updated by target and individually true but Statement (II) is not
sometimes remains same the correct explanation of Statement (I)
(D) PC is independent of branch instruction (C) Statement (I) is true but Statement (II) is
execution false
Q.23 Match List-I with List-II and select the correct (D) Statement (I) is false but Statement (II) is
answer using the codes given below the lists : true
List-I Q.26 For the daisy chain scheme of connecting I/O
A. A[I] = B[J] devices, which of the following statements is
B. While [*A++]; true?
C. Int temp = *x; (A) It gives non-uniform priority to various
List-II devices.
1. Indirect addressing (B) It gives uniform priority to all devices,
2. Indexed addressing (C) It is only useful for connecting slow
3. Autoincrement devices to a processor.
Codes : (D) It requires a separate interrupt pin on the
A B C processor for each device.
(A) 3 2 1 Q.27 Match List-I with List-II and select the correct
answer using the codes given below the lists:
(B) 1 3 2
(C) 2 3 1 List-I
(D) 1 2 3 A. Regs [ R4 ] ← Regs[ R4 ] + Regs[ R3 ]
Q.24 For computers based on three-address B. Regs [ R4 ] ← Regs[ R4 ] + 3
instruction formats, each address field can be
C. Regs [ R4 ] ← Regs[ R4 ] + Mem[Regs[ R1 ]]
used to specify which of the following :
S1 : A memory operand List-II
S2 : A processor register 1. Immediate
S3 : An implied accumulator register 2. Register
(A) Either S1 or S2 3. Displacement
(B) Either S2 or S3 Codes:
(C) Only S2 and S3 A B C
(D) All of S1, S2 and S3 (A) 3 2 1
Q.25 Statement (I) : In the Von Neumann (B) 2 1 3
architecture the program execution is (C) 1 2 3
essentially sequential in nature.
(D) 3 1 2
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GATE ACADEMY® 5 Addressing Modes
Q.28 Match List-I with List-II and select the correct (A) Memory location 1000 has value 20
answer using the codes given below the lists? (B) Memory location 1020 has value 20
List-I (C) Memory location 1021 has value 20
A. 0 - address instruction (D) Memory location 1001 has value 20
B. 1- address instruction Q.32 Which of the following is not valid class of
interrupts?
C. 2 - address instruction
1. Program
D. 3- address instruction
2. Timer
List-II
3. I/O
1. T = TOP (T − 1) 4. Hardware failure
Y =Y + X
2. (A) 1 and 3
3. Y = A − B (B) 1, 2 and 4
4. ACC = ACC − X (C) 2 and 3
Codes: (D) None of these
Q.33 System calls are usually invoked by using
A B C D
1. An indirect jump
(A) 1 2 3 4
2. A software interrupt
(B) 3 2 4 1
3. Polling
(C) 2 3 1 4 4. A privileged instruction
(D) 1 4 2 3 (A) 2 and 3 (B) 1 and 3
Q.29 In a certain processor, a 2 byte jump instruction (C) 1, 2, 3 and 4 (D) 3 and 4
is encountered at memory address 3010 H, the Q.34 Which of the following affects processing
jump instruction is in PC relative mode. The power?
instruction is JMP-7 where- 7 is signed byte. (A) Data bus capacity
Determine the Branch Target Address (B) Addressing scheme
(A) 3005 H (B) 3009 H (C) Clock speed
(C) 3003 H (D) 3007 H (D) All of these
Q.30 A CPU has 24-bit instructions. A program Q.35 Microinstruction length is determined by
starts at address 300 (in decimal). Which one 1. The maximum number of simultaneous
of the following is a legal program counter (all micro operations that must be specified.
values in decimal)? 2. The way in which the control information
(A) 400 (B) 500 is represented or encoded.
(C) 600 (D) 700 3. The way in which the next
microinstruction address is specified.
[GATE 2006, IIT Kharagpur]
(A) 1 and 2 (B) 2 and 3
Q.31 The memory location 1000,1001 and 1020
(C) 1 and 3 (D) All of these
have data values 18, 1 and 16 respectively
Q.36 The following diagram shows, Which
before the following, program is executed.
addressing mode?
MOVI Rs, 1 ; Move immediate
Lower High
LOAD Rd, 1000 (Rs.) ; Load from memory Opcode
Address Address
ADDI Rd, 1000 ; Add immediate
Memory
STOREI 0(Rd), 20 ; Store immediate
Which of the statement below is TRUE after Operand
the program is executed?

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Computer Organization & Architecture [Workbook] 6 GATE ACADEMY®
(A) Immediate addressing mode Q.39 Assume that the memory is byte addressable
(B) Indirect addressing mode and the word size is 32 bits. If an interrupt
(C) Extended addressing mode occurs during the execution of the instruction
(D) None of the above "INC R3", what return address will be pushed
on to the stack?
Common Data for (A) 1005 (B) 1020
Questions 37, 38 & 39
(C) 1024 (D) 1040
Consider the following program segment. Here R1, R2 Self-Practice Questions :
and R3 are the general purpose registers. Q.1 Suppose a processor does not have any stack
Instructions Operation Instructions pointer register. Which of the following
size (number of statements is true?
words) (A) It cannot have subroutine call instruction
MOV R1, R1 ← M 2 (B) It can have subroutine call instruction, but
3000 [3000] no nested subroutine calls
LOOP; 1 (C) Nested subroutine calls are possible, but
MOV R2, R1 R2 ← M [R3] 1 interrupts are not
ADD R2, R1 R2 ← R1+R2 1 (D) All sequences of subroutine call and also
MOV (R3), M [R3] ← R2 1 interrupts are possible
R2 [GATE 2001, IIT Kanpur]
INCR3 R3 ← R3+1 1 Q.2 A processor needs software interrupt to
DEC R1 R1 ← R1-1 1 (A) Test the interrupt system of the processor
BNZ LOOP Branch on not 2 (B) Implement co-routines
zero (C) Obtain system services which need
HALT Stop 1 execution of privileged instructions
(D) Return from subroutine
Assume that the content of memory location 3000 is [GATE 2001, IIT Kanpur]
10 and the content of the register R3 is 2000. The
Q.3 A CPU generally handles an interrupt by
content of each of the memory locations from 2000 to
executing an interrupt service routine
2010 is 100. The program is loaded from the memory
(A) As soon as an interrupt is raised
location 100. All the numbers are in decimal.
[GATE 2007, IIT Kanpur] (B) By checking the interrupt register at the
end of fetch cycle
Q.37 Assume that the memory is word addressable.
The number of memory references for (C) By checking the interrupt register after
accessing the data in executing the program finishing the execution of the current
completely is instruction
(A) 10 (B) 11 (D) By checking the interrupt register at fixed
time intervals.
(C) 20 (D) 21
Q.38 Assume that the memory is word addressable. [GATE 2009, IIT Roorkee]
After the execution of this program, the Q.4 The following register holds the instruction
content of memory location 2010 is before it goes for decode? [ESE 2012]
(A) 100 (B) 101 (A) Data register
(C) 102 (D) 110 (B) Accumulator

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GATE ACADEMY® 7 Addressing Modes
(C) Address register Q.11 Consider the following :
(D) Instruction register 1. Operation code
Q.5 In a microprocessor, the register which holds 2. Source operand reference
address of the next instruction to be fetched? 3. Result operand reference
[ESE 2014] 4. Next instruction reference
(A) Accumulator Which of the above are typical elements of
(B) Program counter machine instructions?
(A) 1, 2 and 3 only
(C) Stack Pointer
(B) 1, 2, and 4 only
(D) Instruction register
(C) 3 and 4 only
Q.6 Which of the following 2 registers are used to
(D) 1, 2, 3 and 4
access the memory?
Q.12 An addressing mode in which the location of
(A) Instruction register and program counter
the data is contained within the mnemonic, is
(B) Address register and program counter known as
(C) Program counter and stack pointer (A) Immediate addressing mode
(D) Address register and data register (B) Implied addressing mode
Q.7 Which is not a CPU architecture? (C) Register addressing mode
(A) Single accumulator architecture (D) Direct addressing mode
(B) General register architecture Q.13 An instruction is stored at location X with its
(C) Base register architecture address field at location X+1. The address field
(D) Stack register has the value Y. A processor register contains
the number Z. evaluate the effective address, if
Q.8 Effective address is calculated by adding or
addressing mode is
subtracting displacement value to
1. Direct
(A) Immediate address
2. Immediate
(B) Relative address
3. Relative
(C) Absolute address
4. Register indirect
(D) Base address
5. Index addressing
Q.9 In case the code is position independent, the Q.14 A relative branch mode type instruction is
most suitable addressing mode is stored in memory at address 300. The branch
(A) Direct mode is made to an address 450.
(B) Indirect mode What should be the value of relative address
(C) Relative mode field of the instruction?
(D) Indexed mode Q.15 Which of the following is/are true of the auto-
Q.10 The addressing mode that permits relocation, increment addressing mode?
without any change whatsoever in the code is I. It is useful in creating self-relocating
(A) Indirect addressing code.
(B) Base register addressing II. If it is included in an instruction set
architecture, then an additional ALU is
(C) Indexed register
required for effective address calculation
(D) PC relative addressing
III. The amount of increment depends on the
[GATE 1998, IIT Delhi] size of the data item accessed
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Computer Organization & Architecture [Workbook] 8 GATE ACADEMY®
(A) I only (B) II only field of instruction contains value 230. The
(C) III only (D) II and III value of Program Counter (PC) before the
fetch of this instructions (assume all the
Q.16 A computer has instruction size of 16 bits and
numbers in decimal) is _______.
has 16 programmer visible registers. Each
instruction has two source and one destination (A) 326 (B) 330
operands and uses only register direct (C) 334 (D) 322
addressing. The maximum number of op-codes Q.20 In which addressing mode, the effective
that this processor can have is equal to address of the operand is generated by adding
(A) 64 (B) 32 a constant value to the content of a register?
(C) 16 (D) 8 (A) Absolute mode
(B) Indirect mode
Q.17 Match List-I with List-II and select the correct
(C) Immediate mode
answer using the codes given below the lists.
(D) Index mode
List-I
Q.21 The register which keeps track of the execution
A. Indirect addressing of a program and which contains the memory
B. Immediate addressing address of the instruction which is to be
C. Auto decrement addressing executed next is known as______.
List-II (A) Index-Register
1. Loops (B) Memory address register
(C) Program counter
2. Pointers
(D) Instruction registers
3. Constants
Q.22 Relative Addressing Mode is used to write
Codes : position-independent code because
A B C (A) The Code in this mode is easy to atomize
(A) 3 2 1 (B) The Code in this mode is easy to
(B) 1 3 2 (C) The Code in this mode is easy to make
(C) 2 3 1 resident.
(D) Code executes faster in this mode.
(D) 3 1 2
Q.23 The register which contains the data to be
Q.18 A certain processor supports only the
written into or read out to the addressed
immediate and the direct addressing modes.
location is known as
Which of the following programming language
(A) Memory address register
features cannot be implemented on this
(B) Memory data register
processor?
(C) Program computer
(A) Pointers
(D) Index register
(B) Arrays
Q.24 An interrupt that can be temporarily ignored by
(C) Records the counter is known as
(D) Recursive procedures with local variable (A) Vectored interrupt
Q.19 An instruction of size 48 is stored in memory (B) Non- maskable interrupt
which is a branch instruction and it uses PC (C) Maskable interrupt
relative mode. The target for this instruction is (D) Low priority interrupt
stored on address 560. The relative address
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GATE ACADEMY® 9 Addressing Modes
Q.25 Consider a high-level language statement Assuming that memory location 100 contains
while [*i − − ] then which addressing mode is the value 35 (Hex), and the memory location
suitable for it? 200 contains the value A4 (Hex), what could
(A) Autoincrement be said about the final result?
(B) Indexed (A) Memory location 100 contains value A4
(C) Displacement (B) Memory location 100 contains value D4
(D) Autodecrement (C) Memory location 100 contains value D9
Q.26 Addressing mode is _____. (D) Memory location 200 contains value 35
(A) Explicitly specified Q.29 MOV [BX], AL type of data addressing is
called [ISRO 2011]
(B) Implied by the instruction
(A) Register addressing
(C) Both (a) and (b)
(B) Immediate addressing
(D) Neither (a) nor (b)
(C) Register indirect addressing
Q.27 Match List-I with List –II and select the correct
answer using the code given below the lists: (D) Register relative
List-I Q.30 The immediate addressing mode can be used
for
A. MOV X,R1
1. Loading internal registers with initial
B. STORE X
values 1.
C. POP X
2. Perform arithmetic or logical operation on
List-II data contained in instructions 2.
1. Three-address instruction Which of the following is true ? [ISRO 2020]
2. Zero-address instruction (A) Only 1
3. One-address instruction (B) Only 2
4. Two-address instruction (C) Both 1 and 2
Codes: (D) Immediate mode refers to data in cache
A B C
(A) 4 3 2
(B) 3 2 1
(C) 2 3 4
(D) None of these
Q.28 A certain processor executes the following set
of machine instructions sequentially.
MOV R0 , #0
MOV R1 ,100( R0 )
ADD R1 , 200( R0 )
MOV 100( R0 ), R1

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Computer Organization & Architecture [Workbook] 10 GATE ACADEMY®

Answers :

Classroom Practice Questions

1. A 2. B 3. D 4. B 5. C

6. D 7. 50 8. D 9. D 10. D

11. A 12. A 13. C 14. 16383 15. 500

640,
8, 24, 301,
16. 17. 18. 436 19. –16 20. B
224 × 32 942,
260
21. C 22. C 23. C 24. A 25. A

26. A 27. B 28. D 29. A 30. C

31. D 32. D 33. A 34. D 35. D

36. C 37. D 38. A 39. C

Self-Practice Questions

1. A 2. C 3. C 4. D 5. B

6. D 7. C 8. D 9. D 10. D

Y, X+1,
11. D 12. B 13. X+1+Y, 14. –150 15. C
Z, Y+Z
16. C 17. C 18. A 19. A 20. D

21. C 22. B 23. B 24. C 25. D

26. C 27. A 28. C 29. C 30 C



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 2 Control Unit

Classroom Practice Questions : Which of the following pairs of expressions

represent the circuit for generating control
Q.1 Arrange the following configurations for CPU
signals S5 and S10 respectively?
in decreasing order of operating speeds:
{(Ij + Ik) Tn indicates that the control signal
Hardwired control, vertical micro-
should be generated in time step Tn if the
programming, horizontal micro-programming
instruction being executed is Ij or Ik}
(A) Hardwired control, vertical micro-
(A) S5 = T1+I2.T3 and S10 =
programming, horizontal micro-
(I1+I3).T4+(I2+I4).T5
programming
(B) S5 = T1+(I2+I4).T3 and S10 =
(B) Hardwired control, horizontal micro-
(I1+I3).T4+(I2+I4).T5
programming, vertical micro-
programming (C) S5 = T1+(I2+I4).T3 and S10 =
(I2+I3+I4).T2+(I1+I3).T4+(I2+I4).T5
(C) Horizontal micro-programming, vertical
micro-programming, hardwired control (D) S5 = T1+(I2+I4).T3 and S10 =
(I2+I3).T2+I4.T3+(I1+I3).T4+(I2+I4).T5
(D) Vertical micro-programming, horizontal
micro-programming, hardwired control [GATE 2005, IIT Bombay]
[GATE 1999, IIT Bombay] Q.3 An instruction set of a processor has 125
signals which can be divided into 5 groups of
Q.2 A hardwired CPU uses 10 control signals S1 to
mutually exclusive signals as follows:
S10, in various time steps T1 to T5, to
implement 4 instructions I1 to I4 as shown Group 1 : 20 signals, Group 2 : 70 signals,
below : Group 3 : 2 signals, Group 4 : 10 signals,
Group 5 : 23 signals.
T1 T2 T3 T4 T5
How many bits of the control words can be
I1 S1, S3, S2, S4, S1, S7 S10 S3,
saved by using vertical microprogramming
S5 S6 S8
over horizontal microprogramming?
I2 S1, S3, S8, S9, S5, S6, S6 S10
(A) 0 (B)103
S5 S10 S7
(C) 22 (D) 55
I3 S1, S3, S7, S8, S2, S6, S10 S1,
[GATE 2005, IIT Bombay]
S5 S10 S9 S3
Q.4 Consider a CPU where all the instructions
I4 S1, S3, S2, S6, S5, S10 S6, S10
require 7 clock cycles to complete execution.
S5 S7 S9
There are 140 instructions in the instruction
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Computer Organization & Architecture [Workbook] 12 GATE ACADEMY®
set. It is found that 125 control signals are transmission with 1 start bit, 8 data bits, 2 stop
needed to be generated by the control unit. bit and 1 parity bit.
While designing the horizontal (i) What is the efficiency of the transmission
microprogrammed control unit, single address line?
field format is used for branch control logic. (ii) If the transfer rate of the line is 2000 bits
What is the minimum size of the control word per second, then effective transfer rate is?
and control address register? Q.8 An asynchronous link between two computers
(A)125, 7 (B) 125, 10 uses the start-stop scheme, with one start bit
(C) 135, 7 (D) 135, 10 and one stop bit, 8 data bits and a transmission
rate of 48.8kbits/s. what is the effective
[GATE 2008, IISc Bangalore]
transmission rate as seen by the two
Q.5 Consider the following data path diagram -
computers?
BUS
(A) 480 bytes/s (B) 488 bytes/s
(C) 4880 bytes/s (D) 4800 bytes/s
TEMP 1
Q.9 An asynchronous serial communication is
MAR MDR IR PC R0 TEMP 2
R1
employing 8 character bits, 1 parity bit, 2 start
ALU
bits and 1 stop bit. To maintain a rate of 500
To Memory R7
char/sec the minimum transfer rate should be
Consider an instruction: R0 ← R1 + R2. The required is ______ bits/sec?
following steps are used to execute it over the Q.10 Consider a CPU with clock rate of 200MHz. If
given data path. Assume that PC is the CPU has average of CPI of 5 then average
incremented approximately. The subscripts r instruction execution time is?
and w indicate read and write operations, Q.11 A CPU runs of 500MHz clock rate and is
respectively. executing a program which consists 1000
1. R2r ,TEMP1r , ALUadd ,TEMP2w instructions. If the measured average CPI
(Cycles per instructions) for the program is 6
2. R1r , TEMP1w
then total time required to run the program on
3. PCr , MAR w , MEMr CPU is ______ microseconds?
Q.12 During DMA master which of the following is
4. TEMP2r , R0w
not used by CPU
5. MDR r , IR w I. System Bus
Which one of the following is the correct order II. Memory
of execution of the above steps? III. ALU
(A) 3, 5, 1, 2, 4 (B) 3, 5, 2, 1, 4 IV. Registers
(A) Only I and II (B) Only III and IV
(C) 1, 2, 4, 3, 5 (D) 2, 1, 4, 5, 3
(C) Only I and IV (D) Only I, II and III
[GATE 2020, IIT Delhi]
Q.13 A microprogram is
Q.6 How many 8-bit characters can be transmitted
(A) Usually written in high level language
per second over 9600 bits/second serial
(B) A sequencing programme for the control
communication link using a parity
unit of any processor
synchronous mode of transmission with 1 start
(C) A programme for microcomputers
bit, 8 data bits, 2 stop bits and 1 parity bit?
(D) A programme written in assembly
Q.7 How many 8-bit character can be transmitted
language
using a parity synchronous mode of
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GATE ACADEMY® 13 Control Unit

Q.14 Statement (I) : The data path contains all Q.17 A microprogrammed control unit.
circuits to process data within the CPU with (A) Is faster than a hard- wired control unit.
help of which data is suitably transformed. (B) facilitates easy implementation of new
Statement (II) : It is the responsibility of the co instructions.
path to generate control and timing signals as (C) Is useful when very small programs are to
required by the opcode. be run.
Codes : (D) Usually refers to the control unit of a
(A) Both statement (I) and Statement (II) are microprocessor.
individually true and Statement (II) is the Q.18 In Flynn’s classification of computers, the
correct explanation of Statement (I) vector and array classes of machines belong to
(B) Both Statement (I) and Statement (II) are (A) Single instruction and single data category
individually true but Statement (II) is not (B) Single instruction and multiple data
the correct explanation of Statement (I) category
(C) Statement (I) is true but Statement (II) is (C) Multiple instruction and single data
false category
(D) Statement (I) is false but Statement (II) is (D) Multiple instruction and multiple data
true category
Q.15 In a microprocessor, the service routine for a Q.19 The following are the some of the sequences of
certain interrupt starts from a fixed location of operations in instruction cycle, which one is
memory which cannot be externally set, but the correct sequence?
interrupt can be delayed or rejected. Such an (A) 
interrupt is PC → Address register
(A) Non-maskable and non-vectored Data from memory → Data register
(B) Maskable and non-vectored Data register → IR
PC + 1 → PC
(C) Non-maskable and vectored
(B)
(D) Maskable and vectored
Address register → PC
Q.16 Consider the following statements :
Data register → Data from memory
1. The processor interrupts the program
Data register → IR
currently being executed.
PC+1 → PC
2. The action requested by the interrupt is

performed by the ISR.
(C) 
3. Interrupts are enabled and execution of
Data from memory → Data register
the interrupted program is resumed.
PC → Address register
4. The device raises an interrupt request.
Data register → IR
5. The device is informed that its request has
PC+1 → PC
been recognized and in response, it
deactivates the interrupt request signal. (D) None of these

Arrange the above statements meaningfully, Self-Practice Questions :

then what should be the sequence? Q.1 Two control signals in microprocessor which
(A) 4, 5, 1, 2, 3 (B) 4, 1, 5, 2, 3 are related to Direct Memory Access (DMA)
are
(C) 2, 4, 5, 1, 3 (D) 4, 5, 1, 3, 2
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Computer Organization & Architecture [Workbook] 14 GATE ACADEMY®
(A) INTR and INTA (B) the CPU does not know, which device
(B) RD and WR cause the interrupt without polling each
(C) SO and SI I/O interface.
(C) the branch address is always assigned to a
(D) HOLD and HLDA
fixed location in memory.
Q.2 The advantage of vertical Micro programmed
(D) None of the above
control unit is
Q.7 The system bus is made up of
(A) Faster than horizontal Micro programmed
(A) Data bus
control unit.
(B) Data bus and address bus
(B) Requires small size control memory
(C) Data bus and control bus
(C) Does not require signal memory (D) Data bus control bus and address bus
(D) All of the above Q.8 Horizontal microprogramming
Q.3 Data transfer between the main memory and (A) Does not require use of signal decodes.
the CPU register takes place through two (B) Results in larger sized micro-instructions.
registers, namely. (C) Uses one bit for each control signal.
(A) General purpose register and MDR (D) All of these
(B) Accumulator and Program counter Q.9 Asynchronous data transfer between two
(C) MAR and MDR independent units requires that control signals
(D) MAR and Accumulator be transmitted between the communicating
units to indicate the time at which data is being
Q.4 Which of the following are the advantages of a
transmitted, way of achieving this _____.
hard wired control over a micro programmed
control? (A) is by means of a strobe pulse from one of
the unit
1. It uses less hardware
(B) Is by means of handshaking
2. It generates control signal faster
(C) Both (a) and (b)
3. It is more reliable
(D) None of these
Select the correct answer using codes given Q.10 Which statement is false in case of
below. microprogram control?
(A) 1 and 2 (B) 1 and 3 (A) In a microprogram control, the control
(C) 2 and 3 (D) 1, 2 and 3 variables that initiate microperations are
Q.5 What is micro program? stroed in memory. The control memory is
(A) The name of source program in micro usually a ROM, since the control
computers sequence is permanent and needs no
alternation.
(B) The set of instructions indicating the
primitive operations in a system (B) The control variables stored in memory
are read one at a time to initiate the
(C) Primitive form of macros used in
sequence of microperations for the
assembly language programming
system.
(D) Program of very small size
(C) The words stored in a control memory are
Q.6 In a vectored interrupt : micro instructions, and each micro
(A) the interrupting device supplies the branch instruction specifies one or more
information to the processor through an microperations for the components in the
interrupt vector. system.

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GATE ACADEMY® 15 Control Unit

(D) Once these microoperations are executed, Q.12 A CPU runs at 80MHZ and executing
the control unit must determine its next instructions with average cycles per instruction
address. Therefore, all bits of the micro (CPI) as 1.6. The MIPS (million instructions
instruction are used to control the per second) count of the CPU is
generation of the address for the next (A) 50 (B) 60
micro instruction. (C) 500 (D) 600
Q.11 During DMA transfer, DMA controller takes
over the busses to manage the transfer
(A) Directly from CPU to memory
(B) Directly from memory to CPU
(C) Indirectly between the I/O device and
memory
(D) Directly between the I/O device and
memory

Answers :

Classroom Practice Questions

1. B 2. D 3. B 4. D 5. B

800 2/3, 1333

6. 7. 8. C 9. 6000 10. 0.025 μsec
char/bit bits/second
11. 12 12. A 13. B 14. A 15. D

16. B 17. B 18. B 19. A

Self-Practice Questions

1. D 2. B 3. C 4. C 5. B

6. A 7. D 8. D 9. C 10. D

11. D 12. A



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 3 Pipelining

Classroom Practice Questions : clock cycles for the EX stage depends on the
instruction. The ADD and SUB instructions
Q.1 The performance of a pipelined processor
need 1 clock cycle and the MUL instruction
suffers if
needs 3 clock cycles in the EX stage. Operand
(A) The pipeline stages have different delays
forwarding is used in the pipelined processor.
(B) Consecutive instructions are dependent on
What is the number of clock cycles taken to
each other
complete the following sequence of
(C) The pipeline stages share dependent instructions?
hardware resources
ADD R2, R1, R0, R 2 ← R1 + R 0
(D) All of the above
[GATE 2002, IISc Bangalore] MUL R4, R3, R2, R 4 ← R3* R 2
Q.2 A 4-stage pipeline has the stage delays as 150, SUB R6, R5, R4, R 6 ← R5 − R 4
120, 160 and 140 nanoseconds respectively.
(A) 7 (B) 8
Registers that are used between the stages have
(C) 10 (D) 14
a delay and 5 nanoseconds each. Assuming
constant clocking rate, the total time taken to [GATE 2007, IIT Kanpur]
process 1000 data items on this pipeline will be Q.4 Consider a 4-stage pipeline processor. The
(A) 120.4 microseconds number of cycles needed by the four
(B) 160.5 microseconds instructions I1 , I 2 , I 3 , I 4 in stages
(C) 165.5 microseconds S1 , S 2 , S3 , S 4 is shown below.
(D) 590.0 microseconds S1 S2 S3 S4
[GATE 2004, IIT Delhi]
I1 2 1 1 1
Q.3 Consider a pipelined processor with the
following four stages. I2 1 3 2 2
IF : Instruction Fetch I3 2 1 1 3
ID : Instruction Decode and
Operand Fetch I4 1 2 2 2
EX : Execute
What is the number of cycles needed to
WB : Write Back execute the following loop?
The IF, ID and WB stages take one clock cycle
For (i = 1 to 2){(I1; I2; I3; I4)}
each to complete the operation. The number of
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GATE ACADEMY® 17 Pipelining

(A) 16 (B) 23 relative frequencies of there operations are 40

(C) 28 (D) 30 %, 20 %, 40 % respectively. Suppose that due
[GATE 2009, IIT Roorkee] to clock skew and setup, pipelining the
Q.5 The instruction pipeline of a RISC processor machine adds 1 ns overhead to the clock. How
has the following stages: Instruction Fetch much speed up in the instruction execution rate
(IF), Instruction Decode (ID), Operand Fetch will be gain from a pipeline?
(OF), Perform Operation (PO) and Writeback (A) 5 times (B) 8 times
(WB), The IF, ID, OF and WB stages take 1 (C) 4 times (D) 4.5 times
clock cycle each for every instruction. Q.9 A 5 stage pipeline is used to overlap all the
Consider a sequence of 100 instructions. In the instructions except the branch instructions.
PO stage, 40 instructions take 3 clock cycles The target of the branch can’t be fetched till the
each, 35 instructions take 2 clock cycles each, current instruction is completed. What is
and the remaining 25 instructions take 1 clock throughput of the system if 20 % of
cycle each. Assume that there are no data instructions are branch instructions? Ignore the
hazards and no control hazards. overhead of buffer register. Each stage is
The number of clock cycles required for having same amount delay. The pipeline clock
completion of execution of the sequence of is 10 ns. Branch penalty is of 4 cycles.
instruction is ______ . (A) 55 MIPS (B) 45 MIPS
[GATE 2018, IIT Guwahati] (C) 65 MIPS (D) None of these
Q.6 Given a 5 stage pipeline with stages taking 1, Q.10 Pipelining is an implementation technique
2, 3, 1, 1 units of time, the clock period of the where multiple instructions are overlapped in
pipeline is execution. What among the given is the
(A) 8 (B) 1/8 function of the pipeline.
(C) 1/3 (D) 3 (A) Increase the length of machine cycle
Q.7 Consider a pipeline processor with 4 stages S1 (B) Decrease the individual instruction
to S4. We want to execute the following loop: execution time
for (i = 1; i < = 1000; i + + )[ I 1, I 2, I 3, I 4] (C) Increase the instruction throughput
(D) None of these
Where the time taken (in ns) by instructions
Q.11 Assume the individual stages of the data path
I 1 to I 4 for stages S1 to S 4 are given below:
have the following latencies.
S1 S2 S3 S4 Instruction fetch (IF) : 12 ns
I1 1 2 1 2 Instruction decode (ID) : 8 ns
I2 2 1 2 1 Execution (EX) : 6 ns
I3 1 1 2 1 Memory(MEM) : 9 ns
I4 2 1 2 1 Write back (Wb) : 5 ns
Find the clock time (in ns) in a non-pipelined
The output of I1 for i = 2 will be available
(single cycle) processor.
after
(A) 40 (B) 60
(A) 11 ns (B) 12 ns
(C) 35 (D) 45
(C) 13 ns (D) 28 ns Q.12 A branch mark program is running on a 40
Q.8 Consider the unpipelined machine with 10 ns MHz processor. The executed program
clock cycles. It uses four cycles for ALU consists of 100000 instruction executions, with
operations and branches, whereas five cycles the following instruction mix and clock cycle
for memory operations. Assume that the count.
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Computer Organization & Architecture [Workbook] 18 GATE ACADEMY®
Instruction Instruction Cycles per Q.15 A non-pipeline system takes 50 ns to process a
type count instruction task. The same task can be processed in a six-
segment pipeline with a clock cycle of 10ns.
Integer 45000 1
Determine the speedup ratio of the pipeline for
arithmetic
100 tasks. What is the maximum speedup that
Data transfer 32000 2 can be achieved?
Floating point 15000 2
Self-Practice Questions :
Control 8000 2
Q.1 Pipeline improves CPU performance due to
transfer
(A) Reduced memory access time
The execution time in msec is _______. (B) Increased clock speed
Q.13 Assume a stage pipeline with the following (C) The introduced of parallelism
stages :
(D) Additional functional units
S1 : Instruction fetch
Q.2 An instruction cycle refers to
S 2 : Instruction decode (A) Fetching an instruction
S3 : Execute (B) Clock speed

S 4 : Memory write (C) Fetching, decoding and executing an

instruction
S5 : Write back
(D) Executing an instrument
Program consists of 16 instructions Q.3 Assume that the time required for the eight
( I1 , I 2 , I 3 ,......I16 ) . In which I 6 is a functional units, which operate in each of the
unconditional branch instruction transfer the eight cycles, are as follows
controls of I12 . In the pipeline, branch target 5ns, 8ns, 6ns, 10ns, 15ns, 12ns, 6ns, 8ns
address will be available at the end of execute Assume that pipe lining adds 1 ns of overhead
state. Each instruction spends the same amount find the speedup versus the single cycle data
of time in all the pipeline stages. The cycle path.
time of the pipeline is 10 nsec. What is the time (A) 4.67 (B) 4.375
(in nsec) required to execute the above (C) 4.44 (D) 4.285
program without using branch prediction?
Q.4 What is the control unit’s function in the CPU?
(A) 170 (B) 180
(A) To decode program instructions
(C) 200 (D) 140
(B) To transfer data to primary storage
Q.14 Which of the following instruction processing
(C) To perform logical operations
activity of the CPU can be pipelined?
(D) To store program instructions
1. Instruction encoding
Q.5 We have two designs D1 and D 2 for a
2. Operand loading
synchronous pipeline processor. D1 has 5
3. Operand storing
pipeline stages with execution times of 3 nsec,
(A) 1 and 2 only 2 nsec, 4 nsec, 2 nsec and 3 nsec while the
(B) 2 and 3 only design D 2 has 8 pipeline stages each with 2
(C) 1 and 3 only nsec execution time. How much time can be
(D) 1, 2 and 3 saved using design D 2 over design D1 for
executing 100 instructions?
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GATE ACADEMY® 19 Pipelining

(A) 214 nsec (B) 202 nsec The average operand fetch rate of CPU is
(C) 86 nsec (D) 200 nsec ______.
Q.6 What will be the efficiency (in percentage) of (A) 40.8 (B) 56.8
the pipeline if 5 stage pipelined with the (C) 60.8 (D) 58.7
respective delay of 20, 30, 40, 50, 60? Q.9 A 5 stage pipelined processor has IF, ID, EXE,
Q.7 Consider a pipelined system with four stages : MEM and WB. WB stage operation is divided
IF, ID, EX, WB. Following chart shows the into two parts. In the first part register write
clock cycles required by each instruction to operation and in the second part register read
complete each stage. operation is performed. The latencies of all
Instruction Instruction Write those stages are 300, 400, 500, 500 and 300 (in
Instru- Instruction
Decode Execute Back nano second) respectively. Consider the
ctions Fetch (IF)
(ID) (EX) (WB) following code is executed on this processor.
I0 1 1 2 1 I1 : ADD R3 , R2 , R4 ; R3 → R2 + R4
I1 2 2 3 1 I 2 : SUB R6 , R4 , R3 ; R6 → R4 − R3
I2 2 2 2 2 I3 : ADD R7 , R5 , R3 ; R7 → R5 + R3
I3 2 1 1 1 I 4 :SUB R1 , R7 , R4 ; R1 → R7 − R4
I4 3 2 1 2 Find minimum number of nop instructions (no
operation) to eliminate hazards without using
How many clock cycles are required to operand forwarding. (Assume each instruction
complete the above instructions? takes one cycle to complete its operation in
(A) 16 (B) 9 ever stage).
(C) 14 (D) 13 Q.10 Comparing the time T 1 taken for a single
Q.8 Consider a hypothetical processor operating on instruction on a pipelined CPU with time T 2
500 MHz frequency which uses different taken on a non-pipelined but identical CPU, we
operand accessing mode described below : can say that [GATE 2000, IIT Kharagpur]
Operand Fetching Frequency (A) T 1 ≤ T 2
Mode (%) (B) T 1 ≥ T 2
Indirect addressing mode 25 (C) T 1 < T 2
Direct addressing mode 30 (D) T 1 is T 2 plus the time taken for one
instruction fetch cycle
Register addressing mode 20
Q.11 For a pipelined CPU with a single ALU,
Register indirect 15
consider the following situations
addressing mode
1. The j + 1 instruction uses the result of the
Indexed addressing mode 10
j − th instruction as an operand
Consider the following data regarding different 2. The execution of a conditional jump
operations performed : instruction
Operation No. of cycle needed 3. The j − th and j + 1 instructions require
Memory reference (MR) 8 the ALU at the same time
ALU operation 4 Which of the above can cause a hazard?
Register reference (RR) 0 [GATE 2003, IIT Madras]
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Computer Organization & Architecture [Workbook] 20 GATE ACADEMY®
(A) 1 and 2 only (B) 2 and 3 only Q.13 A non pipelined single cycle processor
(C) 3 only (D) All of above operating at 100 MHz is converted into a
synchro-nous pipelined processor with five
Q.12 Consider an instruction pipeline with four
stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5
stages (S1, S2, S3 and S4) each with
nsec and 2.5 nsec, respectively. The delay of
combinational circuit only. The pipeline
the latches is 0.5 nsec. The speedup of the
registers are required between each stage and
pipeline processor for a large number of
at the end of the last stage. Delays for the
instructions is
stages and for the pipeline registers are as
given in the figure. [GATE 2008, IISc Bangalore]
(A) 4.5 (B) 4.0
Pipeline Register (Delay 1 ns)

(C) 3.33 (D) 3.0

Pipeline Register (Delay 1 ns)

Pipeline Register (Delay 1 ns)

Pipeline Register (Delay 1 ns)

Q.14 Which of the following are true in a pipelined
Stage Stage Stage Stage
S1 S2 S3 S4 processor?
Delay Delay Delay Delay
5ns 6ns 11ns 8ns
1. Bypassing can handle all RAW hazards.
2. Register renaming can eliminate all
register carried WAR hazards.
What is the approximate speedup of the 3. Control hazard penalties can be
pipeline in steady state under ideal conditions eliminated by dynamic branch prediction.
when compared to the corresponding non-
[GATE 2008, IISc Bangalore]
pipeline implantation?
(A) 1 and 2 only (B) 1 and 3 only
[GATE 2011, IIT Madras]
(C) 2 and 3 only (D) 1, 2 and 3
(A) 4.0 (B) 2.5
(C) 1.1 (D) 3.0

Answers :

Classroom Practice Questions

1. D 2. C 3. B 4. D 5. 219

6. D 7. A 8. C 9. A 10. C

11. A 12. B 13. A 14. B 15. 5

Self-Practice Questions

1. C 2. C 3. b 4. A 5. B

6. 67 7. A 8. B 9. 4 10. B

11. D 12. B 13 C 14. B



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