International Journal of Electronics Signals and Systems

Volume 2 Issue 1 Article 10

July 2012

DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC

ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS
COMPARATOR USING CUSTOM DESIGN APPROACH
CHANNAKKA LAKKANNAVAR
Department of E&CE., S.D.M. College of Engineering & Technology, Dharwad-02, [email protected]

SHRIKANTH K. SHIRAKOL
Department of E&CE., S.D.M. College of Engineering & Technology, Dharwad-02, [email protected]

KALMESHWAR N. HOSUR
Department of E&CE., S.D.M. College of Engineering & Technology, Dharwad-02,
[email protected]

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Recommended Citation
LAKKANNAVAR, CHANNAKKA; SHIRAKOL, SHRIKANTH K.; and HOSUR, KALMESHWAR N. (2012)
"DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC ARCHITECTURE WITH DIFFERENTIAL
AMPLIFIER AS COMPARATOR USING CUSTOM DESIGN APPROACH," International Journal of Electronics
Signals and Systems: Vol. 2 : Iss. 1 , Article 10.
DOI: 10.47893/IJESS.2012.1065
Available at: https://www.interscience.in/ijess/vol2/iss1/10

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 DESIGN, IMPLEMENTATION AND ANALYSIS OF FLASH ADC
ARCHITECTURE WITH DIFFERENTIAL AMPLIFIER AS
COMPARATOR USING CUSTOM DESIGN APPROACH

1
CHANNAKKA LAKKANNAVAR, 2SHRIKANTH K. SHIRAKOL, 3KALMESHWAR N. HOSUR
1, 2, 3
Department of E&CE., S.D.M. College of Engineering & Technology, Dharwad-02
1
[email protected] , [email protected], [email protected]

Abstract— Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage
read channel and an optical receiver because they represent the interface between the real world analog signal and the
digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-to-
digital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using
180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption
are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit
precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard
gpdk180nm technology library using Cadence tool.

Keywords— Flash ADC, Resolution, power consumption, gpdk180

.

I. INTRODUCTION implemented with pipelined, successive

approximation, and sigma-delta modulators. These
With the rapid growth of modern communications are all useful for the medium speed conversion and
and signal processing systems, handheld wireless high resolution applications. On the other hand, the
computers and consumer electronics are becoming flash architecture is suitable for high speed
increasingly popular. Mixed-signal integrated circuits conversion and low resolution applications due to its
have a tendency in the design of system-on-chip parallel architecture.
(SOC) in recent years. SOC designs have made
possible substantial cost and form factor reductions, II. BACKGROUND
in part since they integrate crucial analog interface
circuits, such as ADCs with digital computing and The paper on “The CMOS Inverter as a
signal processing circuits on the same die. The Comparator in ADC Designs”, spinger Analog
interfaces only occupy a small fraction of the chip die Integrated Circuits and Signal Processing, Vol.39,
and for SOC designs, the technology selection and pp.147-155, 2004 by Tangel A. Choi K discussed
system design choices are mainly driven by digital about the advancement of technology, digital signal
circuit requirements [1]. processing has progressed dramatically in recent
For high-speed applications, a flash ADC is often years.
used. Resolution, speed, and power consumption are Signal processing in digital domain provides high
the three key parameters for an analog-to-digital level of accuracy, low power consumption and small
converter (ADC). These parameters cannot be silicon area besides providing flexibility in design
changed once an ADC is designed. While one can use and programmability. The design process is also quite
6-bit precision from an 8-bit ADC, it is non-optimal faster and cost effective. Furthermore, their
resulting in slower speed and extra power implementation makes them suitable for integration
consumption due to full 8-bit internal operation. In with complex digital signal processing blocks in a
this paper, a new flash ADC design is proposed that compatible low-cost technology, particularly CMOS
is a true variable-power and variable-resolution ADC. [1].
It can operate at higher speed and will consume less This evolution of technology provides much faster
power when operating at a lower resolution. Such transistors with smaller sizes, making it possible to
features are highly desirable in many wireless and have very high clock rate in digital circuits. In the
mobile applications. For example, the strength of a end, it leads us to design a very high speed as well as
radio frequency (RF) signal varies greatly depending systems with small die area called System on a chip
on geographic location. Optimally, the ADC (SoC), with a smaller number of chips using
resolution can be reduced upon the reception of increased integration level.
strong signal and can be increased upon the reception However, “CMOS Integrated Analog-to-Digital and
of weak signal. Substantial reduction in power Digital-to-Analog Converters”, 2nd Edition, 2005 by
consumption at lower resolution will prolong the Rudy J. van de Plassche et al, deals with the evolution
battery life [1]. Low power ADC architectures are

International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231-5969, Vol-2, Iss-1
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Design, Implementation and Analysis of Flash ADC Architecture with differential amplifier as Comparator Using Custom Design Approach

of technology has not provided same level of benefit advantages as an improved gain, or power savings
for the analog circuit design. So to extract the that would have benefit to our ADC precision and
advantages of digital signal processing, there is a efficiency. When the input signal voltage is less than
trend of shifting signal processing from analog to the reference voltage, the comparator output is at
more efficient digital domain and dealing with the logic ‘0’.when the input signal voltage is higher than
analog signals only in the input-output stages. This the reference voltage, the comparator output is at
has resulted in the requirement of smart converters logic ‘1’. The comparators give the 2n-1 levels of
between analog and digital signals to cope up with outputs in terms of reference voltage.
the evolution of technology [3].
Section III discuss about the ADC architecture, in the mean 3. Priority encoder: The output of the comparators is
while Section IV about its Implementation. Section V, VI in the encoded form. Therefore a priority encoder has
describes the experimental results and Conclusion to be designed in order to convert the encoded signal
respectively. into n bits data (digital) which is unipolar binary
code[4][6].
III. FLASH ADC ARCHITECTURE
VI. DESIGN AND IMPLEMENTATION

This section deals with implementation of three

components as discussed in section III.
1. The resistor string
The 4 bit flash ADC, needs 24 resistances [fig.,1].
The two extreme resistors are calculated to delimit
the voltage input range. Each resistor divides the
reference voltage to feed a comparator. The higher
the resistance value is, the weaker the current is
consumed in the device. That is why a high resistance
will minimize power dissipation. Nevertheless, we
Fig.1: Flash ADC architecture have to put a reasonable value for this resistor string:
it should stand lower than the input resistance of the
The above Fig.1., shows a typical flash ADC comparators. We expected to convert any voltage
block diagram. For an "4" bit converter, the circuit between 0 and 1.8 V.
employs 24-1= 15 comparators. A resistive divider In general, the voltage division takes place as follows:
with 24 = 16 resistors provides the reference voltage Va = (M*Vref)/2n …………… (1)
The reference voltage for each comparator is one Where,
least significant bit (LSB) greater than the reference M = No., of resistors at which voltage division
voltage for the comparator immediately below it. occurs.
Each comparator produces a "1" when its analog n = No., of bits.
input voltage is higher than the reference voltage 2n = Total No., of resistors used.
applied to it. Otherwise, the comparator output is "0". The design of resister string for proposed Flash ADC
The Flash ADC consists of the following components is done using schematic approach in cadence as
which are given below: shown in fig., 2.
1. Resister string: In an ‘n’ bit flash ADC, 2n
resistances are necessary. The two extreme resistors
are calculated to delimit the voltage input range. Each
resistor divides the reference voltage to feed a
comparator. The higher the resistance value is, the
weaker the current is consumed in the device. That is
why a high resistance will minimize power
dissipation. Nevertheless, we have to put a reasonable
value for this resistor string: it should stand lower
than the input resistance of the comparators.

2. Comparator: Here 2n-1 differential amplifiers are

used as comparators in“n” bits flash-ADC
architecture. We first tried to implement a complex
type of differential amplifier. But this element was
not easy enough to understand and use for beginners.
We consequently decided to prefer a basic design to
realize our ADC. This decision made us loose several
Fig. 2: Resistor string for proposed flash ADC.

International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231-5969, Vol-2, Iss-1
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Design, Implementation and Analysis of Flash ADC Architecture with differential amplifier as Comparator Using Custom Design Approach

The Table I show the voltage division for resistor Hence forth the design of comparator is shown in fig.
string with reference voltage is taken to be 1.8 V. 3., uses
24-1=15 differential amplifiers are used as
Table I: Voltage division occurs as follows: comparators in 4-bit flash-ADC architecture.
Working of Comparator:
M* Va*= (M*Vref)/2n When the input signal voltage is less than the
reference voltage, the comparator output is at logic
Tap 1 0.1125V ‘0’.when the input signal voltage is higher than the
Tap 2 0.225V reference voltage, the comparator output is at logic
Tap 3 0.3375V ‘1’. The comparators give the 15 levels of outputs in
Tap 4 0.45V terms of reference voltage. In transient response,
Tap 5 0.5625V during 0 to 5ns time V1 is ‘0’,V2 is ‘1’,so output will
Tap 6 0.675V be ‘0’ because V1<V2 and during 5 to 10 ns time V1
Tap 7 0.7875V is ‘1’,V2 is ‘0’, so output will be ‘1’ because V1>V2.
Tap 8 0.9V
Tap 9 1.0125V 3. Priority encoder stage:
Tap 10 1.125V
Tap 11 1.2375V
Tap 12 1.35V
Tap 13 1.4625V
Tap 14 1.575V
Tap 15 1.6875V
Tap 16 1.8V
*M= Resistor tap Number & Va=Voltages of each
resistor tap
2. The Comparator
Fig. 4: Priority encoder stage
The proposed flash ADC consists of comparator as
one of the important component, this comparator is The output of the comparators is in the encoded form.
designed in such a way that which is less immunity Therefore a priority encoder has to be designed in
for noise and with high common mode rejection ratio. order to convert the encoded signal into 4 bits data
Hence, the Differential Amplifier is used to achieve (digital) which is unipolar binary code.
the same. The logic employed in designing the priority encoder
is explained as follows,
D1=C1C′2C′4C′6C′8C′10C′12C′14+C3C′4C′6C′8C′10C′12C′
14+C5C′6C′8C′10C′12C′14+C7C′8C′10C′12C′14+C9C′10C′12
C′14 +C11C′12C′14+C13C′14+C15.

D2=C2C′4C′5C′8C′9C′12C′13+C3C′4C′5C′8C′9C′12C′13+C
6C′8C′9C′12C′13+C7C′8C′9C′12C′13+C10C′12C′13+C11C′12
C′13 +C14 +C15.

D3=C4C′8C′9C′10C′11+C5C′8C′9C′10C′11+C6C′8C′9C′10C
′11+C7
C′8C′9C′10C′11+C12+C13+C14+C15.

D4 = C8+C9+C10+C11+C12+C13+C14+C15.

V. EXPERIMENTAL RESULTS

This Section clearly disscuss about the simulation

results of above said three important components of
flash ADC, the work is carried out on cadence
virtuoso the simulation is done using spectre and
layout using assura.
Fig.5., discuss about transient response for resistor
Fig. 3. Proposed comparator design
string of voltage at resister taps. These tap voltages
become inputs to comparator stage.

International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231-5969, Vol-2, Iss-1
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Design, Implementation and Analysis of Flash ADC Architecture with differential amplifier as Comparator Using Custom Design Approach

Fig. 8 shows transient response for Vin = 0.8V, so

here Vin will be in range between 0.7875≤Vin≥0.9,
so comparator output will be “000000011111111”
and priority encoder output will be “0111”.

Fig. 5: Transient response for resistor string.

When the input signal voltage is less than the
reference voltage, the comparator output is at logic
‘0’,when the input signal voltage is higher than the
reference voltage, the comparator output is at logic
‘1’. The comparators give the 15 levels of outputs in Fig 8: Transcient response for Vin=0.8V, output will be 0111
terms of reference voltage. In transient response,
during 0 to 5ns time V1 is ‘1’,V2 is ‘0’, hence output
will be ‘1’ because V1>V2 and during 5 to 10 ns time
V1 is ‘0’,V2 is ‘1’, hence output will be ‘0’ because
V1<V2 shown in Fig.6.,

Fig.9: Transient response for Vin = 1.02V, output will be 1001

Fig. 9 shows transient response for Vin = 1.02V, so

Fig.6: Transient response for comparator here Vin will be in range between 1.0125≤Vin≥1.125,
so comparator output will be “000000111111111”
The schematic simulation of 4 bit Flash and priority encoder output will be “1001”.
ADC using Cadence tool is shown in Fig.7-11.

Fig.7., shows transient response for Vin = 0V, so here

Vin will be in range between 0≤Vin≥0.112, so
comparator output will be “000000000000000” and
priority encoder output will be “0000”.

Fig.10: Transient response for Vin = 1.8V, output will be 1111

Fig.10. shows transient response for Vin = 1.8V, so

here Vin will be in range between 1.6875≤Vin, so
comparator output will be “111111111111111” and
Fig.7: Transient response for Vin=0V, output will be 0000 priority encoder output will be “1111”.

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Design, Implementation and Analysis of Flash ADC Architecture with differential amplifier as Comparator Using Custom Design Approach

nwell & nmos with psubstrate,each comparator is

constructed from 32 pcapacitor & 13 presister pmos
Table II. Specifications Summary of ADC
and nmos of width 2µm and length 180ηm.
Calculated layout area is 821634.1415 (ηm)2 .
Technology 180ηm
Analog voltage, Vin 0 to 1.8V
Reference voltage, Vref 1.8V
Vdd 4V
Resolution 4-bits
Speed 3.8 GS/sec
Power Dissipation 49.94mW
SNR 25.84 dB
Standard Deviation 12ηs
Mean 19ηs
Calculated layout area 821634.145
(ηm)2

Resisters Priority encoder stage

Comparator
stage stage

Fig. 12: Layout design of Flash ADC

VII. CONCLUSION

The schematic and layout of register stage,

comparator stage, and priority encoder stage are
designed and integrated. From table II Gives brief
design summary of flash ADC i.e., the integrated
flash ADC is operated at 4-bit precision with analog
Fig. 11: Flash ADC outputs for analog input of 0 to 1.8V and input voltage of 0 to 1.8V, supply voltage 4V,
4.4M Hz Input frequency
Resolution 4bits, SNR 25.84dB, consumes 49.94mW
power, speed is 3.8GS/s and layout Area is
Fig.11., shows outputs for analog input of 0 to 1.8V 0.821634µm2. The ADC is designed and
and 4.4M Hz input frequency using sample and hold implemented in standard gpdk180nm cmos
circuit. technology of version – IC 6.1 using Cadence
virtuoso tool.
VI. Layout design for proposed ADC design
ACKNOWLEDGMENT
Layout design of resister string made up of
16 polyresisters metals, which is connected to 15 We thank the Management, the Principal/Director
outputs with Metal1-poly, this design is made inside and Staff of Sri Dharmasthala Manjunatheshwara
PR (Place and Route) boundary, each Resister is College of Engineering and Technology, Dhavalgiri,
constructed from polycrystalline silicon and poly is Dharwad, Karnataka, India for encouraging us for
having width of 600ηm, segment length of 79.2µm, this research work.
sheet resistivity 7.5Ω, body resistance 990Ω, contact First and second Authors express their heartily thanks
resistance 10Ω and end resistance 0Ω. Layout design to Prof. Kotresh E. Marali, for his kind support in
of comparator, totally it contains two pmos & nmos carrying out this research work.
of gpdk180 libraries, where pmos is connected with

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Design, Implementation and Analysis of Flash ADC Architecture with differential amplifier as Comparator Using Custom Design Approach

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