EE214

Analog Integrated Circuit Design

Boris Murmann
Stanford University
[email protected]
Copyright © 2004 by Boris Murmann

B. Murmann EE 214 Lecture 1 (HO#2) 1

 A Few Words About Your Instructor

• New Assistant Professor in EE

• PhD, UC Berkeley 2003
– Digitally assisted A/D conversion
– Use sloppy analog circuits (low power, fast)
– Correct errors using digital post-processor
• ~ 4 years work experience in IC industry
– Mixed signal IC design, low power, high voltage
• Current research direction
– Advanced digital correction schemes for data converters
– Analog/Digital/Communication layer co-design and cross-
level optimization

B. Murmann EE 214 Lecture 1 (HO#2) 2

 EE214 Basics (1)

• Teaching assistants
– Mona Jarrahi, Jason Hu
– OH hours: Tue, Wed, Thu and Sun 6-7:30 PM (CIS lounge)
– Review session: Fridays1:15-2:05, Skilling 191 (Live on E3)
• Administrative support
– Ann Guerra, CIS 207
• Lectures are televised and on the web, but please come to class
to keep the discussion intercative
• Web page: http://eeclass.stanford.edu/ee313
– Check regularly, especially FAQ section
– Register for online access to grades and solutions

B. Murmann EE 214 Lecture 1 (HO#2) 3

 EE214 Basics (2)

• Required text
– Analysis and Design of Analog Integrated Circuits, 4th
Edition, Gray, Hurst, Lewis and Meyer, Wiley, 2001.
• Useful reference
– The Designer’s Guide to Spice and Spectre, Ken Kundert,
Kluwer Academic Publishers, 1995. (On reserve in
Engineering Library)
• Course prerequisites
– EE101B or equivalent
– Basic device physics and models
• PN junctions, MOSFETs, BJTs
– Basic linear systems (poles, zeros)
– Please talk to me if you are not sure if you have the required
background

B. Murmann EE 214 Lecture 1 (HO#2) 4

 Assignments

• Homework: (30%)
– Handed out on Mondays, due following Monday in class
– No credit for late homework
– Policy for off-campus students: Fax/send before deadline
stated on handout
• Midterm Project: (30%)
– Design of an amplifier
– Work individually, OK to discuss with others
– No layout, just design and simulation
• Final Exam (40%)

B. Murmann EE 214 Lecture 1 (HO#2) 5

 Honor Code

• Please remember you are bound by the honor code

– I will trust you not to cheat
– I will try not to tempt you
• But if you are found cheating it is very serious
– There is a formal hearing
– You can be thrown out of Stanford
• Save yourself and me a huge hassle and be honest
• For more info
– http://www.stanford.edu/dept/vpsa/judicialaffairs/guiding/pdf/
honorcode.pdf

B. Murmann EE 214 Lecture 1 (HO#2) 6

 Be Reasonable When Asking TAs

• The TAs will not give you "the answer times two"…
• They will also not debug your Spice deck
– Figuring out what's wrong with your circuit is an essential
component of this class

B. Murmann EE 214 Lecture 1 (HO#2) 7

 Circuit Simulation

• Primary tools: HSpice/AWaves

– You can use other tools at "own risk" (e.g. LTSpice)
– Tutorial docs and example simulation decks for HSpice and
LTSpice are provided in private area of web site
• Great alternative to AWaves: Plot HSpice results using Matlab
– Download "Hspice Toolbox" at:
http://www-mtl.mit.edu/research/perrottgroup/tools.html#hspice

• EE214 Technology
– 0.35µm CMOS
– BSIM3v3 models provided in private area of web site
• First review session (this week) will focus on simulation basics

B. Murmann EE 214 Lecture 1 (HO#2) 8

 A Word of Caution
• What most people know
– Even a very large number of monkeys randomly arranging
characters will probably never manage to write an interesting
book
• What some people tend to forget
– Even a very large number of "Spice Monkeys" will never
come up with an interesting new circuit that outperforms
state-of-the-art
• Spice is nothing but a "calculator" that lets you evaluate and test
your ideas
• There is no need to simulate anything unless you already know
the (approximate) answer!

B. Murmann EE 214 Lecture 1 (HO#2) 9

 Course Topics

• CMOS technology and device models

• Single-stage and multi-stage amplifiers
• Current sources and mirrors, active loads
• Differential pairs
• Operational and transconductance amplifiers
• Feedback, stability and compensation
• Temperature and supply independent biasing
• Electronic noise basics

B. Murmann EE 214 Lecture 1 (HO#2) 10

 Lecture 1
CMOS Technology
Long Channel MOS Model

Boris Murmann
Stanford University
[email protected]
Copyright © 2004 by Boris Murmann

B. Murmann EE 214 Lecture 1 (HO#2) 11

 Overview
• Reading
– 2.8 (MOS fabrication), 2.9 (Active MOS devices)
– 2.10.1 (Resistors), 2.10.2 (Capacitors)
– 1.1, 1.5.0, 1.5.1, 1.5.2, 1.5.3 (Large signal MOS model)
• Introduction
– In this first lecture, we will cover some of the background
that positions EE214 as an introductory course on circuit
design using CMOS technology. In the lectures to come, we
will focus on the problem of amplifier design as a vehicle to
establish a set of considerations that apply to more complex
circuits and also other technologies. At first, we will review
the ‘long channel model’ of a MOS transistor. Driven by
circuit examples, we will later augment this simple model to
include additional effects that are relevant to analog circuit
design.

B. Murmann EE 214 Lecture 1 (HO#2) 12

 The Big Picture

Transducer Frequency
User
Antenna Amplifier Translation, ADC DSP
Interface
Sensor Filtering

EE252 EE214 EE314 EE264

EE315
EE312 EE314 EE315 EE271
... ….

• Most modern electronic information processing systems rely on

amplification of "small" physical signals
– E.g. signal from RF antenna, disk drive head, microphone, …
• EE214 uses amplifiers as a vehicle to teach you the basics of
analog integrated circuit analysis and design
– Material forms basis for more complicated circuits

B. Murmann EE 214 Lecture 1 (HO#2) 13

 The Decomposition/Modeling Problem

Here's a
simple
hydraulic
model of
our
amplifier

B. Murmann EE 214 Lecture 1 (HO#2) 14

 Analysis vs. Design
• Unlike common perception, analog circuit analysis and design is
not "black magic"
• Circuit analysis
– The art of decomposing a circuit into manageable pieces
– Based on the simplest, but sufficiently accurate models
– One circuit ⇒ One solution
• Circuit design
– The art of synthesizing circuits based on experience from
extensive analysis
– One set of specifications ⇒ Many solutions
– Design skills are best acquired through "learning by doing"
• This is why we'll have a midterm design project

B. Murmann EE 214 Lecture 1 (HO#2) 15

 Technological Progress

Vacuum Tube Transistor Modern Discrete

1906 1947 Transistors

Integrated Circuit
1958 Modern
CMOS

B. Murmann EE 214 Lecture 1 (HO#2) 16

 Discrete vs. Integrated Circuits

Discrete Audio Amplifier Integrated CMOS Audio Amplifier

• Minimize transistor count • "Unlimited" number of transistors

• Devices usually don't match • Devices match well
• Arbitrary resistor values • Keep resistors < 10…100k
• Capacitors 1pF…10mF • Keep capacitors < 10…50pF

B. Murmann EE 214 Lecture 1 (HO#2) 17

 Modern Integrated Circuit Technologies

Parameter CMOS Si BJT SiGe BJT

Device Speed High High High
Noise Poor Good Good
Transconductance Poor Good Good
Intrinsic gain Poor Better Best

• Why use CMOS for analog integrated circuits?

– Low cost, driven by high volume digital ICs
– Integration with high density digital circuits
• BiCMOS tends to be expensive

B. Murmann EE 214 Lecture 1 (HO#2) 18

 Basic MOS Operation (1)

0V 0V
0V

0V

• With zero voltage across all terminal pairs, device is "off"

– Back to back reverse biased pn junctions

B. Murmann EE 214 Lecture 1 (HO#2) 19

 Basic MOS Operation (2)

>0

• With a positive gate bias applied, electrons are pulled toward

the positive gate electrode
• Given a large enough bias, the electrons start to "invert" the
surface (p→n type), a conductive channel forms
– Magic "threshold voltage" Vt – more later
B. Murmann EE 214 Lecture 1 (HO#2) 20
 Basic Operation (3)

ID=?
>0

VDS>0

• If we now apply a positive drain voltage, current will flow

• How can we calculate this current as a function of VGS, VDS?

B. Murmann EE 214 Lecture 1 (HO#2) 21

 Assumptions

>0

VDS>0

1) Current is controlled by the mobile charge in the channel. This is a very

good approximation.
2) "Gradual Channel Assumption" - The vertical field sets channel charge,
so we can approximate the available mobile charge through the voltage
difference between the gate and the channel
3) The last and worst assumption (we will fix it later) is that the carrier
velocity is proportional to lateral field (ν = µE). This is equivalent to Ohm's
law: velocity (current) is proportional to E-field (voltage)

B. Murmann EE 214 Lecture 1 (HO#2) 22

 First Order IV Characteristics (1)

• What we know:

QI ( y ) = Cox [VGS − V ( y ) − Vt ]

I D = Qn ⋅ v ⋅ W

v = µ⋅E

∴ I D = Cox [VGS − V ( y ) − Vt ] ⋅ µ ⋅ E ⋅ W

B. Murmann EE 214 Lecture 1 (HO#2) 23

 First Order IV Characteristics (2)

I D = Cox [VGS − V ( y ) − Vt ] ⋅ µ ⋅ E ⋅ W
dV ( y )
E=
dy
I D dy = WµCox [VGS − V ( y ) − Vt ] ⋅ dV
L VDS
I D ∫ dy = WµCox ∫ [VGS − V ( y ) − Vt ] ⋅ dV
0 0

W ⎡ VDS ⎤
I D µCox
= ⎢(VGS − Vt ) − ⎥ ⋅ VDS
L ⎣⎢ 2 ⎥⎦

• For VDS/2 << VGS-Vt, this looks a lot like a linear resistor: I=1/R × V
• Lets plot this IV relationship...

B. Murmann EE 214 Lecture 1 (HO#2) 24

 Plot of First Order IV Curves

ID

VGS-Vt

VDS

• Something is wrong here...

– Current should never decrease with increasing VDS
• What happens when VDS>VGS-Vt?
– VGD = VGS-VDS becomes less than Vt, i.e. no more
channel or "pinch off"

B. Murmann EE 214 Lecture 1 (HO#2) 25

 Pinch-Off
– VGS +
+ VDS –

N N
Qn(y), V(y)

Voltage at the end of channel

y
Is fixed at VGS-Vt
y=0 y=L

• Effective voltage across channel is VGS - Vt

– After channel charge goes to 0, there is a high lateral field
that ‘sweeps’ the carriers to the drain, and drops the extra
voltage (this is a depletion region of the drain junction)
• To first order, current becomes independent of VDS

B. Murmann EE 214 Lecture 1 (HO#2) 26

 Modified Plot and Equations

Triode Forward
Region Active Region

ID

VGS-Vt

VDS

W ⎡ VDS ⎤
Triode Region: I D = µCox ⎢(VGS − Vt ) − ⎥ ⋅ VDS
L ⎢⎣ 2 ⎥⎦

W ⎡ (VGS − Vt ) ⎤ 1 W
Forward Active: I D = µCox (V − V ) − ⋅ (V − V ) = µC (V − V ) 2
⎣⎢ ⎥⎦
GS t GS t ox GS t
L 2 2 L

B. Murmann EE 214 Lecture 1 (HO#2) 27

 Model Accuracy

• The above equations constitute the most basic MOS IV model

– "Long channel model", "Quadratic model", "Low field model"
• Unfortunately it doesn't describe modern CMOS devices
accurately
– Pushing towards extremely small geometries has resulted in
very high electric fields
• Some of the assumptions on slide 22 become invalid
• Other second order dependencies arise
• Nevertheless, we will use this simple model in the first few
lectures to develop some basic circuit intuition
– Will fix and refine as we go…

B. Murmann EE 214 Lecture 1 (HO#2) 28