RTS Module 2 Part A Notes
RTS Module 2 Part A Notes
This chapter provides a brief overview of some of the basic ideas relating computer hardware. Such
as microprocessors, microcomputers and special purpose computers. A detailed explanation of
standard methods for data transfer including consideration for the use of interrupts is provided. The
emphasis through is on principle involved and not on the characteristics of a particular microprocessor
or microprocessor support chips.
The general purpose microprocessors include the Intel XX86 series, Motorola 680XX series, National
32XXX series and Zilog Z80 & Z8000 Series.
A characteristic of computers used in control systems is that they are modular: they provide the means
of adding extra units, in particular specialized input and output devices to a basic unit. The capabilities
of the basic unit in terms of its processing power, storage capacity, I/O bandwidth and interrupt
structure determine the overall performance of the system. A simplified block diagram of the basic
unit is shown in figure 3.1. The ALU, control, register, memory and I/O units represent a general
purpose digital computer.
Central Processing Unit:
The ALU together with control unit and general purpose registers make up the CPU. The ALU
contains the circuit necessary to carry out arithmetic and logic operations for ex- to add numbers,
subtract numbers and compare two numbers. Associated with it may be hardware units to provide
multiplication and division of fixed point numbers and, in the more powerful computers, floating point
arithmetic unit.
The general purpose registers can be used for storing data temporarily while it is being processed.
Most computers now have CPUs with several general purpose registers.
The control unit continually supervises the operations within the CPU: it fetches program instructions
from main memory, decodes the instructions and sets up the necessary data paths and timing cycles
for the executions of the instructions.
The features of CPU which determine the processing power available and hence influence the choice
of computer for process control include:
i. Word length;
ii. Instruction set;
iii. Addressing methods;
iv. Number of registers;
v. Information transfer rates; and
vi. Interrupt structure.
The basic instruction set of the CPU is also important in determining its overall performance
with desirable features:
Storage:
The storage used on computer control systems divides into two main categories:
a) Fast access storage
b) Auxiliary storage.
The fast access memory is that part of the system which contains data, programs and results which are
currently being operated on. In addition to RAM - R/W is now common to have ROM, PROM or
EPROM for storage of critical code or predefined functions.
The auxiliary storage medium is typically disc or magnetic tape. These devices provide bulk storage
for programs or data which are required infrequently at a much lower cost than fast access memory.
The penalty is a much larger access time and the need for interface boards and software to connect
them to the CPU and care has to be taken in deciding on the appropriate transfer techniques for data
between CPU, fast access memory and the backing store.
1. SISD : Single instruction stream Single data stream-single instruction operates on a single data
stream. One instruction is sent to processor and one data is transferred to memory.
2. SIMD: Single instruction stream, multiple data stream- single instruction connected to multiple processor.
Data will be shared in memory with the interconnection of networks.
3. MISD: Multiple instruction stream, Single data stream- multiple controllers with the multiple instruction but
single data will be shared within a memory unit.
4. MIMD: Multiple instruction stream, multiple data stream- most powerful class of parallel computers. In this
architecture each processor can execute different program on different data set. The most widely used MIMD
system is the INMOS transputer. Each transputer chip has a CPU, on board memory, an external memory
interface and communication links for direct point to point connection to other transputer chips. An individual
chip can be used as a stand alone computing device, the power of transputer is obtained when several transputers
are interconnected to form a parallel processing network. INMOS developed a special programming language,
occam for use with the transputer.
To read the lines connected to the digital input register the computer has to place the address of the register on the address
bus and decoding circuitry is required in the interface to select data input register. In addition to select signal an enable
signal may also be required, this could be provided by the read signal from the computer control bus. In response to both
the select and enable signals the digital input register enables its output gates and puts data onto the computer data bus.
For proper operation of the data bus the digital input register must connect its output gates to the data bus only when it is
selected and enable. If it connects at any other time it will corrupts data intended for other devices.
The timing of transfer of information is governed by the CPU timing. For this system it is assumed that transfer requires
3 cycles of system clock, labelled T1, T2 and T3. The address lines begin to change at the beginning of cycle T1 and they
are guaranteed to be valid by the start of cycle T2, also t the start of cycle T2 the READ line becomes active. For the
correct read operation DIR has to place stable data at the negative going edge of the clock during T3 cycle and data must
remain on the data lines until the negative going edge of the following clock cycle. The actual time taken to transfer the
data from data bus to the CPU may be much shorter than the time for which data is valid.
A simple digital output interface is shown in figure 3.6. Digital output is the simplest form of output, all that is
required is a register or latch which can hold the data output from the computer. To avoid the data in the register
changing when the data on the data bus changes, the output latch must respond only when it is addressed. The
enable signal is used to indicate to the device that the data is stable on the data bus and can be read. The latch
must be capable of accepting the data in a very short length of time typically less than 1 microsecond. The
output from the latch is set of logic levels typically o to +5V, if these levels are not adequate to operate the
actuators on the plant some signal conversion is necessary.
Pulse Interfaces:
In its simplest form a pulse input interface consists of a counter connected to a line from the plant. The counter
is reset under program control and after a fixed length of time the contents are read by computer. A typical
arrangement is shown in figure 3.5, which also shows a simple pulse output interface. The transfer of data from
the counter to the computer uses techniques similar to those for a digital input.
To operate the analog input interface the computer issues a start or sample signal, typically a short
pulse and in response the ADC switches the sample –hold into SAMPLE for a short period after
which the quantisation process commences. Quantisation process may take from a few
microseconds to several milliseconds. On completion of the conversion the ADC raises a ready or
complete line which is either polled by the compute or is used to generate an interrupt.
Use of separate ADC for each analog input is expensive and multiplexer is used to switch the
inputs from several input lines to a single ADC. For high level (0 to 10 V) signals the multiplexer
is usually a solid state device, for low level signals in the millivolt range mercury wetted reed-
relay switch units are used. For the low level signals a programmable gain amplifier is usually
used between the multiplexer and sample –hold unit.
DAC is simpler than ADC and as a consequence it is normal to provide one converter for each
output. Each DAC is connected to the data bus and the appropriate channel is selected by putting
channel address on the computer data bus. The DAC acts as a latch and holds the previous value
sent to it until the next value sent. The conversion time is typically from 5 to 20ms and typically
analog outputs are -5 to +5V, -10 to +10V or current output of 0 to 20mA.