DRAM Evolution

o 11 generations; 1k (1971) to 1G (2004)

o introduce 1st generation production device as
representative of each generation
o point out major developments in mainstream
DRAM
• interface, architecture
• process, circuits
o future trends
• high speed interface
• merged DRAM and logic
• multilevel DRAM
2
 Early Computer Memory

o Early computers employed;

• Cathode Ray Tubes
• Acoustic Delay Lines
• Magnetic Drums
o Core memory was developed in the early 50's
• Torroidal ferrite material, 1.25mm O.D.
• Non-volatile storage
• 3D, 2D, 2 1/2D
o In the 60's
• Transistor, then monolithic peripheral circuits
• Plated wire - new magnetic memory technology
3
 Semiconductor Memory

o In the mid-60's, 64bit bipolar memory chips

became available
• costly, high-performance applications
• IBM Cache memory, 60ns, 112kB+
o By the late 60's 256bit static MOS memory
became available
• more cost-effective, 3-5¢/bit
• replacing small core arrays, e.g .. printer buffer
• simple packaging, boards needed connection on
one side only

4
 1k DRAM

o Intel 1103 - introduced late 1971

o cost effective w.r.t. core, <1 ¢/bit
o PMOS, silicon gate, 1M1 P
o Vss=16v, Vbb=20v, (Vdd=Ov)
o 300ns access, 580ns cycle
A3 RNJ
A2 Vss
AO CE
A1 A4
PRC Dout•
A9 AB
A6 Din
AS Vdd
A7 Vbb

5
 1k DRAM (Intel 11 03)
( 32 rows (RIW sel.) )

Die Size : 10.4mm2 Refresh: 32

Cell Size : 3750J.tm 2(37o/o) Interface : x1 CE, PRC
·6 Process : 12J.tm PMOS 1P1 M Supply: 16v, 20v (Vbb)
 3T Cell

o Gain element in cell, inverting

o Several variations
• shared R/W enable
• shared R/W data bus
o Intel 1103 shown, 2ms retention

Write Enable

Write Data Read Data

7
 4k DRAM

o Texas Instruments TMS4030 introduced 1973

o NMOS, 1M1 P, TTL 1/0
o 1T Cell, Open Bit Line, Differential Sense Amp
o Vdd=12v, Vcc=5v, Vbb=-3/-5v (Vss=Ov)
o many package variants; 22, 18, 16 pin DIP
Vbb Vss
A9 AB
A10 A7 Vbb Vss
A11 A6 110 A11 Vbb Vss
cs· Vdd AO A10 Din CAS*
Din CE A1 A9 WE* Dout
Dout* NC A2 AB RAS* cs·
AO A5 RIW A7 AO A3
A1 A4 CE A6 A2 A4
A2. A3 A3 A5 A1 AS
Vee WE* A4 Vdd Vdd Vee

Tl, Intel Tl Mostek (EDOI)

8
 MOSAID 4k DRAM

-
...1

-
~
en
3=
...0
~

Die Size : 9.6mm2 Refresh: 64

Cell Size : 850J..tm 2 (36%) Interface: x1 CE
9 Process : 8J..tm NMOS 2P1 M Supply: 12v, 5v, -5v
 1T Cell and Sense Amp

o Open bit line, Vss precharge level

o Dummy cell required to set reference level
o Consumes static power in active cycle

Xo

I I
Precharge Gen.

10
 16k DRAM

o Mostek MK4116, introduced 1977

o Address multiplex, Page mode
o NMOS, 2P1M
o Vdd=12v, Vcc=5v, Vbb=-5v (Vss=Ov)
o Vdd-Vt precharge, dynamic sensing, no restore
Vbb Vss
Din CAS*
WE* Dout
RAS* AS
AO A3
A2. A4
A1 AS
Vdd Vee

11
 MOSAID 16k DRAM
~-----128 columns (8/L)

Die Size : 16.6mm2 Refresh : 128

Cell Size: 4751J.m 2 (47%) Interface : x1 RAS/CAS
12
Process : 51J.m NMOS 2P1 M Supply : 12v, 5v, -5v
 Double Poly Cell

• Bitlines - active
• Wordlines - metal
Bitline

l Wordline (metal)

Wordline (metal)

Wordline (metal)

Active

Poly 1

Poly2

13
 64k DRAM

o Many changes at once - no dominant design

o Attempts to standardize 7-9v Vdd failed
o 5v only 16k and 64k were introduced 1980
o Internal Vbb generator
o Boosted Wordline and Active Restore
• eliminate Vt loss for '1'
o x4 pinout Vss
OE* 1
1/01
Din CAS* 1/02 CAS*
WE* Oout 1/03
RAS* AS AO
AO A3 A1
A2 A4 A2
A1 7 A3
Vee A7

64k X 1 16k X 4

14
 MOSAID 64k DRAM
~------ 256 columns (512 B/L) -------~

Die Size : 32mm2 Refresh : 256

Cell Size: 234flm2 (48°/o) Options : x1, x4
15
Process : 3flm NMOS 2P1 M Supply: 5v
 Boosted WL Driver
Vdd Vdd Vdd Vdd
X-decoder

s~ s~ xo=Q--1
Xn
W/L driver

Cb
sxy SXO W/L

other
W/L boost W/L
generator ) drivers

R
XO:Xn
=-::;::=======================Vdd; Vss
_ _ _ _ _ _ _ _ _ Vss; Vdd
(Ct = Cb + Csxo + Cwl)

A - - cJ- -- -- -- -- -- - - - Vss; Vdd-Vtn; 2Vdd-Vtn; Vdd(2+Cb/Ct)-Vtn

SXG I _________ Vss;Vdd

B
SXE -
- - r:J-
--
=1

= = = = = =
·EJ- - - - - - - -
Vss; Vdd-Vtn; 2Vdd-Vtn; Vdd(2+Cb/Ct)-Vtn
Vss; Vdd+Vtn; Vss

SXO ----.L.- ___________ Vss; Vdd; Vdd(1+Cb/Ct)

- - - - --r-----------
SXB =-==-==-:=r=:..:===-==-==-====-=~
Vss; Vdd
W/L ----~-- _ _ _ _ _ _ _ _ Vss; Vdd; Vdd(1+Cb/Ct)

16
 256k DRAM

o Folded bitline architecture

• Common mode noise to coupling to 8/Ls
• Easy Y-access
o NMOS 2P1M
• poly 1 plate
• poly 2 (polycide) -gate, W/L
• metal- 8/L
AS
oe·
1/01
D redundancy Din
we· Dout
1/02
we· 1/03
RAS* A6 RAS• AO

A1
A4 A3
Vee Vee A7

256k X 1 64kx4

17
 MOSAID 256k DRAM
512 columns (8/L) -------~

-
...I

-~

Die Size : 33mm2 Refresh : 256

Cell Size : 73J.!m 2(58°/o) Options : x1 , x4
Process : 2J..tm NMOS 2P1 M Supply: 5v
18
 Folded Bitline Architecture

o Active restore sense amp

o Vdd precharge (not shown)
DB DB* Xo X1 X254 Xm Xo Xo*

Y;
T T

Precharge Gen.
T T T

19
 1M DRAM

o CMOS, N-well, Vbb substrate, 3P1 M

o Boosted circuits used extensively
o N-channel output devices
o Vdd/2 bitline reference, Vdd/2 cell plate
• eliminate reference cell and bump sensitivity
o DIP, SOJ packages
Vss 1/01

AO OE*
A1 A7
A6
A3 A5 A2
Vee A4 A3
Vee
1M X 1
256k X 4

20
 MOSAID 1M DRAM
~----1024 columns (2048 B/L) ----~

(I)

..
3:
0

Die Size : 44mm 2 Refresh : 512

Cell Size: 22.4J.Lm 2 (53°/o) Options: x1, x4
Process : 1.2J..Lm CMOS n-well 3P1 M Supply : 5v
21
 Triple Poly Planar Cell

• poly1 - plate
• poly2 - gate, W/L
• poly3 (polycide) - B/L
• metal - W/L strap
Wll Wit W/L W/L W/l

Bitline (polycide)

Bitline (polycide)
D
Active

Poly 1

22
 4M DRAM

3D stacked or trench cell

0
0 CMOS 4P1M
0 x16 introduced
0 Self Refresh Vee Vss
1/01 1/016
1102 1/015
0 350mil SOJ, ZIP packages 1/03 1/014
1/04 1/013
Vee Vss
1/05 1/012
1/06 1/011
400mil
1/07 1/010
50 mil
Din Vss 1/01 Vss 1/0B 1/09
pitch
WE* Dout 1/02 1/04 NC NC
RAS* CAS* WE* 1/03 NC CASL*
NC NC RAS* CAS* WE* CASH*
A10 350mil A9 A9 5 350mil OE* RAS* OE*
50mil 50mil NC AB
pitch pitch
AO AB AO AB AO A7
A1 A7 A1 A7 A1 A6
A2 A6 A2 A6 A2 AS
A3 AS A3 AS A3 A4
Vee A4 Vee A4 Vee Vss
23 4M X 1 1M x4 256k X 16
 MOSAID 4M DRAM
2048 columns (4096 8/L) - - - - - - - - - - ?

Die Size : 77mm2 Refresh: 2k

Cell Size : 9.2Jlm2 (50°/o) Interface : x8 PSRAM
Process : 0.7f..lm CMOS n-well 3P2M Supply: 5v
24
 3D Cell Structures

o Build cell in vertical dimension - shrink area

while maintaining 30fF cell capacitance
o Early trench cells stored charge on outside
o Bitline contact a challenge in early stacked cells
Trench Cell Stacked Cell

p-

25
 16M DRAM

0 EDO - Extended Data Out

0 5v external, internal Vdd regulation 3-4v
0 CMOS n-well 4P2M Vee Vss
1/01 I/01S
0 Double metal 1/02 1/015
1/03 1/014

• Multiplexed S/A 1/04

Vee
1/05 3S
1/013
Vss
1/012

• Shared Y-Decoder Vee

1/01
1/02
Vss
1/04
1/03
1/0S
1/07
1/08
9
400mil

p1tch
35
34
10 5?mil 33
1/011
11010
1/09
0 Vpp supply WE*
RAS* 5 400mil 22
CAS*
OE*
NC
NC
11 NC
CASL*
NC S 50mil 21 A9 WE* CASH*
0 SOJ and TSOP A10
pitch
AB
RAS*
NC
OE*
A9
AO A7 NC AB
0 LOC leadframe A1
A2
AS
AS
AO
A1
A7
AS
A3 A4 A2 AS
Vee Vss A3 A4
Vee Vss
4Mx4
1M X 1S
26
 MOSAID 16M DRAM

4096 columns (8192 B/L) ------~

Die Size : 137mm2 Refresh : 2k/4k

Cell Size: 4.5J.Lm 2 {55%) Options: x1, x4, x8
Process : 0.5J.Lm CMOS n-well 4P2M Supply : 5v {with reg), 3.3v
27
 Vpp Supply/Wordline Driver

o Vpp regulated to Vdd + Vtn (cell transistor)

o Eliminate double bootstrapped voltages
o Also used for
• Isolation devices
• N-channel output driver
Vpp Vpp Vpp
Vdd
Level
-+ Shifter
cfl2 W/L

EN XO
pump
Xn
Decoder

28
 64M DRAM

0 Vdd = 3.3v, separate Vddq/Vssq Vdd

000

0 SDRAM interface Vddq

001
52
51
Vssq
0014
002 5 0013

• pipelined, burst 1/0 Vssq

003
004
6 Vddq
0012
0011

• multi-bank, event driven Vddo

005

•
006
clocked inputs, terminated 1/F Vssq 43 Vddq
007 13 42 008
Vdd 14 400mll 41 Vss
0 CMOS 4P2M triple well, Vss sub. OOML
O.Bmm
15 pitch 40 NC,VREF
WE* 16 OOMU
CAS* CK
0 COB - Cell Over Bitline RAS* CKE
cs· NC
BAO A11
0 Staggered sense amplifier BA1/A12 A9
A10/AP AS
AO 32 A7
0 512 cells/column A1 A6
A2 AS
A3 A4
0 54pin TSOP for x4/8/16 Vdd Vss

4Mx 16
29'
 MOSAID 64M SDRAM
~-------- 16384 rows---------~

l
Die Size: 193mm2 Features: 4 bank, DLL
Cell Size : 1.2~-tm 2 (42%) Options : x4, x8, x16
Process : 0.32Jlm CMOS 3-well 4P2M Supply : 3.3v (internal 2.5v reg)

30
 SDRAM Operation

o 1OOMHz, BL=2, CL=3, WL=O shown

o Sustained Read or Write bursts (BL=4)
o 2N rule, Gap for Read-Write transition
Act. Act. Read Read Wrile Read Read
BankO
. Bank1. col.a
. col.x ~
col.. b Write
col..y coLe
. col.z.
CLK
CE*
RAS*
LllJ1J1fW1JL! .----
..-
..
.
~--:--
-
. ..
1 -::------~~---:------+-----
~
:<trr:d : ~ •

CAS*
~:r~: l~--~
~ ~ y y :
·:J:.

Addr. ITI rr;1l cf3 lcrxl let~ lc~1vl lcq~ lcjzl

WE* ~ 1 1( faa ~ ): w-----ill:--:-
:- -+--:- - -
; : : : Rear data : i"'e daia In : :
DO . : ' : \ a la+1 lx•1H b b+11vl v+1 r-~
X

31
 256M DRAM
Vdd 1

0 CMOS 4P3M triple well, Vss sub. 000

Vddq Vssq
001 0014

0 Hierarchical W/L
62 0013
Vssq 6 Vddq
003 0012

0 DDR- Double Data Rate SDRAM 004

VddQ
0011
Vsso
oos 0010

• Differential clock inputs DQ6

Vssq
007 13 54
009
Vddq
OOB

• Din sampled on both clock edges NC

Vddq
14
400mil
0.65mm
15 pitch 52
53 NC
Vssq
uoos
•
LOOS 16 51
Dout produced on both edges NC 17 50 NC
Vdd 18 49 Vref

• Data strobe input/output NC

LDM*
WE*
19 48 Vss
UDM*
CK*

• terminated 1/0 - SSTL CAS*

RAS*
cs·
CK
CKE
NC

0 DLL - Delay Locked Loop NC

BAO
NC,A12
A11

aligns output data edges with clock Al:~

A9

• input, removes PVT sensitivity A1 AS

A2 AS
A3 A4
Vdd Vss
32
16M X 16
 IBM/Toshiba/lnfineon 256M SDRAM
16384 columns (32768 B/L)

Row decoder

512r x 2048c

Column decoder

Die Size : 220mm2 Features: 4 bank/8 bank

Cell Size: 0.47f..lm2(57%) Options : x4, x8, x16, x32
Process : 0.22f..lm CMOS trench Supply: 3.3v (internal 2.5v and
cell, 3M 1.8v reg), later 2.5v
33
DDR Operation

o 1OOMHz clock, 200Mb/s/p data rate

o BL=2, CL=2, WL=1 shown
o Commands on CLK rising edge only - 2N part
Act. Act. Read Read Write Write Read Read
BankO Bank1
.. . col.a col.x col.b
.. col.y
.. cote col.z

CLK L!L:
.. .·.-------.
.:
CE*
.. ..
RAS* --u-wr---~:---:----+--~-_,_--....,._~---

:<
.: tmd ):
.----, .----~-~

CAS* i
: ol : ~

I r~ I ic?3 lc ~xl 1$ lc~vl lc~ ~izl

--~~~~~.~
- --~
~ ----~~ .
~ Read data : ; Write data Jn :
--------;---~
;
~
--tJ
+
a la+1 1 x lx+1 H
•
b lb+1 1 v
~

~
l v+ct+
ll ~
~
~ - - - - - 11 c lc+1 1
t
.:
• •
.:
i--' -4
 1G DRAM

o CMOS 4P4M process

o High-K dielectric (Ta20 5 } stacked cell, vertical
access transistor trench cell
o Hierarchical B/L
o DDR2 SDRAM
• Differential data strobe
• 4N prefetch
• Posted CAS latency
• On die termination (ODT) and Off Chip Driver
impedance adjustment (ODT)
o BGA package
35
 IBM/Infineon 1G DDR SDRAM
~--------- 65536 rows --------~

r
Row decoder

2048r x 4096c

l
Die Size: 390mm2 Features : 8 bank/16 bank
Cell Size: 0.25J..Lm 2{68%) Options : x16, x32
Process : 0.18J..Lm CMOS trench Supply : 2.5v {internal 2.1 v and
cell, 3M 1.5v reg), later 1.8v
36
 Embedded DRAM
o Motivation
• Form Factor - achieve higher level of integration
• Density - 5-1 Ox embedded SRAM
• Active Power - eliminate chip to chip bus - CV2f,
termination, DLL power
• Standby Power - self refresh current consumption
less than 130nm 6T SRAM leakage
• Bandwidth - super wide on chip busses, sub 5ns
random access achievable
• Granularity - optimize memory size, configuration
• SEA superior to 130nm SRAM and below due to
high node capacitance
37
Embedded DRAM (continued)

o Process Variants
• Trench (IBM, Toshiba, Sony)
);> cell created before logic devices, high cell RC
• Stacked (Renesas, others)
);> deep contact, planarization
• MiM (NEG, STMicro, TSMC)
);> logic compatable, low cell RC
o Embedded DRAM Drawbacks
• Cost Adder - 4 to 5 additional mask steps
• Portability - non-standard processes
• Highly specialized design, test, product eng.
Example: 90nm High Speed eDRAM
Macrocell
440Jm 50 urn
....__
......
o 2Mbit 00nk7 00nk15

o 16 bank OOnk6 00nk14

0 128 bit 1/0 OOnk5 00nk13

o 1GHz clock 00nk4 00nk12

balk:_io OOnk_io
o 3-1-1-1 access
bmk_io
.
aamous mux +ClOCK trunK
OOnk_io

o 4ns tRC OOnkO

-=::::..=== -·
OOnk8 redwulancy fuses
. ---
.-
o full BIST OOnkl OOnk9

o 1.2v, 1OOmA (R) OOnk2 OOnkiO

hmk3 OOnkll
o 25°/o cell

~1
efficiency rrn:ro_end

' Area= 930um x 1632wn = 1.52nun2

 Example: 90nm High Speed eDRAM
Macrocell (continued}
1G I I -r--
t ~ ~ I

1.cl ---~-~---------------~--------------~--
o Hspice -·2
1
I
~------~---------------~------------
: wl
1
I
I
-~--
I
I

-- ~~b
~~~
~~~b~
~~~------ _L __
:

______ j _____
simulation "C"
c
IJ uoom
1
. ..~~··---["fr·l···-~-- ,.- -;
( - - - - - -,··--· - - - - - - - r-.
...:..::-··--~-·---~
:
- 't-- 1- - - - - -1- r --
I -_ ' - .

j' - ' •\ . -l -
1, _---- _J1)t:~ --- ____ ~~ f- - ~-\ ~c~l!_n~-- _Ji~\1
o 0.9v ~ GOOm
:I
r•
1
·-----~-< - J- - )- --4------ l
n ·

--~ll I ~- J-I --~-

- -

- .... I
i ,, :
I ______ - ~ -f-
.,_ -
t ~ :r~
400111 ~ I 1
1 1 I I ' '

o slow models 200m ------- ·E1r·-- l ------ I ..' '"~~'"'t" •

II• I
~-
!.Q- t
•
J.J"lf
ll~ I IJ
L - --~-•
I
I l
I
_l_ - - - - - - .J
'
-I~--
___....
I
~ . '~
() ..... ~-
~
~~~·
•
1)1 1 1
... . ~
I
1. •
·~~~ ~
I
-·--..-.,., ..
o BL precharge
I I I

an 10n
Time (1111) (TIM !:)

at start of cycle "'bankx4 model slm

I.G -------r--------------T--------------~--
05102/20

__ = =1l __;_ ______ c _-:__-l ======~,- -!- _

1 ,......... I

o 75-80°/o cell 1 .4

1 .2
____ -L-L _____, ________ l ____________ -'t- _! __
I , --· I I

I I
I
I
I •
I
I '

restore "C"
:.=.
1
I
------ -:----- _,_-------- +------------- ... -:--
- ·- -!-, - r--1, ,--, l . - - -.-··- ··· --1-
I • I

II tlOOill _ lkc -- -:-t- -•·- -lr -- --r- - -r ~ r-- .L ~-:- • -- -:~-

j'
~ GOOn I -Ll--- -i-~-1--
1• ~
1,'----1---r~~-~~---L . t_l___ _f_L
' •: ' 1I :~
•IOOill
I

1 r-t--- !-rt--t- -----J---·n--r---r ; -~---- -~-r

•, J ctk :1 1 , 1
1 r 1
1

200111
~ ~ -~---- :· ·1 1--t--t --1·----u--1--- , r--,---- -:-1
0 ~"'-l ---- ...
~~
.,_J __L,_ '-----1!. . ....__,__,_ ---- .:
I

: !

40 en an 1011
·11rn~ (lin) (TIMI")
 Example: 90nm Low Power eDRAM
Macrocell
E
c5
..r 300um 1400um
~~~~~~~~~~~ ~ ~~~~~~~~~~~ ~
u ~~
.....
.... .....
c~
~ ~ ~ ~
-
~
a.256WL
r + 4Red
:9
~
512+8Red
.
RI nnir"
~

~
~

~
['
... ....
2M Subblock

c:; ... 256WL c:;

E
~
c -
~

r +4Red
~
-
~
~
-
~
-
~
~ ~ ~ ~
2M Subblock
~
Vl
d)
v.l

c:; c:; c:; c:; &:

c~ - - - -
d)
~ a. 256WL ~ ~ ~
,~
~ +4Red ~ ~ ~
·-~
tl)
:::3 2M Subblock
c:; ... 256WL c:; c:;
c~
~

,
-
~
~ +4Red
~
~
~
~
~
~

E
.... ... 2M Subblock
1400um ~
• 8Mb, 6ns access and cycle time CoreiO,Col Red I OOum
• 64bit asynchronous interface Control, BIST, Macro 10 250um
• 3.27mm2, 47% cell efficiency ,
• 25mA active current
•100uA self refresh, 50uA sleep mode current @ 55°C
41
 Example: 90nm High Bandwidth
eDRAM Macrocell
o 32Mbit, 4096 bit 1/0
o 500MHz Synchronous interface
o 4 word bank interleaved burst- 256GByte/s
o 11.9mm2 (52°/o cell efficiency)
5247um

BmkO

2 cdive
wadlnes / Bmkl
-

~ Bmkl
2272um

BmkO
Cmtrd + 1,0 + BIST

42
 Example: 90nm High Bandwidth
eDRAM Macrocell (continued}
Reads from single bank TRC ::: 16ns

512MHzCLK

READ jBa;;kOJL__ _ _ _ _ _ _ _ _ _ ____.lsankO I

Address XAddrA X X AddrB X

Q<4095:0>
------------~--~~--~----------------~--
XAo XAt XA2 XA3 Xao

Interleaved bank reads TRC = 16ns

512MHzCLK

READ j sankO l...________--.~1 Bankt l_ _ _ _____,I BankO ~---~----

Address XAddrA X XAddrB X XAddrC X

Q<4095:0> ----------.. IX.J. _

Ao-.~.X.l-A_
t --LJ..X_
A2_..u..XA_3__,_X~...-s_
o --L.l. Xo_t__,_X~...-B_
2 ----LJX._
B3-.~.X.i__§
_

43
 Example: 90nm Low Power Custom
DRAM
o For low power high bandwidth MCM application
o 1 .Ov unterminated 128 bit interface, 500Mbit/s/pin
o 1.0v core supply, 200mW active power
o 43.4mm 2 (53°/o cell efficiency)
o bonding pads on one side of chip
10.6 rrrn

-~ t- ~-~ -
~ ~ ~ ~ ~ ~

co
6 ~.~~ £~ £~
6 ~t-p- CO«; 6c:
co cp
6~
CO«; ~ £~ £~
4.4 rrrn

~ ~ ~ ~ ~ ~ ~ ~

cocc~
6 6t £~ £~
CO•O
6~
COC'
6t £~ £~
co~~

,...., I Y"\
44 .....
""""'''' ',.....,
+JXrl
 Example: 90nm Low Power Custom
DRAM (continued)
o Shared 128 bit bidirectional DQ bus
o Unidirectional differential source synchronous
DDR clocks
• lntermittant clocks with preamble to save power
• CCLK - Command, DCLK - Write Data, QCLK -
Read Data
o One pair of DCLK and one pair of QCLK for
every 32 bits of data
o Master DLL uses CCLK for reference
o Write latency = Read latency for minimum gap
between read and write
o Controller drives DQ except during Read
45
 Example: 90nm Low Power Custom
DRAM (continued)
Continuous 8-Word Read Bursts TRC = 20ns

CCLK

RD

ADDR<I6:0_>_

QCLK<3:0>
_ X_..._X-------'!'-;__.X
...... .._______ ,!--------
ILlLSl__
o~tn~ ~~~~~~~~~ X X X X X X
---------------~~~~~~~~~~ 4-~-4~~4-~

ADDR<I6:0>
---~~----------~~~-----------+

QCLK<3:0> - -+-----------'

46
 References and Acknowledgments
W.M. Regitz, J.Karp, "A Three-Transistor Cell, 1024-Bit, 500ns MOS RAM", ISSCC, Feb. 1970, p. 42-43.
W.F. Jordan, "Main Memory, Past, Present, and Future", Honeywell Computer Journal, p. 52-57
L.L Vadasz, H.T. Chua, A.S. Grove, "Semiconductor Random Access Memories", IEEE Spectrum, May 1971, p. 40-48.
L. Altman, "Special Report: Semiconductor RAMs Land Computer Mainframe Jobs", Electronics, Aug. 28, 1972, p. 63-77.
C. Kuo, N. Kitagawa, E. Ward, P. Drayer, "Sense Amplifier Design is Key to 1-Transistor Cell in 4096 bit RAM",
Electronics, Sept. 13, 1973, p.116-121.
D. House, 'Which Way for 4k ... 16, 18, or 22 Pin?", Intel Application Brief AP-11, 1975.
D. Coker, "16k RAM Eases Memory Design for Mainframes and Minicomputers", Electronics, April28, 1977, p.115-119.
The Semiconductor Memory Book, Intel Marketing Communications, Wiley, 1978
G.R.M. Rao, J. Hewkin, "64k Dynamic RAM Needs Only One Sv Supply to Outstrip 16k Parts", Electronics, Sept. 28,
1978, p.109-116.
J. Posa, "Dynamic RAMs- What to Expect Next: A Special Report", Electronics, May 22, 1980, p.119-129.
R. Bernhard, ''The 64kbRAM Teaches a VLSI Lesson", IEEE Spectrum, June 1981, p.38-42.
R.C. Foss, ''The Evolution of Dynamic RAM", International Symposium on VLSI, Taiwan, Feb.1985. p. 9-13.
R.C. Foss, ,.Mega RAMs". European Solid State Circuits Conference, Sept. 1986, p.1-3.
"MOS DRAM Industry Survey, 1976-1980", Vol. 1-10, Chipworks, 1993.
G. Allan, ..MOSAID DRAM Design Course Notes", June 1996.
T. Kirihata et.al. "A 220mm2 4 and 8 Bank 256Mb SDRAM with Single Sided Stitched WL Architecture", ISSCC, Feb 1998
T. Kirihata et.al. "A 390mm2 16 Bank 1Gb DDR SDRAM with Hybrid Bitline Architecture", ISSCC, Feb 1999

Many thanks to Dick Foss and Graham Allan of MOSAID for their advice and encouragement, and to Terry Ludlow of
Chipworks for providing the report "MOS DRAM Industry Survey, 1976-1980'' which contained many of the references.

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