NAME: MOMINA AMIN

ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

BAHRIA UNIVERSITY KARACHI CAMPUS

DIGITAL LOGIC DESIGN

LAB EXPERIMENT # 6

XOR gate as magnitude comparator & parity

EQUIPMENT:-

1. IC: 7408 LS, 7432 LS, 7404 LS, and 7486 LS.
2. Bread board.
3. Digital Logic Probe.
4. DC supply (0 and +5V).

THEORY:-
The XOR gate (sometimes EOR gate or EXOR gate) is a digital logic gate that
implements an exclusive disjunction; that is, it behaves according to the truth table shown
below. A true output (1) results if one, and only one, of the inputs to the gate is true (1). If
either inputs are false (0) or both are true (1), a false output (0) results. A way to
remember XOR is "one or the other but not both". It represents the inequality function,
i.e., the output is HIGH (1) if the inputs are not alike otherwise the output is LOW (0).

Input A Input B Output Y= A⊕B

0 0 0

0 1 1

1 0 1

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

1 1 0

This function is addition modulo 2. As a result, XOR gates are used to implement binary
addition in computers. A half adder consists of an XOR gate and an AND gate.

EXCLUSIVE-OR FUNCTION:-
The exclusive-OR (XOR), denoted by the symbol ⊕, is a logical operation that performs
the following Boolean operation:

The exclusive-NOR, also known as equivalence function performs the following Boolean
operation:

APPLICATION OF XOR GATE

MAGNITUDE COMAPARATOR:-

A digital comparator or magnitude comparator is a hardware electronic device that

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)
than, less than or equal to the other number. Comparators are used in a central processing
units (CPU) and microcontrollers.

Consider two 2-bit binary numbers A and B such that

A = A1A0

B = B1B0

Here each subscript represents one of the digits in the numbers.

EQUALITY:-

The binary numbers A and B will be equal if all the pairs of significant digits of both
numbers are equal, i.e.,

A1 = B1 and A0 = B0

Since the numbers are binary, the digits are either 0 or 1 and the Boolean function for
equality of any two digits Ai and Bi can be expressed as;

xi = Ai Bi + Ai’ Bi’

xi is 1 only if Ai and Bi are equal.

For the equality of A and B, all xi variables (for i = 0, 1) must be 1.

So the quality condition of A and B can be implemented using the AND operation as

(A = B) = x1x0

The binary variable (A=B) is 1 only if all pairs of digits of the two numbers are equal.

INEQUALITY:-

In order to manually determine the greater of two binary numbers, we inspect the relative
magnitudes of pairs of significant digits, starting from the most significant bit, gradually
proceeding towards lower significant bits until an inequality is found. When an inequality
is found, if the corresponding bit of A is 1 and that of B is 0 then we conclude that A>B.

This sequential comparison can be expressed logically as:

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)
(A > B) = A1 B1’ + x1A0 B0’

(A < B) = A1’ B1 + x1A0’ B0

(A>B) and (A < B) are output binary variables, which are equal to 1 when A>B or A<B
respectively.

The operation of a single bit digital comparator can be expressed as a truth table:

INPUT OUTPUTS
A1 A0 B1 B0 A<B A=B A>B
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0
0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 0 0 1
1 1 1 1 0 1 0

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)
PARITY GENERATION AND CHECKING:-

Exclusive-OR gates are useful for generating and checking a parity bit that is used for
detecting/correcting errors during transmission of binary data over communication
channels. Transmitting a 3-bit message with even parity bit. The three bits x, y, and z
constitute the message and are the inputs to the circuit. The parity bit P is the output,
which is an odd function and can be expressed as:

P=z⊕y⊕x

The truth table and the logic diagram for the parity generator are shown below.

The three bits in the message together with the even parity pit P are transmitted. The
receiver at the destination checks for even number of 1’s in the 4-bit message and
generates an error C equal to 1 if the number of 1’s in the message is odd. Here, again, we
can use the odd function property of the XOR gate that produces an output of 1 if odd
number of inputs is equal to 1. The truth table and the logic diagram for the parity
checker are shown below.

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

PROCEDURE:-

 At first make the circuit for 2-bit magnitude comparator and check the equality and
inequality as shown in truth table.
 Now make the circuit for 3-bit even parity checker and verify the truth table.
 Make the Multisim simulation for magnitude comparator and parity checker.

OBSERVATION/RESULTS and DISCUSSION:-

Make the circuit diagram for 2-bit magnitude comparator and fill the truth table.

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

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NAME: MOMINA AMIN
ENROLLNMENT : 02-134231-034
PROGRAM : BS(CS) -2(A)

Teacher Signature: ________________________

Student Registration No.: ___02-134231-034_____________________

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