Basics of the MOSFET

MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

Introduction- the MOSFET

Metal Oxide Semiconductor Field Effect Transistor

The name describes nearly everything about the device itself.

The first three words Metal Oxide Semiconductor describes the layer-wise
structure of the device.

The last three words Field Effect Transistor describes the principle of
operation.

Metal
Oxide
Semiconductor

Debapratim Ghosh Dept. of EE, IIT Bombay 2/20

 Basics of the MOSFET
MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

MOS Structure Physics

MOS transistors can be of two types- NMOS and PMOS.
An NMOS has a lightly doped p-substrate (where there is scarcity of
electrons).
The metal terminal is called the Gate.
The oxide layer (usually SiO2 ) is an insulator.
The p-type substrate is grounded while the gate voltage VG is varied.
We will see how the MOS structure behaves as VG is varied.
VG

p-sub

Debapratim Ghosh Dept. of EE, IIT Bombay 3/20

 Basics of the MOSFET
MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

MOS Structure Physics- Accumulation

Let us apply a negative gate voltage i.e. VG < 0.
This negative VG sets up an electric field through the oxide.
The electrons (minority carriers) are pushed away towards ground, and the
holes (majority carriers) are pushed towards the oxide.
The region below the oxide is now devoid of n-type charge carriers.
This region of operation is called accumulation region.

VG < 0

+++++++++++++++ E-field
--------

Debapratim Ghosh Dept. of EE, IIT Bombay 4/20

 Basics of the MOSFET
MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

MOS Structure Physics- Depletion

Let us apply a small positive gate voltage.
This small VG sets up a weak electric field though the oxide.
The holes are now pushed away from the oxide, deep into the substrate.
However, the electric field is too weak to pull all the minority electrons
towards the oxide.
At this time, the immediate region below the oxide is devoid of any mobile
charges (electrons or holes).
This region of operation is called depletion region.
VG = 0+

Weak E-field

Region devoid of carriers

Accumulated carriers

Debapratim Ghosh Dept. of EE, IIT Bombay 5/20

 Basics of the MOSFET
MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

MOS Structure Physics- Inversion

Let us now increase the gate voltage VG .
As VG increases, the electric field becomes stronger, and the minority
electrons accumulate below the oxide.
At a certain value of VG , the concentration of moblie electrons becomes so
high that the region just below the oxide becomes as n-type as the rest of the
substrate is p-type.
This region of operation is called inversion region.
These accumulated electrons can now be used to generate a current.
VG ≫ 0

E-field
----------------

Debapratim Ghosh Dept. of EE, IIT Bombay 6/20

 Basics of the MOSFET
MOS Structure
The MOSFET Operation
MOS Structure Operation
The Experiment

MOS Threshold Voltage

To accumulate mobile electrons below the oxide, the gate voltage VG has to be
sufficiently high to cross the “threshold”. This is governed by a number of factors.

The work-function difference between the gate and the silicon substrate (this
leads to the “flatband” voltage).
The gate voltage component required to bring about surface inversion
(surface just below the oxide).
The concentration of acceptor ions in the substrate.
The concentration of trapped charges inside the oxide.
The substrate voltage (so far weve assumed it to be ground).

Note:
The threshold voltage VTN for NMOS is positive.
The threshold voltage VTP for PMOS is negative.
Debapratim Ghosh Dept. of EE, IIT Bombay 7/20
 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

The MOS Transistor

Once the threshold has been crossed, we need to make the electrons move,
i.e. set up a current.
For this, we need two more terminals- Source (S) and Drain (D), and a
potential across them to control the flow of electrons.
The drain and source are heavily-doped n-type regions.
We now have a 4-terminal device- drain, source, gate and body.
The drain and source can be interchanged!
Gate (G)
Source (S) Drain (D)

n+ n+
p-substrate

Body (B)

Debapratim Ghosh Dept. of EE, IIT Bombay 8/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

MOS Transistor Characteristics- Linear Region

Assume that VG > VTN and VGS − VTN > VDS .
The device is on as the threshold has been crossed. The inversion layer (full
of electrons) is now a connecting path between the two n+ -type source and
drain regions.
Due to a nonzero VDS , electrons flow from the drain to the source via the
inversion layer. The inversion layer is now called a channel.
The current flowing in the channel is called the drain current (ID ). For this
bias condition, ID is given by
kn 2
ID = (2(VGS − VTN )VDS − VDS ) (1)
2
VG
VS = 0 VD

n+ n+
+
n channel

Debapratim Ghosh Dept. of EE, IIT Bombay 9/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

MOS Transistor Characteristics- Linear Region (cont’d...)

Based on our discussion so far, try to do the following exercises.

For the above biasing, plot a graph of ID v/s VGS as you increase VGS ,
starting from 0V. You may assume that VDS is small (though not necessary).
Now you know why this is called the linear region!

Now for a given VGS , plot a graph of ID v/s VDS as you increase VDS ,
starting from 0V. At what value of VDS is the ID maximum?

Debapratim Ghosh Dept. of EE, IIT Bombay 10/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

MOS Transistor Characteristics- Saturation Region

We have seen that the ID reaches a maxima when VDS = VGS − VTN .
At this time, we see that the VGD = VTN . At this time, the channel depth at the
drain-substrate interface is zero. This is called pinch-off.
When VDS is increased further, VGD < VTN and the pinchoff point shifts towards
the source.
The ID is now very weakly dependent on VDS . The channel voltage is equal to
VDS,sat = VGS − VTN . The rest of the drain bias voltage is across the pinched-off
region.
Substituting VDS = VGS − VTN in equation (1), we get
kn
ID = (VGS − VTN )2 (2)
2
VG
VS = 0 VD

n+ n+

Debapratim Ghosh Dept. of EE, IIT Bombay 11/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

The Saturation Region (cont’d...)

From equation (2) we see that ID is now independent of VDS .
The plot of ID v/s VDS in the saturation region is a straight line parallel to
the VDS axis.
That does not happen practically. If the effective length after pinch-off, i.e.
L′ , is significantly less, ID does change with VDS !
We know that, kn = µn Cox ( WL ). After pinch-off, we have kn = µn Cox ( W
L′ ).
′
Assume L = L − ∆L. Substitute this in (2).
VG
VS = 0 VD

n+ L′ n+
L

Debapratim Ghosh Dept. of EE, IIT Bombay 12/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

The Saturation Region (cont’d...)

We now have ! !
1 µn Cox W
ID = (VGS − VTN )2 (3)
1 − ∆L
L
2 L
p
It can also be shown that, ∆L ∝ VDS − VDS,sat . Using power series, we get

∆L
1− = 1 − λVDS
L
Assuming λVDS ≪ 1, equation (3) now becomes
!
µn Cox W
ID = (VGS − VTN )2 (1 + λVDS ) (4)
2 L

Clearly, the decrease in channel length causes ID to be linearly varying with VDS !
This is called channel length modulation, and is a critical issue in IC design.

Debapratim Ghosh Dept. of EE, IIT Bombay 13/20

 Basics of the MOSFET
The MOS Transistor
The MOSFET Operation
Operating Regions of the MOSFET
The Experiment

BJT and MOSFET- A Comparison

Bipolar Junction Transistor MOS Transistor

1. Current-controlled current source 1. Voltage-controlled current source

2. Current flows due to both electrons 2. Current flows due to one type of
and holes (bipolar) carrier (unipolar)

3. No two terminals are interchange- 3. Source and Drain can be inter-

able. changed.

4. No two terminals are strictly iso- 4. Gate is isolated by means of an

lated. insulator.

C D
B G B
E S
An n-p-n BJT An n-channel MOSFET
Debapratim Ghosh Dept. of EE, IIT Bombay 14/20
 MOS Transistor Types
• Rabaey Ch. 3 (Kang & Leblebici Ch. 3)
• Two transistor types (analogous to bipolar NPN, PNP)
– NMOS: p-type substrate, n+ source/drain, electrons are
charge carriers
– PMOS: n-type substrate, p+ source/drain, holes are
charge carriers
gate gate

N+ N+ P+ P+
source drain source drain
P-substrate N-substrate
bulk (substrate) bulk (substrate)
NMOS PMOS
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 MOS Transistor Symbols
NMOS D PMOS D

G B G B

S S
D D

G B G B

S S
D D

G B G B

S S
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 Note on MOS Transistor Symbols
• All symbols appear in literature
– Symbols with arrows are conventional in analog papers
– PMOS with a bubble on the gate is conventional in digital
circuits papers
• Sometimes bulk terminal is ignored – implicitly
connected to supply:

NMOS PMOS

• Unlike physical bipolar devices, source and drain are

usually symmetric

Amirtharajah/Parkhurst, EEC 118 Spring 2011 32

 MOS Transistor Structure
• Important transistor physical characteristics
– Channel length L = LD – 2xd (K&L L = Lgate – 2LD)
– Channel width W
– Thickness of oxide tox

W
tox
L

xd
Amirtharajah/Parkhurst, EEC 118 Spring 2011 33
 MOS Transistor Regions of Operation
• Three main regions of operation
• Cutoff: VGS < VT
No inversion layer formed, drain and source are
isolated by depleted channel. IDS ≈ 0
• Linear (Triode, Ohmic): VGS > VT, VDS < VGS-VT
Inversion layer connects drain and source.
Current is almost linear with VDS (like a resistor)
• Saturation: VGS > VT, VDS ≥ VGS-VT
Channel is “pinched-off”. Current saturates
(becomes independent of VDS, to first order).

Amirtharajah/Parkhurst, EEC 118 Spring 2011 34

 Fabrication Process
• Substrate is grown and then cut
– Round silicon wafers are used
– Purity emphasized to prevent impurities from
affecting operation (99.9999% pure)
• Each layer deposited separately
• Some layers used as masks for later layers
• Planar process is important
– Requires minimum percent usage of metal to
ensure flatness

Amirtharajah/Parkhurst, EEC 118 Spring 2011 35

 Silicon Substrate Manufacturing

Amirtharajah/Parkhurst, EEC 118 Spring 2011 36

 Building a Golf Course with Similar Process

• Plane drops materials from the air

– Sand, then dirt, then grass seeds, then trees
– Certain masks applied during process to prevent material
from hitting particular areas
– For instance: After Sand, mask placed over areas where
sand trap will exist. Mask later taken off at end of process
to reveal sand trap.
Amirtharajah/Parkhurst, EEC 118 Spring 2011 37
 Fabrication: Patterning of SiO2 Step I

• Grow SiO2 on Si by exposing to O2

– High temperature accelerates this process
• Cover surface with photoresist (PR)
– Sensitive to UV light (wavelength determines feature size)
– Positive PR becomes soluble after exposure
– Negative PR becomes insoluble after exposure
Amirtharajah/Parkhurst, EEC 118 Spring 2011 38
 Fabrication: Patterning of SiO2 Step II

• Exposed PR removed with a solvent

• SiO2 removed by etching (HF – hydrofluoric acid)
• Remaining PR removed with another solvent

Amirtharajah/Parkhurst, EEC 118 Spring 2011 39

 NMOS Transistor Fabrication

• Thick field oxide grown

• Field oxide etched to create area for transistor
• Gate oxide (high quality) grown

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 NMOS Transistor Fabrication

• Polysilicon deposited (doped to reduce resistance R)

• Polysilicon etched to form gate
• Gate oxide etched from source and drain
– Self-aligned process because source/drain aligned by
gate
• Si doped with donors to create n+ regions
Amirtharajah/Parkhurst, EEC 118 Spring 2011 41
 NMOS Transistor Fabrication

• Insulating SiO2 grown to cover surface/gate

• Source/Drain regions opened
• Aluminum evaporated to cover surface
• Aluminum etched to form metal1 interconnects
Amirtharajah/Parkhurst, EEC 118 Spring 2011 42
 MOS Transistor Types
• Rabaey Ch. 3 (Kang & Leblebici Ch. 3)
• Two transistor types (analogous to bipolar NPN, PNP)
– NMOS: p-type substrate, n+ source/drain, electrons are
charge carriers
– PMOS: n-type substrate, p+ source/drain, holes are
charge carriers
gate gate

N+ N+ P+ P+
source drain source drain
P-substrate N-substrate
bulk (substrate) bulk (substrate)
NMOS PMOS
Amirtharajah/Parkhurst, EEC 118 Spring 2011 4
 MOS Transistor Symbols
NMOS D PMOS D

G B G B

S S
D D

G B G B

S S
D D

G B G B

S S
Amirtharajah/Parkhurst, EEC 118 Spring 2011 5
 Note on MOS Transistor Symbols
• All symbols appear in literature
– Symbols with arrows are conventional in analog papers
– PMOS with a bubble on the gate is conventional in digital
circuits papers
• Sometimes bulk terminal is ignored – implicitly
connected to supply:

NMOS PMOS

• Unlike physical bipolar devices, source and drain are

usually symmetric

Amirtharajah/Parkhurst, EEC 118 Spring 2011 6

 MOS Transistor Structure
• Important transistor physical characteristics
– Channel length L = LD – 2xd (K&L L = Lgate – 2LD)
– Channel width W
– Thickness of oxide tox

W
tox
L

xd
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 NMOS Transistor I-V Characteristics I

• I-V curve vaguely resembles bipolar transistor curves

– Quantitatively very different
– Turn-on voltage called Threshold Voltage VT
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 NMOS Transistor I-V Characteristics II

• Drain current varies quadratically with gate-source

voltage VGS (in Saturation)

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 MOS Transistor Operation: Cutoff
• Simple case: VD = VS = VB = 0
– Operates as MOS capacitor (Cg = gate to channel)
– Transistor in cutoff region
• When VGS < VT0, depletion region forms
– No carriers in channel to connect S and D (Cutoff)
Vg < VT0
Vs = 0 Vd = 0
depletion
source drain region
P-substrate
VB = 0
Amirtharajah/Parkhurst, EEC 118 Spring 2011 10
 MOS Transistor Operation: Inversion
• When VGS > VT0, inversion layer forms
• Source and drain connected by conducting n-
type layer (for NMOS)
– Conducting p-type layer in PMOS

Vg > VT0
Vs = 0 Vd = 0
depletion
source drain region
P-substrate

inversion VB = 0
layer
Amirtharajah/Parkhurst, EEC 118 Spring 2011 11
 Threshold Voltage Components
• Four physical components of the threshold voltage
1. Work function difference between gate and channel
(depends on metal or polysilicon gate): ΦGC
2. Gate voltage to invert surface potential: -2ΦF
3. Gate voltage to offset depletion region charge:
QB/Cox
4. Gate voltage to offset fixed charges in the gate oxide
and oxide-channel interface: Qox/Cox

ε ox
Cox = : gate oxide capacitance per unit area
tox
Amirtharajah/Parkhurst, EEC 118 Spring 2011 12
 Threshold Voltage Summary
• If VSB = 0 (no substrate bias):
QB 0 Qox
VT 0 = Φ GC − 2φ F − − (K&L 3.20)
Cox Cox

• If VSB ≠ 0 (non-zero substrate bias)

VT = VT 0 + γ ( − 2φ F + VSB − 2φ F ) (3.19)

• Body effect (substrate-bias) coefficient:

2qN Aε Si
γ= (K&L 3.24)
Cox
• Threshold voltage increases as VSB increases!
Amirtharajah/Parkhurst, EEC 118 Spring 2011 13
 Threshold Voltage (NMOS vs. PMOS)

NMOS PMOS

Substrate Fermi
potential
φF < 0 φF > 0

Depletion charge
density
QB < 0 QB > 0

Substrate bias
coefficient
γ>0 γ<0

Substrate bias voltage VSB > 0 VSB < 0

Amirtharajah/Parkhurst, EEC 118 Spring 2011 14

 Body Effect
• Body effect: Source-bulk voltage VSB affects threshold
voltage of transistor
– Body normally connected to ground for NMOS, Vdd
(Vcc) for PMOS
– Raising source voltage increases VT of transistor
– Implications on circuit design: series stacks of devices

If Vx > 0,
A VSB (A) > 0,
Vx VT(A) > VTO
B
VT0

Amirtharajah/Parkhurst, EEC 118 Spring 2011 15

 MOS Transistor Regions of Operation
• Three main regions of operation
• Cutoff: VGS < VT
No inversion layer formed, drain and source are
isolated by depleted channel. IDS ≈ 0
• Linear (Triode, Ohmic): VGS > VT, VDS < VGS-VT
Inversion layer connects drain and source.
Current is almost linear with VDS (like a resistor)
• Saturation: VGS > VT, VDS ≥ VGS-VT
Channel is “pinched-off”. Current saturates
(becomes independent of VDS, to first order).

Amirtharajah/Parkhurst, EEC 118 Spring 2011 16

 MOSFET Drain Current Overview

μCox W
Saturation: ID = (VGS − VT ) (1 + λVDS )
2

2 L

Linear (Triode, Ohmic):

⎛ VDS ⎞
2
I D = μCox ⎜⎜ (VGS − VT )VDS −
W
⎟⎟
L⎝ 2 ⎠
Cutoff: ID ≈ 0

“Classical” MOSFET model, will discuss deep submicron

modifications as necessary (Rabaey, Eqs. 3.25, 3.29)
Amirtharajah/Parkhurst, EEC 118 Spring 2011 17
 Cutoff Region
VG
VS VD

depletion
source drain region
substrate

• For NMOS: VGS < VTN VB

• For PMOS: VGS > VTP
• Depletion region – no inversion
• Current between drain and source is 0
– Actually there is always some leakage (subthreshold)
current
Amirtharajah/Parkhurst, EEC 118 Spring 2011 18
 Linear Region
• When VGS>VT, an inversion layer forms between drain and
source
• Current IDS flows from drain to source (electrons travel
from source to drain)
• Depth of channel depends on V between gate and channel
– Drain end narrower due to larger drain voltage
– Drain end depth reduces as VDS is increased
Vg > VT0
Vs=0 Vd < VGS-VT0
depletion
source drain
Channel region (larger
(inversion layer) at drain end)
P-substrate
VB = 0
Amirtharajah/Parkhurst, EEC 118 Spring 2011 19
 Linear Region I/V Equation Derivation

• Gradual Channel Approximation:

– Assume dominant electric field in y-direction
– Current is constant along channel
• Integrate differential voltage drop dVc = IDdR along y
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 Linear Region I/V Equation

• Valid for continuous channel from Source to Drain

I D = μ nCox
W
L
[
(VGS − VT )VDS − 12 VDS2 ]
W
Device transconductance: k n = μ nCox
L
Process transconductance: k = μ nCox
'
n

ID = k
W
L
'
n [
(VGS − VT )VDS − 2 VDS
1 2
]
Amirtharajah/Parkhurst, EEC 118 Spring 2011 21
 Saturation Region
• When VDS = VGS - VT:
– No longer voltage drop of VT from gate to substrate at drain
– Channel is “pinched off”
• If VDS is further increased, no increase in current IDS
– As VDS increased, pinch-off point moves closer to source
– Channel between that point and drain is depleted
– High electric field in depleted region accelerates electrons
towards drain Vg > VT0
Vs=0 Vd > VGS-VT0
depletion
source drain region

pinch-off point VB = 0
Amirtharajah/Parkhurst, EEC 118 Spring 2011 22
 Saturation I/V Equation
• As drain voltage increases, channel remains
pinched off
– Channel voltage remains constant
– Current saturates (no increase with increasing VDS)
• To get saturation current, use linear equation with
VDS = VGS - VT

I D = μ nCox (VGS − VTN )

1W 2
2
L

Amirtharajah/Parkhurst, EEC 118 Spring 2011 23

 MOS I/V Characteristics
• I/V curve for ideal MOS device
• VGS3> VGS2 >VGS1

VGS3
Drain current IDS

Linear VGS2

VGS1

Saturation

Drain voltage VDS

Amirtharajah/Parkhurst, EEC 118 Spring 2011 24

 Channel Length Modulation
• In saturation, pinch-off point moves
– As VDS is increased, pinch-off point moves closer to source
– Effective channel length becomes shorter
– Current increases due to shorter channel

L = L − ΔL
'

I D = μ nCox (VGS − VTN ) (1 + λVDS )

1W 2
2
L
λ = channel length modulation coefficient

Amirtharajah/Parkhurst, EEC 118 Spring 2011 25

 MOS I/V Curve Summary
I/V curve for non-ideal NMOS device:

VDS = VGS-VT
VGS3 with channel-
length
Drain current IDS

Linear VGS2 modulation

VGS1 without channel-

length modulation
(λ=0)
Saturation

Drain voltage VDS

Amirtharajah/Parkhurst, EEC 118 Spring 2011 26

 MOS I/V Equations Summary
Cutoff VGS < VTN
⇒ ID = 0
VGS > VTP
Linear
VGS ≥VTN, VDS <VGS −VTN
VGS ≤VTP, VDS >VGS −VTP
W
L
[
⇒ID = μCox (VGS −VT )VDS − 12 VDS
2
]
Saturation
VGS ≥VTN, VDS ≥VGS −VTN
⇒ID = 2 μCox (VGS −VT ) (1+λVDS)
1 W 2

VGS ≤VTP, VDS ≤VGS −VTP L

Note: if VSB ≠ 0, need to recalculate VT from VT0
Amirtharajah/Parkhurst, EEC 118 Spring 2011 27
 A Fourth Region: Subthreshold
VGS
⎛ V
− DS ⎞
Subthreshold: ID = ISe
n kT q ⎜1 − e kT q ⎟
⎜ ⎟
⎝ ⎠
• Sometimes called “weak inversion” region
• When VGS near VT, drain current has an exponential
dependence on gate to source voltage
– Similar to a bipolar device
• Not typically used in digital circuits
– Sometimes used in very low power digital applications
– Often used in low power analog circuits, e.g. quartz
watches
Amirtharajah/Parkhurst, EEC 118 Spring 2011 28
 MOSFET Scaling Effects

• Rabaey Section 3.5 (Kang & Leblebici Section 3.5)

• Scaling provides enormous advantages
– Scale linear dimension (channel length) by factor S > 1
– Better area density, yield, performance
• Two types of scaling
– Constant field scaling (full scaling)
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID/S; P’ = P/S2 ;
Vdd’ = Vdd/S
• Power Density P’/A’ = stays the same Change these two
– Constant voltage scaling
• A’ = A/S2; L’ = L/S; W’ = W/S; ID’ = ID*S; P’ = P*S;
Vdd’ = Vdd
• Power Density P’/A’ = S3*P (Reliability issue)
Amirtharajah/Parkhurst, EEC 118 Spring 2011
This changed as well 29
 Short Channel Effects
• As geometries are scaled down
– VT (effective) goes lower
– Effective channel length decreases
– Sub-threshold Ids occurs
• Current goes from drain to source while Vgs < Vt
– Tox is scaled which can cause reliability problems
• Can’t handle large Vg without hot electron effects
– Changes the Vt when carriers imbed themselves
in the oxide
– Interconnects scale
• Electromigration and ESD become issues

Amirtharajah/Parkhurst, EEC 118 Spring 2011 30

 MOSFET Capacitances
• Rabaey Section 3.3 (Kang & Leblebici Section 3.6)
• Oxide Capacitance
– Gate to Source overlap
– Gate to Drain overlap
– Gate to Channel
• Junction Capacitance
– Source to Bulk junction
– Drain to Bulk junction

Amirtharajah/Parkhurst, EEC 118 Spring 2011 31

 Oxide Capacitances: Overlap

source Ldrawn drain

xd

• Overlap capacitances
– Gate electrode overlaps source and drain regions

– xd is overlap length on each side of channel

– Leff = Ldrawn – 2xd (effective channel length)
– Overlap capacitance:
CGSO = CGDO = CoxWxd Assume xd equal on both sides
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 Total Oxide Capacitance
• Total capacitance consists of 2 components
– Overlap capacitance
– Channel capacitance Cgs Cgd
source drain
Cgb
• Cutoff:
– No channel connecting to source or drain

– CGS = CGD = CoxWxd

– CGB = CoxWLeff

– Total Gate Capacitance = CG = CoxWL

Amirtharajah/Parkhurst, EEC 118 Spring 2011 33

 Oxide Capacitances: Channel
• Linear mode
– Channel spans from source to drain
– Channel Capacitance split equally between S and D
1 1
CGS = C oxWLeff CGD = C oxWLeff CGB = 0
2 2
– Total Gate capacitance CG = CoxWL
• Saturation regime
– Channel is pinched off: Channel Capacitance --
2
CGD = Wxd Cox CGS = CoxWLeff + COX Wxd CGB = 0
3
– Total Gate capacitance:
CG = 2/3 CoxWLeff + 2xdWCOX
Amirtharajah/Parkhurst, EEC 118 Spring 2011 34
 Oxide Capacitances: Channel

Cg,total
(no overlap,
xd = 0)

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 Junction Capacitance

Reverse-biased P-N junctions!

Capacitance depends on reverse-bias voltage.

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 Junction Capacitance

A 2qε N d N a
For a P-N junction: Cj =
2 V0 − V N d + N a
qε Si N d N a
If V=0, cap/area = C j0 =
2V0 N d + N a

AC j 0
General form: Cj = m
⎛ V ⎞
⎜⎜1 − ⎟⎟
⎝ V0 ⎠

m = grading coefficient (0.5 for abrupt junctions)

(0.3 for graded junctions)
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 Junction Capacitance
• Junction with substrate
– Bottom area = W * LS (length of drain/source)
– Total cap = Cj
• Junction with sidewalls
– “Channel-stop implant”
– Perimeter = 2LS + W
– Area = P * Xj
– Total cap = Cjsw
• Total junction cap C = Cj + Cjsw

Amirtharajah/Parkhurst, EEC 118 Spring 2011 38

 Junction Capacitance
• Voltage Equivalence Factor
– Creates an average capacitance value for a
voltage transition, defined as ΔQ/ΔV
⎛
− AC j 0V0 ⎜ ⎛ V2 ⎞
1− m
⎛ V1 ⎞ ⎞⎟
1− m

Ceq = ⎜⎜1 − ⎟⎟ − ⎜⎜1 − ⎟⎟ = AK eq C j 0

(V2 − V1 )(1 − m ) ⎜⎝ ⎝ V0 ⎠ ⎝ V0 ⎠ ⎟⎠

K eq =
− 2 V0
(V2 − V1 )
(
V0 − V2 − V0 − V1 ) (abrupt junction only)

Cdb = AK eq C j 0 + PX j K eqswC jsw0

Amirtharajah/Parkhurst, EEC 118 Spring 2011 39