274 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO.

2, FEBRUARY 2020

Low Latency Floating-Point Division

and Square Root Unit
Javier D. Bruguera , Senior Member, IEEE

Abstract—Digit-recurrence algorithms are widely used in actual microprocessors to compute floating-point division and square root.
These iterative algorithms present a good trade-off in terms of performance, area and power. We present a floating-point division and
square root unit, which implements a radix-64 floating-point division and a radix-16 floating-point square root. To have an affordable
implementation, each radix-64 division iteration and radix-16 square root iteration are made of simpler radix-4 iterations: 3 radix-4
iterations in division and 2 in square root. Speculation is used between consecutive radix-4 iterations to get a reduced timing. There are
three different parts in digit-recurrence implementations: initialization, digit iterations, and rounding. The digit iteration is the iterative part
and it uses the same logic for several cycles. Division and square root share partially the initialization and rounding stages, whereas each
one has different logic for the digit iterations. The result is a low-latency floating-point divider and square root, requiring 11, 6, and 4 cycles
for double, single and half-precision division with normalized operands and result, and 15, 8 and 5 cycles for square root. One or two
additional cycles are needed in case of subnormal operand(s) or result.

Index Terms—Digit-recurrence algorithms, floating-point division, and square root

1 INTRODUCTION
and square root are some of the most representa- of interest, double, single and half-precision, digit-recurrence
D IVISION
tive floating-point functions in modern processors.
Although they are less frequent than the two basic arithme-
methods are faster. Multiplicative methods rely on several
iterations of a fused multiply-add (FMA) operation, and the
tic operations, addition and multiplication, a poor perfor- latency of a single FMA is between 3 and 6 cycles [13], [22],
mance when computing these operations can impact the [25]. In some cases, this is the latency of our proposed divider
processor global performance. for single-precision.
For a low precision computation of these functions, it is In this paper the architecture of a floating-point unit imple-
possible to employ direct table look-up, bipartite tables [3], menting a radix-64 digit-recurrence divider and a radix-16
[24] (table look-up and addition), or low-degree polynomial square root is described. A radix-r digit-recurrence algorithm,
or rational approximations [12], [15], [27], [28], but the area being r a power of 2, is an iterative algorithm where a radix-r
requirements become prohibitive for table-based methods digit, log2 ðrÞ bits, of the result quotient or root, is obtained
when performing medium or high precision computations every iteration. To get an energy and timing efficient imple-
(such as the single and double-precision floating-point for- mentation both the division and the square root iteration are
mat). More efficient alternatives are iterative algorithms [7] obtained by overlapping simpler radix-4 iterations. Hence,
On one hand, digit-recurrence methods [5], [7] have linear three radix-4 division iterations are overlapped in a single
convergence and are based on subtraction; but their linear cycle providing 6 bits of the quotient per cycle, which is equiv-
convergence sometimes leads to long latencies and makes alent to a radix-64 iteration. Similarly, two radix-4 square root
them inadequate methods for these computations. High- iterations are overlapped in a single cycle providing 4 bits of
radix digit-recurrence methods result in faster but bigger the root per cycle, which is equivalent to a radix-16 iteration.
designs. On the other hand, multiplicative-based methods A digit-recurrence division or square root algorithm with
[4], [8], [20], [21], such as the Newton-Raphson and Gold- floating-point operands has three parts: pre-processing, digit
schmidt algorithms, have quadratic convergence at the iterations, and post-processing. The pre-processing includes
expense of greater hardware requirements. operands unpacking, operands normalization (if required)
The energy efficiency of both approaches has been recently and initialization. Digit iterations is the iterative part of the
analyzed and the conclusion is that the digit-recurrence digit-recurrence algorithm. Post-processing consists of the
approach is much more energy efficient than the multiplica- rounding logic and right-shift in case of a subnormal result
tive methods [17]. In addition, for the floating-point precisions (in division only). The pre-processing and post-processing
logic is mostly shared between division and square root,
whereas the iterative part, the digit iterations, are specific for
 The author is with the ARM Ltd, CB1 9NJ Cambridge, U.K. either operation.
E-mail: [email protected]. To improve the timing of the division iteration we have
Manuscript received 1 Apr. 2019; revised 4 Oct. 2019; accepted 11 Oct. 2019. used the divisor pre-scaling technique [6]. This is a well-
Date of publication 16 Oct. 2019; date of current version 13 Jan. 2020. known technique to simplify the quotient-digit selection
(Corresponding author: Javier D. Bruguera.)
Recommended for acceptance by N. Takagi. function, probably the most timing critical step in a digit-
Digital Object Identifier no. 10.1109/TC.2019.2947899 recurrence algorithm. The selection function is simplified by
0018-9340 ß 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See ht_tp://www.ieee.org/publications_standards/publications/rights/index.html for more information.

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 275

scaling the divisor to a value close enough to 1. This way, the The partial result before iteration i is defined as
radix-4 selection function is independent of the divisor. This
X
i
scaling is carried out before the digit iterations. R½i ¼ pj  rj ; (1)
Additionally, some other techniques has been used to j¼0
improve the timing or latency of division and/or square
root, and each algorithm iteration is described by the following
equations:
 To reduce the timing, speculation is used between
consecutive radix-4 iterations in the cycle. d Tb½iÞ
piþ1 ¼ SELðrem½i; (2)
 First iteration is not carried out in the iterative part
but in the pre-processing stage; this way, latency is rem½i þ 1 ¼ r  rem½i  piþ1  f½i þ 1; (3)
reduced by 1 cycle for given precisions.
– Division: The first iteration, which gives the inte- d
being rem½i and Tb½i estimations with a few bits of the
ger digit of the result, is carried out in parallel remainder rem½i and the divisor (in case of division) or the
with the operands pre-scaling, contributing to partial result R½i (in case of square root), respectively. The
save one cycle in single-precision. number of bits in the estimation needed for the selection
– Square root: The first iteration is skipped and inte- function SEL depends on the radix and the operation. Term
grated in the initialization stage. The partial root f½i þ 1 is different for each operation.
and the remainder for the second iteration are For a fast iteration, the remainder is kept in carry-save of
easily obtained from the input value. This way, signed–digit redundant representation. In our implementa-
the latency is reduced by 1 cycle in double and tion, we have chosen a radix-2 signed-digit representation
single-precision. for the remainder, with a positive and a negative word.
The result is a low-latency unit with 11, 6, and 4 cycles On the other hand, note that because of the algorithm
latency for double-precision, single-precision and half- convergence conditions and the multiplication times r in
precision division, respectively, and 15, 8, and 5 cycles latency Equation (3), the remainder will have several bits in the inte-
for double-precision, single-precision and half-precision ger part; the number of integer bits depending on the radix,
square root. These latencies include the pre-processing and the digit set, and the operation.
post-processing cycles and correspond to a division or square Then, every iteration a radix-r digit of the result is
root with normalized operands and result. In case of subnor- obtained from the current remainder, and a new remainder
mal operands, one or two additional normalization cycles are is computed for the next iteration.
needed. Similarly, in case of a division subnormal result an Then, the number of iterations is
additional cycle after the rounding cycle is added to right shift it ¼ dn=log 2 ðrÞe; (4)
the result and adjust the exponent.
This unit has been implemented in a processor with a being n the number of bits of the result, including the bits
frequency of 3 GHz. required for rounding.
The floating-point division has been already described The number of cycles is directly related to the number of
in [1]. In this paper, the square root implementation is iterations and to the number of iterations performed per
discussed and some more details about the division cycle. Then, considering m iterations per cycle, the number
implementation are provided. Only the operations on the of cycles is
mantissas are shown; the sign and exponent are obtained
separately. cycles ¼ dit=me: (5)
The rest of the paper is organized as follows. Section 2 is
a brief description of the foundations of digit-recurrence Equations (1) to (4) can be particularized to radix-4, r ¼ 4,
division and square root. In Section 3 the general architec- division and square root.
ture is presented and the main features of the proposed
unit are outlined. In Sections 4 and 5 the implementation 2.1 Radix-4 Division
of both the divider and the square root is described. Some The floating-point division of a dividend x and a divisor d
considerations about how subnormals operands and result produces a quotient q ¼ x=d. The partial quotient before
are processed are given in Section 6. Finally, in Section 7 iteration i and the digit obtained at iteration i are called Q½i
the unit is compared with other implementations in actual and qiþ1 respectively, then Equation (1) is rewritten as
processors, and in Section 8 the main conclusions are
presented. X
i
Q½i ¼ qj  4j : (6)
j¼1

2 DIGIT-RECURRENCE ALGORITHMS FOR DIVISION

AND SQUARE ROOT It has been shown that a simpler implementation is
obtained if the divisor is scaled to be close to 1 [6]. In this case
Digit-recurrence is a class of iterative algorithms which the selection function is independent on the divisor, then
compute a radix-r result digit piþ1 , with r a power of 2, and
a remainder rem½i every iteration [5], [7]. The remainder is d
qiþ1 ¼ SELðrem½iÞ (7)
used to obtain the next radix-r digit. Note that each radix-r
digit represents log2 ðrÞ bits of the results. rem½i þ 1 ¼ 4  rem½i  qiþ1  d: (8)

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276 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

Note that f½i þ 1 ¼ d, and the initial value for the remain-
der is rem½0 ¼ x.
For this implementation, it has been determined that
only the 6 most-significant bits (MSB) of the remainder,
three integer bits and three fractional bits, are required to
select the next quotient digit with Equation (7) [7].

2.2 Radix-4 Square Root

The floating–point
pffiffiffi square root of the operand x produces a
root s ¼ x. The partial root before iteration i and the digit
obtained at iteration i are called S½i and siþ1 respectively,
then Equation (1) is rewritten as

X
i
S½i ¼ sj  4j s0 ¼ 1: (9)
j¼0

The square root iteration is defined by equations

d S½iÞ
siþ1 ¼ SELðrem½i; b (10)

rem½i þ 1 ¼ 4  rem½i  siþ1

(11)
 ð2  S½i þ siþ1  4ðiþ1Þ Þ:

For square root

f½i þ 1 ¼ 2  S½i þ siþ1  4ðiþ1Þ ; (12)

then

rem½i þ 1 ¼ 4  rem½i  siþ1  f½i þ 1: (13)

Fig. 1. General organization of the unit.
The initial values for remainder and partial root are
rem½0 ¼ x  1 and S½0 ¼ 1:0, respectively. The digit iterations stage is the iterative part of the digit-
In the selection function (Equation (10)) 9 bits of the recurrence algorithm. Division and square root have a dif-
remainder, the 4 integer bits and 5 fractional bits, and 5 bits ferentiate digit iteration logic, although the registers are
of the partial root, the integer bit and 4 fractional bits, are shared. This logic is divided into two parts, (1) remainder
checked [7]. calculation, and (2) quotient/root digit calculation and par-
tial quotient/root updating. As stated in the introduction,
3 GENERAL ARCHITECTURE AND MAIN FEATURES radix-64 division and radix-16 square root iterations are
obtained by overlapping simpler radix-4 iterations each
The two floating-point operations being performed in this cycle: three radix-4 iterations in division, and two radix-4 in
unit are division and square root. The general organization is square root. Every iteration a new value for the partial quo-
shown in Fig. 1. The three parts of the digit-recurrence imple- tient/root and the remainder is computed. Redundant
mentation, pre-processing, digit iterations and post-process- radix-2 signed-digit representation is used for both, partial
ing, are clearly marked.1 These three parts share the registers result and remainder; therefore two words, positive word
for the partial quotient/root, remainder, and some other and negative word, are used to represent the remainder and
signals. partial result; The updated remainder and partial quotient/
In the pre-processing stage operands are unpacked, and root are passed back for the next cycle. After the last itera-
the first iteration of division or square root is carried out. In tion, the unrounded quotient/root and the final remainder
addition, in case of division, divisor and dividend are scaled are passed to the post-processing stage.
to put the divisor in a narrow interval around þ1 so that the As said before, division and square root have separated
quotient-digit selection is simplified. Any subnormal oper- digit iteration logic. However, there are some previous pro-
and is normalized in this stage; the normalization logic is posal combining the digit iteration logic for division and
used for 1 or 2 cycles depending on the number of subnormal square root [2], [18]. Although the area would be smaller, in
operands. The partial quotient/root and remainder initial our implementation the stage timing would be affected; in par-
values are passed to the digit iterations. ticular, it would be impossible to have three radix-4 division
iterations in the same cycle. As it will be shown in Sections 4.2
1. Pre- and post-processing can take more than 1 cycle. Pre-process- and 5.2, the remainder update is done with 3-to-2 carry-save
ing takes 1, 2 or 3 cycles whether there are none, one or two subnormal adders in the division iteration, and with 4-to-2 carry-save
operands, respectively. Post-processing can take 2 cycles if the division
quotient is subnormal. These additional pre- and post-processing cycles adders in the square root iteration. In a combined unit 4-to-2
are not shown in the figure. carry-save adders need to be used in both division and square

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 277

root remainder update; consequently, three radix-4 iterations 3.2 Floating-Point Square-Root
wouldn’t fit in one cycle and the performance would be The unit computes the floating-point
pffiffiffi square-root of the oper-
degraded. Note that the area would be smaller because part of and, x, to obtain the root, S ¼ x. The operand needs to be
the carry-save adders could be removed. normalized, x 2 ½1; 2Þ, although a subnormal operand is
The post-processing stage rounds the quotient/root. Final accepted; in this case, the subnormal operand is normalized
remainder and unrounded result need to be assimilated, that before the digit iterations.
is subtract the negative word form the positive word, to get The normalized operand needs to be right shifted by 1 or
the remainders’ sign and the non-redundant unrounded 2 bits before the iterations. This is because:
result, and the result is rounded to get the final quotient or
root. In a floating-point division, the final quotient can be a 1) The algorithm requires the operand to be in [0.5,1),
subnormal number. In this case the mantissa needs to be 2) In case of an operand with an even exponent, after the
right-shifted to have a IEEE standard compliant result [11]. shift to have the operand in [0.5,1) the exponent
The post-processing stage is not longer discussed because becomes odd; then the mantissa is divided by 2 and the
it is a traditional floating-point rounding stage. exponent is incremented to have again an even expo-
The algorithm used for the division and square root is the nent; otherwise, the square-root cannot be calculated.
radix-4 digit-recurrence algorithm with three (division) or Then, the input to the iterations is
two (square root) iterations per cycle, and with a signed- 
0 x=2 if exponent is odd
digit representation of the quotient with digit set f2; 1; 0; x ¼ : (14)
x=4 if exponent is even
þ1; þ2g; that is, being r ¼ 4, a ¼ 2, the radix and the digit
set respectively.
Consequently, x0 2 ½0:25; 1Þ and the root will be in [0.5,1).
With the radix-4 algorithm, 2 bits of the quotient or root
The first iteration is skipped and integrated into the ini-
are obtained every iteration. As three radix-4 iterations are
tialization of the remainder and partial root, reducing the
performed per clock cycle in division, 6 bits of the quotient
number of iterations by 1 without affecting the timing. The
are obtained every cycle, which is equivalent to a radix-64
latency is related to the number of iterations and to the num-
divider. Similarly, two radix-4 iterations are performed per
ber of iterations per cycle, and skipping the first iteration
clock cycle in square root, and 4 bits of the root are obtained
results in 1-cycle latency reduction in double- and single-
every cycle, which is equivalent to a radix-16 square root.
precision.
Let’s now describe the main features of the division and
square root implementations.
3.3 Early Termination Mode
3.1 Floating-Point Division There is an early-termination mode for exceptional oper-
ands. The early termination occurs when any of the oper-
The divider performs the floating-point division of a divi-
ands, or the only square root operand, are NaN, infinity, or
dend, x, and a divisor, d, to obtain a quotient, q ¼ x=d. The
zero, or a power of 2 with normalized operands. In the latter
two operands need to be normalized, x; d 2 ½1; 2Þ, although
case, three cases are differentiated,
subnormal operands are accepted; in this case, the subnor-
mal operands are normalized before the digit iterations. 1) Division by a power of 2. The result is obtained by
If the two operands are normalized in [1,2), the result is in merely incrementing or decrementing the exponent
[0.5,2); this way two bits to the right of the least–significant of the dividend.
bit (LSB) of the quotient are needed for rounding, the guard 2) Square root with an even power of 2. The operand is
and the round bits. The guard bits is used for rounding when a power of 4. The result is a power of 2 and the calcu-
the result is normalized, q 2 ½1; 2Þ, whereas the round bit is lation of the square root is carried out by merely
used for rounding when the result is not normalized, halving the input exponent
q 2 ½0:5; 1Þ. In this latter case, the results is left-shifted by 3) Square root pwith
ffiffiffi an odd power of 2. The mantissa of
1 bit, and the guard and round bits become the LSB and the the result is 2 and the exponent is obtained by halv-
guard bit, respectively, of the normalized result. ing the input exponent minus 1.
However, to simplify the rounding, the final quotient is
forced to be in q 2 ½1; 2Þ. Note that q < 1 only if x < d. This 3.4 Latency
situation is detected in pre-processing and the dividend is For normal operands and result, the latency is composed of
left-shifted by 1 bit in such a way that q ¼ 2  x=d and 1 cycle for pre-processing, several cycles for digit iterations,
q 2 ½1; 2Þ. Of course, the mantissa is the same as in x=d but and 1 cycle for post-processing. There are no cycles for oper-
the exponent needs to be decremented. ands’ normalization, nor for right-shifting the result. Then,
Each iteration, a digit of the quotient is obtained by means the latency is the number of cycles of the iterative part plus
of a selection function. In order to have a quotient-digit selec- 2. Therefore, for practical floating-point formats, double,
tion function independent of the divisor, the divisor has been singe and half-precision, DP, SP and HP, respectively, the
scaled close to 1. To preserve the result the dividend needs to number of bits n, the number of iterations, the number of
be scaled by the same amount as the divisor. cycles (see Equations (4) and (5)), and the latency are:
In addition, note that the first quotient digit, which is the Division:
integer digit of the result, can take only values fþ1; þ2g,
and its calculation is much simpler than the calculation of  DP: n ¼ 53, it ¼ 27, cycles ¼ 9, latency ¼ 11
the remaining digits. Then, it is obtained in parallel with the  SP: n ¼ 24, it ¼ 12, cycles ¼ 4, latency ¼ 6
operand pre-scaling, saving one cycle in single-precision.  HP: n ¼ 11, it ¼ 6, cycles ¼ 2, latency ¼ 4

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278 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

TABLE 1 4 DIVIDER MICROARCHITECTURE

Result Digit Representation
In this section the divider is described. The divider microarch-
Digit pos. word neg. word itecture has been already discussed in [1]. In the following the
2 10 00 pre-processing stage, with focus on the operand pre-scaling
1 01 00 and the calculation of the integer digit, and the digit iterations
0 00 00 stage are presented.
1 00 01
2 00 10 4.1 Operand Pre-Scaling and Integer Digit
Calculation
Pre-scaling is a well-know technique to simplify the quotient
Square Root: digit selection function. Here we give a brief description of
 DP: n ¼ 54, it ¼ 27, cycles ¼ 13, latency ¼ 15 this technique. A detailed description can be found in [6].
 SP: n ¼ 25, it ¼ 13, cycles ¼ 6, latency ¼ 8 The divisor is scaled to a value close to 1 so that the quo-
 HP: n ¼ 12, it ¼ 6, cycles ¼ 3, latency ¼ 5 tient-digit selection is independent of the divisor. As shown
in [6], the selection function is quite simple: the remainder
Note that the number of bits n includes the guard bit for
estimation is compared with a few low-precision wired
division; as the quotient has been forced to be in [1,2), only
selection constants.
one additional bit for rounding is needed. On the other
If the divisor is not pre-scaled, the selection function in
hand, in case of square root, the root is in [0.5,1) then two
d dÞ Although
Equation (7) would become qiþ1 ¼ SELðrem½i;
additional bits are required for rounding. In addition, the
the divisor is the same for every iteration and known in
integer bit is not included in n. In division the integer bit is
advance, it has to be taken into account for the quotient-digit
obtained in pre-processing stage. In square root the root has
selection. Consequently, a look-up table storing the selection
to be left-shifted by one bit and the first computed fractional
constants for every quotient interval would be needed for
bit becomes the integer bit.
the quotient-digit selection. This look-up table is not
required when the divisor is pre-scaled.
3.5 Quotient/Root and Remainder Representation It has been determined that for a radix-4 digit recurrence it
The partial result is saved in a redundant radix-4 signed-digit is enough to have the scaled divisor in the range ½1  1=64;
representation with 2 words: a positive word, quot root pos, 1 þ 1=8. The divisor is multiplied by a scaling factor M ¼
storing the positive digits, and a negative word, quot root neg, 1 þ b  23 , with 0  b  8, and b 6¼ 7, which depends only
storing the negative digits. Each iteration, the new computed on the three most-significant bits of the divisor. The pre-
result digit is concatenated to the actual partial result to get scaling can be implemented as the addition of the divisor
the new partial result. plus 2 or 1 multiples of the divisor. The dividend has to be
For example, the final single precision result pre-scaled by the same amount to get the correct result.
quot root ¼ 2 0 0 ð1Þ 2 1 ð1Þ 0 0 0 1 1 1; The block diagram of this cycle is shown in Fig. 2. During
this cycle, in addition to the operands pre-scaling, the first
is represented as iteration is carried out, and the operands are compared to
force the result to be in [1,2)]:
quot root pos ¼ 2 0 0 0 210 000 111
1) As part of the pre-scaling, redundant carry-save rep-
quot root neg ¼ 0 0 0 1 001 000 0 0 0:
resentations of pre-scaled divisor and dividend are
obtained.
Note that if the quotient digit is 0, there is a 0 in both the
2) The redundant pre-scaled divisor and dividend are
positive and the negative words.
assimilated to a non-redundant representation, scaled
Therefore, four bits are used to represent each digit, 2
divisor and scaled dividend in the figure, to get the
positive bits and 2 negative bits. The representation of each
remainder after the first iteration, rem½1. The non-
digit is shown in Table 1. Then, the binary result for the
redundant divisor is used in the digit iterations as
example above is
well (see Equation (8)).
quot root pos ¼ 10:00 00 00 10 01 00 00 00 00 01 01 01 3) The operands are compared and the dividend is left-
shifted by 1 bit if x < d. To save time, the compari-
quot root neg ¼ 00:00 00 01 00 00 01 00 00 00 00 00 00:
son is carried out in parallel with the pre-scaling
4) In parallel with the operands’ redundant to non-
The non-redundant result is obtained by subtracting the
redundant conversion, the integer digit, q1 of the
negative word form the positive word
quotient is obtained as well. This is a simplified digit
quot root ¼ 1:111111100011000000010101: quotient calculation, because as the quotient is posi-
tive and in [1,2), the integer radix-4 digit can only
Note that in SP the last bit computed in the iterations is not take values q1 ¼ þ1; or q1 ¼ þ2.
part of the result, it is part of the sticky bit. Then the guard The integer digit calculation is replicated for
bit is the second LSB, g ¼ 0 x < d and for x  d, obtaining two quotient digit
The remainder is also represented with two words, a posi- candidates, for dividend larger than divisor and for
tive word, rem pos, and a negative word, rem neg. This way, dividend smaller than divisor. The result of the com-
the remainder can be updated without any carry propagation. parison selects the correct digit.

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 279

Fig. 2. Pre-processing stage for division: pre-scaling and integer quotient digit calculation.

5) The next remainder, rem½1, (see Equation (3)) is For the selection of qiþ1 the 6-bit remainder estimate is
obtained from the non-redundant scaled dividend computed with the 6-bit adder in front of the first SELECT
(positive word of the remainder) and the non- block.
redundant scaled divisor (negative word of the To select digits qiþ2 and qiþ3 the 9 MSBs of the speculative
remainder). The operands comparison is used in rem½i þ 1 are assimilated. Note that, the 9 MSBs are assimi-
the selection of the scaled dividend as well, in such lated because although the selection function for qiþ2 only
a way that the scaled dividend is 1-bit left-shifted if needs the 6 MSBs, 2 additional bits are required for the
the divisor is larger than the dividend. On the other selection of qiþ3 because of the 2-bit left-shift of rem½i þ 2,
hand, the scaled divisor is 1-bit left-shifted if the and the other additional bit is used to catch the carry into
quotient digit is þ2 and is not shifted if the quotient the least-significant position of the 8 bits.
digit is þ1. Digit qiþ1 selects the 9 MSBs, among the 5 speculatively
calculated MSBs, that are going to be used in the selection
4.2 Digit Iteration of qiþ2 . Note that only 6 bits are used in the selection.
The actual implementation of the floating-point divider per- The 6 MSBs so obtained may be different to the 6 MSB
forms three radix-4 iterations per cycle. So, the logic has obtained directly from rem½i þ 1, because the þ1 to com-
been optimized taking this fact into account. Fig. 3 shows plete the 2’s complement of the sum word in the assimila-
the block diagram of a digit iteration cycle; that is the com- tion of rem½i þ 1 is added at a different position. In the
putation of three radix-4 iterations. The block diagram in actual implementation in Fig. 3, it is added at the position of
Fig. 3 is split into two parts, (1) quotient digit selection and, the 8th MSB whereas, in case of being obtained directly
(2) remainder calculation. from rem½i þ 1, it would be added at the position of the 6th
The remainders rem½i þ 1, rem½i þ 2 and rem½i þ 3 are MSB. Consequently, the carry into the 6th MSB can be dif-
computed speculatively according to Equation (8). So, five ferent. This difference makes the end-points of the intervals
remainders are computed every iteration, one remainder in Table 2 a get a wrong selection when the carry into the
for each possible value of the quotient digit; the correct 6th MSB bit is zero. This is corrected with the selection func-
remainder is selected when the digit is obtained. Note that, tion shown in Table 2 b. Note that the selection of the inter-
the remainder has to be left-shifted by two bits as part of the val end-points depends on the carry into the 6th MSB (carry
computation of the next remainder. column in the table) .
The quotient-digit selection uses an estimation of the Therefore, it is clear that the carry into the 6th bit is
remainder to obtain the next quotient digit (Equation (7)). As required for the selection of the q½i þ 2 digit. Hence, the 9–
said in Section 2.1, it has been determined that only the 6 bit adder has to be split into a 6–bit adder and a 3-bit adder
most-significant bits (MSB) of the remainder are required, to get access to this carry.
three integer bits and three fractional bits. The quotient digit In parallel with the selection of qiþ2 , the 6 MSB to be used
selection function is shown in Table 2 a. The intervals in the selection of digit qiþ3 are computed speculatively for
4  rem½i for the selection of every digit has been obtained every value of qiþ2 . Thus, the non-redundant estimation of
following the methodology described in [7]. rem½i þ 2 is obtained in the five 7-bit adders, by adding the

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280 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

Fig. 3. Division digit iteration stage.

shifted 7 MSB of rem½i þ 1 plus the 7 MSBs of qiþ2  d. organization, the latency is also reduced by 1 cycle. The
Then, digit qiþ2 is used to select the correct adder output, first iteration is skipped and integrated in the initialization
and qiþ3 is selected according to Table 2 a. stage. The partial root and the remainder for the second
This way, the delay of the logic in the cycle has been iteration are easily obtained from the input value x0 in
reduced with respect to a plain implementation of the three Equation (14).
quotient-digit selection functions.
In the quotient-digit selection, SELECT block in the figure, 5.1.1 New Initial Values for the Partial Root
the quotient digit is coded as a 1-hot 5-bit code fqp2; and the Remainder
qp1; qz; qn1; qn2g, so that for example, qp2 ¼ 1, qp1 ¼ qz ¼
As the first iteration is being skipped, the initial values for
qn1 ¼ qn2 ¼ 0 if qjþ1 ¼ þ2. The logic function to get every bit
the partial root and the remainder are those for the second
in the 1-hot 5-bit code is relatively simple, a 3-level 2-input
iteration in case the first iteration is not skipped. To get
gate logic function. Each time a new digit is obtained it is
these new initial values it has to be taken into account that
concatenated to the partial quotient.
the first digit can take only values f2; 1; 0g, because the
integer digit is 1, s0 ¼ 1, and the result is in [0.5,1). This
5 SQUARE ROOT MICROARCHITECTURE reduced set of possible values for the first digit is still fur-
ther reduced if odd and even input exponents are consid-
In this section the square root implementation is described.
ered separately.
The focus is in the skipping of the first iteration in the pre-
Let us consider the square root operand being
processing stage, and in the digit iterations stage.
x ¼ 1:x0 x1 x2 x3 x4 . . . xn1 :
5.1 Latency Reduction by Skipping the
First Iteration As stated in Section 3.2, this operand will be right-shifted
As explained in Section 2, the calculation of the square root is by 1 or 2 bits, depending whether the operand’s exponent is
composed of several iterations, the number of iterations odd or even, to get x0 , the input to the square root digit-
depending on the precision (number of bits) of the final result. recurrence algorithm (see Equation (14)).
The larger the number of iterations the larger the latency. In the following discussion, the initial values for remainder
By skipping the first iteration the number of iterations is and partial root are rem½0 ¼ x0  1 and S½0 ¼ 1, respectively
reduced by 1 and, for some floating-point precisions and (see Section 2.2)

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 281

TABLE 2 and the remainder is

Quotient-Digit Selection
rem½1 ¼ 4  rem½0:

In this case, as rem½0 is non-redundant, the positive

word of the signed-digit rem½1 is rem pos½1 ¼ 4 
rem½0, and the negative word is rem neg½1 ¼ 0. Then

rem pos½1 ¼ 111x0 :x1 x2 x3 . . . xn1 000

(16)
rem neg½1 ¼ 0000:000 . . . 0:

2) s1 ¼ 1. The partial root is obtained by the concate-

nation of s1
S½1 ¼ 0:75 ¼ 0:11;

and the remainder is

rem½1 ¼ 4  rem½0 þ f½1:

Now rem½1 is the sum of 4  rem½0 and f½1.

Then rem pos½1 is 4  rem½0, and rem neg½1 is the
2’s complement of f½1. From Equations (12) it can be
easily derived that

f½1 ¼ 1:75 ¼ 0001:110000:

Therefore

rem pos½1 ¼ 111x0 :x1 x2 x3 . . . xn1 000

(17)
rem neg½1 ¼ 1110:010 . . . 0:
Input Operand with Odd Exponent. Operand x is right-
Input Operand with Even Exponent. Operand x is right-
shifted by 1 bit to the get x0 , with x0 2 ½0:5; 1Þ
shifted by 2 bits to the get x0 , with x0 2 ½0:25; 0:5Þ
x0 ¼ 0:1x0 x1 x2 x3 x4 . . . xn1 0:
x0 ¼ 0:01x0 x1 x2 x3 x4 . . . xn1 :
Then, the initial values for partial root and remainder are
Then
S½0 ¼1
rem½0 ¼1111:1x0 x1 x2 x3 . . . xn1 0; S½0 ¼ 1
rem½0 ¼ 1111:01x0 x1 x2 x3 . . . xn1 ;
and the shifted remainder is
4  rem½0 ¼ 111x0 :x1 x2 x3 . . . xn1 000: and
4  rem½0 ¼ 1101:x0 x1 x2 x3 . . . xn1 00:
Under these circumstances, given the values of 4  rem½0
and S½0, the only possible values for the root digit are
Now, the first digit s1 2 f2; 1g
s1 ¼ f1; 0g, with
 
1 if x0 ¼ 0 2 if x0 ¼ 0
s1 ¼ : s1 ¼ :
0 if x0 ¼ 1 1 if x0 ¼ 1

Then, the redundant representation of the partial root is

Putting together both cases, the redundant representation of
the partial root is
S pos½1 ¼ 01:00
S pos½1 ¼01:00 (18)
(15) S neg½1 ¼ 00:x0 x0 :
S neg½1 ¼00:0x0 :
The new initial remainder rem½1 is as follows
Then, the new initial remainder rem½1, according to
1) s1 ¼ 1. This is the same case as item 2) above, input
Equation (11), is as follows
operand with odd exponent, but with a different x0
1) s1 ¼ 0. The partial root is obtained by the concatena- operand
tion of s1 S½1 ¼ 0:75 ¼ 0:11
S½1 ¼ 1:00; f½1 ¼ 1:75 ¼ 0001:110000 . . .

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282 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

Then New Initial Partial Root. According to Equations (15) and

(18), the possible values of the partial root are
rem pos½1 ¼ 1101:x0 x1 x2 x3 . . . xn1 00
(19) S pos ¼ 01:00 (23)
rem neg½1 ¼ 1110:010 . . . 0:

2) s1 ¼ 2. The partial root is 00:x0 x0 if exp even
S neg ¼ : (24)
00:0x0 if exp odd
S½1 ¼ 0:5 ¼ 0:10;
and the remainder is 5.2 Digit Iteration
The actual implementation of the floating-point square root
rem½1 ¼ 4  rem½0 þ 2  f½1: performs two radix-4 iterations per cycle. So, the logic has
been optimized taking this fact into account. Fig. 4 shows the
Now, rem½1 is the sum of 4  rem½0 and 2  f½1. block diagram of a digit-iteration cycle; that is the computa-
Then rem pos½1 is 4  rem½0, and rem neg½1 is the tion of two radix-4 iterations. Note that, the implementation
2’s complement of 2  f½1. From Equation (12) it can in figure is split into two parts, (1) remainder calculation,
be easily derived that and (2) digit selection and root updating.
As for division, the remainder is speculatively computed
f½1 ¼ f pos½1  f neg½1 ¼ 0001:100000 . . . 0:
according to Equation (11). So, 5 remainders are computed
Therefore every iteration, one remainder for each value of the root digit,
and the correct remainder is selected when the digit has been
rem pos½1 ¼ 1101:x0 x1 x2 x3 . . . xn1 00 obtained. Note that, the remainder has to be left-shifted by
(20) two bits as part of the computation of the next remainder.
rem neg½1 ¼ 1101:000 . . . 0:
The computation of remainders rem½i þ 1 and rem½i þ 2
involves the calculation of f½i þ 1 and f½i þ 2, respectively,
5.1.2 Putting it All Together according to Equation (12).
The new initial values for rem pos½1 and rem neg½1 are As shown in Equation (12), f½i þ 1 is obtained by
given by Equations (16), (17), (19) and (20). On the other concatenating (no addition needed) the selected digit siþ1 to
hand, the initial values for S½1 are given by Equations (15) the shifted partial root 2  S½i. Note that this equation dif-
and (18). These are the value of the remainder and partial fers of the updating of the partial root (Equation (9)) only in
root for the second iteration. Now, all these equations need the left shifting of S½i. To save the digit position where
to be combined to get the new initial value for the remainder the siþ1 digit has to be concatenated, a mask (mask½i in the
and the partial root. figure) is used. This mask has the same wordlength as the
New Initial Remainder. The new partial remainder is given root, and it is initialized to 0000110 . . . 0. Note that each digit
by Equations (16), (17), (19) and (20). From these equations, has two bits including digit s0 . As shown in Fig. 5, the two
the negative word of the remainder can take the following 1s of this initial value are pointing to the second fractional
values: digit, because the first iteration has been integrated into the
8 initialization step (see Section 5.1).
>
> 0000:000 . . . 0 if exp odd; x0 ¼ 1 Then, the 5 different speculative f½i þ 1 are obtained, one
<
1110:010 . . . 0 if exp odd; x0 ¼ 0 f½i þ 1 per digit value. The f½i þ 1 are obtained in redun-
rem neg½1 ¼
>
> 1110:010 . . . 0 if exp even; x0 ¼ 1 dant form as well, with a positive word and a negative word.
:
1101:000 . . . 0 if exp even; x0 ¼ 0: In case of a positive digit, the digit is concatenated to the
(21) shifted positive partial root word and 0s are concatenated to
The value of the negative word of the remainder, rem the shifted negative partial root word. Similarly, in case of a
neg½1, is easily set by selecting one of the four values above negative digit, the digit is concatenated to the shifted nega-
for the 6 most-significant bits during the unpacking or the tive partial root word and 0s are concatenated to the shifted
normalization cycle, checking the less significant bit of the positive partial root word. This updating is similar to the
exponent and x0 . The remaining bits are all zero. updating of the partial root shown in Fig. 5, but shifting the
On the other hand, the values the positive word can take partial root before the concatenation.
are To keep the mask always updated, pointing to the posi-
8 tion where the next digit has to be concatenated, the mask is
>
> 111x0 :x1 . . . xn1 000 if exp odd; x0 ¼ 1 right–shifted by 2 bits at the end of every iteration.
<
111x0 :x1 . . . xn1 000 if exp odd; x0 ¼ 0 The left part of the figure is the digit selection and root
rem pos½1 ¼
>
> 1101:x0 x1 . . . xn1 00 if exp even; x0 ¼ 1 updating, according to Equations (10) and (9) respectively.
:
1101:x0 x1 . . . xn1 00 if exp even; x0 ¼ 0: The root update make use of the mask described above for
(22) the concatenation of the obtained root digit to the partial
root.
Note that all these values corresponds to the fractional
The digit selection is implemented differently in the first
part of x0 with two leading 1s and three trailing 0s
and the second iteration in the cycle. The root digit selection
11 fracðx0 Þ 000; requires to obtain an estimate of the remainder and of the
partial root; in particular, the estimate of the partial root is
and can be easily obtained in the pre-processing stage. required to determine the interval of the partial root [5], [7].

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 283

Fig. 4. Square root digit iteration stage.

Both, the remainder and the partial root, are kept in redun- Once the interval is known, four selection constants are
dant representation. It has been determined that the 9 MSBs obtained; these selection constants correspond to the lower
of the remainder (4 integer bits and 5 fractional bits) and the points of the remainder intervals for a root-digit equal to
5 MSBs of the partial root (the integer bit and 4 fractional 1, 0, þ1, and þ2 [5], [7]. The selection constants are 7-bit
bits) are enough for the root digit selection. width; so only the 7 most–significant bits of the remainder
The assimilation of the 5 MSBs of the partial root gives estimate has to be compared against these selection con-
the partial root interval. Taking into account that the partial stants to determine the next-root digit. Then, using a set of
root is in ½0:5; 1Þ, that is the lower half [0,0.5) of the range is four 7-bit comparators, the root-digit is obtained.
not used, only 8 intervals, I0 ; . . . ; I7 , are possible. Moreover, To speed up the digit selection in the second iteration in
an additional interval I8 is considered for the partial root the cycle and to balance the delay of the remainder calcula-
being S½i ¼ 1:0 . . . 0. tion and the digit selection in the first iteration in the cycle,
the 9 most–significant bits (MSB) of the remainder rem½i þ 1
are speculatively assimilated to its non-redundant represen-
tation. This allows to eliminate the 9-bit adder in the selection
of siþ2 .

6 SUBNORMAL OPERANDS AND/OR RESULT

The microarchitecture described in Sections 4 and 5 assumes
the inputs are normal. In case of having any subnormal,
Fig. 5. Initial value for the mask and digit concatenation. the input pre-processing stage is a bit different: subnormal

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284 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

TABLE 3 TABLE 4
Division and Square Root Latencies Latency Comparison

Division Square root Division Square root

Algorithm
DP SP HP DP SP HP HP SP DP HP SP DP
Normal inputs, normal result 11 6 4 15 8 5 AMD K7 multiplicative – 16 20 – 19 27
Normal inputs, subn result 12 7 5 – – – AMD Jaguar multiplicative – 14 19 – 16 27
One subn input, normal result 13 8 6 16 9 6 IBM zSeries radix-4 – 23 37 – – –
One subn input, subn result 14 9 7 – – – IBM z13 radix-8/4 – 18 28 – 22 37
Two subn input, normal result 14 9 7 – – – HAL Sparc multiplicative – 16 19 – 22 27
Intel Penryn radix-16 – 12 20 – 12 20
This paper radix-64/16 4 6 11 5 8 15
operands are normalized after the operand unpacking, and
before the pre-scaling (division) or the skipping of the first
iteration (square root). Consequently, because of the normal- half precision (10 fractional bits plus the guard bit). Addi-
ization, the input pre-processing needs more than one cycle. tionally, there is an integer digit which can be 1 or 2, but
In case of a subnormal result the post-processing stage this integer digit is obtained in parallel with the pre-scaling
requires two cycles: rounding and result normalization. and it does not count in the digit iterations cycles.
The digit iterations stage remains the same. Regarding the square root, the number of root bits is 54
for double precision, 25 for single precision and 12 for half
precision.
7 EVALUATION Then, as explained in Section 3.4, the number of digit
In this section we evaluate the proposed division/square cycles in division is 9, 4, and 2 for double precision, single
root unit in terms of latency, area, and timing, and compare precision and half precision respectively; whereas, the num-
it with other recent divider/square root or division only ber of digit cycles in square root is 13, 6, and 3 for double,
units in commercial processors. single and half precision, respectively.
Unfortunately, the references with the description of the Finally, the number of post-processing cycles is one if
division and square root units of the commercial processors result is normal or two if the result is subnormal (only in
that are included in this comparison does not contain any division).
information about static or dynamic power. Consequently, As an example, the cycles for the single precision divi-
although power, static and dynamic, is also an important sion are shown below,
metric, it has not been included in this discussion.
1) Normal inputs, normal result:
PRE - DGT - DGT - DGT - DGT - RND
7.1 Latency
2) Normal inputs, subnormal result:
The latency of division and square root calculation with the PRE - DGT - DGT - DGT - DGT - RND - RSH
proposed unit is shown in Table 3. The table shows the 3) One subnormal input, normal result:
latency for the three floating-point precisions of interest, UNP - NM - PSC - DGT - DGT - DGT - DGT - RND
double, single and half-precision, DP, SP and HP, respec- 4) One subnormal input, subnormal result:
tively, and for any combination of normal and subnormal UNP-NM-PSC-DGT-DGT-DGT-DGT-RND - RSH
input operands and result. Note that the square root result 5) Two subnormal inputs,normal result:
cannot be subnormal and that it has only one operand. UNP-NM-NM-PSC-DGT-DGT-DGT-DGT-RND
The latency is the sum of the number of cycles devoted to
where PRE is the pre-processing cycle with operands
pre-processing, plus the number of digit iterations cycles,
unpacking, pre-scaling and first iteration. This stage is split
plus the number of cycles for post-processing.
into unpacking (UNP) and normalization (NM) if any of the
The number of pre-processing cycles depends on the
operands is subnormal as shown in items 3) to 5). On the
number subnormals operands and on the operation. In divi-
other hand, DGT is a digit iteration cycle. Finally, RND and
sion it can be one, three, or four pre-processing cycles. If
RSH are the rounding and right-shift cycles, respectively,
both operands are normal unpacking and pre-scaling are
the post-processing cycles. Note that, the RSH cycle is only
done in the same cycle. In case of one subnormal operand
need in case of a subnormal quotient.
there are three independent cycles for unpacking, normali-
Table 4 compares the latency of the proposed divider/
zation and pre-scaling. Finally, if both operands are subnor-
square root unit with the latency of some other recent pro-
mal there are one cycle for unpacking, two normalization
cessors2 for floating-point half, single and double precisions
cycles, and one cycle for pre-scaling.
with normalized operands and result, Intel Penryn [2], IBM
Similarly, for square root there can be one pre-processing
cycle for unpacking if the operand is normal or two pre-
processing cycles, for unpacking and normalization, if the 2. Some other modern processors, such as AMD Ryzen, Intel Sky-
lake, and Intel Broadwell, are not included in the table because we have
operand is subnormal. not been able to find the full latency figures of floating-point division
The number of digit cycles depends on the number of and square root. However, some partial figures are given in [9]: the
result bits required. In division the number of fractional bits latency is specified with a cycle range which includes all the floating-
of the quotient the algorithm has to obtain is 53 for double point precisions. Thus, the floating-point division latency for Ryzen,
Skylake and Broadwell is 8-15 cycles, 14-16 cycles, and 10-15 cycles,
precision (52 fractional bits plus the guard bit), 24 for single respectively. Similarly, the square root latency for Ryzen, Skylake and
precision (23 fractional bits plus the guard bit) and 11 for Broadwell is 8-20 cycles, 14-21 cycles, and 10-23 cycles, respectively

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 285

zSeries [10], IBM z13 [14], HAL Sparc [16], AMD K7 [19], part. As for the divisor, in the digit iteration stage there are
AMD Jaguar [23]. The latencies shown in the table include the five 58-bit CSAs for iteration for a total of fifteen 58-bit
iteration cycles and the pre- and post-processing cycles, such CSAs, five 9-bit CPAs, and five 7-bit CPAs, plus the logic
as unpacking, pre-scaling and rounding. Note that no cycles for the selection of three quotient digits and the multi-
for normalization are included here because it has been plexers, twelve 58-bit 4:1 muxes and two 5:1 small wide
assumed that the operands are already normal; although, as muxes. In addition, in the pre-scaling logic three 58-bit add-
stated previously, the proposed divider can handle subnor- ers and some additional logic, two CSAs, multiplexers, and
mal inputs and output. a reduced selection logic, are needed.
It has to be pointed out that the latency in Table 4 is in The digit iteration stage in the square root has ten 4-to-2
cycles, and the comparison is done only in terms of the carry-save adders,3 six 8-bit adders and eight 7-bit compara-
latency without taking into account that different processors tors in the digit selection logic, plus some additional logic.
might run at different frequencies.
Most of the design in the table uses a multiplicative divi- 7.2.2 Other Division/Square Root or Division Only Units
sion algorithm, and one of them uses a radix-4 digit-recur-
The area of the radix-4 divider [10] is much smaller than the
rence implementation.
area in our proposal. The redundant partial remainder con-
As shown in the table, our proposal gets much lower
sists of a sum part of 116 bits and a carry part of 28 bits
latencies. The multiplicative implementation are limited by
(only 1 out 4 carries are flopped); the 6 most-significant bits
the latency of the multiplier of multiply-and-accumulate
must be in non-redundant format because they are used for
units that, as stated in the introduction, can be very signifi-
the quotient digit selection. The iteration is implemented
cant. On the other hand, the implementation in [10] uses a
with one stage of 116-bit 3-to-2 CSA and one stage of a 4-bit
very low radix, which implies a high number of iterations,
CPA; an additional 6-bit CPA is needed to deliver the 6
although its implementation is quite simple.
most-significant bits to the digit selection table.
The Intel Penryn processor [2] implements a radix-16
The radix-16 division/square root unit in [2] has been
combined division/square root unit by cascading two radix-
obtained by concatenating two radix-4 iterations in the same
4 iterations every cycle. Consequently, the latency is almost
cycle. Although the paper doesn’t provide any area break-
halved with respect to that of the radix-4 unit. As it is a com-
down, some area information is provided in a later publica-
bined unit, division and square root have the same latency.
tion [18] by different authors. Replication is used in the
Finally, the IBM z13 processor [14] has a divide and square
remainder calculation at each radix-4 iteration; five partial
root unit supporting single, double and quad precision, and
remainders are computed speculatively and then one of them
all the hexadecimal floating-point data types. The underlying
is selected once the digit is determined. Consequently, eight
algorithm is a radix-8 division and radix-4 square root, gener-
full-length 3-to-2 CSAs , four per radix-4 iteration, are used.
ating 3 bits per cycle and 2 bits per cycle respectively. The
The inputs to the 3-to-2 CSAs are the redundant partial
major challenge was to perform a radix-8 divide or radix-4
remainder and the f-vector, which is different for division
square root step on a wide quad precision mantissa, 113 bits
and square root; consequently, eight f-vector are specula-
plus some extra rounding bits, and fit it in a single cycle.
tively generated. Each of these full-length f-vectors is
In our implementation we have been able to put in a
obtained with a sequencer and a set of muxes.
single cycle three and two radix 4 iterations, for division
No area data is provided for the divide and square root
and square root respectively, by using speculation between
unit of the IBM z13 processor [14]. However, we can guess
iteration in the same cycle. In addition, there are only one
that the wider quad-precision datapath adds a large area
pre-processing cycle before the iterations, unpacking of
overhead.
operands and pre-scaling, and one post-processing cycle for
Finally, multiplicative division implementations [16],
rounding after the iterations.
[19], [23] involve only modest additional cost because the
7.2 Area existing FP multipliers are reused to perform each algo-
The area is strongly dependent on the algorithm, digit-recur- rithm iteration. Only a look-up table for the initial seed and
rence or multiplicative, being used for division and square some additional logic is needed to implement the divider.
root. In general, multiplicative algorithms have smaller area The total storage required for reciprocal and reciprocal
requirements if the multipliers or FMA units are shared with square root initial approximations in [19], [23] is 69 Kbits. In
other floating-point instructions. In case of digit-recurrence [16] the table is even smaller, 3.5 Kbits.
algorithms, the radix has also a great impact, the larger the
radix the large the area. 7.3 Timing
Therefore, the area of our division/square root unit is For the critical path delay estimation the Logical Effort
much larger than the area of the other units in the table; model [26] is used in this section. Table 5 summarizes the
however, our focus was on obtaining a low latency divi- delay of the basic gates (upper part) and of the main mod-
sion/square root unit. ules in Figs. 2 and 3 (middle and lower parts respectively)
The area of the rounding stage is not included in the dis- in terms of a FO4 and its equivalent in picoseconds. We
cussion because it should be roughly the same for all the units. have considered a FO4 delay of 6 ps. The load of every sig-
nal has been taken into account, so that a fanout of n adds a
7.2.1 Division/Square Root Unit in this Paper delay equivalent to log 4 n FO4.
Our unit uses a large number of 3-to-2 carry-save adders
(CSA) and carry-propagate adders (CPA) in the iterative 3. Roughly, each 4-to-2 carry-save adder is equivalent to two CSAs

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286 IEEE TRANSACTIONS ON COMPUTERS, VOL. 69, NO. 2, FEBRUARY 2020

TABLE 5 It is interesting to mention here that the combined divi-

Delay of Basic Gates and Modules of the sion and square root unit in [18] implements a radix-16 divi-
Divider and Square Root sion and square root iteration by overlapping two radix-4
FO4 ps iterations. There are quite a few similarities between the
square root in this unit and in our proposal: in both units
inverter 1 6 speculation is used in the calculation of the second digit in
2-input gate 1.33 8
basic gates 3-input gate 1.67 10 the cycle. In addition, as shown in Section 5.2, our proposal
xor gate 2 12 uses speculation in the calculation of the remainder as well.
2:1 mux 2.66 16 Note that in case of not using speculation in the remainder
58-bit adder 14.35 86 calculation, the critical path for the square root digit cycle
54-bit sub 14.35 86 would have the calculation of f½i þ 2 and a 4-to-2 CSA after
pre-scaling the second comparator, resulting in a delay larger than that
reduced SEL logic 4 24
2:1 mux with load 2:66 þ log 4 ð58Þ 40 of the division cycle.
6-bit adder 9.43 56
7-bit adder/comp. 9.34 56 7.3.3 Unit Critical Path
9-bit adder 11 66 The common division and square root critical path delay is
digit 3-to-2 CSA 4 24
cycle 4-to-2 CSA 6 36 tunit ¼ maxftdiv ; tsqrt g ¼ 300 ps: (25)
5:1 mux 4.33 26
division SEL logic 5:33 þ log 4 ð64Þ 50
sqrt comparators 9:34 þ log 4 ð64Þ 78 8 CONCLUSIONS
The architecture of a common unit for a radix-64 floating-
*Due to fanout.
point divider, providing 6 bits of the quotient per cycle, and
radix-16 square root, providing 4 bits of the root per cycle,
The fanout affects especially to the SELECT division
is presented.
module in Fig. 3 and to the comparators in Fig. 4 . The mod-
To get a simple implementation and an affordable timing
ules’ output, the quotient or root digit, has a high fanout,
the radix-64 division iteration and the radix-16 floating-
roughly 64 gates.
point square root iteration are built with 3 and 2 radix-4 iter-
ations, respectively. Each radix-4 iteration provides 2 bits of
7.3.1 Division the quotient or root for a throughput of 6-bit per cycle in
In the pre-scaling cycle there are two paths with roughly the division and 4 bits per cycle in square root. To improve the
path the same estimated delay, timing, speculation has been used between consecutive iter-
54-bit sub ! 2:1 mux with large fanout ! 2:1 mux ations in the cycle.
Additionally, some other improvements have been done
and in both division and square root. To have a simple digit selec-
2:1 mux ! 3:2 CSA ! 58-bit adder ! 2:1 mux tion logic, the divisor has been pre-scaled to a value close to
1, in such a way that the digit selection function does not
being the delay of each path 142 ps. Note the large fanout in
depend on the divisor, it depends only on the 6 most-signifi-
the first path 2:1 mux.
cant bits of the remainder. Pre-scaling has been implemented
In the digit cycle, there are several candidates to be the
as the addition of three terms, which depend on the most-sig-
critical path, but due to large fanout at the output of the SEL
nificant bits of the divisor. Of course, the dividend has to be
logic, the critical path consists of
scaled by the same amount as the divisor as well.
6-bit adder ! SEL logic ! 5:1 mux ! SEL logic ! Further latency reductions for some floating-point divi-
5:1 mux ! SEL logic ! 5:1 mux sion are obtained by left-shifting the dividend by 1 bit when
with an estimated delay of 300 ps it is larger than the divisor to have the result in [1,2), and by
Then, in conclusion, the critical path of the divider is in performing the first iteration, which gives the integer digit
the digit cycle and has a estimated delay of of the result, in parallel with the pre-scaling.
Regarding the square root, the first iteration has been
tdiv ¼ 300 ps skipped and integrated in the initialization stage. This way,
the latency has been reduced by 1 cycle in single and double
7.3.2 Square Root precision.
The result is a low latency floating-point digit-recurrence
The critical path is in the digit cycle. As in division, due to
divider and square root unit, with latencies of 11, 6 and 4
the large fanout of the root digit the critical path is going
cycles for double-precision, single-precision and half-preci-
through the selection logic of the two root digits,
sion division, and 15, 8 and 5 cycles for double-precision,
8-bit adder ! comparator ! 5:1 mux ! comparator single-precision and half-precision square root.
! root update
taking into account that the root update is basically an ACKNOWLEDGMENTS
and-or logic the estimated square root delay is The author would like to thank to the computer arithmetic
team at ARM Inc in Austin, TX, USA, for their help and sup-
tsqrt ¼ 250 ps:
port while the author was with ARM in Austin.

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BRUGUERA: LOW LATENCY FLOATING-POINT DIVISION AND SQUARE ROOT UNIT 287

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