Ministry of Higher Education and Scientific Research

Technology University

Department of Control Engineering and Systems

2019
 Multiplexers

It is a combinational and circuit that selects binary information from one of many input
times and direct it to a single output line. The selection of particular input line is controlled
by a set of selection lines. Normally ,There are 2n input lines and n selection lines whose
bit combinations determine which input is selected.

A logic circuit and Block Diagram for 2-to-1 Multiplexer shown below .

I0
I0 F
2×1 F I1
I1
s
s
s (selection line)

Block circuit Logic circuit

* when s=0 , the Upper AND gate is enable and I0 has a path to the output .
* when s=1 , the Lower AND gate is enable and I1 has a path to the output .

The input is ( 2n )
selection line is ( n )
If the input is two that means 21 = 2
then the selection line is ( 1 )

1
4 - to - 1 line multiplexer is shown below

S1 S2 F
0 0 I0
0 1 I1 Function Table
1 0 I2
1 1 I3

I0

I1
F
I2

I3

S0 S1

LOGIC CIRCUIT

I0 4×1
I1
MUX F
12
13 S0 S1

The I/P is 4 that's mean 22 = 4

* the selection line is ( 2 )

2
Ex / Implement the following Boolean function using 4 × 1 multiplexer

F = Ʃ (1,3,5,6)

No . of selection line = 2 (A,B)

A B C F
0 0 0 0
I0 = C
0 0 1 1
0 1 0 0
I1 = C
0 1 1 1
1 0 0 0
I2 = C
1 0 1 1
1 1 0 1
I3 = C
1 1 1 0

C I0
I1 4×1
F
I2 MUX
I3
S1 S0

A B

3
Ex / Implement the following function using 4 × 1 multiplexer

F =(x1,x2,x3,x4)= Ʃm (1,2,6,8,9,10,12) + d(3,5,13,14)

No . of selection line = 2 (x1,x2)

x3
x1 x2 x3 x4 F x4 0 1
0 0 0 0 0 0 0 1
0 0 0 1 1 I0 = x3 + x4
I0 1 1 d
0 0 1 0 1
0 0 1 1 d x3
x4 0 1
0 1 0 0 0
0 1 0 1 d 0 0 1
I1 I1 = x3 x4
0 1 1 0 1 1 d 0
0 1 1 1 0
1 0 0 0 1 x4x3 0 1
1 0 0 1 1 I2 0 1 1
1 0 1 0 1 I2 = x4 + x3
1 0 1 1 0 1 1 0
1 1 0 0 1 x4 x3 0 1
1 1 0 1 d I3 0 1 d
1 1 1 0 d
I3 = x3
1 1 1 1 0 1 d 0

4
Ex / Implement the following function using 4 × 1 multiplexer and any required logic

gates

F = Ʃm (0,1,3,4,8,9,15)

No . of selection line = 2 (A,B)

C
A B C D F D 0 1
0 0 0 0 1 0 1 0
0 0 0 1 1 I0 = C + D
I0 1 1 1
0 0 1 0 0
0 0 1 1 1 C
D 0 1
0 1 0 0 1
0 1 0 1 0 0 1 0
I1 I1 = C D
0 1 1 0 0 1 0 0
0 1 1 1 0
C
1 0 0 0 1 D 0 1
1 0 0 1 1 I2 0 1 0
1 0 1 0 0 I2 = C
1 0 1 1 0 1 1 0
1 1 0 0 0 D C 0 1
1 1 0 1 0 I3 0 0 0
1 1 1 0 0
I3 = CD
1 1 1 1 1 1 0 1

5
If C and D are selection line

A
A B C D F B 0 1
0 0 0 0 1 0 1 1
0 0 0 1 1 I0 = A + B
I0 1 1 0
0 0 1 0 0
0 0 1 1 1 A
B 0 1
0 1 0 0 1
0 1 0 1 0 0 1 1
I1 I1 = B
0 1 1 0 0 1 0 0
0 1 1 1 0
A
1 0 0 0 1 B 0 1
1 0 0 1 1 I2 0 0 0
1 0 1 0 0 I2 = 0
1 0 1 1 0 1 0 0
1 1 0 0 0 B
A
0 1
1 1 0 1 0 I3 0 1 0
1 1 1 0 0
I3 = AB + AB
1 1 1 1 1 1 0 1
=A B

6
Ex /construct 16 × 1 MUX with two 8 × 1 MUX and 2 × 1 MUX for the following
function :

F = Ʃm(0,1,3,4,8,9,15)

EN

1 I0
1 I1
0 I2
1 I3 8 × 1
1 I4 MUX
0 I5
0 I6
I7
B C D

2×1
MUX F

EN
A
1 I0
1 I1
I2
I3 8 × 1
I4 MUX
I5
I6
1 I7
B C D

7
 DEMULTIPLEXER ( ONE TO MANY )

The Demultiplexer is the reverse of the multiplexer where it receives the input information
on a single line and transmits this information on one of the 2n possible output lines
( 1 - to - 2n )

D0
1×4
D1
Input
MUX D2
D3
s1 s0

8
Ex / Construct 4 ×1 MUX only to implement the function

F (a,b,c,d) = Ʃm(0,1,5,7,9,10,12,15)

1 = I0
1 = I1
4×1
0 = I2
0 = I3 c d

0 = I4
1 = I5
4×1
0 = I6
1 = I7 c d

4×1 F

0 = I8
a b
1 = I9
4×1
1 = I10
0 = I11 c d

1 = I12
0 = I13
4×1
0 = I14
1 = I15 c d

9
Ex / construct 16 × 1 MUX using 8 × 1 MUX
abcd

I0
I1
I2
I3 8×1
I4
I5
I6
I7

b c d
4×1 F

I0 a
I1
I2
I3 8×1
I4
I5
I6
I7

b c d

10
Ex / construct 8×1 MUX using 2×1

a b c
0 0 0
0 1 1

I0
2×1
I1

C 2×1

I2
2×1
I3
b

C 2×1 F

I4
2×1 a
I5

2×1
C

I6
2×1 b
I7

11
Ex / Implement the following logic function using only one 4 MUX with other logic

gate

F = Ʃm( 0,2,5,7)

S.L Residul
A B C F
0 0 0 1
I0
0 0 1 0
0 1 0 1
I1
0 1 1 0
1 0 0 0
I2
1 0 1 1
1 1 0 0
I3
1 1 1 1

C
4 to 1

F
MUX

s1 s0

A B

12